Signal waveform data dynamic switching method and device based on FPGA

Abstract

The invention provides a signal waveform data dynamic switching method and device based on an FPGA, and the method comprises the steps: an upper computer generates a signal waveform file containing multiple segments of signal waveform data, and generates a corresponding DDR initial address and length mapping table based on each segment of signal waveform data, the FPGA receives a signal waveform file, sends the signal waveform file, a DDR initial address and a length mapping table to the DDR and the RAM, after an upper computer sends a playing starting command, the playing device responds to a trigger signal input by the outside through the GPIO, after the FPGA receives the trigger signal from the GPIO and detects that the trigger signal is valid, the FPGA locks and reads a port value of the GPIO, the FPGA selects a target signal waveform needing to be played based on the port value, and the target signal waveform is played according to the selected target signal waveform. Target signal waveform data corresponding to the target signal waveform is read in the DDR through the DataMover module, and the FPGA inputs the target signal waveform data into the DAC in real time for signal waveform playing.

Description

Technical Field

[0001] The present application relates to the field of data processing and communication technology, and in particular to a method and device for dynamically switching signal waveform data based on FPGA. Background Art

[0002] In scenarios such as radar signal processing, communication signal testing, and automatic test equipment, various systems usually need to dynamically switch to play different signal waveforms according to trigger signals, that is, the waveform data needs to be dynamically switched. For example, in radar systems, pulse, linear frequency modulation, or noise waveforms need to be switched according to the scenario; in communication test systems, the modulation signal type needs to be dynamically adjusted.

[0003] Currently, the dynamic switching of waveform data usually relies on a high-bandwidth transmission link to send waveform data from a host computer to a playback device in real time.

[0004] However, the existing method of dynamic waveform data switching requires the host computer to send data files every time an event is triggered, which brings data delay and packet loss problems when the signal waveform is transmitted from the host computer to the playback device in real time, and the stability is average. In addition, the delay in reading signal waveform data is high and the reading speed is slow, which makes the waveform switching efficiency low. At the same time, it is difficult to meet the needs of various complex application scenarios (such as high-speed switching and high-time precision application scenarios), and the scalability and flexibility are average. Summary of the invention

[0005] In view of this, the purpose of this application is to provide a method and device for dynamic switching of signal waveform data based on FPGA. The host computer pre-sends the signal waveform file to DDR through the communication interface and the FPGA, and the host computer does not need to re-send the signal waveform file at the next trigger event, thereby avoiding the data delay and packet loss caused by the real-time transmission of the signal waveform from the host computer to the playback device, and improving the efficiency and stability of signal waveform data transmission; through the DDR cache and DataMover module, low-latency reading of signal waveform data is achieved, thereby achieving a shorter waveform switching time and improving the efficiency of waveform switching. At the same time, it supports dynamic switching of multiple waveform types and waveform data of different lengths, can adapt to a variety of complex application scenarios, and has high scalability and flexibility.

[0006] In a first aspect, an embodiment of the present application provides a signal waveform data dynamic switching method based on FPGA, which is applied to a signal waveform data dynamic switching device; the signal waveform data dynamic switching device includes a host computer, an FPGA, and a DAC; the FPGA includes a DataMover module; the FPGA communicates with the outside through GPIO, the FPGA has a RAM inside, and the FPGA has a DDR externally; the DAC corresponds to a playback device; the method includes: The host computer generates a signal waveform file containing multiple segments of signal waveform data, generates a corresponding DDR start address and length mapping table based on each segment of signal waveform data, and sends the signal waveform file and the DDR start address and the length mapping table to the DDR and the RAM; wherein the DDR is used to store the signal waveform file, and the RAM is used to store the DDR start address and the length mapping table; After the host computer issues a playback start command, the playback device starts to respond to an external trigger signal input through the GPIO, the FPGA receives the trigger signal from the GPIO and after detecting that the trigger signal is valid, locks the port value of the GPIO, and reads the port value on the GPIO through the GPIO; The FPGA selects a target signal waveform to be played based on the port value, and reads target signal waveform data corresponding to the target signal waveform in the DDR through a DataMover module; The FPGA inputs the target signal waveform data into the DAC in real time, and outputs the target signal waveform data through the DAC, so as to perform signal waveform playback on the target signal waveform data based on the DAC.

[0007] In a possible implementation manner, the host computer generates a signal waveform file containing multiple segments of signal waveform data, and generates a DDR start address and length mapping table of the signal waveform file based on each segment of signal waveform data, including: The host computer generates a required signal waveform file containing multiple segments of signal waveform data on a preset generation tool based on a preset DAC resolution and sampling rate; The signal waveform file is stored as a binary signal waveform file, and the length of each signal waveform in the binary signal waveform file is determined; Generate the corresponding DDR start address and length mapping table based on the length of each signal waveform.

[0008] In a possible implementation manner, sending the signal waveform file, the DDR start address, and the length mapping table to the DDR and the RAM includes: The host computer sends the signal waveform file to the DDR of the FPGA external plug-in for caching through a preset communication interface with the FPGA; The DDR start addresses and length mapping table of the multiple segments of signal waveform data in the signal waveform file are sent to the RAM inside the FPGA.

[0009] In a possible implementation manner, the step of selecting the target signal waveform to be played based on the port value includes: Based on the port value, obtain the DDR start address and the RAM address index value of the length mapping table; The target DDR starting address and target length information corresponding to the signal waveform to be played are read in the RAM through the address index value, so as to determine the target signal waveform to be played based on the target DDR starting address and the target length information.

[0010] In a possible implementation, the method further includes: Determine the setting parameters required for loop playback of the target signal waveform data, and perform corresponding loop playback settings on the software of the host computer based on the setting parameters; In response to completing the setting of loop playback on the software of the host computer, the target signal waveform data is loop played until the FPGA receives a new trigger signal input from the external source from the GPIO.

[0011] In a possible implementation, the method further includes: In response to the FPGA receiving a new trigger signal input from the GPIO, obtaining a new port value on the GPIO through the GPIO; A corresponding new target signal waveform is selected based on the new port value, and the corresponding new target signal waveform data is re-read to dynamically switch to the new signal waveform.

[0012] In a possible implementation manner, generating a signal waveform file containing multiple segments of signal waveform data includes: Obtain waveform parameters of a signal waveform; After the waveform parameters are set on the software of the host computer, a corresponding signal waveform file is generated by the software.

[0013] In a possible implementation, the method further includes: Get the number of GPIO interfaces; The maximum number of the signal waveform data is determined based on the number of the GPIO interfaces, and the maximum number of groups supported by the RAM to store the DDR start address and the length mapping table is determined based on the maximum number of the signal waveform data.

[0014] In a possible implementation manner, the DAC corresponds to a data receiving bus; and inputting the target signal waveform data into the DAC in real time includes: The target signal waveform data is sent to the DAC in real time through the data receiving bus of the DAC.

[0015] In a second aspect, the embodiment of the present application further provides a signal waveform data dynamic switching device based on FPGA, the signal waveform data dynamic switching device based on FPGA includes a host computer, FPGA, and DAC; the FPGA includes a DataMover module; the FPGA communicates with the outside through GPIO, the FPGA has RAM inside, and the FPGA has DDR externally; the DAC corresponds to a playback device; The FPGA-based signal waveform data dynamic switching device is used to execute the FPGA-based signal waveform data dynamic switching method provided by the first aspect embodiment.

[0016] The embodiment of the present application provides a method and device for dynamically switching signal waveform data based on FPGA. The host computer generates a signal waveform file containing multiple segments of signal waveform data, generates a corresponding DDR start address and length mapping table based on each segment of signal waveform data, and sends the signal waveform file and the DDR start address and length mapping table to DDR and RAM. After the host computer sends a playback start command, the playback device starts to respond to an external trigger signal input through GPIO. The FPGA receives the trigger signal from the GPIO and locks the port value of the GPIO after detecting that the trigger signal is valid, and reads the port value on the GPIO through the GPIO. The FPGA selects the target signal waveform to be played based on the port value, and reads the target signal waveform data corresponding to the target signal waveform in the DDR through the DataMover module. The FPGA inputs the target signal waveform data into the DAC in real time, and outputs the target signal waveform data through the DAC, so as to perform signal waveform playback on the target signal waveform data based on the DAC. In this application, the host computer pre-sends the signal waveform file to the DDR through the communication interface and the FPGA, and the host computer does not need to re-send the signal waveform file at the next trigger event, avoiding the data delay and packet loss caused by the real-time transmission of the signal waveform from the host computer to the playback device, and improving the efficiency and stability of the signal waveform data transmission; through the DDR cache and DataMover module, low-latency reading of the signal waveform data is achieved, thereby achieving a shorter waveform switching time and improving the efficiency of waveform switching. At the same time, it supports dynamic switching of multiple waveform types and waveform data of different lengths, which can adapt to a variety of complex application scenarios and has high scalability and flexibility.

[0017] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 is a flow chart of a method for dynamically switching signal waveform data based on FPGA provided in an embodiment of the present application; Figure 2 It is a structural schematic diagram of a signal waveform data dynamic switching device; Figure 3 It is a schematic diagram of the overall process of dynamic switching of signal waveform data. DETAILED DESCRIPTION

[0020] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0021] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0022] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0023] Considering that in scenarios such as radar signal processing, communication signal testing, and automatic test equipment, various systems usually need to dynamically switch to play different signal waveforms according to trigger signals, that is, the waveform data is dynamically switched. For example, in radar systems, pulse, linear frequency modulation, or noise waveforms need to be switched according to the scenario; in communication test systems, the modulation signal type needs to be dynamically adjusted.

[0024] At present, the dynamic switching of waveform data usually relies on a high-bandwidth transmission link to send waveform data from the host computer to the playback device in real time. However, the existing method of dynamic switching of waveform data requires the host computer to send data files every time an event is triggered, which brings data delay and packet loss problems when the signal waveform is transmitted from the host computer to the playback device in real time, and the stability is average. In addition, the delay in reading signal waveform data is high and the reading speed is slow, which makes the waveform switching efficiency low. At the same time, it is difficult to meet the needs of various complex application scenarios (such as high-speed switching and high-time precision application scenarios), and the scalability and flexibility are average.

[0025] In response to this problem, the present application provides a method and device for dynamically switching signal waveform data based on FPGA. The host computer pre-sends the signal waveform file to DDR through the communication interface and the FPGA. The host computer does not need to re-send the signal waveform file when the next trigger event occurs, thereby avoiding the data delay and packet loss caused by the real-time transmission of the signal waveform from the host computer to the playback device, and improving the efficiency and stability of signal waveform data transmission; through the DDR cache and DataMover module, low-latency reading of signal waveform data is achieved, thereby achieving a shorter waveform switching time and improving the efficiency of waveform switching. At the same time, it supports dynamic switching of multiple waveform types and waveform data of different lengths, can adapt to a variety of complex application scenarios, and has high scalability and flexibility.

[0026] Figure 1 It is a flowchart of a method for dynamic switching of signal waveform data based on FPGA provided according to an embodiment of the present application. The method for dynamic switching of signal waveform data based on FPGA of the present application is applied to a device for dynamic switching of signal waveform data.

[0027] The signal waveform data dynamic switching device includes a host computer, FPGA (Field-Programmable Gate Array), DAC (Digital-to-Analog Converter); FPGA includes a DataMover module (a component for data migration, i.e., a data handling module); FPGA communicates with the outside through GPIO (General Purpose Input / Output), there is RAM (Random Access Memory) inside the FPGA, and FPGA has DDR (i.e., DDR SDRAM, double rate synchronous dynamic random access memory, referred to as DDR) externally; DAC corresponds to a playback device. For example, Figure 2 As shown, the Host software represents the host computer of this application.

[0028] like Figure 1 As shown, the FPGA-based signal waveform data dynamic switching method of the embodiment of the present application may specifically include: S101, the host computer generates a signal waveform file containing multiple segments of signal waveform data, generates a corresponding DDR start address and length mapping table based on each segment of signal waveform data, and sends the signal waveform file and the DDR start address and length mapping table to DDR and RAM.

[0029] S102, after the host computer sends a playback start command, the playback device starts to respond to the external trigger signal input through GPIO, the FPGA receives the trigger signal from the GPIO and after detecting that the trigger signal is valid, locks the port value of the GPIO, and reads the port value on the GPIO through the GPIO.

[0030] S103, the FPGA selects the target signal waveform to be played based on the port value, and reads the target signal waveform data corresponding to the target signal waveform in the DDR through the DataMover module.

[0031] S104, the FPGA inputs the target signal waveform data into the DAC in real time, and outputs the target signal waveform data through the DAC, so as to perform signal waveform playback on the target signal waveform data based on the DAC.

[0032] In the above-mentioned FPGA-based signal waveform data dynamic switching method, the host computer pre-sends the signal waveform file to the DDR through the communication interface and the FPGA, and the host computer does not need to re-send the signal waveform file at the next trigger event, thereby avoiding the data delay and packet loss caused by the real-time transmission of the signal waveform from the host computer to the playback device, and improving the efficiency and stability of signal waveform data transmission; through the DDR cache and DataMover module, low-latency reading of signal waveform data is achieved, thereby achieving a shorter waveform switching time and improving the efficiency of waveform switching. At the same time, it supports dynamic switching of multiple waveform types and waveform data of different lengths, can adapt to a variety of complex application scenarios, and has high scalability and flexibility.

[0033] The above exemplary steps of the embodiment of the present application are described below with reference to specific examples: S101, the host computer generates a signal waveform file containing multiple segments of signal waveform data, generates a corresponding DDR start address and length mapping table based on each segment of signal waveform data, and sends the signal waveform file and the DDR start address and length mapping table to DDR and RAM.

[0034] It should be noted that this application involves parameter configuration. Optionally, the configuration information of DDR includes at least clock frequency, DDR model, transmission rate, and data bit width; the configuration information of RAM includes at least interface type, storage type, data bit width, and storage depth; the configuration information of DataMover includes at least transmission direction, data bit width, burst length, and address bit width. For example, DDR configuration: clock frequency 133.333MHz, transmission rate 2400MT / s, data bit width 64bit, and maximum support for 19.2GB / s transmission bandwidth; RAM configuration: AXI interface, true dual-port RAM, bit width 64bit, depth 8192, used to store the start address and length table of the signal waveform, the start address and length information each occupy 32bit, and 4GB address access control can be achieved; DataMover configuration: MM2S interface, bit width 512bit, burst length 64, working clock 300MHz, and maximum 19.2GB / s transmission bandwidth can be achieved.

[0035] In an embodiment of the present application, DDR is used to store signal waveform files, and RAM is used to store DDR starting address and length mapping tables; the host computer (through software) generates a signal waveform file containing multiple segments of signal waveform data, and generates a DDR starting address and length mapping table corresponding to each segment of signal waveform data based on each segment of signal waveform data, and sends the signal waveform file and the DDR starting address and length mapping table to DDR and RAM for subsequent processing.

[0036] It should be noted that the maximum number of signal waveform data is determined based on the number of GPIO interfaces, and the maximum number of groups supported by RAM to store DDR start address and length mapping tables is determined based on the maximum number of signal waveform data. Specifically, the maximum number of signal waveform data is determined according to the number of GPIO interfaces. For example, the signal waveform data supports a maximum of 2 N Segments, where N is the number of GPIO interfaces. Taking 13 GPIO inputs as an example, the maximum number of signal waveform data is 8192, and there can be 1 to 8192 segments of signal waveform data, that is, 1 to 8192 segments of signal waveform switching can be achieved. The internal RAM of FPGA supports the storage of a maximum of 8192 groups of DDR start address and length mapping tables.

[0037] Among them, the signal waveform data supports a variety of waveform types and signal waveform data of different lengths, that is, the signal waveform data can be a variety of waveform types and signal waveform data of different lengths; the types of signal waveforms include at least single-tone signals, linear frequency modulation signals or other custom waveforms. In addition, the maximum value of the signal waveform file is the capacity of DDR; the sum of the data volume of each segment of signal waveform data does not exceed the total capacity of DDR. For example, the total capacity of FPGA external DDR is 4GB, and a maximum of 4GB of signal waveform files can be cached, and the sum of the data volume of each segment of signal waveform does not exceed the DDR capacity; the internal RAM of FPGA supports a capacity of 64KB, which is used to store the DDR starting address and length mapping table, and supports the storage of a maximum of 8192 groups of signal waveform starting addresses and length mapping tables.

[0038] Optionally, generating a signal waveform file containing multiple segments of signal waveform data includes: obtaining waveform parameters of the signal waveform; and generating a corresponding signal waveform file through the software after setting the waveform parameters on the software of the host computer. In short, after the host computer sets the waveform parameters of the signal waveform through the software, the corresponding signal waveform file is generated through the software.

[0039] Optionally, when the host computer generates a signal waveform file containing multiple segments of signal waveform data and generates a DDR start address and length mapping table of the signal waveform file based on each segment of signal waveform data, the host computer generates the required signal waveform file containing multiple segments of signal waveform data on a preset generation tool based on a preset DAC resolution and sampling rate; stores the signal waveform file as a binary signal waveform file, and determines the length of each segment of the signal waveform in the binary signal waveform file; generates a corresponding DDR start address and length mapping table based on the length of each segment of the signal waveform. The generation tool includes at least matlab and user-defined software.

[0040] Optionally, when sending the signal waveform file and the DDR starting address and length mapping table to the DDR and RAM, the host computer sends the signal waveform file to the DDR of the FPGA plug-in for caching through the preset communication interface with the FPGA; and sends the DDR starting address and length mapping table of multiple segments of signal waveform data in the signal waveform file to the RAM inside the FPGA. Among them, the communication interface includes at least PCIe, Ethernet, USB, etc. Specifically, the signal waveform file is transmitted to the DDR cache of the FPGA plug-in through the communication interface between the host computer and the FPGA, and the starting address (DDR starting address) and length information table (length mapping table) of the signal waveform file are sent to the RAM inside the FPGA. For example, Figure 2 shown.

[0041] It should also be noted that before the signal waveform file and the DDR start address and length mapping table are sent to the DDR and RAM, the playback device is initialized.

[0042] Therefore, the host computer avoids data delay and packet loss problems caused by real-time transmission of the signal waveform from the host computer to the playback device (DAC) by generating and pre-issuing the signal waveform file and the DDR start address and length mapping table, thereby improving the efficiency and stability of signal waveform data transmission.

[0043] S102, after the host computer sends a playback start command, the playback device starts to respond to the external trigger signal input through GPIO, the FPGA receives the trigger signal from the GPIO and after detecting that the trigger signal is valid, it locks the port value of the GPIO and reads the port value on the GPIO through the GPIO.

[0044] In the embodiment of the present application, the play start command is the start command of the entire process of playing the signal waveform, and the port value is the value on the GPIO, that is, the state value. After the host computer sends the play start command, it indicates that the process of playing the signal waveform has started. After the playback device receives the start command, it starts to respond to the external trigger signal input through the GPIO. After the FPGA receives the trigger signal from the GPIO and detects that the trigger signal is valid, it performs the port value of the GPIO and reads the port value on the GPIO through the GPIO for subsequent processing. For example, Figure 2 As shown, after receiving a trigger signal (eg, a signal in the form of 0 / 1) input from the outside through the GPIO, the FPGA reads the value on the GPIO for subsequent processing.

[0045] S103, the FPGA selects the target signal waveform to be played based on the port value, and reads the target signal waveform data corresponding to the target signal waveform in the DDR through the DataMover module.

[0046] In the embodiment of the present application, the target signal waveform is the signal waveform to be played corresponding to the trigger signal. After reading the port value on the GPIO, the FPGA selects the corresponding target signal waveform to be played based on the port value, and reads the target signal waveform data corresponding to the target signal waveform in the DDR through the DataMover module for subsequent processing. Figure 2 shown.

[0047] Optionally, when selecting the target signal waveform to be played based on the port value, the RAM address index value of the DDR start address and length mapping table is obtained based on the port value; the target DDR start address and target length information corresponding to the signal waveform to be played are read in the RAM through the address index value, so as to determine the target signal waveform to be played based on the target DDR start address and target length information. Specifically, the FPGA can obtain the address index value of the DDR start address and length mapping table of the signal waveform file according to the value on the GPIO, and read the DDR start address and waveform length information in the corresponding RAM according to the address index value to realize the selection of the signal waveform, and according to the obtained DDR start address and waveform length information, the FPGA controls the DataMover to read the corresponding signal waveform data.

[0048] Therefore, signal waveform data is read through DataMover, achieving low-latency data reading. S104, the FPGA inputs the target signal waveform data into the DAC in real time, and outputs the target signal waveform data through the DAC, so as to perform signal waveform playback on the target signal waveform data based on the DAC.

[0049] In the embodiment of the present application, after the FPGA reads the target signal waveform data in step S103, the FPGA inputs the target signal waveform data into the DAC in real time, and outputs the target signal waveform data through the DAC, so as to play the signal waveform of the target signal waveform data based on the DAC. Specifically, the signal waveform data obtained by the FPGA from the DDR is directly sent to the DAC data interface to play the signal waveform data.

[0050] It is understandable that the host computer is responsible for sending the signal waveform file, and the subsequent processes are completed inside the FPGA without the need for intervention from the host computer.

[0051] Optionally, the DAC corresponds to a data receiving bus, and the target signal waveform data is sent to the DAC in real time through the data receiving bus of the DAC.

[0052] The embodiment of the present application provides a method for dynamic switching of signal waveform data based on FPGA. The host computer generates a signal waveform file containing multiple segments of signal waveform data, generates a corresponding DDR start address and length mapping table based on each segment of signal waveform data, and sends the signal waveform file and the DDR start address and length mapping table to DDR and RAM. After the host computer sends a playback start command, the playback device starts to respond to an external trigger signal input through GPIO. The FPGA receives the trigger signal from the GPIO and locks the port value of the GPIO after detecting that the trigger signal is valid, and reads the port value on the GPIO through the GPIO. The FPGA selects the target signal waveform to be played based on the port value, and reads the target signal waveform data corresponding to the target signal waveform in the DDR through the DataMover module. The FPGA inputs the target signal waveform data into the DAC in real time, and outputs the target signal waveform data through the DAC, so as to perform signal waveform playback on the target signal waveform data based on the DAC. In the FPGA-based signal waveform data dynamic switching method of the present application, the host computer pre-sends the signal waveform file to the DDR through the communication interface and the FPGA, and the host computer does not need to re-send the signal waveform file at the next trigger event, thereby avoiding the data delay and packet loss caused by the real-time transmission of the signal waveform from the host computer to the playback device, and improving the efficiency and stability of the signal waveform data transmission; through the DDR cache and DataMover module, low-latency reading of the signal waveform data is achieved, thereby achieving a shorter waveform switching time and improving the efficiency of the waveform switching. At the same time, it supports the dynamic switching of multiple waveform types and waveform data of different lengths, which can adapt to a variety of complex application scenarios and has high scalability and flexibility.

[0053] Furthermore, the setting parameters required for loop playback of the target signal waveform data are determined, and corresponding loop playback settings are performed on the software of the host computer based on the setting parameters; in response to completing the loop playback settings on the software of the host computer, the target signal waveform data is looped until the FPGA receives a new trigger signal from the external input from the GPIO.

[0054] It should be noted that after the signal waveform data is played, it can continue to start from the beginning according to the configuration of the host computer software to achieve a loop playback effect; until a new trigger event, that is, a trigger signal, is generated.

[0055] Furthermore, in response to the FPGA receiving a new trigger signal from the external input from the GPIO, a new port value on the GPIO is obtained through the GPIO; based on the new port value, the corresponding new target signal waveform is selected, and the corresponding new target signal waveform data is re-read to dynamically switch to the new signal waveform.

[0056] Specifically, when a new trigger event occurs, that is, a new trigger signal is input externally, the host computer receives the new trigger signal and detects that it is valid, and then continues to re-read the corresponding new GPIO value, and then selects the corresponding signal waveform according to the new GPIO value and reads the corresponding new target signal waveform data, so as to play it and realize the dynamic switching of the signal waveform. In short, every time a trigger signal comes, the target signal waveform data is re-read, switched to the new signal waveform, and the new signal waveform is played.

[0057] It can be understood that the FPGA-based signal waveform data dynamic switching method of the present application mainly includes processes such as file generation, waveform selection, signal waveform data reading and signal waveform playback, among which file generation is implemented by the host computer, and the remaining waveform selection, signal waveform data reading and signal waveform playback processes are all completed by FPGA.

[0058] The following is combined with Figure 2 For further description, Figure 2 As shown, the signal waveform data dynamic switching device of the present application can be simply understood as two parts: the host computer part and the FPGA. Among them, the host computer part involves signal waveform generation, file generation and data sending; the FPGA part includes GPIO signal capture, RAM driver module, DDR interface driver module and DAC driver module, among which, the GPIO signal capture decoding is used to receive the input signal of the GPIO, and decode to obtain the address index value of the RAM start address and length mapping information table; the RAM driver module is used to read the DDR start address and length information corresponding to the signal waveform to be played from the address corresponding to the RAM according to the address index value; the DDR interface driver module is used to realize the driving of the DataMover module and the driving of the DDR, and obtain the waveform data according to the DDR start address and length read from the RAM; the DAC driver module is used for DataMover to read the signal waveform from the DDR, and send it to the DAC chip in real time through the data receiving bus of the external DAC chip to realize the signal waveform playback.

[0059] Accordingly, when designing the module, after receiving the trigger signal, the GPIO control module records the current GPIO encoding value, parses it into a RAM address index value, and outputs the index value to the RAM address mapping module; after receiving the index value from the GPIO control module, the RAM address mapping module reads the corresponding signal waveform starting address and length information according to the index value, and outputs the starting address and length information to the DDR data reading module; the DDR data reading module includes the DataMover driving and state control functions, and after receiving the starting address and length information, controls the DataMover to read the signal waveform data stored in the DDR, and sends it to the DAC interface, supporting the waveform loop reading function; the DAC interface module implements the driving function of the DAC chip, obtains the signal waveform data output by the DDR reading module, and sends it to the DAC chip, completing the data playback function.

[0060] In general, if Figure 3 As shown in the figure, various modules are represented. The host computer generates a signal waveform file, generates the required signal waveform according to the DAC resolution and sampling rate, and contains multiple segments of signal waveform data; generates the corresponding starting address and length mapping table according to the length of the signal waveform file; the host computer sends the signal waveform file, the starting address and the length mapping table through the communication interface, and then starts the system; the FPGA starts to receive the external trigger signal, and after detecting that the trigger signal is valid, locks the state value of the GPIO and converts it into the address index value of the RAM; reads the starting address and length information of the signal waveform to be played stored in the corresponding RAM; controls the DataMover module to read the waveform data from the DDR, and inputs the DAC chip to realize the signal waveform playback.

[0061] Specifically, for example, Figure 3As shown, FPGA receives the external trigger signal Ext_Trig (ExternalTrigger) and reads the value on GPIO, and GPIO And Trig Proc represents the logical combination of GPIO and the external trigger signal, which is used to trigger a specific operation. Index represents the index controller, which is used to manage the address location of data storage or reading. Ctrl_RAM is used to control the RAM read and write operations inside the FPGA. RAM_Addr represents the address bus of the RAM, which specifies the data storage location. DataMover_Driver is the data handling driver module (DataMover), which is responsible for transferring data from RAM to DDR. DDR_Addr&DDR_Length is used to specify the target address and data length of DDR. The config module loads configuration parameters (such as DDR address, data length, etc.). AXI (Advanced eXtensible Interface) is a high-performance bus protocol of ARM, which is used for high-speed data transmission between modules inside the FPGA. DataMover is used to realize data handling (such as from DDR to DAC) through the AXI bus. DAC_Driver is a DAC driver, which is used to control the output of the digital-to-analog converter. DAC_data represents the data source of the digital signal to be converted, that is, the corresponding target signal waveform data, that is, the playback device data. DAC_bus represents the playback device bus. In addition, the DDR controller is used to control the DDR SDRAM. The overall process also involves the communication interface for realizing the communication between the Host upper computer software and the FPGA. It can be understood that the present application uses preset waveform files, starting addresses and length mapping tables, and cooperates with dataMover to achieve fast switching of signal waveforms without the need for the host computer to re-send data files, and the waveform switching time can be achieved within 1 microsecond.

[0062] Therefore, this application realizes low-latency reading of waveform data through DDR cache and DataMover module, meets the switching time requirement within 1 microsecond, and achieves high efficiency; supports dynamic switching of 2^N segments of waveform data, N is the number of GPIO interfaces, adapts to a variety of complex application scenarios, and achieves flexibility; the signal waveform file is pre-sent to the DDR, avoiding the data delay and packet loss problems caused by the real-time transmission of the signal waveform from the host computer to the playback device (DAC), and achieves stability; supports multiple waveform types and waveform data of different lengths, has strong versatility, and achieves scalability.

[0063] It should be noted that the present invention provides a method for dynamically switching signal waveform data based on FPGA, that is, a method for dynamically switching signal waveform data based on FPGA, that is, a method for dynamically switching signal waveform data based on FPGA and DDR SDRAM.

[0064] An embodiment of the present application also provides a signal waveform data dynamic switching device based on FPGA, which includes a host computer, FPGA, and DAC; the FPGA includes a DataMover module; the FPGA communicates with the outside through GPIO, there is RAM inside the FPGA, and the FPGA has a DDR plug-in; the DAC corresponds to a playback device.

[0065] The above-mentioned FPGA-based signal waveform data dynamic switching device is used to execute the above-mentioned FPGA-based signal waveform data dynamic switching method.

[0066] The embodiment of the present application provides an FPGA-based signal waveform data dynamic switching device, in which a host computer generates a signal waveform file containing multiple segments of signal waveform data, generates a corresponding DDR start address and length mapping table based on each segment of signal waveform data, and sends the signal waveform file and the DDR start address and length mapping table to DDR and RAM. After the host computer sends a playback start command, the playback device starts to respond to an external trigger signal input through GPIO, the FPGA receives the trigger signal from the GPIO and locks the port value of the GPIO after detecting that the trigger signal is valid, and reads the port value on the GPIO through the GPIO, the FPGA selects the target signal waveform to be played based on the port value, and reads the target signal waveform data corresponding to the target signal waveform in the DDR through the DataMover module, the FPGA inputs the target signal waveform data into the DAC in real time, and outputs the target signal waveform data through the DAC, so as to perform signal waveform playback on the target signal waveform data based on the DAC. In the FPGA-based signal waveform data dynamic switching device of the present application, the host computer pre-sends the signal waveform file to the DDR through the communication interface and the FPGA, and the host computer does not need to re-send the signal waveform file at the next trigger event, thereby avoiding the data delay and packet loss caused by the real-time transmission of the signal waveform from the host computer to the playback device, and improving the efficiency and stability of the signal waveform data transmission; through the DDR cache and DataMover module, the low-latency reading of the signal waveform data is realized, thereby realizing a shorter waveform switching time and improving the efficiency of the waveform switching. At the same time, it supports the dynamic switching of multiple waveform types and waveform data of different lengths, which can adapt to a variety of complex application scenarios and has high scalability and flexibility.

[0067] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0068] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0069] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0070] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the deployment method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks, or optical disks.

[0071] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A signal waveform data dynamic switching method based on FPGA, applied to a signal waveform data dynamic switching device; the signal waveform data dynamic switching device comprises a host computer, FPGA, and DAC; the FPGA comprises a DataMover module; the FPGA communicates with the outside through GPIO, the FPGA has RAM inside, and the FPGA has DDR externally; the DAC corresponds to a playback device; characterized in that, The method comprises: The host computer generates a signal waveform file containing multiple segments of signal waveform data, generates a corresponding DDR start address and length mapping table based on each segment of signal waveform data, and sends the signal waveform file and the DDR start address and the length mapping table to the DDR and the RAM; wherein the DDR is used to store the signal waveform file, and the RAM is used to store the DDR start address and the length mapping table; After the host computer issues a playback start command, the playback device starts to respond to an external trigger signal input through the GPIO, the FPGA receives the trigger signal from the GPIO and after detecting that the trigger signal is valid, locks the port value of the GPIO, and reads the port value on the GPIO through the GPIO; The FPGA selects a target signal waveform to be played based on the port value, and reads target signal waveform data corresponding to the target signal waveform in the DDR through a DataMover module; The FPGA inputs the target signal waveform data into the DAC in real time, and outputs the target signal waveform data through the DAC, so as to perform signal waveform playback on the target signal waveform data based on the DAC.

2. The method according to claim 1, characterized in that The host computer generates a signal waveform file containing multiple segments of signal waveform data, and generates a DDR start address and length mapping table of the signal waveform file based on each segment of signal waveform data, including: The host computer generates a required signal waveform file containing multiple segments of signal waveform data on a preset generation tool based on a preset DAC resolution and sampling rate; The signal waveform file is stored as a binary signal waveform file, and the length of each signal waveform in the binary signal waveform file is determined; Generate the corresponding DDR start address and length mapping table based on the length of each signal waveform.

3. The method according to claim 2, characterized in that The sending the signal waveform file, the DDR start address, and the length mapping table to the DDR and the RAM includes: The host computer sends the signal waveform file to the DDR of the FPGA external plug-in for caching through a preset communication interface with the FPGA; The DDR start addresses and length mapping table of the multiple segments of signal waveform data in the signal waveform file are sent to the RAM inside the FPGA.

4. The method according to claim 3, characterized in that The step of selecting a target signal waveform to be played based on the port value includes: Based on the port value, obtain the DDR start address and the RAM address index value of the length mapping table; The target DDR starting address and target length information corresponding to the signal waveform to be played are read in the RAM through the address index value, so as to determine the target signal waveform to be played based on the target DDR starting address and the target length information.

5. The method according to claim 4, characterized in that The method further comprises: Determine the setting parameters required for loop playback of the target signal waveform data, and perform corresponding loop playback settings on the software of the host computer based on the setting parameters; In response to completing the setting of loop playback on the software of the host computer, the target signal waveform data is loop played until the FPGA receives a new trigger signal input from the external source from the GPIO.

6. The method according to claim 5, characterized in that The method further comprises: In response to the FPGA receiving a new trigger signal input from the GPIO, obtaining a new port value on the GPIO through the GPIO; A corresponding new target signal waveform is selected based on the new port value, and the corresponding new target signal waveform data is re-read to dynamically switch to the new signal waveform.

7. The method according to claim 6, characterized in that The generating of a signal waveform file containing multiple segments of signal waveform data comprises: Obtain waveform parameters of a signal waveform; After the waveform parameters are set on the software of the host computer, a corresponding signal waveform file is generated by the software.

8. The method according to claim 7, characterized in that The method further comprises: Get the number of GPIO interfaces; The maximum number of the signal waveform data is determined based on the number of the GPIO interfaces, and the maximum number of groups supported by the RAM to store the DDR start address and the length mapping table is determined based on the maximum number of the signal waveform data.

9. The method according to claim 8, characterized in that The DAC corresponds to a data receiving bus; the target signal waveform data is input into the DAC in real time, including: The target signal waveform data is sent to the DAC in real time through the data receiving bus of the DAC.

10. A signal waveform data dynamic switching device based on FPGA, characterized in that: The FPGA-based signal waveform data dynamic switching device includes a host computer, an FPGA, and a DAC; the FPGA includes a DataMover module; the FPGA communicates with the outside through GPIO, the FPGA has a RAM inside, and the FPGA has a DDR externally; the DAC corresponds to a playback device; The FPGA-based signal waveform data dynamic switching device is used to execute the FPGA-based signal waveform data dynamic switching method as described in any one of claims 1-9.

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