Semiconductor device and manufacturing method thereof, electronic device

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, the semiconductor device comprising a plurality of layers of memory cells stacked in a direction perpendicular to a substrate, a first word line, each layer of the memory cells comprising: a first transistor, a second transistor; the first transistor comprising a first semiconductor sub-layer; a second semiconductor sub-layer is arranged between adjacent first semiconductor sub-layers to form a first semiconductor layer, the first semiconductor layer and a control electrode are arranged in a first hole, the first word line is arranged in a second hole and extends in the direction perpendicular to the substrate through the different layers, the distance between the first word line and the first semiconductor sub-layer in a direction parallel to the substrate is less than the distance between the first word line and the second semiconductor sub-layer in the direction parallel to the substrate. The scheme provided by the embodiment can control the parasitic semiconductor layer through the control electrode, thereby avoiding the leakage of the parasitic transistor, and without etching the parasitic channel, avoiding affecting the effective channel of the device.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure relates to, but is not limited to, device design and manufacturing in the technical field of semiconductor technology, in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of the device is increasingly reduced, and the types and quantities of devices contained in a single chip are also increased, so that any slight difference in process production may affect the performance of the device.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs. SUMMARY

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The embodiment of the present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device, which avoids leakage caused by a parasitic transistor and improves device performance.

[0006] The embodiment of the present disclosure provides a semiconductor device, comprising a plurality of layers of memory cells stacked in a direction perpendicular to a substrate, a first word line, wherein,

[0007] Each layer of the memory cell comprises a first transistor and a second transistor; the second transistor and the first transistor are sequentially distributed in a first direction parallel to the substrate;

[0008] The first transistor comprises a first semiconductor sublayer, a first electrode and a second electrode; the first semiconductor sublayer is connected with the first electrode and the second electrode, respectively;

[0009] The second transistor comprises a third gate electrode, and the third gate electrode is connected with the first electrode;

[0010] A second semiconductor sublayer is arranged between adjacent first semiconductor sublayers, and the first semiconductor sublayer and the second semiconductor sublayer are connected to form an integrated structure, which is referred to as a first semiconductor layer, and the first semiconductor layer extends in a direction perpendicular to the substrate;

[0011] A first hole and a second hole penetrating different layers, the second hole and the first hole are in communication, and the first hole is provided with the first semiconductor layer and a control electrode extending in a direction perpendicular to the substrate and penetrating different layers, wherein the first semiconductor layer surrounds the sidewall of the control electrode;

[0012] The first word line is arranged in the second hole and extends along a direction perpendicular to the substrate, and a distance between the first word line and the first semiconductor sub-layer along a direction parallel to the substrate is less than a distance between the first word line and the second semiconductor sub-layer along the direction parallel to the substrate.

[0013] In some embodiments, the semiconductor device further comprises:

[0014] The insulating layer and the conductive layer are alternately arranged from top to bottom along a direction perpendicular to the substrate; the first hole and the second hole penetrate the insulating layer and the conductive layer;

[0015] The first semiconductor layer, the second gate insulating layer surrounding the side wall of the control electrode, and the control electrode are arranged in the first hole from outside to inside.

[0016] The first gate insulating layer surrounding the side wall of the first word line and the first word line are arranged in the second hole from outside to inside.

[0017] In some embodiments, a hole diameter of the first hole in a first sub-hole of the insulating layer is less than a hole diameter of the first hole in a second sub-hole of the conductive layer.

[0018] In some embodiments, a hole diameter of the second hole in a third sub-hole of the insulating layer is less than a hole diameter of the second hole in a fourth sub-hole of the conductive layer.

[0019] In some embodiments, the side wall of the first semiconductor sub-layer is connected with the side wall of the first gate insulating layer, and the side wall of the second semiconductor sub-layer is arranged between the side wall of the first gate insulating layer and the insulating layer.

[0020] In some embodiments, the arrangement direction of the first hole and the second hole is perpendicular to the first direction.

[0021] In some embodiments, the first electrode and the second electrode are arranged on the outer side wall of the first semiconductor sub-layer and are spaced apart along the first direction, and the first word line is arranged on the outer side wall of the first semiconductor sub-layer in a region between the first electrode and the second electrode.

[0022] In some embodiments, a first groove is arranged between adjacent insulating layers and faces away from the first word line, the control electrode, and the second electrode, a bottom wall of the first groove exposes the first gate insulating layer and the first semiconductor sub-layer, the first electrode is arranged on the bottom wall and the side wall perpendicular to the substrate of the first groove, and the second semiconductor layer is arranged on the bottom wall and the side wall perpendicular to the substrate of the first groove and is also arranged on the adjacent insulating layers constituting the side wall of the first groove.

[0023] In some embodiments, the semiconductor device further comprises a second recess extending along a second direction and disposed on a side of the first recess facing away from the first semiconductor layer, the second recess is in communication with a plurality of first recesses in a same column, the second recesses of a second transistor in the same column distributed along the second direction are connected to form an integrated structure, the second semiconductor layer of the second transistor in the same column is connected to form an integrated structure with the second semiconductor layer disposed on the sidewall and bottom wall of the second recess, and the first direction and the second direction are perpendicular to each other.

[0024] In some embodiments, the semiconductor device further comprises a memory cell array distributed along a direction perpendicular to the substrate, each layer of the memory cell array comprises a plurality of rows and columns of memory cells distributed along the first direction and the second direction respectively, and the memory cells in the same position of different layers are a plurality of memory cells stacked along a direction perpendicular to the substrate.

[0025] In some embodiments, the first transistors adjacent along the first direction are connected to different first bit lines.

[0026] In some embodiments, the semiconductor device further comprises a second bit line extending along the second direction and distributed on the bottom wall and sidewall of the second recess in which the second semiconductor layer is disposed.

[0027] In some embodiments, the second transistors adjacent along the first direction are connected to different second bit lines.

[0028] In some embodiments, the second semiconductor layers of the second transistors in different layers are spaced apart.

[0029] In some embodiments, the third gate electrodes and the first electrodes of the same memory cell are connected to form an integrated structure.

[0030] In some embodiments, the second transistor further comprises a third electrode, the third electrodes of the second transistors of the memory cells in the same position of different layers are connected to form an integrated structure extending along a direction perpendicular to the substrate, the integrated structure formed by the connection of the third electrodes comprises a vertical portion extending along a direction perpendicular to the substrate and a horizontal portion extending from the vertical portion along a horizontal direction, and the horizontal portion is connected to the second semiconductor layer distributed on the bottom wall of the first recess and the second semiconductor layer distributed on the region adjacent to the bottom wall of the first recess.

[0031] In some embodiments, the second transistor further comprises a fourth gate electrode disposed on a side of the third electrode away from the first transistor, the fourth gate electrodes of the second transistors of the plurality of memory cells in the same position are connected to form an integrated structure extending along a direction perpendicular to the substrate, and a projection of the fourth gate electrode on the substrate is located within a projection of the first recess on the substrate.

[0032] In some embodiments, the semiconductor device further comprises:

[0033] a third hole penetrating through each of the insulating layers and each of the conductive layers; the third hole comprises a fourth hole and a fifth hole penetrating through each of the insulating layers and each of the conductive layers, and the fourth hole and the fifth hole are arranged in the same direction as the first transistor and the second transistor;

[0034] the third hole is distributed with a third gate insulating layer and a second semiconductor layer from outside to inside;

[0035] the fourth hole is distributed with a plurality of third electrodes connected as an integrated structure;

[0036] the fifth hole is distributed with a fourth gate insulating layer and the fourth gate electrode from outside to inside.

[0037] In some embodiments, a hole diameter of the fifth sub-hole of the insulating layer where the third hole is located is smaller than a hole diameter of the sixth sub-hole of the conductive layer where the third hole is located.

[0038] In some embodiments, the fourth hole comprises a seventh sub-hole of the insulating layer and an eighth sub-hole of the conductive layer, and a boundary of the seventh sub-hole on a side close to the fifth hole in a projection of the substrate overlaps with a boundary of the eighth sub-hole on a side close to the fifth hole in the projection of the substrate, and other boundaries of the seventh sub-hole in the projection of the substrate fall within the projection of the eighth sub-hole.

[0039] In some embodiments, the fifth hole comprises a ninth sub-hole of the insulating layer and a tenth sub-hole of the conductive layer, and a boundary of the ninth sub-hole on a side close to the fourth hole in a projection of the substrate overlaps with a boundary of the tenth sub-hole on a side close to the fourth hole in the projection of the substrate, and other boundaries of the ninth sub-hole in the projection of the substrate fall within the projection of the tenth sub-hole.

[0040] Embodiments of the present disclosure provide a manufacturing method of a semiconductor device, comprising:

[0041] providing a substrate, depositing a first insulating film and a conductive layer film alternately and sequentially on the substrate to form a stack structure comprising insulating layers and conductive layers arranged alternately;

[0042] patterning the stack structure to form first trenches extending along a first direction through each layer, the first trenches including a first transistor region and a second transistor region distributed along the first direction between adjacent first trenches;

[0043] forming second holes through the stack structure in a direction perpendicular to the substrate in the first transistor region, laterally etching the conductive layers in each second hole such that the second hole has a larger aperture in the conductive layer than in the insulating layer, and forming a first gate insulating layer and a first word line of the first transistor sequentially on sidewalls of the second hole;

[0044] forming first holes through the stack structure in a direction perpendicular to the substrate in the first transistor region, laterally etching the conductive layers in each first hole such that the first hole has a larger aperture in the conductive layer than in the insulating layer, and such that each first gate insulating layer between any conductive layers in the second hole is exposed;

[0045] forming a first semiconductor layer connecting each first gate insulating layer, a second gate insulating layer, and a control electrode of the first transistor corresponding to different layers of the first transistor sequentially in the first hole, the first semiconductor layer including a plurality of first semiconductor sub-layers arranged at intervals and a second semiconductor sub-layer between adjacent first semiconductor sub-layers, the first semiconductor sub-layers and the second semiconductor sub-layer being connected to form an integrated structure, a distance between the first word line and the first semiconductor sub-layer along a direction parallel to the substrate being less than a distance between the first word line and the second semiconductor sub-layer along the direction parallel to the substrate;

[0046] forming a second transistor in the second transistor region, the first transistor and the second transistor being connected by the conductive layer as a sidewall of the first hole and a sidewall of the second hole.

[0047] In some embodiments, further comprising:

[0048] forming third trenches through each layer between adjacent first transistor regions along the first direction, the third trenches extending along a second direction; laterally etching the conductive layers in the third trenches to the adjacent first transistor regions to form first lateral trenches, forming a first bit line filling the first lateral trenches in the first lateral trenches, the first lateral trenches being in communication with the first holes and the second holes.

[0049] In some embodiments, forming a second transistor in the second transistor region includes:

[0050] forming a second trench extending in a second direction through layers in between adjacent second transistor regions along the first direction; laterally etching the conductive layers in the second trench to the adjacent second transistor regions to form a second lateral trench in each of the conductive layers;

[0051] forming a third hole through the stack structure in a direction perpendicular to the substrate in the first transistor region, laterally etching the conductive layers in each third hole to form a lateral recess, such that the aperture of the third hole in the conductive layer is larger than the aperture in the insulating layer, and the third hole is in communication with the second trench, and the bottom wall and the sidewall perpendicular to the substrate direction of the lateral recess are the conductive layers;

[0052] forming a third gate insulating layer and a second semiconductor layer of the second transistor in the third hole and the second trench, and the second semiconductor layer is formed only on the inner wall of the second lateral trench and the lateral recess; forming a second bit line filling the second lateral trench in the second lateral trench with the second semiconductor layer;

[0053] forming a fourth hole through the stack structure in a direction perpendicular to the substrate in the third hole, laterally etching the conductive layers in each fourth hole, such that the second semiconductor layer disposed on the bottom wall of the lateral recess and the sidewall close to the bottom wall of the recess is exposed, and each third gate insulating layer between any conductive layers in the fourth hole is exposed; forming a third electrode of the second transistor in the fourth hole.

[0054] In some embodiments, forming a second transistor in the second transistor region further comprises:

[0055] forming a fifth hole through the stack structure in a direction perpendicular to the substrate in the third hole, laterally etching the conductive layers in each fifth hole, such that the second semiconductor layer disposed in the lateral recess not connected to the third electrode is exposed, and each third gate insulating layer between any conductive layers in the fourth hole is exposed, and the third electrode is exposed; forming a fourth gate insulating layer and a fourth gate electrode of the second transistor in the fifth hole.

[0056] Embodiments of the present disclosure provide an electronic device, comprising the semiconductor device of any of the above embodiments, or a semiconductor device manufactured according to the semiconductor device manufacturing method of any of the above embodiments.

[0057] The embodiments of the present disclosure include a semiconductor device and a manufacturing method thereof, and an electronic device. The semiconductor device includes a plurality of layers of memory cells stacked in a direction perpendicular to a substrate, and a first word line. Each layer of the memory cells includes a first transistor and a second transistor. The second transistor and the first transistor are sequentially arranged in a first direction parallel to the substrate. The first transistor includes a first semiconductor sub-layer, a first electrode, and a second electrode. The first semiconductor sub-layer is connected to the first electrode and the second electrode, respectively. The second transistor includes a third gate electrode connected to the first electrode. A second semiconductor sub-layer is arranged between adjacent first semiconductor sub-layers. The first semiconductor sub-layer and the second semiconductor sub-layer are connected to form an integrated structure, which is referred to as a first semiconductor layer. The first semiconductor layer extends in a direction perpendicular to the substrate. A first hole and a second hole pass through different layers. The first hole is provided with the first semiconductor layer and a control electrode extending in the direction perpendicular to the substrate and passing through different layers. The first semiconductor layer surrounds a sidewall of the control electrode. The first word line is arranged in the second hole and extends in the direction perpendicular to the substrate and passes through the different layers. The distance between the first word line and the first semiconductor sub-layer in the direction parallel to the substrate is less than the distance between the first word line and the second semiconductor sub-layer in the direction parallel to the substrate. The semiconductor device provided by the embodiments can control the second semiconductor sub-layer through the control electrode, and the control of the second semiconductor sub-layer by the first word line is weaker than the control of the first semiconductor sub-layer by the first word line, so that the parasitic transistor can be turned off while the first transistor is turned on, leakage caused by the parasitic transistor is avoided, the process is simplified, and the performance of the device is improved.

[0058] Other features and advantages of the present disclosure will be set forth in the description that follows, and in part will be apparent from the description, or can be learned by practice of the present disclosure. The purposes and advantages of the present disclosure can be achieved and obtained by the structure particularly pointed out in the description and the accompanying drawings.

[0059] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0060] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions.

[0061] FIG. 1A A schematic circuit diagram of a memory cell array of a semiconductor device provided for an exemplary embodiment;

[0062] FIG. 1B A schematic circuit diagram of a memory cell provided for an exemplary embodiment;

[0063] FIG. 1C A circuit diagram of a memory cell array of a semiconductor device provided for another exemplary embodiment;

[0064] FIG. 1D for FIG. 1C A circuit diagram of a memory cell in a semiconductor device is shown.

[0065] FIG. 2A A top view of a semiconductor device provided for an exemplary embodiment;

[0066] FIG. 2B For along FIG. 2A Cross-sectional view along the AA direction;

[0067] FIG. 2C For along FIG. 2A Cross-sectional view in the middle BB direction;

[0068] FIG. 2D For along FIG. 2A Cross-sectional view in the CC direction;

[0069] FIG. 2E For along FIG. 2A Cross-sectional view in the DD direction;

[0070] FIG. 2F For along FIG. 2A Cross-sectional view in the EE direction;

[0071] FIG. 1A A top view of a semiconductor device provided for another exemplary embodiment;

[0072] FIG. 1B For along FIG. 2A to FIG. 2F Cross-sectional view along the AA direction;

[0073] FIG. 1A For along FIG. 1A Cross-sectional view in the middle BB direction;

[0074] FIG. 1A For along FIG. 1A Cross-sectional view in the CC direction;

[0075] FIG. 2A to FIG. 2E For along FIG. 2A Cross-sectional view in the DD direction.

[0076] FIG. 2A For along FIG. 2A Cross-sectional view in the EE direction;

[0077] FIG. 2A to FIG. 2F A top view provided for an exemplary embodiment after forming multiple stacked structures;

[0078] FIG. 1C is a cross-sectional view taken along the AA direction of FIG. 17; FIG. 1D is a cross-sectional view taken along the AA direction of FIG. 18;

[0079] FIG. 1C is a plan view of an exemplary embodiment after forming a first trench;

[0080] FIG. 3A is a cross-sectional view taken along the AA direction of FIG. 19; FIG. 3B is a cross-sectional view taken along the AA direction of FIG. 20;

[0081] FIG. 3A is a cross-sectional view taken along the BB direction of FIG. 20; FIG. 3C is a cross-sectional view taken along the BB direction of FIG. 21;

[0082] FIG. 3A is a plan view of an exemplary embodiment after forming a second trench and a third hole;

[0083] FIG. 3D is a cross-sectional view taken along the AA direction of FIG. 22; FIG. 3A is a cross-sectional view taken along the AA direction of FIG. 23;

[0084] FIG. 3E is a cross-sectional view taken along the BB direction of FIG. 23; FIG. 3A is a cross-sectional view taken along the BB direction of FIG. 24;

[0085] FIG. 3F is a plan view of an exemplary embodiment after forming a third gate insulating layer, a second semiconductor layer, and a first protective layer;

[0086] FIG. 3A is a cross-sectional view taken along the AA direction of FIG. 25; FIG. 1C is a cross-sectional view taken along the AA direction of FIG. 26;

[0087] FIG. 1D is a cross-sectional view taken along the BB direction of FIG. 26; FIG. 3A to FIG. 3F is a cross-sectional view taken along the BB direction of FIG. 27;

[0088] FIG. 4A is a plan view of an exemplary embodiment after disconnecting the second semiconductor layer from different layers;

[0089] FIG. 4B is a cross-sectional view taken along the AA direction of FIG. 28; FIG. 4A is a cross-sectional view taken along the AA direction of FIG. 29;

[0090] FIG. 4B is a cross-sectional view taken along the BB direction of FIG. 29; FIG. 4A is a cross-sectional view taken along the BB direction of FIG. 30;

[0091] FIG. 4B is a plan view of an exemplary embodiment after forming a second bit line;

[0092] FIG. 4B is a cross-sectional view taken along the AA direction of FIG. 31; FIG. 5A is a cross-sectional view taken along the AA direction of FIG. 32;

[0093] FIG. 5A is a cross-sectional view taken along the BB direction of FIG. 32; FIG. 5BCross-sectional view in the middle BB direction;

[0094] FIG. 5C Plan view after disconnecting second bit lines of different layers for an exemplary embodiment;

[0095] FIG. 5A Cross-sectional view in the middle AA direction; FIG. 5B

[0096] Cross-sectional view in the middle AA direction; FIG. 5A FIG. 5C Cross-sectional view in the middle BB direction;

[0097] FIG. 5A Plan view after forming third electrodes of second transistors for an exemplary embodiment;

[0098] FIG. 6A Cross-sectional view in the middle AA direction; FIG. 6B

[0099] Cross-sectional view in the middle AA direction; FIG. 6C FIG. 6A Cross-sectional view in the middle BB direction;

[0100] FIG. 6B Plan view after forming fifth holes for an exemplary embodiment;

[0101] FIG. 6A Cross-sectional view in the middle AA direction; FIG. 6C

[0102] Cross-sectional view in the middle AA direction; FIG. 6A FIG. 6A Cross-sectional view in the middle BB direction;

[0103] FIG. 7A Plan view after forming fourth gate insulating layers and second word lines for an exemplary embodiment;

[0104] FIG. 7B Cross-sectional view in the middle AA direction; FIG. 7C

[0105] Cross-sectional view in the middle AA direction; FIG. 7A FIG. 7B Cross-sectional view in the middle BB direction;

[0106] FIG. 7A Plan view after forming third trenches and second holes for an exemplary embodiment;

[0107] FIG. 7C Cross-sectional view in the middle AA direction; FIG. 7A

[0108] Cross-sectional view in the middle AA direction; FIG. 8A FIG. 8B Cross-sectional view in the middle BB direction; ​​​​​

[0109] FIG. 8C For along FIG. 8A Cross-sectional view in the CC direction;

[0110] FIG. 8B A top view provided for an exemplary embodiment after the formation of the third protective layer;

[0111] FIG. 8A For along FIG. 8C Cross-sectional view along the AA direction;

[0112] FIG. 8A For along FIG. 9A Cross-sectional view in the middle BB direction;

[0113] FIG. 9B For along FIG. 9C Cross-sectional view in the CC direction;

[0114] FIG. 9A A top view provided for an exemplary embodiment, after exposing the third trench;

[0115] FIG. 9B For along FIG. 9A Cross-sectional view along the AA direction;

[0116] FIG. 9C For along FIG. 9A Cross-sectional view in the middle BB direction;

[0117] FIG. 10A For along FIG. 10B Cross-sectional view in the CC direction;

[0118] FIG. 10C A top view provided for an exemplary embodiment after the formation of the first line;

[0119] FIG. 10A For along FIG. 10B Cross-sectional view along the AA direction;

[0120] FIG. 10A For along FIG. 10C Cross-sectional view in the middle BB direction;

[0121] FIG. 10A For along FIG. 11A Cross-sectional view in the CC direction;

[0122] FIG. 11B A top view provided for an exemplary embodiment after the formation of a first gate insulating layer and a first word line;

[0123] FIG. 11C For along FIG. 11A Cross-sectional view along the AA direction;

[0124] FIG. 11B For along FIG. 11Aa cross-sectional view in the BB direction;

[0125] FIG. 11C is a cross-sectional view in the AA direction; FIG. 11A a cross-sectional view in the BB direction;

[0126] FIG. 12A is a plan view after forming the first hole for an exemplary embodiment;

[0127] FIG. 12B is a cross-sectional view in the AA direction; FIG. 12C a cross-sectional view in the BB direction;

[0128] FIG. 12A is a cross-sectional view in the AA direction; FIG. 12B a cross-sectional view in the BB direction;

[0129] FIG. 12A is a cross-sectional view in the AA direction; FIG. 12C a cross-sectional view in the BB direction;

[0130] FIG. 12A is a cross-sectional view in the AA direction; FIG. 13A a cross-sectional view in the BB direction;

[0131] FIG. 13B is a plan view after forming the first semiconductor layer, the second gate insulating layer, and the control electrode for an exemplary embodiment;

[0132] FIG. 13C is a cross-sectional view in the AA direction; FIG. 13A a cross-sectional view in the BB direction;

[0133] FIG. 13B is a cross-sectional view in the AA direction; FIG. 13A a cross-sectional view in the BB direction;

[0134] FIG. 13C is a cross-sectional view in the AA direction; FIG. 13A a cross-sectional view in the BB direction;

[0135] FIG. 14A is a cross-sectional view in the AA direction; FIG. 14B a cross-sectional view in the BB direction,

[0136] FIG. 14C is a cross-sectional view in the AA direction; FIG. 14D a cross-sectional view in the BB direction. DETAILED DESCRIPTION

[0137] The embodiments of the present disclosure will be described in detail below with reference to the drawings. The features of the embodiments of the present disclosure and the embodiments can be combined with each other as long as there is no conflict.

[0138] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall be understood as the common meaning understood by a person with ordinary skill in the art to which the present disclosure belongs.

[0139] Embodiments of the present disclosure are not necessarily limited to the sizes of the components illustrated in the drawings, and the shapes, sizes, and the like of the components in the drawings do not reflect actual ones. In addition, the drawings schematically show ideal examples, and embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0140] In the present disclosure, ordinal numbers such as "first", "second", "third", and the like are provided in order to avoid confusion of components, and do not indicate any order, number, or importance.

[0141] In the present disclosure, in order to facilitate the description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of the description of the present specification and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the disclosure, and can be appropriately replaced according to the situation.

[0142] In the present disclosure, unless explicitly specified and limited otherwise, the terms "mount", "connected", "connection" should be interpreted broadly. For example, it can be a physical connection or a signal connection, it can be a contact connection or an integral connection; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0143] In the present disclosure, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

[0144] In the present disclosure, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the current direction in the operation of the circuit, the functions of the "source electrode" and the "drain electrode" are sometimes exchanged with each other. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" can be exchanged with each other.

[0145] In the present disclosure, "connection" includes a case where components are connected together through an element having some electrical action. The element having some electrical action is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected components. Examples of the element having some electrical action include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0146] In the present disclosure, "parallel" means approximately parallel or almost parallel, such as a state in which two straight lines form an angle of -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular, such as a state in which two straight lines form an angle of 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0147] In the present disclosure, "A and B are of an integral structure" can mean that there is no obvious fault or gap as an obvious boundary interface in a microscopic structure. Generally, a film layer formed by patterning on one film layer is integral. For example, A and B use the same material to form one film layer and are simultaneously formed by the same patterning process.

[0148] In the present disclosure, "the orthographic projection of B is located within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0149] For metal-oxide semiconductor as the channel of a transistor, some semiconductor materials are very sensitive to the surrounding environment, especially hydrogen and oxygen, so when manufacturing semiconductor devices, it is necessary to avoid the influence of dry and wet etching on semiconductor materials as much as possible. In a 3D stacked semiconductor device, the semiconductor layer is located in a hole that penetrates each transistor layer, and the hole sidewall is distributed with a semiconductor layer, there are effective channels located in the transistor layer and parasitic channels located between adjacent transistor layers, and the parasitic MOS corresponding to the parasitic channel affects the power consumption of the device. One way to remove the parasitic MOS is to remove the parasitic channel by etching, but the effective channel is easily affected during the etching process, which affects the performance of the device.

[0150] In the example embodiment of the present disclosure, the parasitic semiconductor layer is reserved, and after the semiconductor layer is deposited on the inner sidewall of the hole, no process step of removing the parasitic channel is performed, and the parasitic channel is not etched, but a control electrode of the parasitic MOS is increased, that is, two gate electrodes are arranged in the semiconductor device, the first gate electrode controls the opening and closing of the effective transistor, and the second gate electrode controls the closing of the parasitic transistor between the effective transistors. When the transistor off voltage (for example, a negative voltage for an n-type transistor) is applied to the second gate electrode, the parasitic transistor is turned off, and when data access (writing or reading) is performed, the on voltage (for example, a positive voltage greater than the on threshold voltage of the n-type transistor) is applied to the first gate electrode to turn on the transistor, without turning on the parasitic transistor (the first gate electrode is far away from the parasitic channel of the parasitic transistor, and cannot control the parasitic transistor); in the non-working state (stand-by state) of the memory cell or transistor, for example, the off state, the off voltage (for example, a negative voltage for an n-type transistor) is applied to the first gate electrode and the second gate electrode, so as to turn off the transistor and the parasitic transistor. The scheme does not remove the parasitic semiconductor layer, there is no influence on the channel of the transistor due to the removal of the parasitic semiconductor layer, and the leakage caused by the parasitic transistor can be avoided, so as to improve the performance of the device.

[0151] FIG. 14A A circuit schematic diagram of a semiconductor device is provided for an example embodiment. FIG. 14B For FIG. 14A A circuit schematic diagram of a memory cell in the semiconductor device is shown. FIG. 14C A plan view of a semiconductor device is provided for an example embodiment, FIG. 14A A cross-sectional view along the AA direction in the FIG. 14D A cross-sectional view along the BB direction in the FIG. 14A A cross-sectional view along the CC direction in the FIG. 15A A cross-sectional view along the DD direction in the FIG. 15B A cross-sectional view along the EE direction in the FIG. 15C A cross-sectional view along the EE direction in the FIG. 15A A cross-sectional view along the EE direction in the FIG. 15B A cross-sectional view along the EE direction in the FIG. 15A A cross-sectional view along the EE direction in the FIG. 15C A cross-sectional view along the EE direction in the

[0152] As FIG. 15A , FIG. 15D , FIG. 15A An example semiconductor device is provided in the present disclosure, which includes a plurality of memory cell arrays vertically stacked on a substrate 1, and the plurality of memory cell arrays can be distributed along a third direction Z. The third direction Z can be perpendicular to the substrate 1.

[0153] The memory cell array can include a plurality of first bit lines 30 (such as FIG. 16AWBL00, WBL01, WBL02 in FIG. 1), a plurality of second bit lines 31 (such as RBL00, RBL01, RBL02 in FIG. 1), a plurality of first word lines 40 (such as WWL00, WWL01 in FIG. 1), a plurality of second word lines 46 (such as RWL00, RWL01 in FIG. 1), and a plurality of memory cells S1. The plurality of memory cells S1 of the memory cell array can be arranged along a first direction X and a second direction Y. The first direction X and the second direction Y can be perpendicular to each other. The first bit lines 30 and the second bit lines 31 can be conductive lines extending along the second direction Y parallel to the substrate 1, the plurality of first bit lines 30 of the same memory cell array can be spaced apart from each other, and the plurality of second bit lines 31 of the same memory cell array can be spaced apart from each other. The plurality of first bit lines 30 can be arranged along the first direction X. The plurality of second bit lines 31 can be arranged along the first direction X. The first bit lines 30 and the second bit lines 31 can be arranged along the first direction X. The first bit lines 30 of different memory cell arrays can be stacked on the substrate 1, and the first bit lines 30 of different layers at the same position can be spaced apart from each other. The second bit lines 31 of different memory cell arrays can be stacked on the substrate 1, and the second bit lines 31 of different layers at the same position can be spaced apart from each other. FIG. 16B WBL00, WBL01, WBL02 in FIG. 1), a plurality of second bit lines 31 (such as RBL00, RBL01, RBL02 in FIG. 1), a plurality of first word lines 40 (such as WWL00, WWL01 in FIG. 1), a plurality of second word lines 46 (such as RWL00, RWL01 in FIG. 1), and a plurality of memory cells S1. The plurality of memory cells S1 of the memory cell array can be arranged along a first direction X and a second direction Y. The first direction X and the second direction Y can be perpendicular to each other. The first bit lines 30 and the second bit lines 31 can be conductive lines extending along the second direction Y parallel to the substrate 1, the plurality of first bit lines 30 of the same memory cell array can be spaced apart from each other, and the plurality of second bit lines 31 of the same memory cell array can be spaced apart from each other. The plurality of first bit lines 30 can be arranged along the first direction X. The plurality of second bit lines 31 can be arranged along the first direction X. The first bit lines 30 and the second bit lines 31 can be arranged along the first direction X. The first bit lines 30 of different memory cell arrays can be stacked on the substrate 1, and the first bit lines 30 of different layers at the same position can be spaced apart from each other. The second bit lines 31 of different memory cell arrays can be stacked on the substrate 1, and the second bit lines 31 of different layers at the same position can be spaced apart from each other. FIG. 16C FIG. 16D WBL00, WBL01, WBL02 in FIG. 1), a plurality of second bit lines 31 (such as RBL00, RBL01, RBL02 in FIG. 1), a plurality of first word lines 40 (such as WWL00, WWL01 in FIG. 1), a plurality of second word lines 46 (such as RWL00, RWL01 in FIG. 1), and a plurality of memory cells S1. The plurality of memory cells S1 of the memory cell array can be arranged along a first direction X and a second direction Y. The first direction X and the second direction Y can be perpendicular to each other. The first bit lines 30 and the second bit lines 31 can be conductive lines extending along the second direction Y parallel to the substrate 1, the plurality of first bit lines 30 of the same memory cell array can be spaced apart from each other, and the plurality of second bit lines 31 of the same memory cell array can be spaced apart from each other. The plurality of first bit lines 30 can be arranged along the first direction X. The plurality of second bit lines 31 can be arranged along the first direction X. The first bit lines 30 and the second bit lines 31 can be arranged along the first direction X. The first bit lines 30 of different memory cell arrays can be stacked on the substrate 1, and the first bit lines 30 of different layers at the same position can be spaced apart from each other. The second bit lines 31 of different memory cell arrays can be stacked on the substrate 1, and the second bit lines 31 of different layers at the same position can be spaced apart from each other.

[0154] In some embodiments, the first bit lines 30 are write bit lines (WBL), the second bit lines 31 are read bit lines (RBL), the first word lines 40 are write word lines (WWL), and the second word lines 46 are read word lines (RWL).

[0155] The first word lines 40 and the second word lines 46 can extend along a third direction Z, and the memory cells at the same position stacked in the vertical direction of the substrate 1 share the first word lines 40 and the second word lines 46.

[0156] The memory cell can be a 2T0C memory cell, and the memory cell can include a first transistor and a second transistor. The first transistor can include a first semiconductor sublayer 231, a first gate electrode 26, a first electrode 51, and a second electrode 52. The first gate electrode 26 can be part of the first word line 40, and the first gate electrodes 26 of the first transistors at the same position of different layers can be part of the same first word line 40. The first electrode 51 can be connected to a third gate electrode 21 of the second transistor, and the second electrode 52 can be connected to the first bit line 30. The second electrode 52 can be part of the first bit line 30.

[0157] ​The second electrode 52 of the first transistor of the memory cell of the same column of the same memory cell array can be connected to the same first bit line 30. That is, the second electrodes 52 of the first transistors of the same column distributed along the second direction Y are connected to form the first bit line 30 extending along the second direction Y.

[0158] The first transistor and the second transistor of the same memory cell can be distributed along a first direction X.

[0159] The first transistor can further include a second gate electrode 28, the second gate electrodes 28 of the first transistors of the same position of the memory cell array of different layers being connected to form a control electrode 45.

[0160] In some embodiments, the second transistor can be a double-gate structure, and can include a third gate electrode 21, a fourth gate electrode 22, a second semiconductor layer 25, a third electrode 61, and a fourth electrode 62, the third gate electrode 21 being connected to the first electrode 51, and the second semiconductor layer 25 being connected to the third electrode 61 and the fourth electrode 62, respectively. The connection end of the first electrode 51 and the third gate electrode 21 serves as a storage node (SN), the fourth gate electrodes 22 of the memory cells of the same position of different layers being connected to form a second word line 46, the third electrode 61 can be connected to a ground end (GND), and the fourth electrode 62 can be connected to a second bit line 31. The fourth electrode 62 of the second transistor of the memory cell of the same column of the same memory cell array can be connected to the same second bit line 31. That is, the fourth electrodes 62 of the second transistors of the same column distributed along the second direction Y are connected to form the second bit line 31 extending along the second direction Y.

[0161] In some embodiments, the second transistor can be a single-gate structure, and can include a third gate electrode 21, a second semiconductor layer 25, a third electrode 61, and a fourth electrode 62, the third gate electrode 21 being connected to the first electrode 51, and the second semiconductor layer 25 being connected to the third electrode 61 and the fourth electrode 62, respectively. The third electrodes 61 of the memory cells of the same position of different layers are connected to form a second word line 46.

[0162] The connection end of the first electrode 51 and the third gate electrode 21 serves as a storage node (SN), the fourth gate electrodes 22 are connected to form a second word line 46, the third electrode 61 can be connected to a ground end (GND), and the fourth electrode 62 can be connected to a second bit line 31. The fourth electrode 62 of the second transistor of the memory cell of the same column of the same memory cell array can be connected to the same second bit line 31. That is, the fourth electrodes 62 of the second transistors of the same column distributed along the second direction Y are connected to form the second bit line 31 extending along the second direction Y.

[0163] In some embodiments, the first transistor can be a write transistor, and the second transistor can be a read transistor.

[0164] A semiconductor device including a plurality of vertically stacked memory cells in the same location is described below as an example.

[0165] As shown in FIG. 16A The semiconductor device can include a plurality of layers of memory cells S1 stacked in a direction perpendicular to a substrate 1.

[0166] Each layer of the memory cells S1 includes a first transistor and a second transistor, which are arranged in a first direction X parallel to the substrate 1.

[0167] A plurality of first transistors are arranged in different layers stacked in a direction perpendicular to the substrate 1, and each first transistor can include a first electrode 51, a second electrode 52, a first semiconductor sublayer 231, and a first gate electrode 26, wherein the first semiconductor sublayer 231 is connected to the first electrode 51 and the second electrode 52 of the first transistor, respectively.

[0168] The second transistor can include a third gate electrode 21, a fourth gate electrode 22, a second semiconductor layer 25, a third electrode 61, and a fourth electrode 62, wherein the third gate electrode 21 is connected to the first electrode 51, and the second semiconductor layer 25 is connected to the third electrode 61 and the fourth electrode 62, respectively.

[0169] A second semiconductor sublayer 232 is arranged between adjacent first semiconductor sublayers 231, and the first semiconductor sublayer 231 and the second semiconductor sublayer 232 are connected to form a first semiconductor layer 23 in an integral structure, wherein the first semiconductor layer 23 extends in a direction perpendicular to the substrate 1, and the first semiconductor sublayer 231 is a channel region of the first transistor, and the second semiconductor sublayer 232 is a parasitic semiconductor layer between adjacent first transistors.

[0170] A first word line 40 extends in a direction perpendicular to the substrate 1 through the different layers, and the first gate electrode 26 of each first transistor is part of the first word line 40.

[0171] A first hole K1 and a second hole K2 are arranged through the different layers, the second hole K2 is connected to the first hole K1, and the first semiconductor layer 23 and a control electrode 45 extend in a direction perpendicular to the substrate 1 through the different layers and are arranged in the first hole K1, wherein the first semiconductor layer 23 surrounds a sidewall of the control electrode 45.

[0172] The first word line 40 is arranged in the second hole and extends along the vertical substrate 1 direction through the different layers, and the distance between the first word line 40 and the first semiconductor sub-layer 231 in the direction parallel to the substrate 1 is less than the distance between the first word line 40 and the second semiconductor sub-layer 232 in the direction parallel to the substrate 1.

[0173] The semiconductor device provided by the embodiment can turn off the parasitic transistor through the control electrode 45, avoid the leakage caused by the parasitic transistor, and avoid affecting the channel region of the transistor, simplify the process, and improve the performance of the device.

[0174] The first gate electrode 26 of the first transistor in the different layers can be part of the first word line 40, that is, the first word line 40 is formed first, and the first gate electrode 26 is not separately manufactured, and after the first word line 40 is manufactured, part of the first word line 40 functions as the first gate electrode 26.

[0175] The control electrode 45 can extend along the vertical substrate 1 direction through the different layers and be located in the region surrounded by the first semiconductor layer of the first transistor in each stack. The control electrode 45 includes a plurality of second gate electrodes 28. That is, the second gate electrode 28 is part of the control electrode 45, the control electrode 45 is formed first, and the second gate electrode 28 is not separately manufactured, and after the control electrode 45 is manufactured, part of the control electrode 45 functions as the second gate electrode 28. The second gate electrode 28 and the second semiconductor sub-layer 232 and the two adjacent first semiconductor sub-layers 231 form a parasitic transistor, and the second gate electrode 28 can control the closing of the second semiconductor sub-layer 232 to disconnect the adjacent two first semiconductor sub-layers 231 in signal.

[0176] In some embodiments, the control electrode 45 is configured to apply a first off voltage to close the parasitic transistor between the adjacent first transistors during the working phase of the transistor connected by the first word line 40, and apply a second off voltage to close the first transistor together with the first word line 40 during the non-working phase of the transistor connected by the first word line 40.

[0177] In some embodiments, the first semiconductor layer 23 can surround the sidewall of the control electrode 45.

[0178] In some embodiments, the first semiconductor layer 23 can extend along the sidewall of the control electrode 45 to form a ring-shaped semiconductor layer extending along a direction perpendicular to the substrate 1. The first semiconductor layer 23 can extend only along a direction perpendicular to the substrate 1 (there can be a region protruding along a horizontal direction during the extension), or the first semiconductor layer 23 can extend mainly along a direction perpendicular to the substrate 1, and there can be a region extending along a horizontal direction (parallel to the substrate 1) at the end.

[0179] In the present disclosure, the surrounding can be understood as partial or complete surrounding. For example, the first semiconductor layer 23 surrounding the control electrode 45 can be partial or complete surrounding of the control electrode 45. In some embodiments, the surrounding can be complete surrounding as a whole, and the cross section of the first semiconductor layer 23 can be a closed ring. The cross section is taken along a direction parallel to the substrate. In some embodiments, the surrounding can be partial surrounding, and the cross section after the surrounding is not closed but presents a ring shape. For example, a ring with an opening can be understood as a U-shaped cross section, and the like, where the cross section is taken along a direction parallel to the substrate.

[0180] The semiconductor device can further include a first gate insulating layer 24 surrounding the sidewall of the first word line 40 and extending along a direction perpendicular to the substrate 1. The first word line 40 is insulated from the first semiconductor layer 23 by the first gate insulating layer 24.

[0181] It can be understood that the first word line 40 and the control electrode 45 are respectively located on both sides of the first semiconductor layer 23 and are connected to the first semiconductor layer 23 through the first gate insulating layer 24, so that the channel region of the effective transistor corresponding to the first semiconductor layer 23 can be controlled at the same time, and the parasitic semiconductor layer between the effective transistors can also be controlled at the same time.

[0182] The semiconductor device can further include a second gate insulating layer 27 surrounding the sidewall of the control electrode 45 and extending along a direction perpendicular to the substrate 1, the second gate insulating layer 27 being arranged between the sidewall of the control electrode 45 and the sidewall of the first semiconductor layer 23, and the control electrode 45 being insulated from the first semiconductor layer 23 by the second gate insulating layer 27.

[0183] In some embodiments, the semiconductor device can further include:

[0184] The insulating layers and the conductive layers are alternately arranged from top to bottom along a direction perpendicular to the substrate 1; the first hole K1 and the second hole K2 penetrate each of the insulating layers and each of the conductive layers;

[0185] The second hole K2 has, from the outside to the inside, the first gate insulating layer 24 surrounding the sidewall of the first word line 40 and the first word line 40.

[0186] The first hole K1 has the first semiconductor layer 23, the second gate insulating layer 27 surrounding the sidewall of the control electrode 45, and the control electrode 45 distributed in turn from outside to inside.

[0187] The first electrode 51 and the second electrode 52 are arranged on the conductive layer.

[0188] The scheme provided by the embodiment can form the word line 40, the first gate insulating layer 24, the control electrode 45, the second gate insulating layer 27, and the semiconductor layer 23 at one time, and simplify the process.

[0189] In some embodiments, the first hole K1 located at the first sub-hole of the insulating layer in the orthographic projection of the substrate 1 can fall within the second sub-hole of the conductive layer in the orthographic projection of the substrate 1, that is, the aperture of the first hole K1 located at the first sub-hole of the insulating layer is smaller than the aperture of the first hole K1 located at the second sub-hole of the conductive layer. The scheme provided by the embodiment can make the distance between the first word line 40 and the first semiconductor sub-layer 231 and the second semiconductor sub-layer 232 different (the first semiconductor sub-layer 231 is located at the second sub-hole, the second semiconductor sub-layer 232 is located at the first sub-hole, and the first semiconductor sub-layer 231 is relatively farther from the second semiconductor sub-layer 232 in the first hole K1, so the first semiconductor sub-layer 231 is relatively closer to the first word line 40 than the second semiconductor sub-layer 232), so that the control of the first word line 40 on the second semiconductor sub-layer 232 is weaker than that on the first semiconductor sub-layer 231, and the first word line 40 is prevented from turning on the parasitic transistor when turning on the first transistor.

[0190] In some embodiments, the second hole K2 located at the third sub-hole of the insulating layer in the orthographic projection of the substrate 1 can fall within the fourth sub-hole of the conductive layer in the orthographic projection of the substrate 1, that is, the aperture of the second hole K2 located at the third sub-hole of the insulating layer is smaller than the aperture of the second hole K2 located at the fourth sub-hole of the conductive layer. The scheme provided by the embodiment can make the distance between the first word line 40 and the first semiconductor sub-layer 231 and the second semiconductor sub-layer 232 different (the first semiconductor sub-layer 231 is located at the region where the conductive layer is located, and the first word line 40 protrudes relatively to the fourth sub-hole at the third sub-hole (located at the conductive layer), so the first word line 40 is relatively close to the first semiconductor sub-layer 231 and relatively far from the second semiconductor sub-layer 232), so that the control of the first word line 40 on the second semiconductor sub-layer 232 is weaker than that on the first semiconductor sub-layer 231, and the first word line 40 is prevented from turning on the parasitic transistor when turning on the first transistor.

[0191] In some embodiments, the second hole K2 is located at a third sub-hole of the insulating layer, and the projection of the third sub-hole of the insulating layer on the substrate 1 can fall within the projection of a fourth sub-hole of the conductive layer on the substrate 1 where the second hole K2 is located, and the first hole K1 is located at a first sub-hole of the insulating layer, and the projection of the first sub-hole of the insulating layer on the substrate 1 can fall within the projection of a second sub-hole of the conductive layer on the substrate 1 where the first hole K1 is located. The scheme provided in this embodiment can further expand the distance between the first word line 40 and the second semiconductor layer 232, reduce the influence of the first word line 40 on the parasitic transistor, and be more conducive to turning off the parasitic transistor.

[0192] In some embodiments, the fourth gate electrode 22 of the second transistor of the memory cell at the same position of the multi-layer is connected to form a second word line 46 extending in a direction perpendicular to the substrate 1.

[0193] In some embodiments, the third gate electrode 21 and the first electrode 51 of the same memory cell are connected to form an integrated structure, that is, the third gate electrode 21 and the first electrode 51 share the same electrode.

[0194] In some embodiments, the first electrode 51 and the second electrode 52 are distributed on the outer sidewall of the first semiconductor sub-layer 231 and are spaced apart in the first direction X, and the first word line 40 is distributed on the outer sidewall of the first semiconductor sub-layer 231 between the first electrode 51 and the second electrode 52.

[0195] In some embodiments, a first groove is provided between adjacent insulating layers, the first groove is a horizontal groove, the first groove is away from the first word line 40, the control electrode 45 and the second electrode 52, the bottom wall of the first groove exposes the first gate insulating layer 24 and the first semiconductor sub-layer 231, the first electrode 51 is distributed on the bottom wall and the sidewall perpendicular to the substrate 1 of the first groove, that is, in the plane parallel to the substrate 1, the cross section of the first electrode 51 is U-shaped, the second semiconductor layer 25 is distributed on the bottom wall and the sidewall perpendicular to the substrate 1 of the first groove, and is also distributed on the adjacent insulating layers constituting the sidewall of the first groove. That is, the second semiconductor layer 25 is provided on the inner wall of the first groove (including the bottom wall and each sidewall). The second semiconductor layer 25 is insulated from the first electrode 51 by the third gate insulating layer 29.

[0196] In some embodiments, the semiconductor device further comprises a second recess extending in the second direction Y and disposed on a side of the first recess away from the first semiconductor layer 23, the second recess being in communication with the plurality of first recesses in the same column, the opening of the second recess facing away from the first electrode 51, the second semiconductor layers 25 of the second transistors in the same column distributed in the second direction Y being connected to form an integrated structure, the integrated structure formed by the second semiconductor layers 25 being further disposed on the side wall and bottom wall of the second recess. The third gate insulating layer 29 is further distributed on the side wall and bottom wall of the second recess.

[0197] In some embodiments, the second bit line 31 is distributed on the bottom wall and side wall of the second recess in which the second semiconductor layer 25 is disposed. That is, the semiconductor device is provided with a second recess extending in the second direction, the inner wall of the second recess being sequentially provided with the second semiconductor layer 25 and the second bit line 31. The inner wall of the first recess is provided with the second semiconductor layer 25.

[0198] In some embodiments, in a plane parallel to the substrate 1, the cross section of the third electrode 61 is located within the U-shaped opening formed by the first electrode 51.

[0199] In some embodiments, the third electrodes 61 of the second transistors of the memory cells in the same position in multiple layers are connected to form an integrated structure extending in a direction perpendicular to the substrate 1. The integrated structure formed by the third electrodes 61 comprises a vertical portion extending in a direction perpendicular to the substrate 1 and a horizontal portion extending from the vertical portion in a horizontal direction, and the horizontal portion is connected to the second semiconductor layer 25 distributed on the bottom wall of the first recess, and to the second semiconductor layer 25 distributed in the region adjacent to the bottom wall of the first recess.

[0200] In some embodiments, the fourth gate electrodes 22 of the second transistors of the memory cells in the same position in multiple layers are connected to form an integrated structure extending in a direction perpendicular to the substrate 1, and the orthographic projection of the fourth gate electrode 22 on the substrate 1 is located within the orthographic projection of the first recess on the substrate 1.

[0201] In some embodiments, the second semiconductor layers 25 of the second transistors in different layers are spaced apart.

[0202] In some embodiments, the semiconductor device can further comprise:

[0203] A third hole K3 penetrating each of the insulating layers and each of the conductive layers; the third hole is divided into a fourth hole K4 and a fifth hole K5 penetrating each of the insulating layers and each of the conductive layers, the arrangement direction of the fourth hole K4 and the fifth hole K5 being the same as the arrangement direction of the first transistors and the second transistors;

[0204] The third hole K3 is distributed with the third gate insulating layer 29 and the second semiconductor layer 25 from outside to inside;

[0205] The fourth hole K4 is distributed with a plurality of third electrodes 61 connected into an integrated structure;

[0206] The fifth hole K5 is sequentially distributed with the fourth gate insulating layer 39 and the fourth gate electrode 22 from inside to outside.

[0207] In some embodiments, the third hole K3 is located at the fifth sub-hole of the insulating layer, and the orthographic projection of the fifth sub-hole of the insulating layer on the substrate 1 falls within the orthographic projection of the sixth sub-hole of the conductive layer on the substrate 1. That is, the aperture of the third hole K3 located at the fifth sub-hole of the insulating layer is smaller than the aperture of the third hole K3 located at the sixth sub-hole of the conductive layer.

[0208] In some embodiments, the fourth hole K4 includes the seventh sub-hole of the insulating layer and the eighth sub-hole of the conductive layer, and the boundary of the seventh sub-hole of the insulating layer on the substrate 1 near one side of the fifth hole K5 overlaps with the boundary of the eighth sub-hole of the conductive layer on the substrate 1 near the same side of the fifth hole K5, and the other boundaries of the orthographic projection of the seventh sub-hole of the insulating layer on the substrate 1 fall within the orthographic projection of the eighth sub-hole of the conductive layer on the substrate 1.

[0209] In some embodiments, the fifth hole K5 includes the ninth sub-hole of the insulating layer and the tenth sub-hole of the conductive layer, and the boundary of the ninth sub-hole of the insulating layer on the substrate 1 near one side of the fourth hole K4 overlaps with the boundary of the tenth sub-hole of the conductive layer on the substrate 1 near the same side of the fourth hole K4, and the other boundaries of the orthographic projection of the ninth sub-hole of the insulating layer on the substrate 1 fall within the orthographic projection of the tenth sub-hole of the conductive layer on the substrate 1.

[0210] In some embodiments, the arrangement direction of the first hole K1 and the second hole K2 can be perpendicular to the arrangement direction of the first electrode 51 and the second electrode 52. The arrangement direction of the first electrode 51 and the second electrode 52 is, for example, the first direction X, and the arrangement direction of the first hole K1 and the second hole K2 is, for example, the second direction Y. That is, in the plane parallel to the substrate 1, the first hole K1 and the second hole K2 can be arranged along the second direction Y, and the arrangement order of the first hole K1 and the second hole K2 along the second direction Y is not limited to FIG. 16B As shown in FIG. 1, the positions of the first hole K1 and the second hole K2 can be interchanged.

[0211] In some embodiments, the second hole K2 and the first hole K1 can be located between the first electrode 51 and the second electrode 52.

[0212] In some embodiments, the size of the second sub-hole along the arrangement direction of the first electrode 51 and the second electrode 52 can be the same as the size of the fourth sub-hole along the arrangement direction of the first electrode 51 and the second electrode 52. That is, the size of the second sub-hole along the first direction X can be the same as the size of the fourth sub-hole along the first direction X.

[0213] In some embodiments, the sidewall of the first semiconductor sub-layer 231 can be connected with the sidewall of the first gate insulating layer 24, and the sidewall of the second semiconductor sub-layer 232 can be connected with the sidewall of the first gate insulating layer 24.

[0214] In some embodiments, the first electrode 51 and the second electrode 52 are arranged on the outer sidewall of the first semiconductor sub-layer 231 and are arranged at intervals along the first direction X parallel to the substrate 1, and the word line 40 is arranged on the region between the first electrode 51 and the second electrode 52 on the outer sidewall of the first semiconductor sub-layer 231.

[0215] In some embodiments, the second electrode 52 of the first transistor can be a part of the first bit line 30 to which the second electrode 52 is connected. For example, the first bit line 30 is a straight line (as shown in the figure), and the sidewall of the straight line is connected with the first semiconductor layer 23, or the first bit line 30 has a branch with an integrated design, and the branch is connected with the first semiconductor layer 23, wherein the extension direction of the branch is crossed with the extension direction of the first bit line 30, such as approximately perpendicular. FIG. 16A

[0216] The branch can be a plurality of branches on one sidewall of the first bit line 30, or a plurality of branches on two sidewalls at the same time, and each branch corresponds to form a transistor or a memory cell. FIG. 16C In some embodiments, the first bit line 30 is a straight line, and the sidewall of the straight line is connected with the first semiconductor layer 23 on one side of the first bit line 30. In this embodiment, the transistors of two adjacent columns are connected to different first bit lines 30, and the first bit lines 30 connected by the transistors of the two adjacent columns are separated by an insulating film layer. However, the embodiments of the present disclosure are not limited thereto, and in some embodiments, the first bit line 30 can be connected with the first semiconductor layer 23 on both sides of the first bit line 30, that is, one first bit line 30 can be connected with the first semiconductor layer 23 of the first transistors of two adjacent columns.

[0217] FIG. 16A ​The semiconductor device structure shown is only an example, and the embodiments of the present disclosure are not limited thereto. For structures in which a semiconductor layer extending through multiple layers in a direction perpendicular to the substrate 1 results in parasitic transistors between adjacent first transistors, the parasitic transistors can be turned off by setting a second gate electrode for controlling the parasitic transistors. The embodiments of the present disclosure do not limit the position and shape of the second gate electrode, and the second gate electrode of the parasitic transistor in different layers can be manufactured separately.

[0218] FIG. 16D A circuit schematic diagram of a semiconductor device according to another example embodiment. FIG. 16A A circuit schematic diagram of a semiconductor device according to another example embodiment. FIG. 17A A circuit schematic diagram of a semiconductor device according to another example embodiment. FIG. 17B A circuit schematic diagram of a semiconductor device according to another example embodiment. FIG. 17C A circuit schematic diagram of a semiconductor device according to another example embodiment. FIG. 17A A cross-sectional view along the AA direction in the above-described example embodiment.

[0219] FIG. 17D A cross-sectional view along the BB direction in the above-described example embodiment. FIG. 17A A cross-sectional view along the BB direction in the above-described example embodiment. FIG. 17D A cross-sectional view along the CC direction in the above-described example embodiment. FIG. 17A A cross-sectional view along the CC direction in the above-described example embodiment.

[0220] FIG. 18A A cross-sectional view along the DD direction in the above-described example embodiment. FIG. 18B A cross-sectional view along the DD direction in the above-described example embodiment. FIG. 18C A cross-sectional view along the EE direction in the above-described example embodiment. FIG. 18A A cross-sectional view along the EE direction in the above-described example embodiment. FIG. 18D FIG. 18A FIG. 18D As shown in the above-described example embodiment, the second transistor is a single-gate structure, i.e., the second transistor includes a third gate electrode 21, a third electrode 61, a fourth electrode 62, a third gate insulating layer 29, and a second semiconductor layer 25. The position and shape of the third gate electrode 21, the third electrode 61, the fourth electrode 62, the third gate insulating layer 29, and the second semiconductor layer 25 can refer to the previous embodiment, and will not be described again. The second transistor does not include a fourth gate electrode 22 and a fourth gate insulating layer 39, and the position of the fourth gate electrode 22 and the fourth gate insulating layer 39 can be filled with an insulating film layer. The structure of the first transistor can refer to the previous embodiment, and will not be described again. In the above-described example embodiment, the third electrode 61 of the second transistor at the same position is connected to form a second word line 46.

[0221] ​​The technical solution of the present embodiment is further illustrated by the manufacturing process of the semiconductor device of the present embodiment. The "patterning process" in the present embodiment includes deposition of a film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist, etc., which are mature manufacturing processes in the related art. The "lithography process" in the present embodiment includes coating of a film layer, mask exposure, and development, which are mature manufacturing processes in the related art. Deposition can use known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can use known coating processes, and etching can use known methods, which are not specifically limited herein. In the description of the present embodiment, it should be understood that "film" refers to a thin film of a certain material made on a substrate by deposition or coating process. If the "film" does not need patterning process or lithography process during the entire manufacturing process, the "film" can also be referred to as "layer". If the "film" still needs patterning process or lithography process during the entire manufacturing process, it is referred to as "film" before the patterning process and "layer" after the patterning process. The "layer" after the patterning process or lithography process contains at least one "pattern".

[0222] In some embodiments, when the second transistor is a double-gate structure, the manufacturing process of the semiconductor device can include:

[0223] 101) providing a substrate 1, depositing a conductive layer film and a first insulating film alternately and sequentially on the substrate 1 to form a stack structure, and depositing a hard mask film on the formed stack structure to form a hard mask layer 9, as shown in FIG. 18A and FIG. 19A , wherein FIG. 19B is a top view of the stack structure after formation provided in an exemplary embodiment, FIG. 19C is a cross-sectional view along the AA direction in FIG. 19A . As shown in FIG. 19D , the stack structure can include a stack of conductive layers 11 and first insulating layers 10 arranged alternately.

[0224] In some embodiments, the substrate 1 can be a semiconductor substrate having one or more layers, structures or regions formed thereon. The substrate 1 can be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material.

[0225] In some embodiments, the first insulating film and the conductive layer film can be deposited by a chemical vapor deposition method.

[0226] In some embodiments, the first insulating film can be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K < 3.9, including but not limited to silicon oxide such as silicon dioxide (SiO2), etc.

[0227] In some embodiments, the conductive layer film can be, for example, a conductive material as follows:

[0228] For example, it contains tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt and other metals; it can be a metal alloy containing the aforementioned metals;

[0229] Alternatively, it can be a conductive metal oxide, metal nitride, metal silicide, metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), conductive metal oxide materials such as indium oxide (InO); For example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and other conductive metal nitride materials;

[0230] Alternatively, it can be a conductive polycrystalline silicon, silicon, germanium, silicon germanium, etc. after doping.

[0231] In some embodiments, the hard mask layer 9 includes but is not limited to at least one of the following: carbon, polycrystalline silicon, silicon oxide, etc.

[0232] FIG. 19A The stack structure shown in the middle includes three layers of first insulating layer 10 and three layers of conductive layer 11, which is only an example, and in other embodiments, the stack structure can include more or less layers of first insulating layer 10 and conductive layer 11 arranged alternately.

[0233] 102) Etching the stack structure to form a first trench T1;

[0234] The etching the stack structure to form a first trench T1 can include:

[0235] Etching the plurality of stack structures to form a plurality of first trenches T1 penetrating the plurality of stack structures; The plurality of first trenches T1 extend along a first direction X, and the first transistor region 100 and the second transistor region 200 are included between adjacent first trenches T1 along the first direction X. The first bit line region 300 is included between the first transistor regions 100 adjacent along the first direction X. The conductive layer 11 forms a predetermined pattern, and the predetermined pattern of the conductive layer 11 can include a plurality of first sub-parts and a second sub-part connecting the first sub-parts. The first sub-part can extend along the first direction X, and the second sub-part can extend along the second direction Y. Referring to FIG. 19E The predetermined pattern of the hard mask layer 9 is shown in the figure, and the predetermined pattern of the remaining film layer is consistent with the predetermined pattern of the hard mask layer 9.

[0236] Depositing a second insulating film and grinding it to form a second insulating layer 13 filling the first trench T1; The second insulating layer 13 can be flush with the hard mask layer 9. As FIG. 19A 、 FIG. 20A and FIG. 20B As shown in FIG. 20C is a top view after forming the first trench T1, FIG. 20A is a cross-sectional view alongFIG. 20D a cross-sectional view along the AA direction, FIG. 20A is along FIG. 20E a cross-sectional view along the BB direction. The first direction X and the second direction Y can intersect. In some embodiments, the first direction X and the second direction Y can be perpendicular.

[0237] In some embodiments, the second insulating film can be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc.

[0238] 103) forming a second trench T2 and a third hole K3;

[0239] The forming of the second trench T2 and the third hole K3 can include:

[0240] dry etching the stack structure between the second transistor regions 200 adjacent along the first direction X to form a second trench T2 penetrating through the stack structure, and a third hole K3 penetrating through the stack structure formed at the second transistor region 200. The second trench T2 extends along the second direction Y. The third hole K3 includes a fifth sub-hole at the first insulating layer 10 and a sixth sub-hole at the conductive layer 11, and at this time the aperture of the fifth sub-hole and the sixth sub-hole is consistent; the second trench T2 includes a first sub-trench at the first insulating layer 10 and a second sub-trench at the conductive layer 11, and at this time the width of the first sub-trench along the first direction X is consistent with the width of the second sub-trench along the first direction X;

[0241] lateral etching the conductive layer 11 along the first direction X and the second direction Y within the third hole K3 to expand the aperture of the sixth sub-hole of the third hole K3 at the conductive layer 11, and lateral etching the conductive layer 11 along the first direction X within the second trench T2 to expand the width of the second sub-trench of the second trench T2 at the conductive layer 11 along the first direction X, and making the third hole K3 and the second trench T2 communicate, as shown in FIG. 20A 、 FIG. 20F and FIG. 20A the top view after forming the second trench T2 and the third hole K3, ​ is a cross-sectional view along the AA direction, ​ is along ​ a cross-sectional view along the BB direction. The first direction X and the second direction Y can intersect. In some embodiments, the first direction X and the second direction Y can be perpendicular. ​ is along ​ a cross-sectional view along the BB direction. The first direction X and the second direction Y can intersect. In some embodiments, the first direction X and the second direction Y can be perpendicular.

[0242] At this time, the third hole K3 forms two types of holes with different sizes, along the second direction Y, the aperture of the fifth sub-hole of the first insulating layer 10 where the third hole K3 is located is smaller than the aperture of the sixth sub-hole of the conductive layer 11 where the third hole K3 is located, that is, the fifth sub-hole of the first insulating layer 10 where the third hole K3 is located falls within the orthographic projection of the sixth sub-hole of the conductive layer 11 on the substrate 1. Along the side of the first direction X close to the second trench T2, the boundary of the orthographic projection of the fifth sub-hole on the substrate 1 overlaps with the boundary of the orthographic projection of the sixth sub-hole on the substrate 1 (the boundary of the fifth sub-hole is part of the boundary of the sixth sub-hole), and along the side of the first direction X away from the second trench T2, the orthographic projection of the fifth sub-hole on the substrate 1 falls within the orthographic projection of the sixth sub-hole of the conductive layer 11 on the substrate 1. At this time, the third hole K3 includes the first longitudinal hole K30 which penetrates through the stack structure along the direction perpendicular to the substrate 1 and the first lateral recess K31 which is located in each conductive layer 11. The second trench T2 forms two types of trenches with different sizes, the width of the first sub-trench of the first insulating layer 10 where the second trench T2 is located along the first direction X is smaller than the width of the second sub-trench of the conductive layer 11 along the first direction X, the orthographic projection of the first sub-trench of the first insulating layer 10 where the second trench T2 is located falls within the orthographic projection of the second sub-trench of the conductive layer 11, and the third hole K3 and the second trench T2 are in communication. At this time, the second trench T2 includes the first longitudinal trench T20 which penetrates through the stack structure along the direction perpendicular to the substrate 1 and the first lateral trench T21 and the second lateral trench T22 which are located in each conductive layer 11, and the second bit line 31 is subsequently formed in the first lateral trench T21 and the second lateral trench T22, respectively, and the second transistors in the same layer and in the same column are connected to the same second bit line 31, therefore, the first lateral trench T21 and the second lateral trench T22 extend to the area where the second transistors in the same layer and in the same column are located along the second direction Y. The side wall of the sixth sub-hole has three sides exposed to the conductive layer 11, that is, when the conductive layer 11 is etched laterally, the conductive layer 11 is not etched completely, and part of the conductive layer 11 is still retained. ​ In the area where the third hole K3 is located, the rectangle on the inside is the fifth sub-hole, and the rectangle on the outside is the sixth sub-hole. In the area where the second trench T2 is located, the long strip which penetrates through the second direction Y on the inside is the first sub-trench, and the long strip which penetrates through the second direction Y on the outside is the second sub-trench.

[0243] 104) forming the third gate insulating layer 29 and the second semiconductor layer 25 of the second transistor, and forming the first protective layer 8;

[0244] The third gate insulating layer 29 and the second semiconductor layer 25 forming the second transistor, and the first protective layer 8 can include: sequentially depositing a third gate insulating thin film, a second semiconductor thin film and a first protective layer thin film on the substrate 1 on which the foregoing structure is formed, to form the third gate insulating layer 29, the second semiconductor layer 25 and the first protective layer 8, the first protective layer 8 filling the third hole K3 and the second trench T2, as shown in ​ 、 ​ and ​ wherein, ​ is a plan view after forming the third gate insulating layer 29, the second semiconductor layer 25 and the first protective layer 8, ​ is a sectional view along the AA direction in ​ , and ​ is a sectional view along the BB direction in ​ . The third gate insulating layer 29 covers the side wall and the bottom wall of the third hole K3, and the side wall and the bottom wall of the second trench T2.

[0245] In some embodiments, the third gate insulating thin film can include one or more layers of High-K dielectric material, such as dielectric material with a dielectric constant K≥3.9. In some embodiments, one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. can be included. Exemplary, such as, but not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc. High-K material. The subsequent second gate insulating thin film, the first gate insulating thin film and the third gate insulating thin film are similar and will not be repeated.

[0246] In exemplary embodiments of the present disclosure, the material of the second semiconductor layer 25 can be silicon or polycrystalline silicon material with a band gap less than 1.65 eV, or can be a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.

[0247] For example, the material of the metal oxide semiconductor layer or channel can include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide can also include compounds containing other elements, such as N, Si, etc.; and can also include other small amounts of doped elements.

[0248] In some embodiments, the material of the metal oxide semiconductor layer or channel can include one or more of indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and the like, as long as the leakage current of the transistor meets the requirements, and the specific material can be adjusted according to the actual situation.

[0249] The band gap of these materials is wide, and the leakage current is low. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A. Thus, the working performance of the dynamic memory can be improved.

[0250] The material of the above-mentioned metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

[0251] The material of the first semiconductor layer 23 is similar to that of the second semiconductor layer 25, and will not be described again.

[0252] In some embodiments, the first protective layer film can be an insulating material, including but not limited to SiN and the like.

[0253] 105) disconnecting the second semiconductor layer 25 of different layers;

[0254] The disconnected second semiconductor layer 25 of different layers can include: dry etching from the top layer to the bottom layer to remove the second semiconductor layer 25 and the first protective layer 8 in the first longitudinal hole K30 and the first longitudinal trench T20, so that the second semiconductor layer 25 is disconnected to form a plurality of parts, each part serving as a semiconductor layer of a second transistor, so that the parasitic semiconductor layer between the second transistors can be removed, and the leakage is reduced.

[0255] Depositing a second protective layer film to form a second protective layer 7, such as ​ 、 ​ and ​As shown, where, ​ This is a top view after the second semiconductor layer 25, which is separated from the other layers. ​ For along ​ Cross-sectional view along the AA direction. ​ For along ​ Cross-sectional view along the BB direction. The second protective layer 7 fills the first longitudinal hole K30 and the first longitudinal groove T20.

[0256] In some embodiments, the second protective layer film may be an insulating material, including but not limited to SiN.

[0257] 106) Formation of the second position line 31;

[0258] The formation of the second bit line 31 may include: dry etching from the top layer to the bottom layer to remove the second protective layer 7 in the first longitudinal trench T20, and then wet etching with etching solution in the first longitudinal trench T20 to remove part of the first protective layer 8; that is, lateral etching to remove part of the first protective layer 8 in the first lateral trench T21 and the second lateral trench T22.

[0259] A first conductive thin film is deposited on the substrate 1 forming the aforementioned structure to form a second bit line 31. The second bit line 31 fills the first longitudinal trench T20, the first lateral trench T21, and the second lateral trench T22, as shown below. ​ , ​ and ​ As shown, where, ​ To form the top view after the second position line 31, ​ For along ​ Cross-sectional view along the AA direction. ​ For along ​ Cross-sectional view in the BB direction.

[0260] In some embodiments, the first conductive film includes, but is not limited to, at least one or a combination of the following:

[0261] Metals or alloys, such as those containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc., or metal alloys containing the aforementioned metals;

[0262] Alternatively, it can be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as tin-doped indium oxide (ITO), indium-doped zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), ruthenium oxide (RuOx) and other conductive metal oxide materials; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials.

[0263] The materials of the second, third and fourth conductive films are similar to the first conductive film, and will not be described again.

[0264] 107) disconnecting the second bit lines 31 in different layers;

[0265] The disconnecting the second bit lines 31 in different layers can include: dry etching the second bit lines 31 from the top layer to the bottom layer, removing the second bit lines 31 in the first longitudinal trench T20, forming a plurality of second bit lines 31 distributed in different layers, so that the second bit lines 31 in different layers are disconnected, and the second bit lines 31 in the same layer can be disconnected. The two adjacent second bit lines 31 are located in the first transverse trench T21 and the second transverse trench T22, respectively.

[0266] A third insulating film is deposited on the substrate 1 with the above structure to form a third insulating layer 14, as shown in ​ 、 ​ and ​ , wherein, ​ is a top view after disconnecting the second bit lines 31 in different layers, ​ is a cross-sectional view along the AA direction in ​ , and ​ is a cross-sectional view along the BB direction in ​ . The third insulating layer 14 fills the first longitudinal trench T20. The second bit lines 31 in the same position in different layers are separated by the first insulating layer 10, and the second bit lines 31 in the same layer are separated by the third insulating layer 14.

[0267] In some embodiments, the third insulating film can be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2) and the like.

[0268] 108) forming a third electrode 61 of the second transistor;

[0269] The forming a third electrode 61 of the second transistor can include: removing part of the second protective layer 7 from the top layer to the bottom layer in the third hole K3 by dry etching to form a fourth hole K4, the fourth hole K4 is located at one end of the third trench T2 away from the third hole K3, and the fourth hole K4 is located at the three side walls of the seventh sub-hole of the first insulating layer 10 to expose the third gate insulating layer 29, and one side wall exposes the second protective layer 7;

[0270] Removing part of the first protective layer 8 located in the sixth sub-hole by wet horizontal etching through the fourth hole K4 to expose part of the second semiconductor layer 25 located in the sixth sub-hole, so that the fourth hole K4 is located at the three side walls of the eighth sub-hole of the conductive layer 11 to expose the second semiconductor layer 25, and the other side wall exposes the first protective layer 8 and the second protective layer 7;

[0271] A second conductive film is deposited to fill the fourth hole K4, forming a third electrode 61, as shown in ​ 、 ​ and ​ , wherein ​ is a top view after the third electrode 61 of the second transistor is formed, ​ is a cross-sectional view along the AA direction in ​ , and ​ is a cross-sectional view along the BB direction in ​ . The third electrodes 61 of the second transistors at the same positions of different layers can be connected to form an integrated structure, and the third electrodes 61 can be grounded subsequently. In some embodiments, the third electrodes 61 are source electrodes of the second transistors.

[0272] 109) forming a fifth hole K5;

[0273] The forming of the fifth hole K5 can include: etching and removing the second protective layer 7 from the top layer to the bottom layer in the third hole K3 by dry etching to form the fifth hole K5, the fifth hole K5 being located at one end of the third hole K3 close to the second trench T2, and the fifth hole K5 being located at the three side walls of the ninth sub-hole of the first insulating layer 10 exposing the third gate insulating layer 29, and one side wall exposing the third electrode 61;

[0274] The first protective layer 8 located at the sixth sub-hole is removed by wet horizontal etching through the fifth hole K5, exposing the second semiconductor layer 25 located at the sixth sub-hole, so that the fifth hole K5 is located at the side wall of the tenth sub-hole of the conductive layer 11 exposing the second semiconductor layer 25, the second bit line 31 and the third electrode 61, as shown in ​ 、 ​ and ​ , wherein ​ is a top view after the fifth hole K5 is formed, ​ is a cross-sectional view along the AA direction in ​ , and ​ is a cross-sectional view along the BB direction in ​ .

[0275] 110) forming a fourth gate insulating layer 39 and a second word line 46;

[0276] The forming of the fourth gate insulating layer 39 and the second word line 46 can include: sequentially depositing a fourth gate insulating film and a third conductive film filling the fifth hole K5 on the substrate 1 with the foregoing structure to form the fourth gate insulating layer 39 and the second word line 46, as shown in ​ 、 ​ and ​ , wherein ​ is a top view after the fourth gate insulating layer 39 and the second word line 46 are formed,​ for along ​ the AA direction, ​ for along ​ the BB direction. The second word line 46 simultaneously serves as a gate electrode of the plurality of second transistors, i.e., a fourth gate electrode 22, and the fourth gate electrodes 22 of the plurality of second transistors are connected to form the second word line 46.

[0277] 111) forming a third trench T3 and a second hole K2;

[0278] The forming of the third trench T3 and the second hole K2 can include dry etching the stack structure, forming a third trench T3 through the stack structure in the bit line area 300, and forming a second hole K2 through the stack structure in the first transistor area 100, wherein the second hole K2 includes a third sub-hole in the first insulating layer 10 and a fourth sub-hole in the conductive layer 11, and at this time the aperture of the third sub-hole and the fourth sub-hole is consistent; the third trench T3 includes a third sub-trench in the first insulating layer 10 and a fourth sub-trench in the conductive layer 11, and at this time the width of the third sub-trench along the first direction X is consistent with the width of the fourth sub-trench along the first direction X;

[0279] lateral etching the conductive layer 11 to expand the aperture of the fourth sub-hole of the second hole K2 in the conductive layer 11, and expand the width of the fourth sub-trench of the third trench T3 along the first direction X in the conductive layer 11, as shown in ​ 、 ​ 、 ​ and ​ ​ is a top view after forming the third trench T3 and the second hole K2, ​ for along ​ the AA direction, ​ for along ​ the BB direction, ​ for along ​ ​A cross-sectional view along the CC direction. At this point, the second hole K2 forms multiple holes of different sizes. The diameter of the third sub-hole of the second hole K2 located in the first insulating layer 10 is smaller than the diameter of the fourth sub-hole located in the conductive layer 11. The orthographic projection of the third sub-hole of the second hole K2 located in the first insulating layer 10 onto the substrate 1 falls within the orthographic projection of the fourth sub-hole located in the conductive layer 11 onto the substrate 1. The third trench T3 forms two types of trenches of different sizes. The width of the third sub-trench of the third trench T3 located in the first insulating layer 10 along the first direction X is smaller than the width of the fourth sub-trench located in the conductive layer 11 along the first direction X. The orthographic projection of the third sub-trench of the third trench T3 located in the first insulating layer 10 onto the substrate 1 falls within the orthographic projection of the fourth sub-trench located in the conductive layer 11, and the second hole K2 and the third trench T3 are connected. At this time, in addition to the second longitudinal trench T30 that runs through the stacked structure perpendicular to the substrate 1, the third trench T3 also includes two lateral trenches: the third lateral trench T31 ​​and the fourth lateral trench T32. Subsequently, the first line 30 is formed in the third lateral trench T31 ​​and the fourth lateral trench T32 respectively. The first transistors in the same layer and column are connected to the same first line 30. Therefore, the third trench T3 extends along the second direction Y to the area where the first transistors in the same layer and column are located.

[0280] 112) Formation of a third protective layer 6;

[0281] The formation of the third protective layer 6 may include: depositing a third protective layer film on the substrate 1 on which the aforementioned structure is formed, thereby forming the third protective layer 6, wherein the third protective layer 6 fills the second hole K2 and the third trench T3, as shown below. ​ , ​ , ​ and 15D As shown, where, ​ To form a top view after the third protective layer 6 is created, ​ For along ​ Cross-sectional view along the AA direction. ​ For along ​ Cross-sectional view in the BB direction. ​ For along ​ Cross-sectional view in the CC direction.

[0282] In some embodiments, the third protective layer film is an insulating material with an etching selectivity ratio to the first insulating film, such as SiN.

[0283] 113) Expose the third trench T3;

[0284] Exposing the third trench T3 may include: etching away the third protective layer 6 of the third trench T3, exposing the third trench T3, that is, the third protective layer 6 in the third trench T3 is completely etched away, so that the first bit line 30 can be formed in the third trench T3 subsequently.​ 、 ​ 、 ​ and ​ wherein, ​ is a top view after exposing the third trench T3, ​ is a cross-sectional view along the AA direction in ​ FIG. 16C is a cross-sectional view along the BB direction in FIG. 16A FIG. 16D is a cross-sectional view along the CC direction in FIG. 16A

[0285] In some embodiments, the third protective layer 6 in the second longitudinal trench T30 can be removed by dry etching first, and then the third protective layer 6 in the third and fourth lateral trenches T31 and T32 can be removed by wet etching.

[0286] 114) forming the first bit line 30;

[0287] The forming of the first bit line 30 can include: depositing a fourth conductive thin film on the substrate 1 with the above structure; dry etching from the top layer to the bottom layer to remove the fourth conductive thin film in the second longitudinal trench T30 to form the first bit line 30; the removing of the fourth conductive thin film in the second longitudinal trench T30 can disconnect the first bit lines 30 in different layers, and can disconnect the first bit lines 30 in the same layer and adjacent to each other. The two first bit lines 30 in the same layer and adjacent to each other are located in the third and fourth lateral trenches T31 and T32 respectively.

[0288] depositing a fourth insulating thin film on the substrate 1 with the above structure to form a fourth insulating layer 15, which fills the second longitudinal trench T30, as shown in FIG. 17A 、 FIG. 17B 、 FIG. 17C and FIG. 17D wherein, FIG. 17A is a top view after forming the first bit line 30, FIG. 17B is a cross-sectional view along the AA direction in FIG. 17A FIG. 17C is a cross-sectional view along the BB direction in FIG. 17A FIG. 17D is a cross-sectional view along the CC direction in FIG. 17A

[0289] The first bit lines 30 in the same position and in different layers are spaced by the first insulating layer 10, and the first bit lines 30 in the same layer and adjacent to each other are spaced by the fourth insulating layer 15.

[0290] In some embodiments, the fourth insulating thin film can be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2) and the like.

[0291] ​​​​​​115) Forming a first gate insulating layer 24 and a first word line 40;

[0292] The formation of the first gate insulating layer 24 and the first word line 40 may include: sequentially depositing a first gate insulating film and a first gate electrode film within the second hole K2 to form the first gate insulating layer 24 and the first word line 40; the first word line 40 filling the second hole K2, such as... FIG. 18A , FIG. 18B , FIG. 18C and 18D As shown, where, FIG. 18A A top view after the formation of the first gate insulating layer 24 and the first word line 40. FIG. 18B For along FIG. 18A Cross-sectional view along the AA direction. FIG. 18C For along FIG. 18A Cross-sectional view in the BB direction. FIG. 18D For along FIG. 18A Cross-sectional view along the CC direction. The first gate electrode 26 of the first transistor at the same location on different layers is part of the first word line 40. The first gate insulating layer 24 covers the bottom and sidewalls of the second hole K2.

[0293] In some embodiments, the first gate electrode thin film may be one or more of the following different types of materials:

[0294] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal alloy containing these metals.

[0295] Alternatively, it can be conductive metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and aluminum-doped zinc oxide (AZO); or conductive metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0296] Alternatively, it could be polycrystalline silicon, silicon, germanium, silicon-germanium, etc., which become conductive after doping.

[0297] 116) Form the first hole K1;

[0298] The formation of the first hole K1 may include: dry etching the stacked structure to form a first hole K1 penetrating the plurality of stacked structures in the first transistor region 100, wherein the first hole K1 includes a first sub-hole located in the first insulating layer 10 and a second sub-hole located in the conductive layer 11, and the apertures of the first sub-hole and the second sub-hole are the same; the first hole K1 and the second hole K2 are connected.

[0299] Laterally etch the conductive layer 11 to enlarge the aperture of the second sub-hole of the first hole K1 located in the conductive layer 11, such as... FIG. 19A , FIG. 19B , FIG. 19C , FIG. 19D and FIG. 19E As shown, where, FIG. 19A To form a top view after the first hole K1, FIG. 19B For along FIG. 19A Cross-sectional view along the AA direction. FIG. 19C For along FIG. 19A Cross-sectional view in the BB direction. FIG. 19D For along FIG. 19A Cross-sectional view in the CC direction. FIG. 19E For along FIG. 19A A cross-sectional view along the DD direction. The DD direction is parallel to the AA direction. At this time, the first hole K1 forms multiple holes of two different sizes. The diameter of the first sub-hole of the first hole K1 located in the first insulating layer 10 is smaller than the diameter of the second sub-hole located in the conductive layer 11. That is, the orthogonal projection of the first sub-hole of the first hole K1 located in the first insulating layer 10 onto the substrate 1 falls within the orthogonal projection of the second sub-hole located in the conductive layer 11 onto the substrate 1. In this step, the remaining conductive layer 11 is the first electrode 51 of the first transistor. The first electrode 51, as the sidewall of the first lateral groove K31, is disposed on the outer sidewall of the third gate insulating layer 29 (the sidewall opposite to the third hole K3).

[0300] 117) Forming a first semiconductor layer 23, a second gate insulating layer 27, and a control electrode 45;

[0301] The formation of the first semiconductor layer 23, the second gate insulating layer 27, and the control electrode 45 may include: sequentially depositing a semiconductor thin film, a second gate insulating film, and a second gate electrode thin film within the first hole K1 to form the first semiconductor layer 23, the second gate insulating layer 27, and the control electrode 45, wherein the control electrode 45 fills the first hole K1. FIG. 20A , FIG. 20B , FIG. 20C , FIG. 20D , FIG. 20E and FIG. 20F As shown, where, FIG. 20A This is a top view after the formation of the first semiconductor layer 23, the second gate insulating layer 27, and the control electrode 45. FIG. 20B For along FIG. 20A Cross-sectional view along the AA direction. FIG. 20C For along FIG. 20A Cross-sectional view in the BB direction. FIG. 20D For along FIG. 20A Cross-sectional view in the CC direction. FIG. 20E For alongFIG. 20A a cross-sectional view in a DD direction, FIG. 20F is along FIG. 20A a cross-sectional view in an EE direction. The EE direction is perpendicular to the AA direction.

[0302] In some embodiments, the second gate electrode film can be one or more of the following different types of materials:

[0303] For example, containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc. metal; can be containing the metal alloy of the aforementioned metals;

[0304] Or, can be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc. such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), etc. metal oxide material with high conductivity; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc. metal nitride material;

[0305] Or, can be doped polycrystalline silicon, silicon, germanium, silicon germanium, etc. after conducting.

[0306] In another exemplary embodiment, the manufacturing process of the semiconductor device can include:

[0307] 201)~208), synchronizing steps 101)~108); forming a structure as shown in FIGS. 11A-11C The third electrode 61 formed in this step also serves as a second word line;

[0308] 209)~215), synchronizing steps 111)~117), forming a structure as shown in FIGS. 3A-3F In this embodiment, steps 109)~110) are not performed, and the fourth gate insulating layer 39 and the fourth gate electrode 22 are not generated.

[0309] The embodiments of the present disclosure also provide an electronic device comprising the semiconductor device of the foregoing embodiments, or a semiconductor device manufactured according to the semiconductor device manufacturing method of any one of the foregoing embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, etc. The storage device can include a memory in a computer, etc., which is not limited here.

[0310] Although the present application has been described with reference to the above embodiments, the contents described are merely employed embodiments for facilitating the understanding of the present application, and are not intended to limit the present application. Any modification and change in the form and details can be made by any person skilled in the art without departing from the spirit and scope of the present application, and the patent protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, characterized in that, Includes multiple layers of memory cells stacked in a direction perpendicular to the substrate, and a first word line, wherein, Each layer of the memory cell includes: a first transistor and a second transistor; the second transistor and the first transistor are sequentially distributed along a first direction parallel to the substrate; The first transistor includes a first semiconductor sublayer, a first electrode, and a second electrode; the first semiconductor sublayer is connected to the first electrode and the second electrode, respectively. The second transistor includes a third gate electrode connected to the first electrode; A second semiconductor sublayer is disposed between adjacent first semiconductor sublayers. The first semiconductor sublayer and the second semiconductor sublayer are connected to form an integral structure called the first semiconductor layer. The first semiconductor layer extends in a direction perpendicular to the substrate. A first hole and a second hole penetrating different layers are provided, the second hole is connected to the first hole, and a first semiconductor layer and a control electrode are disposed in the first hole, which extend along the direction perpendicular to the substrate and penetrate different layers, wherein the first semiconductor layer surrounds the sidewall of the control electrode; The first word line is disposed in the second hole and extends through the different layers along the direction perpendicular to the substrate. The distance between the first word line and the first semiconductor sublayer along the direction parallel to the substrate is less than the distance between the first word line and the second semiconductor sublayer along the direction parallel to the substrate.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: An insulating layer and a conductive layer are alternately distributed from top to bottom along a direction perpendicular to the substrate; the first hole and the second hole penetrate the insulating layer and the conductive layer. The first hole contains, from the outside to the inside, the first semiconductor layer, the second gate insulating layer surrounding the sidewall of the control electrode, and the control electrode; The second hole contains, from the outside to the inside, a first gate insulating layer and the first word line, which surround the sidewall of the first word line.

3. The semiconductor device according to claim 2, characterized in that, The diameter of the first sub-hole located in the insulating layer is smaller than the diameter of the second sub-hole located in the conductive layer.

4. The semiconductor device according to claim 2, characterized in that, The diameter of the third sub-hole of the second hole located in the insulating layer is smaller than the diameter of the fourth sub-hole of the second hole located in the conductive layer.

5. The semiconductor device according to claim 2, characterized in that, The sidewall of the first semiconductor sublayer is connected to the sidewall of the first gate insulating layer, and the insulating layer is disposed between the sidewall of the second semiconductor sublayer and the sidewall of the first gate insulating layer.

6. The semiconductor device according to claim 2, characterized in that, The arrangement direction of the first hole and the second hole is perpendicular to the first direction.

7. The semiconductor device according to claim 2, characterized in that, The first electrode and the second electrode are distributed on the outer wall of the first semiconductor sublayer and are spaced apart along the first direction. The first word line is distributed in the area between the first electrode and the second electrode on the outer wall of the first semiconductor sublayer.

8. The semiconductor device according to claim 7, characterized in that, A first groove with an opening opposite to the first word line, the control electrode, and the second electrode is provided between adjacent insulating layers. The bottom wall of the first groove exposes the first gate insulating layer and the first semiconductor sublayer. The first electrode is distributed on the bottom wall of the first groove and the side wall perpendicular to the substrate. The second semiconductor layer is distributed on the bottom wall of the first groove and the side wall perpendicular to the substrate, and is also distributed on the adjacent insulating layer constituting the side wall of the first groove.

9. The semiconductor device according to claim 8, characterized in that, The semiconductor device further includes a second groove disposed on the side of the first groove away from the first semiconductor layer and extending along a second direction, the second groove communicating with a plurality of first grooves in the same column, the opening of the second groove away from the first electrode, the second semiconductor layers of the second transistors distributed in the same column along the second direction being connected to form an integral structure, the integral structure formed by the second semiconductor layer being disposed on the sidewall and bottom wall of the second groove, the first direction and the second direction intersecting.

10. The semiconductor device according to claim 7, characterized in that, The semiconductor device further includes: a memory cell array distributed along a direction perpendicular to the substrate, each layer of the memory cell array including multiple rows and columns of memory cells distributed along the first direction and the second direction respectively, the multiple layers of memory cells stacked along a direction perpendicular to the substrate being multiple memory cells at the same position in different layers, and the second electrodes of the first transistors in the same column distributed along the second direction being connected to form a first line extending along the second direction.

11. The semiconductor device according to claim 10, characterized in that, The first transistors adjacent to each other along the first direction are connected to different first bit lines.

12. The semiconductor device according to claim 9, characterized in that, The semiconductor device further includes: a second bit line extending in a second direction distributed on the bottom wall and side wall of the second groove where the second semiconductor layer is disposed.

13. The semiconductor device according to claim 12, characterized in that, The second transistors adjacent to each other along the first direction are connected to different second bit lines.

14. The semiconductor device according to claim 8, characterized in that, The second semiconductor layers of the second transistors in different layers are spaced apart.

15. The semiconductor device according to claim 8, characterized in that, The third gate electrode and the first electrode of the same memory cell are connected to form an integrated structure.

16. The semiconductor device according to claim 8, characterized in that, The second transistor further includes a third electrode, wherein the third electrodes of the second transistors of the memory cells at the same location in the multilayer are connected to form an integral structure extending in a direction perpendicular to the substrate. The integral structure formed by the third electrode connection includes a vertical portion extending in a direction perpendicular to the substrate and a horizontal portion extending in a horizontal direction from the vertical portion. The horizontal portion is connected to a second semiconductor layer distributed on the bottom wall of the first groove and to a second semiconductor layer distributed in a region adjacent to the bottom wall of the first groove.

17. The semiconductor device according to claim 16, characterized in that, The second transistor further includes a fourth gate electrode disposed on the side of the third electrode opposite to the first transistor. The fourth gate electrodes of the second transistors of the multilayer memory cells at the same location are connected to form an integral structure extending in a direction perpendicular to the substrate, and the orthogonal projection of the fourth gate electrode on the substrate is located within the orthogonal projection of the first groove on the substrate.

18. The semiconductor device according to claim 17, characterized in that, The semiconductor device further includes: A third hole penetrating each of the insulating layers and each of the conductive layers; the third hole includes a fourth hole and a fifth hole penetrating each of the insulating layers and each of the conductive layers, the arrangement direction of the fourth hole and the fifth hole being the same as the arrangement direction of the first transistor and the second transistor; The third hole has a third gate insulating layer and a second semiconductor layer distributed from the outside to the inside; The fourth hole contains multiple third electrodes connected in an integral structure; The fifth hole contains, from the outside to the inside, a fourth gate insulating layer and a fourth gate electrode.

19. The semiconductor device according to claim 18, characterized in that, The diameter of the third hole located in the fifth sub-hole of the insulating layer is smaller than the diameter of the third hole located in the sixth sub-hole of the conductive layer.

20. The semiconductor device according to claim 18, characterized in that, The fourth hole includes a seventh sub-hole located in the insulating layer and an eighth sub-hole located in the conductive layer. The boundary of the seventh sub-hole in the orthographic projection of the substrate, which is closer to the fifth hole, overlaps with the boundary of the eighth sub-hole in the orthographic projection of the substrate, which is closer to the fifth hole. The other boundaries of the seventh sub-hole in the orthographic projection of the substrate fall within the orthographic projection of the eighth sub-hole in the substrate.

21. The semiconductor device according to claim 18, characterized in that, The fifth hole includes a ninth sub-hole located in the insulating layer and a tenth sub-hole located in the conductive layer. The boundary of the ninth sub-hole in the orthographic projection of the substrate, which is closer to the fourth hole, overlaps with the boundary of the tenth sub-hole in the orthographic projection of the substrate, which is closer to the fourth hole. The other boundaries of the ninth sub-hole in the orthographic projection of the substrate fall within the orthographic projection of the tenth sub-hole in the substrate.

22. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, and a first insulating film and a conductive layer film are sequentially and alternately deposited on the substrate to form a stacked structure including alternately arranged insulating and conductive layers; The stacked structure is patterned to form a first trench extending along a first direction through each layer, and a first transistor region and a second transistor region distributed along the first direction are included between adjacent first trenches. A second hole is formed in the first transistor region, penetrating the stacked structure in a direction perpendicular to the substrate. A conductive layer is laterally etched in each second hole, such that the aperture of the second hole in the conductive layer is larger than the aperture in the insulating layer. A first gate insulating layer and a first word line of the first transistor are sequentially formed on the sidewall of the second hole. A first hole is formed in the first transistor region in a direction perpendicular to the substrate, penetrating the stacked structure. The conductive layer is laterally etched in each first hole, such that the aperture of the first hole in the conductive layer is larger than the aperture in the insulating layer, and each first gate insulating layer between any conductive layers in the second hole is exposed. Within the first hole, a first semiconductor layer, a second gate insulating layer, and control electrodes corresponding to the first transistors of different layers are sequentially formed, each connecting the first gate insulating layer. The first semiconductor layer includes a plurality of spaced first semiconductor sublayers and a second semiconductor sublayer located between adjacent first semiconductor sublayers. The first semiconductor sublayer and the second semiconductor sublayer are connected to form an integral structure. The distance between the first word line and the first semiconductor sublayer in the direction parallel to the substrate is less than the distance between the first word line and the second semiconductor sublayer in the direction parallel to the substrate. A second transistor is formed in the second transistor region, and the first transistor and the second transistor are connected by a conductive layer that serves as the sidewall of the first hole and the sidewall of the second hole.

23. The method for manufacturing a semiconductor device according to claim 22, characterized in that, Also includes: A third trench is formed between adjacent first transistor regions along a first direction, extending through each layer; the third trench extends along a second direction. The conductive layer is laterally etched into the third trench to the adjacent first transistor region to form a first lateral trench. A first line is formed in the first lateral trench to fill the first lateral trench. The first lateral trench is connected to the first hole and the second hole.

24. The method for manufacturing a semiconductor device according to claim 22, characterized in that, Forming the second transistor in the second transistor region includes: A second trench extending in the second direction through each layer is formed between adjacent second transistor regions along the first direction; the conductive layer is laterally etched into the second trench to the adjacent second transistor region, and a second lateral trench is formed in each conductive layer; A third hole is formed in the first transistor region, penetrating the stacked structure in a direction perpendicular to the substrate. A transverse groove is formed in each third hole by transverse etching of the conductive layer, such that the aperture of the third hole in the conductive layer is larger than the aperture in the insulating layer. The third hole communicates with the second trench, and the bottom wall and the side wall perpendicular to the substrate of the transverse groove are the conductive layer. A third gate insulating layer and a second semiconductor layer of the second transistor are formed in the third hole and the second trench, and the second semiconductor layer is formed only on the inner wall of the second lateral trench and the lateral groove; a second bit line is formed in the second lateral trench where the second semiconductor layer is formed to fill the second lateral trench; A fourth hole is formed in the third hole, penetrating the stacked structure in a direction perpendicular to the substrate. The conductive layer is laterally etched in each fourth hole, exposing the second semiconductor layer disposed on the bottom wall of the lateral groove and the side wall near the bottom wall of the groove, and exposing each third gate insulating layer between any conductive layers in the fourth hole. The third electrodes of a plurality of second transistors are formed in the fourth hole.

25. The method for manufacturing a semiconductor device according to claim 24, characterized in that, Forming the second transistor in the second transistor region further includes: A fifth hole is formed in the third hole, penetrating the stacked structure in a direction perpendicular to the substrate. The conductive layer is laterally etched in each fifth hole, such that a second semiconductor layer disposed in the lateral groove and not connected to the third electrode is exposed, and each third gate insulating layer between any conductive layers in the fourth hole is exposed, and the third electrode is exposed; a fourth gate insulating layer and a fourth gate electrode of a plurality of second transistors are formed in the fifth hole.

26. An electronic device, characterized in that, This includes the semiconductor device as described in any one of claims 1 to 21, or the semiconductor device manufactured by the semiconductor device manufacturing method according to any one of claims 22 to 25.

Images