Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device includes: a lower structure; a first region including a plurality of first conductive layers vertically stacked over the lower structure in a first direction; a second region including a plurality of second conductive layers stacked in the first direction, the second conductive layers having the same horizontal length; and a plurality of contact structures respectively coupled to the second conductive layers, in which each second conductive layer includes: a first horizontal conductive line; a second horizontal lead; and a pad between the first horizontal conductive line and the second horizontal conductive line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0148192, filed on October 31, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a semiconductor device, and more particularly, to a semiconductor device including a three-dimensional (3D) memory cell and a method for manufacturing the semiconductor device. Background Art

[0004] In order to cope with the demands for large capacity and miniaturization of memory devices, a technology for providing a three-dimensional (3D) memory device in which a plurality of memory cells are stacked has been proposed. Summary of the invention

[0005] Embodiments of the present disclosure relate to a semiconductor device including a highly integrated memory cell and a method for manufacturing the semiconductor device.

[0006] According to an embodiment of the present disclosure, a semiconductor device may include: a lower structure; a first region including a plurality of first conductive layers vertically stacked on the lower structure in a first direction; a second region including a plurality of second conductive layers stacked in the first direction, the second conductive layers having the same horizontal length; and a plurality of contact structures respectively coupled to the second conductive layers, wherein each second conductive layer includes: a first horizontal conductive wire; a second horizontal conductive wire; and a pad between the first horizontal conductive wire and the second horizontal conductive wire.

[0007] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: forming a first stack of first conductive layers above a lower structure, each first conductive layer including a pair of upper horizontal conductive lines and a lower horizontal conductive line; forming a second stack of second conductive layers above the lower structure, each second conductive layer including a first horizontal conductive line, a second horizontal conductive line, and a pad located between the first horizontal conductive line and the second horizontal conductive line; forming contact holes in the second stack, the height of the contact holes gradually decreasing in the direction of the second conductive layer stack; and forming contact plugs respectively coupled to the second conductive layers exposed by the contact holes.

[0008] According to another embodiment of the present disclosure, a semiconductor device includes: a lower structure; a unit array area, including a plurality of horizontal conductive lines vertically stacked on the lower structure in a first direction; a connection area, including a plurality of layers stacked in the first direction and having the same horizontal length; and a plurality of contact structures respectively coupled to the layers, wherein each layer includes: a first horizontal conductive line; a second horizontal conductive line; and a pad located between the first horizontal conductive line and the second horizontal conductive line.

[0009] According to another embodiment of the present disclosure, a semiconductor device includes: an alternating stack of conductive layers and dielectric layers disposed above a lower structure; and an array of contact plugs disposed in the alternating stack, the contact plugs being horizontally spaced apart from each other in a first horizontal direction and having different heights, wherein top surfaces of the contact plugs are disposed on the same horizontal plane and bottoms of the contact plugs are respectively coupled to the conductive layers, and wherein the contact plugs penetrating the uppermost conductive layer are laterally surrounded by the conductive layer and by a conductive layer located above the conductive layer adjacent to the contact structure.

[0010] According to another embodiment of the present disclosure, a semiconductor device includes: a first cell array region and a second cell array region laterally arranged above a lower structure; a connection region arranged between the first cell array region and the second cell array region and shared by the first cell array region and the second cell array region; and an array of contact plugs arranged in the connection region, the contact plugs being horizontally spaced apart from each other in a first horizontal direction and having different heights, wherein the first cell array region, the second cell array region and the connection region include a vertical stack of common horizontal conductors, and top surfaces of the contact plugs are arranged on the same horizontal plane, and bottoms of the contact plugs are coupled to the common horizontal conductors, and wherein a contact plug penetrating the uppermost common horizontal conductor is laterally surrounded by the common horizontal conductor, and is laterally surrounded by a common horizontal conductor located above the common horizontal conductor adjacent to the contact structure.

[0011] According to another embodiment of the present disclosure, a semiconductor device includes: a lower structure; a first memory cell array and a second memory cell array, each memory cell array including a plurality of first conductive layers stacked on the lower structure; a connecting portion disposed between the first memory cell array and the second memory cell array and including a plurality of second conductive layers, wherein each second conductive layer includes two horizontal conductive lines, and a pad located between the two horizontal conductive lines.

[0012] Other features, aspects, and advantages of embodiments of the present disclosure will become apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A is a schematic perspective view showing a storage unit according to an embodiment of the present disclosure.

[0014] Figure 1B It is shown Figure 1A Schematic cross-sectional view of a memory cell shown in .

[0015] Figure 1C It is shown Figure 1A A plan view of the switching element shown in FIG.

[0016] Figure 2 is a schematic plan view showing a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 3A It is shown Figure 2 A schematic perspective view of a memory cell array MCA1 is shown in FIG.

[0018] Figure 3B is along Figure 2 Schematic cross-sectional view taken along line AA′ shown in FIG.

[0019] Figure 3C It is shown Figure 2 A schematic three-dimensional diagram of the sub-memory cell array MV1 shown in FIG.

[0020] Figure 3D is along Figure 2 A schematic cross-sectional view taken along line BB′ shown in FIG.

[0021] Figures 4 to 22 A method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0022] Figures 23 to 31 A method for forming a connection portion according to an embodiment of the present disclosure is shown.

[0023] Figures 32 to 40 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0024] Figure 41 to Figure 43 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0025] Figures 44 to 46 is a perspective view showing a memory cell array according to other embodiments of the present disclosure. DETAILED DESCRIPTION

[0026] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Throughout the disclosure, throughout the multiple figures and embodiments of the present disclosure, the same reference numerals refer to the same parts. The drawings are not necessarily drawn to scale, and in some cases, the scale may be enlarged in order to clearly illustrate the features of the embodiments. When the first layer is referred to as being "on" the second layer or "on" a substrate, it refers not only to the situation where the first layer is directly formed on the second layer or the substrate, but also to the situation where the third layer is present between the first layer and the second layer or between the substrate.

[0027] The following embodiments described below relate to three-dimensional memory cells, and memory cells may be stacked vertically to increase memory cell density and reduce parasitic capacitance.

[0028] Figure 1A is a schematic perspective view showing a storage unit according to an embodiment of the present disclosure. Figure 1B It is shown Figure 1A Schematic cross-sectional view of a memory cell shown in . Figure 1C It is shown Figure 1A A plan view of the switching element shown in FIG.

[0029] refer to Figures 1A to 1C , the memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0030] The first wire BL may be vertically oriented in the first direction D1. The first wire BL may include a bit line. The first wire BL may be referred to as a vertical wire, a vertically oriented bit line, a vertically extending bit line, or a columnar bit line. The first wire BL may include a conductive material. The first wire BL may include a silicon-based material, a metal-based material, or a combination thereof. The first wire BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The first wire BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first wire BL may include a stack of titanium nitride and tungsten (TiN / W).

[0031] The switching element TR may have a function of controlling the voltage (or current) supplied to the data storage element CAP during the data writing and data reading operations performed on the data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second wire DWL. The second wire DWL may include a horizontal wire or a horizontal word line, and the horizontal layer HL may include an active layer. The switching element TR may include a transistor, in which case the second wire DWL may be used as a gate electrode. The switching element TR may also be referred to as an access element or a selection element. The second wire DWL may be referred to as a horizontal gate electrode or a horizontal word line.

[0032] The horizontal layer HL may extend in a second direction D2 intersecting the first direction D1. The second wire DWL may extend in a third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 may be a vertical direction, the second direction D2 may be a first horizontal direction, and the third direction D3 may be a second horizontal direction. The horizontal layer HL may extend in a first horizontal direction (i.e., the second direction D2), and the second wire DWL may extend in a second horizontal direction (i.e., the third direction D3).

[0033] The horizontal layer HL may be horizontally oriented in the second direction D2 from the first wire BL. The second wire DWL may have a dual structure. For example, the second wire DWL may include an upper horizontal wire G1 and a lower horizontal wire G2 facing each other, with the horizontal layer HL interposed therebetween. The interlayer dielectric layer GD may be formed on the upper surface and the lower surface of the horizontal layer HL. The upper horizontal wire G1 may be disposed in the upper portion of the horizontal layer HL, and the lower horizontal wire G2 may be disposed in the lower portion of the horizontal layer HL. The second wire DWL may include a pair of upper horizontal wires G1 and lower horizontal wires G2. In the second wire DWL, the same driving voltage may be applied to the upper horizontal wire G1 and the lower horizontal wire G2. For example, the upper horizontal wire G1 and the lower horizontal wire G2 may form a pair to be coupled to one memory cell MC. According to another embodiment of the present disclosure, different driving voltages may be applied to the upper horizontal wire G1 and the lower horizontal wire G2. In this case, one of the upper horizontal wire G1 or the lower horizontal wire G2 may be used as a back gate or a shielding gate.

[0034] Return to reference Figure 1C , each of the upper horizontal line G1 and the lower horizontal line G2 may have a width in the second direction D2, for example, a width of an overlapping portion overlapping with the horizontal layer HL, which is greater than a width of a non-overlapping portion that does not overlap with the horizontal layer HL. Due to the width difference, the second wire DWL may have a notch-shaped sidewall. The second wire DWL may include a channel overlapping portion WLP and a channel non-overlapping portion NOL. The channel overlapping portion WLP may refer to a portion overlapping with the channel CH of the horizontal layer HL, and the channel non-overlapping portion NOL may refer to a portion that does not overlap with the horizontal layer HL. The channel overlapping portion WLP may have a cross shape as shown. In another embodiment, the channel overlapping portion WLP may have a rhombus shape.

[0035] From a top view perspective, the horizontal layer HL may have a cross shape as shown, however, in another embodiment, it may have a diamond shape. According to another embodiment of the present disclosure, a side surface of the horizontal layer HL may have a curved shape or a rounded (or curved) shape.

[0036] The horizontal layer HL may include a semiconductor material. For example, the horizontal layer HL may include polycrystalline silicon, single crystal silicon, germanium, or silicon germanium. According to another embodiment of the present disclosure, the horizontal layer HL may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO). According to another embodiment of the present disclosure, the horizontal layer HL may include a conductive metal oxide. According to another embodiment of the present disclosure, the horizontal layer HL may include a two-dimensional material. For example, the two-dimensional material may include MoS 2 、MoSe 2 、MoTe 2 , WS 2 ,WSe 2or WTe 2 .

[0037] The upper (top) surface and the lower (bottom) surface of the horizontal layer HL may be flat. The upper surface and the lower surface of the horizontal layer HL may be parallel to each other in the second direction D2.

[0038] The horizontal layer HL may include a channel CH, a first doped region SR between the channel CH and the first conductive line BL, and a second doped region DR between the channel CH and the data storage element CAP. When the horizontal layer HL is formed of an oxide semiconductor material, the channel CH may be formed of an oxide semiconductor material, and the first doped region SR and the second doped region DR may be omitted. The horizontal layer HL may also be referred to as an "active layer or thin body". The channel CH and the channel overlap portion WLP of the second conductive line DWL may overlap each other. The channel CH may have a cross shape or a diamond shape as shown. The size of the channel overlap portion WLP of the second conductive line DWL may be greater than the size of the channel CH. The channel overlap portion WLP of the second conductive line DWL may completely overlap with the channel CH.

[0039] The first doping region SR and the second doping region DR may be doped with impurities of the same conductive type. The first doping region SR and the second doping region DR may be doped with N-type conductive impurities or P-type conductive impurities. The first doping region SR and the second doping region DR may include at least one impurity selected from the following: arsenic (As), phosphorus (P), boron (B), indium (In), and a combination thereof. The first doping region SR may be coupled to the first conductive line BL, and the second doping region DR may be coupled to the data storage element CAP. The first doping region SR and the second doping region DR may be referred to as "first source / drain region and second source / drain region".

[0040] The interlayer dielectric layer GD may be disposed between the horizontal layer HL and the second conductive line DWL. The interlayer dielectric layer GD may be referred to as a gate dielectric layer. The interlayer dielectric layer GD may be referred to as a horizontal layer side dielectric layer. The interlayer dielectric layer GD may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The interlayer dielectric layer GD may include SiO 2 、Si 3 N 4 , HfO 2 、Al 2 O 3 、ZrO 2 , AlON, HfON, HfSiO, HfSiON, HfZrO or a combination thereof. The interlayer dielectric layer GD may be formed by a thermal oxidation process of a semiconductor material.

[0041] The second wire DWL may include a metal-based material, a semiconductor material, or a combination thereof. The second wire DWL may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second wire DWL may include a TiN / W stack in which titanium nitride and tungsten are stacked sequentially. The second wire DWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, while the P-type work function material may have a high work function of about 4.5 eV or greater. The second wire DWL may include a stack of a low work function material and a high work function material.

[0042] The data storage element CAP may include a storage element such as a capacitor. The data storage element CAP may be horizontally arranged in the second direction D2 from the switching element TR. The data storage element CAP may include a first electrode SN, and the first electrode SN extends horizontally in the second direction D2 from the horizontal layer HL. The data storage element CAP may also include a second electrode PN located above the first electrode SN, and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN, the dielectric layer DE, and the second electrode PN may be horizontally arranged in the second direction D2. The first electrode SN may include an inner space and a plurality of outer surfaces, and the inner space of the first electrode SN may include a plurality of inner surfaces. The outer surface of the first electrode SN may include a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode SN may extend vertically in the first direction D1, and the horizontal outer surface of the first electrode SN may extend horizontally in the second direction D2 or the third direction D3. The inner space of the first electrode SN may be a three-dimensional space. The dielectric layer DE may conformally cover the inner and outer surfaces of the first electrode SN. The second electrode PN may be arranged in the inner space of the first electrode SN above the dielectric layer DE. A portion of the outer surface of the first electrode SN may be electrically connected to the second doping region DR of the horizontal layer HL. The second electrode PN of the data storage element CAP may be coupled to the common plate PL.

[0043] The data storage element CAP may be a three-dimensional structure. The first electrode SN may have a three-dimensional structure, and the first electrode SN of the three-dimensional structure may have a horizontal three-dimensional structure oriented in the second direction D2. As an example of a three-dimensional structure, the first electrode SN may have a cylindrical shape. The cylindrical shape of the first electrode SN may include a cylindrical inner surface and a cylindrical outer surface. A portion of the cylindrical outer surface of the first electrode SN may be electrically connected to the second doping region DR of the horizontal layer HL. The dielectric layer DE and the second electrode PN may be disposed on the cylindrical inner surface of the first electrode SN.

[0044] According to another embodiment of the present disclosure, the first electrode SN may have a column shape or a cylindrical barrel shape. The cylindrical barrel shape may refer to a structure in which a column shape and a barrel shape are combined.

[0045] The first electrode SN and the second electrode PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO 2 ), iridium (Ir), iridium oxide (IrO 2 ), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, titanium silicon nitride / titanium nitride (TiSiN / TiN) stack or a combination thereof. The second electrode PN may include a combination of a metal-based material and a silicon-based material. For example, the second electrode PN may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap filling material filling the inside of the first electrode SN, titanium nitride (TiN) may be used as the second electrode PN of the data storage element CAP, and tungsten nitride may be a low resistance material.

[0046] The dielectric layer DE may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, a perovskite material, or a combination thereof. The high-k material may include hafnium oxide (HfO 2 )、ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ) or strontium titanium oxide (SrTiO 3 According to another embodiment of the present disclosure, the dielectric layer DE may be formed of a composite layer including two or more layers of the above-mentioned high-k material.

[0047] The dielectric layer DE may be formed of a zirconium (Zr)-based oxide. 2 ) stacked structure. The dielectric layer DE may include ZA (ZrO 2 / Al 2 O 3 ) stack or ZAZ(ZrO 2 / Al 2 O 3 / ZrO 2) stack. The ZA stack may have an aluminum oxide (Al 2 O 3 ) stacked on zirconium oxide (ZrO 2 ) structure. The ZAZ stack may have a sequential stack of zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ) and zirconium oxide (ZrO 2 ) structure. ZA stacking and ZAZ stacking can be referred to as zirconium oxide (ZrO 2 ) layer. According to another embodiment of the present disclosure, the dielectric layer DE may be formed of a hafnium (Hf)-based oxide. The dielectric layer DE may have a 2 ) stacked structure. The dielectric layer DE may include HA (HfO 2 / Al 2 O 3 ) stack or HAH(HfO 2 / Al 2 O 3 / HfO 2 ) stack. The HA stack may have aluminum oxide (Al 2 O 3 ) stacked on hafnium oxide (HfO 2 ) structure. The HAH stack can have a sequential stack of hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ) and hafnium oxide (HfO 2 ) structure. HA stacking and HAH stacking can be referred to as hafnium oxide (HfO 2 ) layer. In ZA stacking, ZAZ stacking, HA stacking and HAH stacking, aluminum oxide (Al 2 O 3 ) can have a higher 2 ) and hafnium oxide (HfO 2 ) has a large band gap energy. 2 O 3 ) can have a higher 2 ) and hafnium oxide (HfO 2 ) has a low dielectric constant. Therefore, the dielectric layer DE may include a stack of a high-k material and a high-bandgap material having a bandgap energy greater than that of the high-k material. The dielectric layer DE may include silicon oxide (SiO 2 ) instead of aluminum oxide (Al 2 O 3) as a high bandgap material. By including a high bandgap material in the dielectric layer DE, leakage current can be suppressed. The high bandgap material can be thinner than the high-k material. According to another embodiment of the present disclosure, the dielectric layer DE may include a stacked structure in which a high-k material and a high bandgap material are alternately stacked. For example, the dielectric layer DE may include ZAZA (ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 ) stack, ZAZAZ(ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 2 / ZrO 2 ) stacking, HAHA(HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 ) stack or HAHAH(HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 / HfO 2 ) stacked. In the above stacked structure, aluminum oxide (Al 2 O 3 ) can be compared with zirconium oxide (ZrO 2 ) and hafnium oxide (HfO 2 )Thin.

[0048] According to another embodiment of the present disclosure, the dielectric layer DE may include a high-k material and a high bandgap material, and the dielectric layer DE may have a stacked structure in which a plurality of high-k materials and a plurality of high bandgap materials are stacked, or a mixed structure in which the high-k material and the high bandgap material are mixed with each other.

[0049] According to another embodiment of the present disclosure, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include HfZrO.

[0050] According to another embodiment of the present disclosure, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, or a combination of a high-k material or a ferroelectric material and an antiferroelectric material.

[0051] According to another embodiment of the present disclosure, an interface control layer may be further formed between the first electrode SN and the dielectric layer DE to improve leakage current. The interface control layer may include titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), niobium nitride (NbN), or a combination thereof. An interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0052] The data storage element CAP may include a three-dimensional capacitor. The data storage element CAP may include a metal-insulator-metal (MIM) capacitor. The data storage element CAP may be replaced with other data storage materials. For example, the data storage material may be a thyristor, a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material.

[0053] For example, the memory cell MC may include a thyristor, the first wire BL may be a cathode wire, and the data storage element CAP may be replaced by an anode wire. Therefore, the horizontal layer HL may include four semiconductor layers stacked in the second direction D2. The thyristor may include a first diode and a second diode coupled in series. When a forward bias of the same voltage is applied to the thyristor, the thyristor may have a high conductance state in which a large amount of current flows or a low conductance state in which a small amount of current flows or no current flows. The memory cell MC according to this embodiment of the present disclosure may have a "1" state and a "0" state, respectively, by utilizing the high conductance state and the low conductance state of the thyristor.

[0054] Return to reference Figure 1A and Figure 1B , the memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround the outer wall of the first conductive line BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC and the second contact node SNC may include doped polysilicon, and the first doping region SR and the second doping region DR may include impurities diffused from the first contact node BLC and the second contact node SNC, respectively.

[0055] Figure 2 is a schematic plan view showing a semiconductor device according to an embodiment of the present disclosure. Figure 3A It is shown Figure 2 A schematic perspective view of a memory cell array MCA1 is shown in FIG. Figure 3B is along Figure 2 Schematic cross-sectional view taken along line AA′ shown in FIG. Figure 3C It is shown Figure 2 A schematic three-dimensional diagram of the sub-memory cell array MV1 shown in FIG. Figure 3D is along Figure 2 A schematic cross-sectional view taken along line BB′ shown in FIG.

[0056] refer to Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D , the semiconductor device 100 may include a first region R1 and a second region R2. The first region R1 may be a region where a memory cell MC is formed, and the second region R2 may be a region where a contact structure CS is formed. The contact structure CS of the second region R2 may be coupled to a portion of the memory cell MC. The semiconductor device 100 may further include a third region R3, and the third region R3 may be a region where a memory cell MC is formed, just like the first region R1. The first region R1 and the third region R3 may be referred to as a memory cell region, and the second region R2 may be referred to as a connection region. The first region R1 and the third region R3 may share the second region R2. The second region R2 may also be referred to as a shared connection region, a shared contact region, or a common contact region.

[0057] The semiconductor device 100 may include a plurality of memory cell arrays MCA1 and MCA2 that share the second region R2 and are spaced apart from each other in the third direction D3. Each of the memory cell arrays MCA1 and MCA2 may include a plurality of memory cells MC. For each memory cell MC, reference may be made to Figures 1A to 1C Each memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0058] Each of the memory cell arrays MCA1 and MCA2 may include a three-dimensional array of memory cells MC. The three-dimensional array of memory cells MC may include a column array of memory cells MC and a row array of memory cells MC. The column array of memory cells MC may include a plurality of memory cells MC stacked in a first direction D1, and the row array of memory cells MC may include a plurality of memory cells MC arranged horizontally in a second direction D2 and a third direction D3. Each of the memory cell arrays MCA1 and MCA2 may have a mirror-type structure in which two memory cells MC share a first conductive line BL. According to another embodiment of the present disclosure, the semiconductor device 100 may further include a sub-memory cell array having a mirror-type structure in which two memory cells MC share a second electrode PN of a data storage element CAP.

[0059] Each of the memory cell arrays MCA1 and MCA2 may include a vertical stack WLS extending longer in the third direction D3. The vertical stack WLS may be disposed in the first region R1, the second region R2, and the third region R3.

[0060] Each of the memory cell arrays MCA1 and MCA2 may include a plurality of sub-memory cell arrays MV1 and MV2 that share a second wire DWL in a third direction D3. Each of the sub-memory cell arrays MV1 and MV2 may include a vertical stack WLS that extends longer in the third direction D3. The vertical stack WLS may refer to a second wire DWL that is vertically stacked in the first direction D1. The vertical stack WLS may be disposed in a first region R1, a second region R2, and a third region R3. The vertical stack WLS may extend from the first region R1 to the second region R2 and the third region R3. Each second wire DWL that forms the vertical stack WLS may have an integrated structure that extends from the first region R1 to the second region R2 and the third region R3.

[0061] The inter-cell dielectric layer IL may be disposed between the memory cells MC stacked in the first direction D1. The inter-cell dielectric layer IL may include, for example, silicon oxide, and may be referred to as a horizontal inter-cell dielectric layer. A hard mask layer HM may be disposed on the uppermost inter-cell dielectric layer IL.

[0062] The cell isolation layers ISOA and ISOB may be disposed between adjacent memory cells MC in the third direction D3. The cell isolation layers ISOA and ISOB may be referred to as vertical inter-cell dielectric layers. The cell isolation layers ISOA and ISOB may include silicon oxide, silicon oxycarbide (SiCO), silicon nitride, or a combination thereof. The cell isolation layers ISOA and ISOB may include a first cell isolation layer ISOA and a second cell isolation layer ISOB. The first cell isolation layer ISOA and the second cell isolation layer ISOB may extend vertically in the first direction D1. The first cell isolation layer ISOA and the second cell isolation layer ISOB may have a column structure extending vertically in the first direction D1. The first cell isolation layer ISOA and the second cell isolation layer ISOB may be alternately and repeatedly disposed in the second direction D2. The first cell isolation layer ISOA may be disposed between the data storage elements CAP in the third direction D3. The second cell isolation layer ISOB may be disposed between the first conductive lines BL in the third direction D3. The second conductive line DWL may be disposed between the first cell isolation layer ISOA and the second cell isolation layer ISOB in the second direction D2. Each of the first and second cell isolation layers ISOA and ISOB may include a stack of a cell isolation liner layer ISOL and a cell isolation gap-filling layer ISOG. The cell isolation liner layer ISOL may include silicon oxide, and the cell isolation gap-filling layer ISOG may include silicon oxycarbide.

[0063] Memory cell arrays MCA1 and MCA2 may be disposed on the lower structure LS.

[0064] The memory cell arrays MCA1 and MCA2 may include a plurality of second conductive lines DWL vertically stacked in a first direction D1. The memory cell arrays MCA1 and MCA2 may include a plurality of horizontal layers HL vertically stacked in the first direction D1. The memory cell arrays MCA1 and MCA2 may include a plurality of data storage elements CAP vertically stacked in the first direction D1. The memory cell arrays MCA1 and MCA2 may include a plurality of first conductive lines BL spaced apart from each other in a third direction D3.

[0065] like Figure 1C As shown, each second conductor DWL may include a channel overlapping portion WLP and a channel non-overlapping portion NOL. The channel overlapping portion WLP may have a cross shape as shown. In another embodiment, the channel overlapping portion WLP may have a diamond shape. The channel overlapping portion WLP may completely overlap with the channel CH. The second conductor DWL extending in the third direction D3 may include a plurality of channel overlapping portions WLP. Since the channel overlapping portion WLP and the channel non-overlapping portion NOL are alternately repeated in the third direction D3, the second conductor DWL may have a notch-shaped sidewall.

[0066] A plurality of first passivation layers BF1 may be disposed between the bottommost second wire DWL in the second wire DWL and the lower structure LS. A second passivation layer BF2 may be disposed between the first wire BL and the lower structure LS. A third passivation layer BF3 may be disposed between the data storage element CAP and the lower structure LS. The first to third passivation layers BF1, BF2, and BF3 may include a dielectric material. The first to third passivation layers BF1, BF2, and BF3 may include silicon oxide. The first wire BL, the second wire DWL, and the data storage element CAP may be electrically disconnected from the lower structure LS by the first to third passivation layers BF1, BF2, and BF3. The first to third passivation layers BF1, BF2, and BF3 may be referred to as a bottom dielectric layer or a bottom passivation layer. The bottommost inter-cell dielectric layer LIL may be disposed between the first passivation layer BF1 and the data storage element CAP.

[0067] The first wire BL may extend vertically from the upper portion of the lower structure LS in the first direction D1. The horizontal layer HL may extend in the second direction D2 crossing the first direction D1. The second wire DWL may extend in the third direction D3 crossing the first direction D1 and the second direction D2.

[0068] From the perspective of the top view, the horizontal layer HL may have a cross shape or a diamond shape. According to another embodiment of the present disclosure, the side surface of the horizontal layer HL may have a curved shape or a circular (or curved) shape. Figure 1BAs shown, the horizontal layer HL may include a channel CH, a first doping region SR between the channel CH and the first conductive line BL, and a second doping region DR between the channel CH and the data storage element CAP.

[0069] The first cover layer BC may be disposed between the second wire DWL and the first wire BL. The second cover layer CC may be disposed between the second wire DWL and the first electrode SN of the data storage element CAP. The first cover layer BC may be disposed between the upper horizontal line G1 and the first wire BL, and the first cover layer BC may be disposed between the lower horizontal line G2 and the first wire BL. The second cover layer CC may be disposed between the upper horizontal line G1 and the first electrode SN of the data storage element CAP, and the second cover layer CC may also be disposed between the lower horizontal line G2 and the first electrode SN of the data storage element CAP. One memory cell MC may include a pair of first cover layers BC and a pair of second cover layers CC.

[0070] The first cover layer BC and the second cover layer CC may include a dielectric material. The first cover layer BC and the second cover layer CC may include silicon oxide, silicon nitride, silicon oxycarbide, an air gap or a combination thereof. The first cover layer BC may include silicon oxide, and the second cover layer CC may include a stack of silicon oxide and silicon nitride.

[0071] The memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround an outer wall of the first conductive line BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC and the second contact node SNC may include doped polysilicon, and the first doping region SR and the second doping region DR may include impurities diffused from the first contact node BLC and the second contact node SNC, respectively.

[0072] The horizontal layers HL of the switching elements TR horizontally arranged in the third direction D3 may share one second wire DWL. The horizontal layers HL of the switching elements TR horizontally arranged in the third direction D3 may be coupled to different first wires BL. The switching elements TR stacked in the first direction D1 may share one first wire BL. The switching elements TR horizontally arranged in the third direction D3 may share one second wire DWL.

[0073] The first cell isolation layer ISOA may be disposed between the first electrodes SN of the data storage element CAP in the third direction D3. The first electrodes SN may be isolated from each other by the first cell isolation layer ISOA. The second electrode PN of the data storage element CAP may be coupled to the common plate PL.

[0074] The lower structure LS may include a semiconductor substrate, a metal interconnect structure, a dielectric structure, a conductive structure, a bonding pad structure, another memory or a peripheral circuit portion.

[0075] For example, the lower structure LS may include a structure in which a peripheral circuit portion, a metal interconnection structure, and a bonding pad structure are stacked in the stated order. The memory cell arrays MCA1 and MCA2 and the peripheral circuit portion of the lower structure LS may be bonded by wafer bonding.

[0076] The peripheral circuit portion of the lower structure LS may be arranged at a level lower than the memory cell arrays MCA1 and MCA2. This may be referred to as a COP (Cell-Over-Peripheral) structure. The peripheral circuit portion may include at least one control circuit for driving the memory cell arrays MCA1 and MCA2. At least one control circuit of the peripheral circuit portion may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit portion may include an address decoder circuit, a read circuit, a write circuit, and the like. At least one control circuit of the peripheral circuit portion may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin channel transistor (FinFET), and the like.

[0077] For example, the peripheral circuit part may include a sub word line driver and a sense amplifier. The first conductive line BL may be coupled to the sense amplifier, and the second conductive line DWL may be coupled to the sub word line driver.

[0078] According to another embodiment of the present disclosure, the peripheral circuit portion may be disposed at a higher level than the memory cell arrays MCA1 and MCA2. This may be referred to as a POC (Peripheral-Over-Cell) structure.

[0079] According to another embodiment of the present disclosure, the memory cell arrays MCA1 and MCA2 may include dynamic random access memory (DRAM), embedded DRAM, NAND, ferroelectric RAM (FeRAM), spin transfer torque RAM (STTRAM), phase change RAM (PCRAM) or resistive RAM (ReRAM).

[0080] refer to Figure 3C and Figure 3D, the sub memory cell array MV1 of the memory cell arrays MCA1 and MCA2 may include a vertical stack WLS and a connection portion PDS.

[0081] The vertical stack WLS may be disposed in the first region R1 and the third region R3, and the connection portion PDS may be disposed in the second region R2. The vertical stack WLS and the connection portion PDS may include a second wire DWL stacked in the first direction D1. The second wire DWL may include a plurality of layers L1, L2, L3, and L4. The layers L1 to L4 may be horizontal layers extending in the third direction D3. The first layer L1 may refer to the uppermost horizontal wire DWL, and the fourth layer L4 may refer to the lowermost horizontal wire DWL. The second layer L2 may be a layer lower than the first layer L1, and the third layer L3 may be a layer lower than the second layer L2. The fourth layer L4 may be a layer lower than the third layer L3.

[0082] The fourth layer L4 , the third layer L3 , the second layer L2 , and the first layer L1 may be stacked in the first direction D1 in the above order.

[0083] The horizontal wire DWL at each layer L1 to L4 of the vertical stack WLS may include a pair of upper horizontal wires G1 and lower horizontal wires G2. The horizontal wire DWL at each layer L1 to L4 of the connection portion PDS may include a pair of upper horizontal wires G1 and lower horizontal wires G2. In this way, the second wire DWL may be disposed in the first region R1 and the third region R3, and a portion of the second wire DWL may extend to the second region R2. The portion of the second wire DWL disposed in the second region R2 may form a connection portion PDS. The connection portion PDS may be referred to as a contact portion, an edge portion, or a pad portion.

[0084] Each of the layers L1 to L4 in the connection portion PDS may further include a pad PD. The pad PD may be disposed between the upper horizontal line G1 and the lower horizontal line G2. Each pad PD may be electrically connected to the upper horizontal line G1 and the lower horizontal line G2. The connection portion PDS may further include an inter-cell dielectric layer IL disposed between the layers L1 to L4.

[0085] The vertical stack WLS may further include a horizontal layer HL and an interlayer dielectric layer GD, which may be disposed between the upper horizontal line G1 and the lower horizontal line G2. The vertical stack WLS may further include an inter-cell dielectric layer IL between the second conductive lines DWL. The inter-cell dielectric layer IL may extend from the vertical stack WLS to the connection portion PDS.

[0086] The lateral lengths of the pads PD in the third direction D3 may be the same. The pads PD and the horizontal layer HL may be spaced apart from each other. The pads PD may be disposed in the second region R2, and the pads PD may not be disposed in the first region R1 and the third region R3.

[0087] The pad PD, the upper horizontal line G1, and the lower horizontal line G2 may include the same material. The pad PD, the upper horizontal line G1, and the lower horizontal line G2 may include a metal-based material. For example, the pad PD, the upper horizontal line G1, and the lower horizontal line G2 may include titanium nitride, tungsten, or a combination thereof. The pad PD, the upper horizontal line G1, and the lower horizontal line G2 may include a metal-based material.

[0088] The second region R2 may include a contact structure CS coupled to each second conductive line DWL of the connection portion PDS. The contact structure CS may include contact plugs CT1, CT2, CT3, and CT4 and contact spacers S1, S2, S3, and S4.

[0089] The second region R2 and the third region R3 may each include an alternating stack of second conductive lines DWL and inter-cell dielectric layers IL and an array of contact plugs CT1, CT2, CT3, and CT4 disposed in the alternating stack, which are laterally spaced apart from each other in a second horizontal direction (i.e., the third direction D3) and have different heights. The top surfaces of the contact plugs CT1, CT2, CT3, and CT4 may be disposed on the same horizontal plane. The bottoms of the contact plugs CT1, CT2, CT3, and CT4 may be adjacent to the second conductive lines DWL, respectively. Each of the contact plugs CT2, CT3, and CT4 penetrating the uppermost second conductive line DWL may be laterally surrounded by the second conductive line DWL located above the second conductive line DWL adjacent to the contact structure CS.

[0090] The first contact plug CT1 may be electrically connected to the second conductive line DWL of the first layer L1. The first contact plug CT1 may be electrically connected to the upper horizontal line G1 of the first layer L1. The second contact plug CT2 may be electrically connected to the second conductive line DWL of the second layer L2. The second contact plug CT2 may be electrically connected to the upper horizontal line G1 of the second layer L2. The third contact plug CT3 may be electrically connected to the second conductive line DWL of the third layer L3. The third contact plug CT3 may be electrically connected to the upper horizontal line G1 of the third layer L3. The fourth contact plug CT4 may be electrically connected to the second conductive line DWL of the fourth layer L4.

[0091] The fourth contact plug CT4 may be electrically connected to the upper horizontal line G1 of the fourth layer L4 .

[0092] The first contact spacer S1 may be disposed on a sidewall of the first contact plug CT1. The second contact spacer S2 may be disposed on a sidewall of the second contact plug CT2. The third contact spacer S3 may be disposed on a sidewall of the third contact plug CT3. The fourth contact spacer S4 may be disposed on a sidewall of the fourth contact plug CT4. The vertical height of the fourth contact plug CT4 may be greater than the vertical height of the third contact plug CT3. The vertical height of the third contact plug CT3 may be greater than the vertical height of the second contact plug CT2. The vertical height of the second contact plug CT2 may be greater than the vertical height of the first contact plug CT1. The vertical height refers to the height in the first direction D1.

[0093] The fourth contact plug CT4 and the fourth contact spacer S4 may penetrate the pad PD of the first layer L1, the second layer L2, and the third layer L3 and the upper horizontal line G1 and the lower horizontal line G2. The fourth contact plug CT4 may be electrically disconnected from the pad PD of the first layer L1, the second layer L2, and the third layer L3 and the upper horizontal line G1 and the lower horizontal line G2 by the fourth contact spacer S4.

[0094] The third contact plug CT3 and the third contact spacer S3 may penetrate the pad PD of the first and second layers L1 and L2 and the upper and lower horizontal lines G1 and G2. The third contact plug CT3 may be electrically disconnected from the pad PD of the first and second layers L1 and L2 and the upper and lower horizontal lines G1 and G2 by the third contact spacer S3.

[0095] The second contact plug CT2 and the second contact spacer S2 may penetrate the pad PD and the upper and lower horizontal lines G1 and G2 of the first layer L1. The second contact plug CT2 may be electrically disconnected from the pad PD and the upper and lower horizontal lines G1 and G2 of the first layer L1 by the second contact spacer S2.

[0096] Return reference from another perspective Figure 3D, the semiconductor device 100 may include a first cell array region R1 and a second cell array region R3 disposed in a lateral direction above the lower structure LS and a connection region R2 disposed between the first cell array region R1 and the second cell array region R3. The connection region R2 is shared by the first cell array region R1 and the second cell array region R3. In addition, an array of contact plugs CT1 to CT4 is disposed in the connection region R2 and is horizontally spaced apart from each other in the first horizontal direction D3. The contact plugs CT1 to CT4 have different heights. Here, the first cell array region R1, the second cell array region R3, and the connection region R2 may include a stack of common second wires DWL, and the top surfaces of the contact plugs CT1 to CT4 may be disposed on the same horizontal plane, and the bottoms of the contact plugs CT1 to CT4 may be coupled to the common second wires DWL, and the contact plugs CT2 to CT4 penetrating the uppermost common second wire DWL may be laterally surrounded by the common second wires DWL, respectively, and are laterally surrounded by the common second wires DWL located above the common second wires DWL adjacent to the contact plugs CT2 to CT4, respectively.

[0097] In addition, the contact plugs CT2 to CT4 may penetrate the common second wire DWL of the first layer L1. The contact plugs CT2 to CT4 may be laterally surrounded by the common second wire DWL of the first layer L1, and the contact plug CT2 may be laterally surrounded by the common second wire DWL of the first layer L1. The contact plug CT3 may be laterally surrounded by the common second wire DWL of the first and second layers, and the contact plug CT4 may be laterally surrounded by the common second wire DWL of the first, second, and third layers L1, L2, and L3. The contact plug CT4 may be laterally surrounded by the common second wire DWL of the third layer L3 located above the common second wire DWL of the fourth layer L4 adjacent to the contact plug CT4. The contact plug CT3 may be laterally surrounded by the common second wire DWL of the second layer L2 located above the common second wire DWL of the third layer L3 adjacent to the contact plug CT3. The contact plug CT2 may be laterally surrounded by the common second conductive line DWL of the first layer L1 over the common second conductive line DWL of the second layer L2 adjacent to the contact plug CT2 .

[0098] According to the above description, the second conductive line DWL of the connection part PDS may have a step-free structure. Since the connection part PDS is formed in a step-free structure, the occupied area (or volume) of the connection part PDS in the second region R2 can be reduced. In addition, since the first region R1 and the third region R3 share one second region R2, the area for forming the second region R2 can be reduced.

[0099] As a comparative example, when the connection portion is formed in a stepped structure, the first region R1 and the third region R3 may each include a stepped second region R2 , and thus the increased second region R2 may increase the area of ​​the semiconductor device.

[0100] Figures 4 to 22 An example of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown. Figures 4 to 22 Shown according to Figure 2 The manufacturing method of the line AA' shown in FIG. Figure 2 The first to third directions D1, D2 and D3 are shown in FIG.

[0101] refer to Figure 4 , the stack SB can be formed on the lower structure 11. The lower structure 11 can be a material suitable for semiconductor processing, including at least one or more of, for example, a conductive material, a dielectric material, and a semiconductor material. A variety of materials can be formed on the lower structure 11. The lower structure 11 may include a semiconductor substrate such as, for example, silicon (including single crystal silicon, polycrystalline silicon, amorphous silicon). The lower structure 11 may also include other materials, such as germanium, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, and multilayers thereof. The lower structure 11 may include a III / V semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. The lower structure 11 may include a silicon-on-insulator (SOI) substrate.

[0102] The stack SB may include a plurality of sub-stacks stacked alternately. Each sub-stack may include a first layer 12A, a second layer 13, a third layer 12B, and a fourth layer 14 stacked in the order described. The first layer 12A and the third layer 12B may include the same material such as, for example, silicon germanium or single crystal silicon germanium. The second layer 13 and the fourth layer 14 may be made of the same material such as, for example, single crystal silicon. The first layer 12A, the second layer 13, the third layer 12B, and the fourth layer 14 may be formed by an epitaxial growth process. The lowermost first layer 12A may be used as a seed layer during the epitaxial growth process. The first layer 12A may be thinner than the second layer 13, and the fourth layer 14 may be thicker than the second layer 13.

[0103] According to this embodiment of the present disclosure, the stack SB may include a plurality of fourth layers 14, a first sacrificial layer stack SB1, a second sacrificial layer stack SB2, a third sacrificial layer stack SB3, a fourth sacrificial layer stack SB4, and a fifth sacrificial layer stack SB5. The stack SB may include a first stack SB1, a fourth layer 14, a second stack SB2, a fourth layer 14, a third stack SB3, a fourth layer 14, a fourth stack SB4, a fourth layer 14, and a fifth stack SB5 stacked in the order described. The second layer 13 may be disposed at the uppermost layer of the stack SB. Each of the first to fifth stacks SB1 to SB5 may be a three-layer stack of the first layer 12A / the second layer 13 / the third layer 12B. For example, when the first layer 12A and the third layer 12B include a silicon germanium layer and the second layer 13 includes a single crystal silicon layer, the first to fifth stacks SB1 to SB5 may include a stack (SiGe / Si / SiGe) of a first silicon germanium / single crystal silicon / a second silicon germanium. The fifth stack SB5 may further include a second layer 13 located on the three-layer stack of the first layer 12A / the second layer 13 / the third layer 12B.

[0104] The second layer 13 may include a first single crystal silicon layer, and the fourth layer 14 may include a second single crystal silicon layer. The second single crystal silicon layer may be thicker than the first single crystal silicon layer. Therefore, in the stacked body SB, the first stack SB1 may be disposed below the second single crystal silicon layer, and the second stack SB2 may be disposed above the second single crystal silicon layer. Each of the first stack SB1 and the second stack SB2 may include a stack of a first silicon germanium layer / a first single crystal silicon layer / a second silicon germanium layer, and the second single crystal silicon layer may be thicker than the first single crystal silicon layer.

[0105] The first layer 12A, the second layer 13, and the third layer 12B may be referred to as “sacrificial layers”, and the fourth layer 14 may be referred to as a “recessed target layer”. The stack SB may be referred to as a “vertical stack”. The stack SB may be formed by alternating a plurality of sacrificial layers and recessed target layers. The sacrificial layers may include first to fifth stacks SB1 to SB5, and each of the first to fifth stacks SB1 to SB5 may include a three-layer stack of the first layer 12A / the second layer 13 / the third layer 12B. The recessed target layer may include the fourth layer 14. Each sacrificial layer may include a three-layer stack of a first silicon germanium layer / a first single crystal silicon layer / a second silicon germanium layer, and each recessed target layer may include a single-layer second single crystal silicon layer, and the second single crystal silicon layer may be thicker than the first single crystal silicon layer.

[0106] As above reference Figures 2 to 3D As described, when the memory cell MC is stacked, the first sacrificial layer stack SB1, the fourth layer 14, the second sacrificial layer stack SB2, the fourth layer 14, the third sacrificial layer stack SB3, the fourth layer 14, the fourth sacrificial layer stack SB4, the fourth layer 14 and the fifth sacrificial layer stack SB5 can be alternately stacked several times.

[0107] According to another embodiment of the present disclosure, the fourth layer 14 may include amorphous silicon or polycrystalline silicon.

[0108] refer to Figure 5 , a portion of the stacked body SB may be etched to form a plurality of first vertical openings 15 and second vertical openings 16 in the stacked body SB. From the perspective of the top view, the first vertical openings 15 and the second vertical openings 16 may be hole-type vertical openings. According to another embodiment of the present disclosure, the first vertical openings 15 and the second vertical openings 16 may be linear vertical openings. From the perspective of the top view, the cross-sections of the first vertical openings 15 and the second vertical openings 16 may be square, circular, or elliptical.

[0109] As described above, the hard mask layer pattern HM1 may be formed to form the vertical openings 15 and 16, and the hard mask layer pattern HM1 may be formed using a double patterning process. The hard mask layer pattern HM1 may include silicon nitride. The hard mask layer pattern HM1 may be formed by an etching process using a mask layer. The hard mask layer pattern HM1 may have a plurality of hole-type openings defined therein.

[0110] refer to Figure 6 , a portion HT of the hard mask layer pattern HM1 may be trimmed.

[0111] The first layer 12A and the third layer 12B may be selectively removed through the first vertical opening 15 and the second vertical opening 16. The first layer 12A and the third layer 12B may be selectively removed by using the difference in etching selectivity between the second layer 13 and the fourth layer 14 and the first layer 12A and the third layer 12B. The first layer 12A and the third layer 12B may be removed by a wet etching process or a dry etching process. For example, when the first layer 12A and the third layer 12B include a silicon germanium layer, and the second layer 13 and the fourth layer 14 include a single crystal silicon layer, the silicon germanium layer may be etched by using an etchant or etching gas having selectivity with respect to the single crystal silicon layer.

[0112] The second layer 13 and the fourth layer 14 may be recessed. In order to recess the second layer 13 and the fourth layer 14, a wet etching process or a dry etching process may be performed. According to this embodiment of the present disclosure, the fourth layer 14 may be partially etched when the second layer 13 is removed. As a result, the second layer 13 may be removed, and the fourth layer 14 may be thinned, as shown in the figure mark "14A". The recess process for forming the thin fourth layer 14A (as the preliminary horizontal layer 14A) may be referred to as a thinning process or a trimming process of the fourth layer 14. In order to form the preliminary horizontal layer 14A, the upper surface, the lower surface, and the side surface of the fourth layer 14 may be recessed. The preliminary horizontal layer 14A may be referred to as a thin-body active layer. The preliminary horizontal layer 14A may include a single crystal silicon layer. The recess process for forming the preliminary horizontal layer 14A may use, for example, HSC1 (hot SC-1). HSC1 may include ammonium hydroxide (NH OH) mixed in a ratio of approximately 1:4:20. 4 OH), hydrogen peroxide (H 2 O 2 ) and water (H 2 The second layer 13 and the fourth layer 14 can be selectively etched by using HSC1.

[0113] The preliminary horizontal layer 14A may be formed by the recessing process of the fourth layer 14 as described above, and the horizontal recesses 17 may be formed between the preliminary horizontal layers 14A. Each of the upper and lower surfaces of the preliminary horizontal layer 14A may be flat.

[0114] The preliminary horizontal layer 14A may have a cross shape from a top view perspective, and a side surface of the preliminary horizontal layer 14A may have a curved shape or a rounded shape.

[0115] After forming the preliminary horizontal layer 14A, the first and second vertical openings 15 and 16 may be expanded. The preliminary horizontal layers 14A may be spaced apart from each other in the second direction D2 by the first and second vertical openings 15 and 16. The preliminary horizontal layer 14A may have a shape merging a plurality of crosses in the third direction D3.

[0116] When the preliminary horizontal layer 14A is formed, the surface of the lower structure 11 may be recessed by a predetermined depth (see reference numeral '11A'). Thus, the bottom depths of the first and second vertical openings 15 and 16 may be increased.

[0117] The first vertical openings 15 and the second vertical openings 16 may be alternately disposed between the preliminary horizontal layers 14A in the second direction D2 .

[0118] refer to Figure 7, a first dielectric layer 18 completely covering the preliminary horizontal layer 14A may be formed. The first dielectric layer 18 may include silicon nitride. The first dielectric layer 18 may completely cover the upper surface, the lower surface, and the side surface of the preliminary horizontal layer 14A.

[0119] When forming the first dielectric layer 18, a dummy dielectric layer 18D may be formed on the surface of the lower structure 11. A portion of the first dielectric layer 18 may completely cover the upper surface, the lower surface, and the side surface of the hard mask layer pattern HM1.

[0120] A second dielectric layer 19 may be formed on the first dielectric layer 18. The second dielectric layer 19 may fill between vertically adjacent first dielectric layers 18. The second dielectric layer 19 may include silicon oxide. Portions of the second dielectric layer 19 may be conformally formed on the surfaces of the first vertical opening 15 and the second vertical opening 16. Figure 6 The reference numeral '17' in FIG. 1 may be filled with a first dielectric layer 18 and a second dielectric layer 19 .

[0121] A sacrificial post 20 may be formed on the second dielectric layer 19 disposed in the first vertical opening 15 and the second vertical opening 16. The sacrificial post 20 may be a sacrificial material and may include amorphous carbon. According to another embodiment of the present disclosure, a post capping layer may be further formed on the sacrificial post 20. The post capping layer may include a metal-based material. The post capping layer may include titanium nitride. Forming the sacrificial post 20 may include depositing a sacrificial material and planarizing the sacrificial material. A planarization process for forming the sacrificial post 20 may be performed until the uppermost first dielectric layer 18 is exposed. Subsequently, the uppermost second dielectric layer 19 may also be planarized until the uppermost first dielectric layer 18 is exposed. The sacrificial post 20 may not be formed between the vertically stacked first dielectric layers 18.

[0122] The second dielectric layer 19 and the sacrificial column 20 may form a first sacrificial column structure SV1 and a second sacrificial column structure SV2 filling the first vertical opening 15 and the second vertical opening 16. The first sacrificial column structure SV1 may fill the first vertical opening 15, and the second sacrificial column structure SV2 may fill the second vertical opening 16. According to another embodiment of the present disclosure, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may include a dielectric material, a carbon-containing material, a metal-based material, or a combination thereof. According to another embodiment of the present disclosure, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof. From the perspective of the top view, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may be hole-type sacrificial columns. According to another embodiment of the present disclosure, a portion of the first dielectric layer 18 may be conformally formed on the surface of the first vertical opening 15 and the second vertical opening 16, so that a portion of the first dielectric layer 18 is also included in the first sacrificial column structure SV1 and the second sacrificial column structure SV2.

[0123] As described above, by forming the preliminary horizontal layer 14A, the first dielectric layer 18, and the second dielectric layer 19, a unit mold structure MD may be formed. The unit mold structure MD may include a plurality of unit molds. Each unit mold may include a plurality of mold layers. The mold layer may refer to the preliminary horizontal layer 14A, the first dielectric layer 18, and the second dielectric layer 19. Each unit mold may include an ONSN (oxide-nitride-silicon-nitride) stack. Here, the ONSN stack may refer to a structure in which silicon oxide, a first silicon nitride, a single crystal silicon layer, and a second silicon nitride are stacked in sequence. Silicon oxide may correspond to the second dielectric layer 19, the first silicon nitride and the second silicon nitride may correspond to the first dielectric layer 18, and the single crystal silicon layer may correspond to the preliminary horizontal layer 14A. The unit mold structure MD including a plurality of unit molds may be referred to as a vertical stack. From another perspective, the unit mold structure may include an ONSNO (oxide-nitride-silicon-nitride-oxide) stack. Here, the ONSNO stack may refer to a structure in which the first silicon oxide, the first silicon nitride, the single crystal silicon layer, the second silicon nitride, and the second silicon oxide are stacked in sequence.

[0124] As mentioned above, by Figures 4 to 7 The sub-stack of the stack SB may be replaced by a unit mold through a series of processes. The first layer 12A, the second layer 13, and the third layer 12B of the stack SB may be replaced by the first dielectric layer 18 and the second dielectric layer 19 of the unit mold structure MD. The fourth layer 14 of the stack SB may become the preliminary horizontal layer 14A of the unit mold structure MD through a recess process. The first dielectric layer 18 may be referred to as a trimming target layer.

[0125] refer to Figure 8 Forming the hard mask level opening HM′ includes removing the hard mask layer pattern HM1 and the uppermost first dielectric layer 18 .

[0126] Although not shown, before forming the hard mask level opening HM′, a Figure 2 The cell isolation layers ISOA and ISOB are shown. In addition, before forming the cell isolation layers ISOA and ISOB, a trimming process of the preliminary horizontal layer 14A may be performed. Through the trimming process, the preliminary horizontal layer 14A may have a shape in which a cross is individually separated in the third direction D3.

[0127] For example, after forming the cell mold structure, forming a cell isolation opening, trimming the preliminary horizontal layer 14A through the cell isolation opening, and forming a cell isolation layer filling the cell isolation opening may be sequentially performed. In addition, before forming the cell mold structure, forming a sacrificial isolation opening in the stack and forming a sacrificial isolation layer filling the sacrificial isolation opening may be performed. The sacrificial isolation layer may be removed to form the cell isolation opening.

[0128] refer to Fig. 9 , the hard mask level opening HM′ may be filled with a top dielectric layer HM. The top dielectric layer HM may include silicon oxide.

[0129] refer to Fig.10 , the sacrificial vertical opening 21 may be formed by removing the second sacrificial post structure SV2. To form the sacrificial vertical opening 21, the second dielectric layer 19 and the sacrificial post 20 of the second sacrificial post structure SV2 may be selectively etched.

[0130] The second dielectric layer 19 may be horizontally recessed through the sacrificial vertical opening 21. Therefore, the first dielectric layer 18 and the dummy dielectric layer 18D may be exposed through the sacrificial vertical opening 21.

[0131] The first dielectric layer 18 and the dummy dielectric layer 18D may be selectively horizontally recessed. As a result, a dielectric level recess 22 may be formed, and a portion of the preliminary horizontal layer 14A may be exposed through the dielectric level recess 22.

[0132] The recessed amount of the first dielectric layer 18 may be greater than the recessed amount of the second dielectric layer 19 .

[0133] refer to Fig.11 , vertical sacrificial structures 23 may be formed to fill the dielectric level recess 22 and the sacrificial vertical opening 21. The vertical sacrificial structures 23 may include a dielectric material, such as silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof. Each vertical sacrificial structure 23 may include an extension portion 23A that fills the dielectric level recess 22.

[0134] refer to Fig.12 , forming the vertical level path 24 includes removing the sacrificial post 20 of the first sacrificial post structure SV1.

[0135] Forming the lower layer gap 25 includes removing the dummy dielectric layer 18D below the vertical step path 24. Before removing the dummy dielectric layer 18D, the bottom surface of the lowermost second dielectric layer 19 may be cut.

[0136] See also Fig.13 , the second dielectric layer 19 may be cut to form a first hole-type vertical opening 26 .

[0137] The first passivation layer BF1 may be formed to fill the lower gap 25. The first passivation layer BF1 may include silicon oxide, and may be formed by first depositing silicon oxide to fill the lower gap 25, and then etching the silicon oxide.

[0138] The second passivation layer BF2 may be formed in a lower region of the first hole-type vertical opening 26. For example, the surface of the lower structure 11 may be oxidized to form the second passivation layer BF2.

[0139] refer to Fig.14 , the first dielectric layer 18 may be removed to form a horizontal level recess 27 extending from the first hole-type vertical opening 26. Portions of the preliminary horizontal layer 14A may be exposed by the horizontal level recess 27. One preliminary horizontal layer 14A may be partially exposed by a pair of horizontal level recesses 27. The horizontal level recess 27 may be disposed between the second dielectric layer 19 and the preliminary horizontal layer 14A. Two horizontal level recesses 27 may face each other with a preliminary horizontal layer 14A therebetween.

[0140] refer to Fig.15 , an interlayer dielectric layer 28 may be formed on the exposed portion of the preliminary horizontal layer 14A. The interlayer dielectric layer 28 may be referred to as a gate dielectric layer. The interlayer dielectric layer 28 may correspond to Figures 1A to 1C The interlayer dielectric layer GD shown in FIG. The interlayer dielectric layer 28 may be formed by oxidizing the surface of the preliminary horizontal layer 14A. According to another embodiment of the present disclosure, the interlayer dielectric layer 28 may be formed by a deposition process of silicon oxide.

[0141] The interlayer dielectric layer 28 may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material or a combination thereof. The interlayer dielectric layer 28 may include SiO 2 、Si 3 N 4 , HfO 2 、Al 2 O 3 、ZrO 2 , AlON, HfON, HfSiO, HfSiON or a combination thereof.

[0142] refer to Fig.16For example, by depositing a conductive material filling the horizontal level recess 27 on the interlayer dielectric layer 28 and etching back the conductive material, a horizontal conductive wire 29 filling the horizontal level recess 27 can be formed on the interlayer dielectric layer 28. The horizontal conductive wire 29 may include a pair of first horizontal conductive wires 29A and second horizontal conductive wires 29B facing each other with a preliminary horizontal layer 14A therebetween. The first horizontal conductive wire 29A and the second horizontal conductive wire 29B may include a metal-based material, a semiconductor material, or a combination thereof. The first horizontal conductive wire 29A and the second horizontal conductive wire 29B may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first horizontal conductive wire 29A and the second horizontal conductive wire 29B may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The first horizontal conductive wire 29A and the second horizontal conductive wire 29B may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, and the P-type work function material may have a high work function of about 4.5 eV or more.

[0143] The horizontal conductor 29 may correspond to Figures 1A to 1C The second wire DWL shown in FIG. 1A and the first horizontal wire 29A and the second horizontal wire 29B may correspond to the upper horizontal wire G1 and the lower horizontal wire G2. Figures 1A to 1C As shown, each of the first horizontal conductive line 29A and the second horizontal conductive line 29B may have a cross shape, and may include a channel overlap portion WLP and a channel non-overlap portion NOL.

[0144] refer to Fig.17 , a first capping layer 30 may be formed on one side surface of each horizontal conductive line 29. The first capping layer 30 may include silicon oxide, silicon nitride, silicon oxycarbide, an embedded air gap, or a combination thereof. A process of depositing a capping material and an etch-back process may be performed to form the first capping layer 30. When or after forming the first capping layer 30, a portion of the interlayer dielectric layer 28 may be removed to expose a first edge portion of each preliminary horizontal layer 14A.

[0145] A vertical conductive line 33 coupled to a first edge portion of each preliminary horizontal layer 14A may be formed. The vertical conductive line 33 may fill the first hole-type vertical opening 26. The vertical conductive lines 33 may be commonly coupled to the preliminary horizontal layers 14A arranged in the first direction D1. The vertical conductive lines 33 may include titanium nitride, tungsten, or a combination thereof, and the vertical conductive lines 33 may be referred to as bit lines or vertical bit lines.

[0146] Before forming the vertical conductive line 33, a first doped region 32 and a first contact node 31 may be formed. The first doped region 32 may be formed in a first edge portion of each preliminary horizontal layer 14A. Forming the first doped region 32 may include depositing polysilicon doped with N-type impurities, performing a heat treatment, and removing the doped polysilicon. The first doped region 32 may include impurities diffused from the doped polysilicon. According to another embodiment of the present disclosure, the first doped region 32 may be formed by a process of doping impurities.

[0147] The first contact node 31 may include doped polysilicon. The first doping region 32 may include impurities diffused from the first contact node 31. A metal silicide layer may also be formed between the vertical conductive line 33 and the first contact node 31.

[0148] The vertical conductors 33 may correspond to Figures 1A to 1C The first contact node 31 may correspond to the first conductive line BL. Figures 1A to 1C The first contact node BLC shown in FIG. Figures 1A to 1C The first doped region SR is shown.

[0149] refer to Fig.18 , a portion of the vertical sacrificial structure 23 may be removed to form a second hole-type vertical opening 34'. One side surface (ie, the second edge portion) of the preliminary horizontal layer 14A may be exposed by the second hole-type vertical opening 34'.

[0150] By removing a portion of the vertical sacrificial structure 23 , a lowermost dielectric layer 23L may be formed on the side surface of the first passivation layer BF1 . According to another embodiment of the present disclosure, the lowermost dielectric layer 23L may not remain.

[0151] A third passivation layer BF3 may be formed on the surface of the lower structure 11. The third passivation layer BF3 may include silicon oxide and may be formed, for example, by an oxidation process.

[0152] The second edge portion of the preliminary horizontal layer 14A may be horizontally recessed in the second direction D2 , and thus the horizontal layer HL may be formed.

[0153] The extended portion of the vertical sacrificial structure 23 (see Fig.12 The reference numeral '23A' in FIG. 1 may be selectively recessed to form a second capping layer 34. The second capping layer 34 may include silicon oxide, silicon nitride, or a combination thereof.

[0154] After forming the second cover layer 34, a storage opening 35 horizontally extending from the second hole-type vertical opening 34' may be formed. The storage opening 35 may be referred to as a capacitor opening.

[0155] The horizontal layer HL may include a first edge and a second edge. The first edge refers to a portion coupled to the first contact node 31 and the vertical conductive line 33. The second edge refers to a portion exposed by the storage opening 35.

[0156] The storage opening 35 may be disposed between vertically adjacent second dielectric layers 19. The second cover layers 34 may be disposed at lower and upper portions of the horizontal layer HL, respectively.

[0157] As described above, forming the horizontal layer HL and the storage opening 35 may include forming the second hole-type vertical opening 34 ′, recessing the preliminary horizontal layer 14A, and forming the second cover layer 34 .

[0158] refer to Fig.19 , the second doping regions 37 may be formed in the second edges of the horizontal layer HL, respectively. Forming the second doping regions 37 may include depositing polysilicon doped with N-type impurities, performing a heat treatment, and removing the doped polysilicon. The second doping regions 37 may include impurities diffused from the doped polysilicon. According to another embodiment of the present disclosure, after the heat treatment, the doped polysilicon may remain.

[0159] The second contact node 36 may be formed on the second edge of the horizontal layer HL. The second contact node 36 may include doped polysilicon. The second doping region 37 may include impurities diffused from the second contact node 36.

[0160] Each horizontal layer HL may include a first doping region 32, a second doping region 37, and a channel 38 horizontally disposed in the second direction D2. The channel 38 may be defined between the first doping region 32 and the second doping region 37. The channel 38 may vertically overlap the horizontal conductive line 29. Figures 1A to 1C As shown, the horizontal layer HL may have a cross shape, and the channel 38 may also have a cross shape.

[0161] refer to Fig. 20 , the first electrodes 39 of the data storage element may be formed on the second contact nodes 36. The first electrodes 39 may have a horizontally oriented cylindrical shape and may be respectively disposed in the storage openings 35. The first electrodes 39 adjacent in the second direction D2 may be spaced apart from each other by the second hole-type vertical openings 34'.

[0162] refer to Fig.21 , the second dielectric layer 19 may be horizontally recessed (see reference numeral '40'). Therefore, the outer wall of the first electrode 39 may be exposed. The recessed second dielectric layer 19 may correspond to Figure 3B The inter-cell dielectric layer IL is shown.

[0163] See also Fig. 22, a dielectric layer 41 may be conformally formed on the first electrode 39, and a second electrode 42 may be sequentially formed on the first dielectric layer 41. The first electrode 39, the dielectric layer 41, and the second electrode 42 may become a data storage element CAP.

[0164] The first electrode 39 may include an inner space and a plurality of outer surfaces, and the inner space of the first electrode 39 may include a plurality of inner surfaces. The outer surface of the first electrode 39 may include a vertical outer surface and a plurality of horizontal outer surfaces. The inner space of the first electrode 39 may be a three-dimensional space. The dielectric layer 41 may conformally cover the inner surface and the outer surface of the first electrode 39. The second electrode 42 may be disposed in the inner space of the first electrode 39 on the dielectric layer 41. Some outer surfaces of the first electrode 39 may be coupled to the horizontal layer HL.

[0165] The first electrode 39 may have a cylindrical shape. The cylindrical shape of the first electrode 39 may include a cylindrical inner surface and a cylindrical outer surface. The dielectric layer 41 and the second electrode 42 may be disposed on the cylindrical inner surface of the first electrode 39.

[0166] The first electrode 39 and the second electrode 42 may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode 39 and the second electrode 42 may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO 2 ), iridium (Ir), iridium oxide (IrO 2 ), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, titanium silicon nitride / titanium nitride (TiSiN / TiN) stack or a combination thereof. The second electrode 42 may include a combination of a metal-based material and a silicon-based material. For example, the second electrode 42 may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap filling material filling the internal space of the first electrode 39, titanium nitride (TiN) may be used as the second electrode 42 of the data storage element CAP, and tungsten nitride may be a low resistance material.

[0167] The dielectric layer 41 may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer 41 may include silicon oxide, silicon nitride, a high-k material, a perovskite material, a ferroelectric material, an antiferroelectric material, or a combination thereof. The dielectric layer 41 may include a high-k material, such as hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O3 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ) or strontium titanium oxide (SrTiO 3 ). The dielectric layer 41 may include ZA (ZrO 2 / Al 2 O 3 ) stack, ZAZ(ZrO 2 / Al 2 O 3 / ZrO 2 ) stack, ZAZA(ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 ) stack, ZAZAZ(ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 / ZrO 2 ) stacking, HA(HfO 2 / Al 2 O 3 ) stack, HAH(HfO 2 / Al 2 O 3 / HfO 2 ) stacking, HAHA(HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 ) stack or HAHAH(HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 / HfO 2 ) stack.

[0168] According to another embodiment of the present disclosure, an interface control layer for reducing leakage current may be formed between the first electrode 39 and the dielectric layer 41. The interface control layer may include titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5), niobium oxide (Nb 2 O 5 ), niobium nitride (NbN), or a combination thereof. An interface control layer may also be formed between the second electrode 42 and the dielectric layer 41.

[0169] Figures 23 to 31 A method for forming a connection portion according to an embodiment of the present disclosure is shown. Figures 23 to 31 The embodiment according to the present disclosure is shown in Figure 2 The method of forming the connection portion is shown in FIG.

[0170] refer to Figures 4 to 17 After the horizontal conductive line 29 and the vertical conductive line 33 are formed, a connection portion may be formed at one side edge portion of the horizontal conductive line 29 .

[0171] refer to Fig.23 , the horizontal conductive lines 29 may each include a pair of first horizontal conductive lines 29A and second horizontal conductive lines 29B. A plurality of horizontal conductive lines DWL may be stacked in the first direction D1. A preliminary horizontal layer 14A and an interlayer dielectric layer 28 may be formed in the first region R1 and the second region R2, respectively. A second dielectric layer 19 may be formed between the horizontal conductive lines 29.

[0172] The horizontal conductive line 29 and the second dielectric layer 19 may be etched to form a pad separation seam WSM′ in the second region R2 .

[0173] refer to Fig.24 , the interlayer dielectric layer 28 and the preliminary horizontal layer 14A may be removed through the pad separation seam WSM' in the second region R2. As a result, a pad type recess PD' may be formed between the first horizontal conductive line 29A and the second horizontal conductive line 29B.

[0174] refer to Fig.25 , a pad PD may be formed to fill the pad-type recess PD'.

[0175] The horizontal conductive line 29 may include a plurality of layers L1, L2, L3, and L4. For example, the first layer L1 may refer to the uppermost layer of the horizontal conductive line 29, and the fourth layer L4 may refer to the lowermost layer of the horizontal conductive line 29. The second layer L2 may be a layer lower than the first layer L1, and the third layer L3 may be a layer lower than the second layer L2. The fourth layer L4 may be a layer lower than the third layer L3.

[0176] The fourth layer L4 , the third layer L3 , the second layer L2 , and the first layer L1 may be stacked in the first direction D1 in the stated order.

[0177] Each horizontal conductive line 29 of the layers L1 to L4 may include a pair of first horizontal conductive lines 29A and second horizontal conductive lines 29B. The horizontal conductive lines 29 may be disposed in the first region R1, and a portion of the horizontal conductive line 29 may extend to the second region R2. The portion of the horizontal conductive line 29 disposed in the second region R2 may be simply referred to as an edge portion or a connection portion PDS.

[0178] The connection part PDS of the horizontal conductive line 29 may include a plurality of layers L1, L2, L3, and L4. Each horizontal conductive line 29 of the layers L1 to L4 in the connection part PDS may include a pair of first horizontal conductive lines 29A and second horizontal conductive lines 29B. In the connection part PDS, the layers L1 to L4 may further include pads PD. Each pad PD may be disposed between the first horizontal conductive line 29A and the second horizontal conductive line 29B. Each pad PD may be electrically connected to the first horizontal conductive line 29A and the second horizontal conductive line 29B.

[0179] The horizontal lengths of the pads PD in the third direction D3 may be the same. The pads PD and the horizontal layer 14A may be spaced apart from each other. The pads PD may not be disposed in the first region R1.

[0180] The pad PD, the first horizontal conductive line 29A, and the second horizontal conductive line 29B may include the same material. The pad PD, the first horizontal conductive line 29A, and the second horizontal conductive line 29B may include a metal-based material. For example, the pad PD, the first horizontal conductive line 29A, and the second horizontal conductive line 29B may include titanium nitride, tungsten, or a combination thereof.

[0181] Then, if Figure 26 to Figure 29 As shown, a plurality of contact holes H1 , H2 , H3 , and H4 may be sequentially formed in the second region R2 .

[0182] refer to Fig.26 The hard mask layer pattern HM and the uppermost second dielectric layer 19 may be etched to form a first contact hole H1. The first contact hole H1 may expose the upper surface of the horizontal conductive line 29 at the first layer L1, ie, the upper surface of the first horizontal conductive line 29A of the first layer L1.

[0183] refer to Fig. 27 , after masking M1 on the first contact hole H1, the hard mask layer pattern HM and the horizontal conductive line DWL of the first layer may be etched to form the second contact hole H2. Similarly, to form the second contact hole H2, the uppermost second dielectric layer 19 and the second dielectric layer 19 between the first layer L1 and the second layer L2 may be etched. The second contact hole H2 may expose the upper surface of the horizontal conductive line 29 of the second layer L2, that is, the upper surface of the first horizontal conductive line 29A of the second layer L2.

[0184] refer to Fig.28, after the first contact hole H1 and the second contact hole H2 are respectively masked M1 and M2, the hard mask layer pattern HM, the horizontal conductive line 29 of the first layer, and the horizontal conductive line 29 of the second layer may be etched to form the third contact hole H3. Similarly, in order to form the third contact hole H3, the second dielectric layer 19 of the uppermost layer, the second dielectric layer 19 between the first layer L1 and the second layer L2, and the second dielectric layer 19 between the second layer L2 and the third layer L3 may be etched. The third contact hole H3 may expose the upper surface of the horizontal conductive line 29 of the third layer L3, that is, the upper surface of the first horizontal conductive line 29A of the third layer.

[0185] refer to Fig.29 , after masking M1, M2, and M3 are performed on the first contact hole H1, the second contact hole H2, and the third contact hole H3, respectively, the hard mask layer pattern HM, the horizontal conductive line 29 of the first layer, the horizontal conductive line 29 of the second layer, and the horizontal conductive line 29 of the third layer may be etched to form a fourth contact hole H4. Similarly, in order to form the fourth contact hole H4, the second dielectric layer 19 of the uppermost layer, the second dielectric layer 19 between the first layer L1 and the second layer L2, the second dielectric layer 19 between the second layer L2 and the third layer L3, and the second dielectric layer 19 between the third layer L3 and the fourth layer L4 may be etched. The fourth contact hole H4 may expose the upper surface of the horizontal conductive line 29 of the fourth layer L4, that is, the upper surface of the first horizontal conductive line 29A of the fourth layer.

[0186] As described above, after forming the first contact hole H1, in order to form the second contact hole H2, the first contact hole H1 is masked by M1. Similarly, when forming the third contact hole H3, the first contact hole H1 and the second contact hole H2 are masked by M1 and M2, and when forming the fourth contact hole H4, the first contact hole H1, the second contact hole H2 and the third contact hole H3 are masked by M1, M2 and M3.

[0187] Through the above series of processes for forming contact holes, the first to fourth contact holes H1, H2, H3 and H4 can be sequentially formed. Therefore, the first contact hole H1 can be shallower than the second contact hole H2, the second contact hole H2 can be shallower than the third contact hole H3, and the third contact hole H3 can be shallower than the fourth contact hole H4. The depths of the contact holes H1 to H4 can gradually become shallower in the direction in which the horizontal conductive lines 29 are stacked (i.e., in the first direction D1).

[0188] According to another embodiment of the present disclosure, the contact holes H1, H2, H3, and H4 may be formed sequentially starting from the deepest contact hole. For example, the fourth contact hole H4, the third contact hole H3, the second contact hole H2, and the first contact hole H1 may be formed in the stated order. Therefore, the order of forming the fourth contact hole H4, the third contact hole H3, the second contact hole H2, and the first contact hole H1 may be modified.

[0189] refer to Fig.30 , contact spacers S1 to S4 may be formed on the sidewalls of the first contact hole H1, the second contact hole H2, the third contact hole H3, and the fourth contact hole H4, respectively. The contact spacers S1 to S4 may be formed by depositing a dielectric material and etching the dielectric material. The contact spacers S1 to S4 may include silicon oxide, silicon nitride, or a combination thereof.

[0190] refer to Fig.31 , contact plugs CT1 to CT4 may be formed in the first contact hole H1, the second contact hole H2, the third contact hole H3, and the fourth contact hole H4, respectively. The contact plugs CT1 to CT4 may include a metal-based material. The contact plugs CT1 to CT4 may include a structure whose height gradually decreases in the direction in which the horizontal conductive lines 29 are stacked (ie, the first direction D1).

[0191] As described above, the second region R2 may include contact structures CS respectively coupled to the horizontal conductive lines 29 of the connection portions PDS. The contact structures CS may include contact plugs CT1, CT2, CT3, and CT4 and contact spacers S1, S2, S3, and S4.

[0192] The first contact plug CT1 may be electrically connected to the horizontal conductive line 29 of the first layer L1. The first contact plug CT1 may be electrically connected to the first horizontal conductive line 29A of the first layer L1. The second contact plug CT2 may be electrically connected to the horizontal conductive line 29 of the second layer L2. The second contact plug CT2 may be electrically connected to the first horizontal conductive line 29A of the second layer L2. The third contact plug CT3 may be electrically connected to the horizontal conductive line 29 of the third layer L3. The third contact plug CT3 may be electrically connected to the first horizontal conductive line 29A of the third layer L3. The fourth contact plug CT4 may be electrically connected to the horizontal conductive line 29 of the fourth layer L4. The fourth contact plug CT4 may be electrically connected to the first horizontal conductive line 29A of the fourth layer L4.

[0193] The first contact spacer S1 may be disposed on the sidewall of the first contact plug CT1, the second contact spacer S2 may be disposed on the sidewall of the second contact plug CT2, the third contact spacer S3 may be disposed on the sidewall of the third contact plug CT3, and the fourth contact spacer S4 may be disposed on the sidewall of the fourth contact plug CT4. The vertical height of the fourth contact plug CT4 may be greater than the vertical height of the third contact plug CT3, the vertical height of the third contact plug CT3 may be greater than the vertical height of the second contact plug CT2, and the vertical height of the second contact plug CT2 may be greater than the vertical height of the first contact plug CT1. Here, the vertical height may refer to the height in the first direction D1.

[0194] The fourth contact plug CT4 and the fourth contact spacer S4 may penetrate the first horizontal conductive line 29A and the second horizontal conductive line 29B and the pad PD of the first layer L1, the second layer L2, and the third layer L3. The fourth contact plug CT4 may be electrically disconnected from the first horizontal conductive line 29A and the second horizontal conductive line 29B and the pad PD of the first layer L1, the second layer L2, and the third layer L3 by the fourth contact spacer S4.

[0195] The third contact plug CT3 and the third contact spacer S3 may penetrate the first and second horizontal conductive lines 29A and 29B and the pad PD of the first and second layers L1 and L2. The third contact plug CT3 may be electrically disconnected from the first and second horizontal conductive lines 29A and 29B and the pad PD of the first and second layers L1 and L2 by the third contact spacer S3.

[0196] The second contact plug CT2 and the second contact spacer S2 may penetrate the first and second horizontal conductive lines 29A and 29B and the pad PD of the first layer L1. The second contact plug CT2 and the first and second horizontal conductive lines 29A and 29B may be electrically disconnected from the pad PD of the first layer L1 by the second contact spacer S2.

[0197] According to the above description, the connection portion PDS of the horizontal conductive line 29 may have a step-free structure. Since the connection portion PDS is formed in the step-free structure, the occupied area (or volume) of the connection portion PDS in the second region R2 may be reduced.

[0198] Figures 32 to 40 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure. Figures 32 to 40 A method of etching a 12-layer connection portion is shown.

[0199] like Figures 4 to 25 As shown, after the horizontal conductive line 29 and the vertical conductive line 33 are formed, a connection portion PDS may be formed at one side edge portion of the horizontal conductive line 29 .

[0200] refer to Fig.25 , the connection portion PDS may include a horizontal conductive line 29 and a pad PD. The pad PD may be disposed between the first horizontal conductive line 29A and the second horizontal conductive line 29B. Each pad PD may be electrically connected to the first horizontal conductive line 29A and the second horizontal conductive line 29B.

[0201] The connection portion PDS may include a plurality of layers L1 to L12. Figures 23 to 31As shown, each of the layers L1 to L12 may include a stack of a first horizontal conductive line G1, a pad PD, and a second horizontal conductive line G2. The connection portion PDS may also include a dummy pad LD and a pad hard mask layer PHM. Hereinafter, for ease of description, the stack of the first horizontal conductive line G1, the pad PD, and the second horizontal conductive line G2 of each layer L1 to L12 will not be shown.

[0202] See also Fig.32 , the pad hole PH may be formed by etching the pad hard mask layer PHM and the dummy pad LD.

[0203] See also Fig.33 , the first etch E1 may be performed by using the first mask layer M1. The first etch E1 may be a single layer etch process, and may etch a first portion of the first layer L1. Four holes may be formed at the first layer L1 through the first etch E1.

[0204] See also Fig.34 , the second mask layer M2 may be formed by thinning the first mask layer M1. When the first mask layer M1 includes a photoresist, the thinning process may refer to a process of reducing the width of the photoresist. The second etch E2 may be performed by using the second mask layer M2. The second etch E2 may be a single-layer etching process. The second portion of the first layer L1 may be etched, and the first portion of the second layer L2 may be etched. The first portion of the first layer L1 and the first portion of the second layer L2 may overlap vertically with each other. During the second etch E2, the first portion of the second layer L2 located below the first portion of the first layer L1 may be etched. As a result of the second etch E2, eight holes may be formed at the first layer L1, and four holes may be formed at the second layer L2.

[0205] refer to Fig.35 , a third mask layer M3 may be formed by thinning the second mask layer M2. A third etch E3 may be performed by using the third mask layer M3. The third etch E3 may be a three-layer etch process, so that the third layer L3, the fourth layer L4, and the fifth layer L5 may be etched. As a result of the third etch E3, three holes may be formed at the first layer L1, the second layer L2, and the third layer L3, two holes may be formed at the fourth layer L4, and one hole may be formed at the fifth layer L5.

[0206] See also Fig.36, by thinning the third mask layer M3, a fourth mask layer M4 may be formed. A fourth etch E4 may be performed by using the fourth mask layer M4. The fourth etch E4 may be a three-layer etch process, so that the sixth layer L6, the seventh layer L7, and the eighth layer L8 may be etched. As a result of the fourth etch E4, six holes may be formed at the first layer L1, the second layer L2, and the third layer L3, five holes may be formed at the fourth layer L4, and four holes may be formed at the fifth layer L5. Three holes may be formed at the sixth layer L6, two holes may be formed at the seventh layer L7, and one hole may be formed at the eighth layer L8.

[0207] refer to Fig.37 , by thinning the fourth mask layer M4, a fifth mask layer M5 may be formed. A fifth etch E5 may be performed by using the fifth mask layer M5. The fifth etch E5 may be a three-layer etch process, so that the ninth layer L9, the tenth layer L10, and the eleventh layer L11 may be etched. As a result of the fifth etch E5, nine holes may be formed at the first layer L1, the second layer L2, and the third layer L3, eight holes may be formed at the fourth layer L4, and seven holes may be formed at the fifth layer L5. Six holes may be formed at the sixth layer L6, and five holes may be formed at the seventh layer L7. Four holes may be formed at the eighth layer L8, and three holes may be formed at the ninth layer L9. Two holes may be formed at the tenth layer L10, and one hole may be formed at the eleventh layer L11.

[0208] refer to Fig.38 , the fifth mask layer M5 can be removed.

[0209] A plurality of contact holes H1 to H12 , for example, 12 contact holes H1 to H12 , may be formed by thinning the mask layers M1 to M5 and etching E1 to E5 as described above. The 12 contact holes H1 to H12 may have different depths. When etching E1 to E5 is performed, the inter-cell dielectric layer 19 may also be etched.

[0210] In another embodiment, the etching process for forming the contact holes H1 to H12 may include a single-layer etching process, a three-layer etching process, a five-layer etching process, or a combination thereof. For example, the etching process for forming the contact holes H1 to H12 may include a single-layer etching of the layers L1 to L12, a three-layer etching of the layers L1 to L12, or a five-layer etching of the layers L1 to L12. Since the layers L1 to L12 may include a stack of conductive layers, the etching process for forming the contact holes H1 to H12 may include a single-layer etching of the conductive layer, a three-layer etching of the conductive layer, or a five-layer etching of the conductive layer. The three-layer etching process is a process that can simultaneously etch three conductive layers, and the five-layer etching process is a process that can simultaneously etch five conductive layers.

[0211] refer to Fig.39, contact spacers S1 to S12 may be formed on sidewalls of the contact holes H1 to H12, respectively. The contact spacers S1 to S12 may be formed by depositing a dielectric material and etching the dielectric material.

[0212] Subsequently, the inter-cell dielectric layer 19 may be etched to be self-aligned with the contact spacers S1 to S12. Therefore, the depths of the contact holes H1 to H12 may become deeper. For example, the contact holes H1 to H12 may expose the surfaces of the corresponding layers L1 to L12, respectively. For example, the contact hole H1 may expose the first layer L1, and the contact hole H12 may expose the twelfth layer L12.

[0213] refer to Fig.40 , contact plugs CT1 to CT12 may be formed in the contact holes H1 to H12, respectively. The contact plugs CT1 to CT12 may include a metal-based material. Among the contact plugs CT1 to CT12, the contact plug CT12 coupled to the horizontal conductive line of the lowermost layer L12 may have the deepest depth. The contact plug CT12 may be called a deep contact plug, and the contact plug CT12 may vertically penetrate the horizontal conductive lines at all layers L1 to L12.

[0214] Figure 41 to Figure 43 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0215] refer to Fig.41 , a stacked body SB10 may be formed on the lower structure 11. The stacked body SB10 may include an alternating stack of a first semiconductor layer and a second semiconductor layer. For example, the alternating stack may include a plurality of silicon germanium layers 12 and a plurality of single crystal silicon layers 14' alternately stacked by an epitaxial growth process. The silicon germanium layer 12 may be a sacrificial layer, and the single crystal silicon layer 14' may be a recessed target layer. The silicon germanium layer 12 may correspond to Figure 4 The first layer 12A or the third layer 12B, and the single crystal silicon layer 14 'may correspond to Figure 4 The fourth layer 14. Figure 4 Different from the stacked body SB of FIG. 1 , the stacked body SB10 may be formed by alternately stacking silicon germanium layers 12 and single crystal silicon layers 14 ′.

[0216] refer to Fig.42 , a hard mask layer pattern HM1 may be formed on the stacked body SB10.

[0217] The stacked body SB10 may be etched by using the hard mask layer pattern HM1 as an etch barrier. As a result, a plurality of first and second vertical openings 15 and 16 may be formed in the stacked body SB10.

[0218] refer to Fig.43 , a preliminary horizontal layer 14A' and a horizontal depression 17 can be formed. Fig.42The recess process of the silicon germanium layer 12 and the single crystal silicon layer 14' is performed to form the preliminary horizontal layer 14A' and the horizontal recess 17. After removing the silicon germanium layer 12, the recess process of the single crystal silicon layer 14' can be performed. The preliminary horizontal layer 14A' can correspond to Figure 6 A preliminary horizontal layer 14A.

[0219] The silicon germanium layer 12 may be recessed by a wet etching process or a dry etching process. The silicon germanium layer 12 may be etched by using an etchant or an etching gas having selectivity with respect to the single crystal silicon layer 14'.

[0220] The recessing process for forming the single crystal silicon layer 14' of the preliminary horizontal layer 14A' may use, for example, HSC1 (Hot SC-1). HSC1 may include ammonium hydroxide (NH4OH) mixed in a ratio of about 1:4:20. 4 OH), hydrogen peroxide (H 2 O 2 ) and water (H 2 The single crystal silicon layer 14' can be selectively etched by using HSC1.

[0221] When the preliminary horizontal layer 14A' is formed, the surface of the lower structure 11 may be recessed to a predetermined depth (see reference numeral '11A'). As a result, the depths of the first and second vertical openings 15 and 16 may be increased.

[0222] Then, you can execute Figures 8 to 31 A series of processes shown in .

[0223] Figures 44 to 46 1 is a perspective view showing a memory cell array according to another embodiment of the present disclosure. The memory cell arrays MCA100, MCA200 and MCA300 may be similar to Figure 3C Therefore, we can refer to the above description of the vertical memory cell array MV1. Figure 3C A detailed description of the constituent elements also appears in.

[0224] The memory cell arrays MCA100 , MCA200 , and MCA300 may include a first region R1 where memory cells are disposed and a second region R2 where a connection portion PDS is disposed.

[0225] refer to Fig.44 , the memory cell array MCA100 may include a plurality of memory cells MC10.

[0226] The memory cell array MCA100 may include a three-dimensional array of memory cells MC10. The three-dimensional array of memory cells MC10 may include a column array of memory cells MC10 and a row array of memory cells MC10. The column array of memory cells MC10 may include a plurality of memory cells MC10 stacked in a first direction D1, and the row array of memory cells MC10 may include memory cells MC10 horizontally arranged in a second direction D2 and a third direction D3.

[0227] Each memory cell MC10 may include a first conductive line BL, a switching element TR, and a data storage element CAP. For detailed description of the first conductive line BL and the data storage element CAP, reference may be made to the above embodiments of the present disclosure.

[0228] The switching element TR may include a horizontal layer HL and a second conductive line DWL. The horizontal layer HL may extend in the second direction D2. The second conductive line DWL may extend in the third direction D3.

[0229] The second conductive line DWL may have a double structure. For example, the second conductive line DWL may include an upper horizontal line G1 and a lower horizontal line G2 facing each other, with a horizontal layer HL interposed therebetween. Figure 1B and Figure 3B As shown, an interlayer dielectric layer GD may be formed on the upper and lower surfaces of the horizontal layer HL.

[0230] Each of the upper horizontal line G1 and the lower horizontal line G2 may include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS may refer to vertical sidewalls. The flat sidewalls FS may have a linear shape extending in the third direction D3.

[0231] The second wire DWL may include a plurality of layers L1, L2, L3, and L4. For example, the first layer L1 may refer to the second wire DWL of the uppermost layer, and the fourth layer L4 may refer to the second wire DWL of the lowermost layer. The second layer L2 may be a layer lower than the first layer L1, and the third layer L3 may be a layer lower than the second layer L2. The fourth layer L4 may be a layer lower than the third layer L3. The fourth layer L4, the third layer L3, the second layer L2, and the first layer L1 may be stacked in the first direction D1 in the stated order. Each second wire DWL of the layers L1 to L4 may include a pair of upper horizontal lines G1 and lower horizontal lines G2.

[0232] The connection portion PDS of the second conductive line DWL may include a plurality of layers L1, L2, L3, and L4. In the connection portion PDS, each second conductive line DWL of the layers L1 to L4 may include a pair of an upper horizontal line G1 and a lower horizontal line G2. In the connection portion PDS, the layers L1 to L4 may further include a pad PD. The pad PD may be disposed between the upper horizontal line G1 and the lower horizontal line G2. The pad PD may be electrically connected to the upper horizontal line G1 and the lower horizontal line G2.

[0233] The horizontal lengths of the pads PD in the third direction D3 may be the same. The pads PD and the horizontal layer HL may be spaced apart from each other. The pads PD may not be disposed in the first region R1.

[0234] In the connection portion PDS, the layers L1 to L4 may contact the contact structure CS.

[0235] refer to Fig.45 , the memory cell array MCA200 may include a plurality of memory cells MC20.

[0236] The memory cell array MCA200 may include a three-dimensional array of memory cells MC20. The three-dimensional array of memory cells MC20 may include a column array of memory cells MC20 and a row array of memory cells MC20. The column array of memory cells MC20 may include a plurality of memory cells MC20 stacked in a first direction D1, and the row array of memory cells MC20 may include a plurality of memory cells MC20 horizontally arranged in a second direction D2 and a third direction D3.

[0237] Each memory cell MC20 may include a first conductive line BL, a switching element TR, and a data storage element CAP. For detailed description of the first conductive line BL and the data storage element CAP, reference may be made to the above embodiments of the present disclosure.

[0238] The switching element TR may include a horizontal layer HL and a second conductive line SWL. The horizontal layer HL may extend in the second direction D2. The second conductive line SWL may extend in the third direction D3.

[0239] The second conductive line SWL may have a single structure. For example, the second conductive line SWL may be disposed on the horizontal layer HL. Figure 1B and Figure 3B As shown, the interlayer dielectric layer GD may be formed between the upper surface of the horizontal layer HL and the second conductive line SWL. According to another embodiment of the present disclosure, the second conductive line SWL may be disposed below the horizontal layer HL.

[0240] The second conductive line SWL may include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS may also be referred to as "vertical sidewalls".

[0241] According to another embodiment of the present disclosure, Figure 1C As shown, the second conductive line SWL may include a channel overlapping portion WLP and a channel non-overlapping portion NOL.

[0242] The second wire SWL may include a plurality of layers L1, L2, L3, and L4. For example, the first layer L1 may refer to the second wire SWL of the uppermost layer, and the fourth layer L4 may refer to the second wire SWL of the lowermost layer. The second layer L2 may be a layer lower than the first layer L1, and the third layer L3 may be a layer lower than the second layer L2. The fourth layer L4 may be a layer lower than the third layer L3. The fourth layer L4, the third layer L3, the second layer L2, and the first layer L1 may be stacked in the first direction D1 in the stated order. Each second wire SWL of the layers L1 to L4 may have a single structure.

[0243] The connection portion PDS of the second wire SWL may include a plurality of layers L1, L2, L3, and L4. Each of the second wires SWL of the layers L1 to L4 in the connection portion PDS may have a single structure. The layers L1 to L4 of the connection portion PDS may directly contact the contact structure CS.

[0244] Reference Fig.46 , the memory cell array MCA300 may include a plurality of memory cells MC30.

[0245] The memory cell array MCA300 may include a three-dimensional array of memory cells MC30. The three-dimensional array of memory cells MC30 may include a column array of memory cells MC30 and a row array of memory cells MC30. The column array of memory cells MC30 may include a plurality of memory cells MC30 stacked in a first direction D1, and the row array of memory cells MC30 may include a plurality of memory cells MC30 horizontally arranged in a second direction D2 and a third direction D3.

[0246] Each memory cell MC30 may include a first conductive line BL, a switching element TR, and a data storage element CAP. For detailed description of the first conductive line BL and the data storage element CAP, reference may be made to the above embodiments.

[0247] The switching element TR may include a horizontal layer HL and a second conductive line GAA-WL. The horizontal layer HL may extend in the second direction D2. The second conductive line GAA-WL may extend in the third direction D3.

[0248] The second conductive line GAA-WL may have a fully surrounding gate structure GAA. For example, the second conductive line GAA-WL may extend in the third direction D3 while surrounding the horizontal layer HL. An interlayer dielectric layer GD may be formed between the horizontal layer HL and the second conductive line GAA-WL. The interlayer dielectric layer GD may surround each horizontal layer HL.

[0249] The second conductive line GAA-WL may include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS may also be referred to as "vertical sidewalls".

[0250] The second conductive line GAA-WL may include a plurality of layers L1, L2, L3, and L4. For example, the first layer L1 may refer to the second conductive line GAA-WL of the uppermost layer, and the fourth layer L4 may refer to the second conductive line GAA-WL of the lowermost layer. The second layer L2 may be a layer lower than the first layer L1, the third layer L3 may be a layer lower than the second layer L2, and the fourth layer L4 may be a layer lower than the third layer L3. The fourth layer L4, the third layer L3, the second layer L2, and the first layer L1 may be stacked in the first direction D1 in the stated order. Each second conductive line GAA-WL of the layers L1 to L4 may have a fully surrounding gate structure.

[0251] The connection portion PDS of the second conductive line GAA-WL may include a plurality of layers L1, L2, L3, and L4. Each second conductive line GAA-WL of the layers L1 to L4 in the connection portion PDS may have a full-surround gate structure. The layers L1 to L4 of the connection portion PDS may directly contact the contact structure CS.

[0252] According to another embodiment of the present disclosure, each memory cell may include a first conductive line BL extending horizontally in a third direction D3, a second conductive line DWL extending vertically in the first direction D1, and a horizontal layer HL extending horizontally in the second direction D2. The second conductive line DWL may have a dual structure, which may be replaced by a single structure or a fully surrounding gate structure.

[0253] According to another embodiment of the present disclosure, the semiconductor device may include: a plurality of first conductive layers 29 vertically stacked on the lower structure 11 of the first region R1 in the first direction D1; a second region R2 including a plurality of second conductive layers L1 to L4, which are stacked on the lower structure 11 of the region R2 in the first direction D1 and have the same horizontal length; and a plurality of contact structures CS, respectively coupled to the second conductive layers L1 to L4. Each of the second conductive layers L1 to L4 may include a first horizontal conductive wire 29A, a second horizontal conductive wire 29B, and a pad PD located between the first horizontal conductive wire 29A and the second horizontal conductive wire 29B. The horizontal lengths of the first horizontal conductive wire 29A, the second horizontal conductive wire 29B, and the pad PD in the third direction D3 may be the same. The first conductive layer 29 may also include a first horizontal conductive wire 29A, a second horizontal conductive wire 29B, and a horizontal layer HL located between the first horizontal conductive wire 29A and the second horizontal conductive wire 29B. The first conductive layer 29 may correspond to Fig.31 The second conductive layers L1 to L4 may correspond to the horizontal conductive lines 29 of Fig.31 Layers L1 to L4.

[0254] Since the connection portion of the wire is formed in a step-free structure according to the present technical level, the occupied area (or volume) of the connection portion can be reduced.

[0255] Although the embodiments of the present disclosure have been described with respect to specific embodiments, it is apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present disclosure as defined in the appended claims. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should include equivalents thereof.

[0256] In the above-described embodiments, all operations may be selectively performed, or some operations may be omitted. In each embodiment, the operations are not necessarily performed in the order described, and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are only examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be understood by those skilled in the art that various modifications may be made on the basis of the technical scope of the present disclosure.

[0257] The embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used here, these terms are only used to describe the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-mentioned embodiments, and many modifications can be made within the scope of the present disclosure. For those skilled in the art, it is obvious that in addition to the embodiments disclosed herein, multiple modifications can also be made on the basis of the technical scope of the present disclosure. In addition, these embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: Lower structure; a first region including a plurality of first conductive layers vertically stacked in a first direction on the lower structure; a second region including a plurality of second conductive layers stacked in the first direction, the second conductive layers having the same horizontal length; as well as a plurality of contact structures, which are respectively coupled to the second conductive layer, Wherein, each of the second conductive layers comprises: A first horizontal conductor; a second horizontal conductive line; and A pad is located between the first horizontal conductive line and the second horizontal conductive line.

2. The semiconductor device according to claim 1, wherein The first horizontal conductive line, the second horizontal conductive line, and the pad have the same horizontal length.

3. The semiconductor device according to claim 1, wherein Each of the first conductive layers comprises: an upper horizontal conductor extending from the first horizontal conductor; and A lower horizontal wire extends from the second horizontal wire.

4. The semiconductor device according to claim 1, wherein: Each of the first conductive layers comprises: an upper horizontal conductor extending from the first horizontal conductor; a lower horizontal conductor extending from the second horizontal conductor; and A horizontal layer is located between the first horizontal conductive line and the second horizontal conductive line.

5. The semiconductor device according to claim 1, wherein Each of the contact structures comprises: a plurality of contact plugs respectively coupled to the second conductive layer; and Contact spacers are respectively disposed on side walls of the contact plugs.

6. The semiconductor device according to claim 1, wherein Each of the contact structures comprises: a plurality of contact plugs, which are respectively coupled to the second conductive layer, and The contact plug has a structure in which a height gradually decreases in a direction in which the second conductive layer is stacked.

7. The semiconductor device according to claim 1, wherein The contact structure comprises: a deep contact plug coupled to a lowermost second conductive layer among the second conductive layers, and The deep contact plug includes a shape vertically penetrating the second conductive layer.

8. The semiconductor device according to claim 1, wherein The first conductive layer and the second conductive layer include the same material.

9. A method for manufacturing a semiconductor device, the method comprising: forming a first stack of first conductive layers over the lower structure, each of the first conductive layers comprising a pair of upper horizontal conductive lines and a lower horizontal conductive line; forming a second stack of second conductive layers above the lower structure, each of the second conductive layers comprising a first horizontal conductive line, a second horizontal conductive line, and a pad located between the first horizontal conductive line and the second horizontal conductive line; forming a contact hole in the second stack, wherein the height of the contact hole gradually decreases in the direction of the second conductive layer stack; as well as Contact plugs respectively coupled to the second conductive layers exposed by the contact holes are formed.

10. The method according to claim 9, wherein: The first horizontal conductive line, the second horizontal conductive line, and the pad are formed to have the same horizontal length.

11. The method according to claim 9, wherein: Forming the contact hole comprises: The second stack is etched into a step-free structure using multiple masks and multiple etching processes.

12. The method according to claim 9, wherein: The contact hole comprises: The shape of the second conductive layer sequentially penetrating the second stack in the direction in which the second conductive layer is stacked.

13. The method according to claim 9, wherein: The first horizontal conductive line extends from the upper horizontal conductive line, and The second horizontal conductive line extends from the lower horizontal conductive line.

14. The method according to claim 9, wherein: The first stack further comprises: The upper horizontal conductive line and the lower horizontal conductive line are horizontal layers.

15. The method according to claim 9, further comprising: After forming the contact hole, a contact spacer is formed on a sidewall of the contact hole.

16. The method according to claim 9, wherein: Forming the contact hole comprises: The contact control is formed by etching the second conductive layer. Wherein, the etching process includes a single-layer etching process, a three-layer etching process, a five-layer etching process or a combination thereof.

17. A semiconductor device comprising: Lower structure; a cell array region including a plurality of horizontal conductive lines vertically stacked in a first direction on the lower structure; a connection region comprising a plurality of layers stacked in the first direction and having the same horizontal length; as well as a plurality of contact structures respectively coupled to the layers, Wherein, each of the layers comprises: A first horizontal conductor; a second horizontal conductive line; and A pad is located between the first horizontal conductive line and the second horizontal conductive line.

18. A semiconductor device comprising: an alternating stack of conductive and dielectric layers disposed over a lower structure; as well as an array of contact plugs arranged in the alternating stack, the contact plugs being horizontally spaced apart from each other in a first horizontal direction and having different heights, wherein the top surfaces of the contact plugs are arranged on the same horizontal plane, and the bottoms of the contact plugs are respectively coupled to the conductive layers, and The contact plug penetrating the uppermost conductive layer is laterally surrounded by the conductive layer and is laterally surrounded by the conductive layer located above the conductive layer adjacent to the contact structure.

Images