Semiconductor device

Abstract

A semiconductor device includes a bottom electrode, a top electrode, and a phase change memory structure. The top electrode is disposed on the bottom electrode. The phase change memory structure is disposed between the top electrode and the bottom electrode. The semiconductor device can reduce power consumption and improve charge transfer speed, thereby providing application potential for high-density semiconductor devices.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Phase-change memory (PCM) is a non-volatile memory technology that uses the special properties of chalcogenide glass to store data. The operating principle of PCM is to switch the phase of the chalcogenide material between an amorphous state and a crystalline state. The amorphous state has high resistance, while the crystalline state has low resistance, thus enabling binary data storage. PCM is known for its high durability, fast read and write speeds, and good scalability, and is a promising alternative to traditional flash memory. However, challenges such as high power consumption and low charge transfer speed have affected its integration into mainstream memory solutions. Summary of the invention

[0003] According to one or more embodiments of the present invention, a semiconductor device includes a bottom electrode, a top electrode, and a phase change memory structure. The top electrode is disposed on the bottom electrode. The phase change memory structure is disposed between the top electrode and the bottom electrode.

[0004] In one or more embodiments of the present invention, the top electrode comprises graphene.

[0005] In one or more embodiments of the present invention, the bottom electrode and the top electrode each include nitrogen-doped graphene.

[0006] In one or more embodiments of the present invention, the phase change memory structure includes germanium antimony telluride, germanium antimony silicon, antimony tritelluride, digermanium hexatelluride dichromium, germanium telluride, vanadium dioxide, molybdenum dioxide, vanadium trioxide, tantalum dioxide, iron tetroxide, ferrous sulfide, titanium pentoxide, lanthanum cobaltate, samarium nickelate, titanium trioxide, tantalum pentoxide or a combination thereof.

[0007] In one or more embodiments of the present invention, the length of the phase change memory structure extending from the top electrode to the bottom electrode is 100 nanometers to 200 nanometers.

[0008] In one or more embodiments of the present invention, the width of the phase change memory structure extending parallel to the top surface of the bottom electrode is 50 nanometers to 100 nanometers.

[0009] In one or more embodiments of the present invention, a width of the bottom electrode extending along a top surface of the bottom electrode is greater than a width of the phase change memory structure extending along the top surface of the bottom electrode.

[0010] In one or more embodiments of the present invention, the semiconductor device further includes a first insulating structure and a second insulating structure disposed on the bottom electrode, wherein the phase change memory structure is laterally sandwiched by the first insulating structure and the second insulating structure in a cross section of the semiconductor device.

[0011] In one or more embodiments of the present invention, the first insulating structure and the second insulating structure respectively contact opposite side walls of the phase change memory structure.

[0012] According to one or more embodiments of the present invention, a semiconductor device includes two electrodes, a plurality of phase change memory structures and an insulating structure. At least one of the two electrodes includes graphene. The plurality of phase change memory structures are disposed between the two electrodes and contact different portions of at least one of the two electrodes. The insulating structure laterally surrounds each of the phase change memory structures.

[0013] In one or more embodiments of the present invention, the other of the two electrodes includes nitrogen-doped graphene.

[0014] In one or more embodiments of the present invention, each of the phase change memory structures includes chromium germanium telluride, germanium antimony telluride, silicon germanium antimony, antimony telluride, germanium telluride, iron sulfide, vanadium dioxide, molybdenum dioxide, vanadium trioxide, niobium dioxide, iron tetroxide, tantalum pentoxide, titanium pentoxide, lanthanum cobaltate, samarium nickelate, titanium trioxide or a combination thereof.

[0015] In one or more embodiments of the present invention, the cross-sectional shape of each phase change memory structure is a regular hexagon.

[0016] In one or more embodiments of the present invention, a distance between any two adjacent phase change memory structures is 50 nanometers to 100 nanometers.

[0017] In one or more embodiments of the present invention, each of the phase change memory structures extends from an inner surface of one of the two electrodes to an inner surface of the other of the two electrodes, and a sidewall of each of the phase change memory structures is straight.

[0018] According to one or more embodiments of the present invention, a semiconductor device includes a bottom electrode, a top electrode, and at least one phase change memory structure, and can be applied to the field of phase change memory. Since at least the bottom electrode for triggering the phase change of the phase change memory structure includes graphene, the material has high carrier mobility, low resistance, excellent thermal conductivity, and flexible electronic properties, so it can reduce power consumption and increase charge transfer speed, thereby providing application potential for high-density semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to make the above and other objects, features, advantages and embodiments of the present invention more clearly understood, the accompanying drawings are described as follows:

[0020] Figure 1 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0021] Figure 2 for Figure 1 The state of the semiconductor device in when it is first triggered by a voltage pulse;

[0022] Figure 3 for Figure 1 The state of a semiconductor device in a device when it is continuously triggered by a voltage pulse;

[0023] Figure 4 are schematic cross-sectional views of semiconductor devices according to some other embodiments of the present invention;

[0024] Figure 5A , Figure 5B and Figure 5C are schematic cross-sectional views of phase change memory structures according to different embodiments of the present invention; and

[0025] Fig. 6A and Figure 6B Schematic cross-sectional views of phase change memory structure arrangements according to different embodiments of the present invention. DETAILED DESCRIPTION

[0026] The following will disclose multiple embodiments of the present invention with the accompanying drawings. For the purpose of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is to say, in some embodiments of the present invention, these practical details are not necessary and therefore should not be used to limit the present invention. In addition, in order to simplify the drawings, some conventional structures and components will be illustrated in a simple schematic manner in the drawings. In addition, for the convenience of readers, the sizes of the components in the drawings are not drawn according to the actual scale.

[0027] It should be understood that although the terms "first", "second", and "third" etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the "first element", "component", "region", "layer" or "part" described below may also be referred to as the second element, component, region, layer or part without departing from the teachings of this article.

[0028] It should be understood that relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element, as shown in the accompanying drawings. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if the device in a figure is turned over, the elements described as being on the "lower" side of other elements will be oriented on the "upper" side of the other elements. Therefore, the exemplary term "lower" can include both "lower" and "upper" orientations, depending on the specific orientation of the figure. Similarly, if the device in a figure is turned over, the elements described as being "lower" or "below" other elements will be oriented as being "above" other elements. Therefore, the exemplary terms "lower" or "below" can include both upper and lower orientations.

[0029] refer to Figure 1 , which is a schematic cross-sectional view of a semiconductor device 100 according to some embodiments of the present invention. The semiconductor device 100 includes two electrodes (i.e., a bottom electrode 110 and a top electrode 120) and a phase change memory structure 130. The top electrode 120 is disposed on the bottom electrode 110, and the phase change memory structure 130 is disposed between the top electrode 120 and the bottom electrode 110 and contacts the top electrode 120 and the bottom electrode 110. The semiconductor device 100 can be applied to the field of phase change memory, for example, as a storage device. During use, current passes through the bottom electrode 110 and the top electrode 120. By controlling the intensity and duration of the voltage pulse, data storage and reading in the semiconductor device 100 can be achieved. Specifically, when the phase change memory structure 130 is subjected to a low-power and long-term voltage pulse, its material will crystallize to form an ordered lattice structure, presenting a crystalline state with high conductivity; when the phase change memory structure 130 is subjected to a high-power and short-term voltage pulse, the atoms of its material will be randomly arranged to form an amorphous state with low conductivity.

[0030] In the present invention, the bottom electrode 110 includes graphene. Selecting graphene as the material of the bottom electrode 110 can well control the phase transition between the amorphous state and the crystalline state of the phase change memory structure 130, thereby greatly improving the read and write performance of the semiconductor device 100. Therefore, the semiconductor device 100 can be reduced to the nanoscale, thereby improving the integration density of various electronic components in the semiconductor device 100. Specifically, the excellent conductivity of graphene at the nanoscale stems from its ballistic transport properties, that is, electrons move in a manner with minimal scattering, resulting in extremely low resistance. Its atomic-scale thickness and two-dimensional lattice structure provide an ideal channel for electrons, reducing interference and energy loss. In addition, strong carbon-carbon bonds and minimal defects further enhance its conductive path, allowing electrons to flow efficiently even at extremely small scales. These properties make graphene perform well in nanoscale applications that require precise and efficient conductivity.

[0031] In some embodiments, the top electrode 120 also includes graphene. In other words, the bottom electrode 110 and the top electrode 120 are made of the same material. In this way, the electrical performance brought by graphene can be further improved. In addition, using the same material as the top electrode 120 and the bottom electrode 110 can simplify the manufacturing process and reduce variability, thereby improving production yield and consistency. This consistency also improves interface compatibility, minimizes defects and instabilities at the interface between the electrode and the memory material, and improves device performance. In addition, consistency ensures symmetrical electrical properties, enhances read and write performance and reduces variability. In addition, matching thermal expansion coefficients between the same materials can reduce stress caused by thermal cycling and improve the stability and life of the device. In short, the overall chemical stability is improved because the risk of unwanted reactions or diffusion between different materials is reduced, thereby promoting long-term reliability.

[0032] In some embodiments, the phase change memory structure 130 may include a germanium antimony telluride alloy (e.g., germanium antimony telluride (GeSbTe)), germanium antimony silicon (SiGeSb), antimony tritelluride (Sb2Te3), germanium telluride (GeTe), chromium digermanium hexatelluride (Cr2Ge2Te6), vanadium dioxide (VO2), molybdenum dioxide (MoO2), vanadium trioxide (V2O3), niobium dioxide (NbO2), iron tetraoxide (Fe3O4), titanium trioxide (Ti3O5), titanium trioxide (Ti2O3), ferrous sulfide (FeS), tantalum pentoxide (Ta2O5), lanthanum cobalt oxide (LaCoO3), samarium nickel oxide (SmNiO3), or a combination thereof. In some embodiments, the bottom electrode 110 and the top electrode 120 may each include nitrogen-doped graphene, and the phase change memory structure 130 may include GeSbTe. Nitrogen-doped graphene has significant advantages when paired with GeSbTe. First, it enhances conductivity and improves charge transfer efficiency, resulting in faster switching speeds and lower power consumption. Second, it provides greater stability, maintaining the integrity of GeSbTe during phase changes due to its better thermal and chemical stability. Third, it reduces contact resistance, minimizes energy losses at the interface between the electrode and the memory material, and improves memory cell efficiency. In addition, nitrogen-doped graphene ensures a uniform interface with GeSbTe, promoting consistent switching behavior between memory cells. Furthermore, its high temperature tolerance further supports stable performance in high temperature environments and extends the service life of the device by reducing degradation at the interface between the electrode and the memory material. In summary, these characteristics highlight the applicability of nitrogen-doped graphene in optimizing the performance, efficiency, and durability of GeSbTe-based memory devices (semiconductor device 100).

[0033] In general, compared with traditional electrode materials such as silver and copper, the combination of nitrogen-doped graphene electrodes and GeSbTe phase change memory structure 130 can greatly reduce the power consumption of the semiconductor device 100 and significantly improve the charge transfer speed, thereby providing the applicability of high-density semiconductor devices.

[0034] refer to Figures 2 to 3 ,in Figure 2 for Figure 1 The semiconductor device 100 is in the state when it is first triggered by a voltage pulse, and Figure 3 for Figure 1 The state of the semiconductor device 100 when it is continuously triggered by a voltage pulse. Specifically, the material of the phase change memory structure 130 may initially be a lattice structure (crystalline state) 130a (see Figure 1 ), when the phase change memory structure 130 is subjected to a high power and short time pulse, the atoms in the material begin to randomly arrange near the bottom electrode 110 and the top electrode 120, forming an amorphous state 130b with low conductivity (see Figure 2 ). Further, when the phase change memory structure 130 is continuously subjected to a high power and short time pulse, the entire phase change memory structure 130 is transformed into an amorphous state 130b (see Figure 3 ). Since the charge transfer speed is significantly improved by the combination of the (nitrogen-doped) graphene electrode and the GeSbTe phase change memory structure 130, the phase transition time of the phase change memory structure 130 from the crystalline state to the amorphous state (or from the amorphous state to the crystalline state) can range from milliseconds to sub-nanoseconds, thereby significantly reducing power consumption.

[0035] Reference again Figure 1In some embodiments, the phase change memory structure 130 can be reduced to a nanometer scale. For example, the phase change memory structure 130 can extend from the bottom surface 121 (inner surface) of the top electrode 120 to the top surface 111 (inner surface) of the bottom electrode 110, wherein the length L of the phase change memory structure 130 from the top electrode 120 to the bottom electrode 110 (i.e., the distance D from the bottom surface 121 of the top electrode 120 to the top surface 111 of the bottom electrode 110) is 100 nanometers to 200 nanometers (e.g., 110 nanometers, 120 nanometers, 130 nanometers, 140 nanometers, 150 nanometers, 160 nanometers, 170 nanometers, 180 nanometers, 190 nanometers), and the width W is the width of the phase change memory structure 130 in the direction perpendicular to the length L (extending in a direction parallel to the top surface 111 of the bottom electrode 110) is 50 nanometers to 100 nanometers (e.g., 60 nanometers, 70 nanometers, 80 nanometers, 90 nanometers). Since the phase change memory structure 130 of the present invention can be reduced to nanometer scale, it has many advantages, such as shorter electron paths leading to increased speed, reduced power consumption, higher storage density, reduced production costs, improved heat management, and more innovative design possibilities. These advantages make memory technology faster, more efficient and cost-effective.

[0036] In addition, since the width W of the phase change memory structure 130 is relatively small, the contact area with the electrodes (i.e., the top electrode 120 and the bottom electrode 110) can be minimized. In this way, the energy required for read and write operations can be reduced by concentrating heat in a smaller area, and the read and write speed can be increased by inducing phase change (phase switching) more quickly. In addition, thermal control is improved by limiting heat diffusion, leakage current is reduced, and the durability of the phase change memory structure 130 is increased by reducing thermal stress and material degradation.

[0037] In some embodiments, the semiconductor device 100 further includes a first insulating structure 140 and a second insulating structure 150 disposed on the bottom electrode 110, wherein the phase change memory structure 130 is viewed from a side cross-sectional view (cross-sectional view) of the semiconductor device. Figure 1In some embodiments, the first insulating structure 140 and the second insulating structure 150 are disposed (sandwiched) between and in contact with the top electrode 120 and the bottom electrode 110. In some embodiments, the top surface 131 of the phase-change memory structure 130, the top surface 141 of the first insulating structure 140, and the top surface 151 of the second insulating structure 150 are coplanar and contact the top electrode 120; similarly, the bottom surface 132 of the phase-change memory structure 130, the bottom surface 142 of the first insulating structure 140, and the bottom surface 152 of the second insulating structure 150 are coplanar and contact the bottom electrode 110. Therefore, the phase-change memory structure 130, the first insulating structure 140, and the second insulating structure 150 have the same length (i.e., length L), which can improve the durability of the semiconductor device 100.

[0038] The first insulating structure 140 and the second insulating structure 150 can protect the phase change memory structure 130 from current leakage, thereby ensuring data integrity, and can limit heat within the phase change region, improve thermal efficiency and reduce the energy required for phase switching. In addition, the first insulating structure 140 and the second insulating structure 150 can protect the semiconductor device 100 from external interference and damage, thereby improving its durability, and maintain the stability and performance of the semiconductor device 100 by preventing unnecessary chemical reactions and element diffusion. In some embodiments, the first insulating structure 140 and the second insulating structure 150 may include materials such as Al2O3, ZrO2 or a combination thereof to better achieve the above effects. In some embodiments, the first insulating structure 140 and the second insulating structure 150 are respectively in contact with the opposite side walls of the phase change memory structure 130 (i.e., the entire first side wall 133 and the entire second side wall 134), so that there is no gap between the insulating structure (i.e., the first insulating structure 140 and the second insulating structure 150) and the phase change memory structure 130. In this way, the first insulating structure 140 and the second insulating structure 150 can provide better protection for the phase change memory structure 130 .

[0039] In some embodiments, the width W1 of the bottom electrode 110 (extending in parallel along the top surface 111 of the bottom electrode 110) is greater than the width W of the phase change memory structure 130 (extending in parallel along the top surface 111 of the bottom electrode 110). In this way, a plurality of phase change memory structures 130 can be disposed on the bottom electrode 110, which helps to improve the integration density of various electronic components in the semiconductor device 100. For more details, please refer to Figure 4, which is a schematic cross-sectional (cross-sectional) diagram of a semiconductor device 100a according to some other embodiments of the present invention. The difference between the semiconductor device 100a and the semiconductor device 100 is that the semiconductor device 100a includes a plurality of phase change memory structures 130 disposed between the top electrode 120 and the bottom electrode 110, and respectively contacting different portions of the bottom electrode 110 (top electrode 120), and the insulating structure 160 is disposed on the bottom electrode 110 and closely surrounds each phase change memory structure 130 from the side. It should be understood that, except for the number of phase change memory structures 130, other features (e.g., materials) and configurations of the phase change memory structure 130 and the insulating structure 160 can refer to the above-mentioned phase change memory structure 130 and the first insulating structure 140 and the second insulating structure 150, respectively, and will not be repeated here.

[0040] refer to Figure 5A , Figure 5B and Figure 5C , which are schematic cross-sectional (cross-sectional) views of a phase change memory structure 130 according to different embodiments of the present invention. In detail, Figure 5A , Figure 5B and Figure 5C The cross section shown is a cross section along the width W direction of the phase change memory structure 130. In other words, Figure 5A , Figure 5B and Figure 5C The cross section shown can be considered as a top view of the phase change memory structure 130. Figure 5A , Figure 5B and Figure 5C As shown, the cross-sectional shape of the phase change memory structure 130 can be a square, a circle, or a regular hexagon. Figure 1 ) is straight, so the phase change memory structure 130 can be a prism or a cylinder. These shapes are easy to manufacture. In some preferred embodiments, the cross-sectional shape (cross-sectional shape) of the phase change memory structure 130 is a regular hexagon. This shape can provide a higher arrangement density of the phase change memory structure 130.

[0041] At the same time, when the cross-sectional shape of the phase change memory structure 130 is a square, the width W of the phase change memory structure 130 is the diagonal length of the square; when the cross-sectional shape of the phase change memory structure 130 is a circle, the width W of the phase change memory structure 130 is the diameter of the circle; when the cross-sectional shape of the phase change memory structure 130 is a regular hexagon, the width W of the phase change memory structure 130 is the diagonal length of the regular hexagon. In some embodiments, the corners R of the phase change memory structure 130 may be sharp corners for ease of manufacturing. In some preferred embodiments, the corners R of the phase change memory structure 130 may be rounded to manage heat accumulation. Specifically, rounded corners can distribute heat more evenly, reduce stress, and improve thermal stability, which helps to enhance the performance and life of the device.

[0042] refer to Fig. 6A and Figure 6B , these figures are schematic cross-sectional views (cross-sectional views) of the arrangement of phase change memory structures 130 according to different embodiments of the present invention. In some embodiments, the phase change memory structures 130 may be arranged at intervals. Fig. 6A As shown, in some embodiments, the phase change memory structure 130 can be arranged in an array. The array arrangement improves scalability, thereby achieving higher storage density. In addition, the array arrangement enhances performance through parallel processing, improves reliability and manages heat more effectively. Figure 6B As shown, in some other embodiments, the PCM structures 130 may be arranged in a staggered manner. The staggered arrangement improves thermal management by better dissipating heat and reducing crosstalk between the PCM structures 130, thereby enhancing the reliability and extending the life of the PCM structures 130.

[0043] In some embodiments, the distance between any two phase change memory structures 130 is 50 nanometers to 100 nanometers (e.g., 60 nanometers, 70 nanometers, 80 nanometers, 90 nanometers). The "distance" here refers to the minimum distance from the sidewall of one phase change memory structure 130 to the sidewall of an adjacent phase change memory structure 130. Too large a distance between the phase change memory structures 130 may lead to challenges in achieving precise and uniform heating during the phase change process. This may result in variability in the crystallization or amorphization process of different phase change memory structures 130, resulting in reduced consistency in data storage and retrieval. On the contrary, if the distance between the phase change memory structures 130 is too small, it may limit the heat dissipation between the phase change memory structures 130, resulting in local overheating, which may cause early wear or degradation of the material. Therefore, maintaining the optimal distance between the phase change memory structures 130 is critical to ensuring consistent and reliable phase change behavior, and is equally important for the efficient operation and durability of phase change memory technology.

[0044] According to the above embodiments, the semiconductor device of the present invention can be applied to the field of phase change memory and can be a memory device. The semiconductor device includes a bottom electrode, a top electrode and at least one phase change memory structure, and can be applied to the field of phase change memory. Since at least the bottom electrode for triggering the phase switching of the phase change memory structure contains graphene, and graphene has high carrier mobility, low resistance, excellent thermal conductivity and flexible electronic properties, it can reduce power consumption and increase charge transfer speed, thereby providing the application possibility of high-density semiconductor devices.

[0045] Although the present invention has been disclosed as above in the form of implementation modes, it is not intended to limit the present invention. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the attached claims.

[0046]

Explanation of symbols

[0047] 100,100a:Semiconductor device

[0048] 110: Bottom electrode

[0049] 111: Top

[0050] 120: Top electrode

[0051] 121: Bottom

[0052] 130: Phase Change Memory Structure

[0053] 130a: Crystalline

[0054] 130b: Amorphous

[0055] 131: Top

[0056] 132: Bottom surface

[0057] 133: First side wall

[0058] 134: Second side wall

[0059] 140: First insulation structure

[0060] 141: Top

[0061] 142: Bottom

[0062] 150: Second insulation structure

[0063] 151: Top

[0064] 152: Bottom

[0065] 160: Insulation structure

[0066] L: Length

[0067] D: Distance

[0068] W: Width

[0069] W1: Width

[0070] R: Corner.

Claims

1. A semiconductor device, characterized in that: include: a bottom electrode including graphene; A top electrode disposed on the bottom electrode; as well as A phase change memory structure is arranged between the top electrode and the bottom electrode. The semiconductor device of claim 1 , wherein the top electrode comprises graphene. 3 . The semiconductor device of claim 2 , wherein the bottom electrode and the top electrode each comprise nitrogen-doped graphene.

4. The semiconductor device of claim 1 , wherein the phase change memory structure comprises germanium antimony telluride, germanium antimony silicon, antimony tritelluride, digermanium hexatelluride dichromium, germanium telluride, vanadium dioxide, molybdenum dioxide, vanadium trioxide, cadmium dioxide, ferrous iron tetroxide, ferrous sulfide, titanium pentoxide, titanium trioxide, tantalum pentoxide, lanthanum cobaltate, samarium nickelate, or a combination thereof. 5 . The semiconductor device according to claim 1 , wherein a length of the phase change memory structure extending from the top electrode to the bottom electrode is 100 nanometers to 200 nanometers. 6 . The semiconductor device according to claim 1 , wherein a width of the phase change memory structure extending parallel to a top surface of the bottom electrode is 50 nanometers to 100 nanometers. 7 . The semiconductor device of claim 1 , wherein a width of the bottom electrode extending along a top surface of the bottom electrode is greater than a width of the phase change memory structure extending along the top surface of the bottom electrode.

8. The semiconductor device according to claim 1, wherein Further including: A first insulating structure and a second insulating structure are disposed on the bottom electrode, wherein the phase change memory structure is laterally sandwiched by the first insulating structure and the second insulating structure in a cross section of the semiconductor device. 9 . The semiconductor device according to claim 8 , wherein the first insulating structure and the second insulating structure contact opposite sidewalls of the phase change memory structure, respectively.

10. A semiconductor device, characterized in that: include: two electrodes, wherein at least one of the two electrodes comprises graphene; a plurality of phase change memory structures disposed between the two electrodes and contacting different portions of at least one of the two electrodes; and The insulating structure laterally surrounds each of the plurality of phase change memory structures. The semiconductor device according to claim 10 , wherein the other of the two electrodes comprises nitrogen-doped graphene.

12. The semiconductor device of claim 10, wherein each of the plurality of phase change memory structures comprises chromium germanium telluride, germanium antimony telluride, silicon germanium antimony, antimony telluride, germanium telluride, iron sulfide, vanadium dioxide, molybdenum dioxide, vanadium trioxide, niobium dioxide, iron tetroxide, tantalum pentoxide, titanium pentoxide, titanium trioxide, lanthanum cobaltate, samarium nickelate, or a combination thereof. 13 . The semiconductor device according to claim 10 , wherein a cross-sectional shape of each of the plurality of phase change memory structures is a regular hexagon. 14 . The semiconductor device according to claim 10 , wherein a distance between any two adjacent ones of the plurality of phase change memory structures is 50 nanometers to 100 nanometers. 15 . The semiconductor device according to claim 10 , wherein each of the plurality of phase change memory structures extends from an inner surface of one of the two electrodes to an inner surface of the other of the two electrodes, and a sidewall of each of the plurality of phase change memory structures is straight.

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