Semiconductor device structure and preparation method thereof, and radio frequency switch and preparation method thereof

Abstract

The invention provides a semiconductor device structure and a preparation method thereof, a radio frequency switch and a preparation method thereof, and electronic equipment. Belongs to the technical field of radio-frequency devices. The preparation method of the semiconductor device structure comprises the following steps: providing a substrate; forming a pattern of a semiconductor layer comprising each PIN unit on the substrate through a pattern composition process; the semiconductor layer comprises a P region, an I region and an N region which are sequentially arranged side by side; forming a first interlayer insulating layer on one side, deviating from the substrate, of the semiconductor layer; forming a pattern comprising a shielding layer on one side, deviating from the substrate, of the first interlayer insulating layer through a pattern composition process; wherein the orthographic projection, on the substrate, of the shielding layer coincides with the orthographic projection, on the substrate, of the I region of the semiconductor layer; respectively carrying out ion implantation on the P region and the N region of the semiconductor layer; and removing the shielding layer, and annealing the semiconductor layer after the ion implantation of the P region and the N region to form a P-type semiconductor, an I-type semiconductor and an N-type semiconductor.

Description

Technical Field

[0001] The present invention belongs to the field of radio frequency technology, and specifically relates to a semiconductor device structure and a preparation method thereof, a radio frequency switch and a preparation method thereof, and electronic equipment. Background Art

[0002] In glass-based PIN diode RF switches, the most important process is to make PIN diode devices, especially to accurately control the parameters of the diode. For PIN diodes, one of the most important parameters is the depletion region width, that is, the thickness of the I layer. According to theoretical derivation, the I region width of PIN diodes generally suitable for 5G radio frequency is on the order of 1um. However, in glass-based processes, it is usually difficult to control the I region width of lateral low-temperature polysilicon LTPS PIN diodes. This is because the ion implantation doping area defined by multiple photolithography masks is usually more susceptible to the influence of photolithography process errors and leads to errors in the implantation definition area.

[0003] At the same time, due to the low mobility of LTPS, if the on-state current is to reach 100mA at 5V drive, the W / L of the PIN device will be designed to be very large, reaching about 1000. Ordinary parallel electrode devices occupy a lot of chip area, making the design layout more difficult and reducing the yield. Summary of the invention

[0004] The present invention aims to solve at least one of the problems in the prior art, and provides a semiconductor device structure and a method for preparing the same, a radio frequency switch and a method for preparing the same, and an electronic device.

[0005] In a first aspect, an embodiment of the present disclosure provides a method for preparing a semiconductor device structure, the semiconductor device structure comprising a substrate substrate, and at least one PIN unit arranged on the substrate substrate, the PIN unit comprising a P-type semiconductor, an I-type semiconductor, and an N-type semiconductor arranged in the same layer and in sequence side by side; the method for preparing the semiconductor device structure comprises:

[0006] Providing a substrate;

[0007] On the substrate, a pattern of a semiconductor layer including each of the PIN units is formed by a patterning process; the semiconductor layer includes a P region, an I region and an N region arranged side by side in sequence;

[0008] forming a first interlayer insulating layer on a side of the semiconductor layer away from the substrate;

[0009] On a side of the first interlayer insulating layer away from the base substrate, a pattern including a shielding layer is formed by a patterning process; wherein an orthographic projection of the shielding layer on the base substrate coincides with an orthographic projection of the I region of the semiconductor layer on the base substrate;

[0010] Performing ion implantation on the P region and the N region of the semiconductor layer respectively;

[0011] The shielding layer is removed, and the semiconductor layer after the ion implantation in the P region and the N region is annealed to form a P-type semiconductor, an I-type semiconductor and an N-type semiconductor.

[0012] The material of the shielding layer includes a metal material; and the step of forming a pattern including the shielding layer by a patterning process on a side of the first interlayer insulating layer away from the base substrate includes:

[0013] On a side of the first interlayer insulating layer away from the base substrate, a first metal film and a first photoresist layer are sequentially formed;

[0014] Exposing, developing and etching the first photoresist layer to form a first photoresist pattern;

[0015] By wet etching, the shielding layer located in the I region is formed, and the orthographic projection of the shielding layer on the substrate overlaps with the orthographic projection of the I region of the semiconductor layer on the substrate;

[0016] The first photoresist pattern is removed.

[0017] Wherein, the metal material includes molybdenum.

[0018] Wherein, the step of respectively implanting ions into the P region and the N region of the semiconductor layer comprises:

[0019] forming a second photoresist layer on a side of the shielding layer away from the substrate;

[0020] Patterning the second photoresist layer to form a second photoresist pattern, wherein the second photoresist pattern exposes the N region of the semiconductor layer;

[0021] Performing ion implantation on the N region;

[0022] removing the second photoresist pattern;

[0023] Forming a third photoresist layer on a side of the semiconductor layer away from the substrate substrate after ion implantation in the N region;

[0024] Patterning the second photoresist layer to form a third photoresist pattern, wherein the third photoresist pattern exposes the P region of the semiconductor layer;

[0025] Performing ion implantation on the P region;

[0026] The third photoresist pattern is removed.

[0027] Wherein, the preparation method further comprises:

[0028] forming a second interlayer insulating layer on a side of the first interlayer insulating layer away from the base substrate;

[0029] On the side of the second interlayer insulating layer away from the base substrate, the first connecting electrode and the second connecting electrode of each PIN unit are formed by a composition process, the first connecting electrode is connected to the P-type semiconductor through a first via hole, and the second connecting electrode is connected to the N-type semiconductor through a second via hole; the first via hole and the second via hole both penetrate the first interlayer insulating layer and the second interlayer insulating layer.

[0030] There are multiple PIN units; the first connection electrodes are connected via a first main body structure, and the second connection electrodes are connected via a second main body structure.

[0031] Wherein, each of the first connecting electrodes, each of the second connecting electrodes, the first main structure and the second main structure are prepared and formed by a single patterning process.

[0032] The first connection electrode of the PIN unit is connected to the P-type semiconductor through a plurality of first vias, and the second connection electrode is connected to the P-type semiconductor through a plurality of second vias.

[0033] The disclosed embodiment also provides a semiconductor device structure, which includes a substrate and at least one PIN unit arranged on the substrate, wherein the PIN unit includes a P-type semiconductor, an I-type semiconductor and an N-type semiconductor arranged in the same layer and in sequence side by side.

[0034] There are multiple PIN units, and the P-type semiconductors of each PIN unit are connected to the same first connection electrode, and the N-type semiconductors of each PIN unit are connected to the same second connection electrode.

[0035] The first connecting electrode and the second connecting electrode are respectively arranged at two opposite sides of the PIN unit.

[0036] Wherein, the first connecting electrode comprises a plurality of first branch structures and a first main structure connected to the first branch structures; one of the first main structures is connected to one of the P-type semiconductors; and / or,

[0037] The second connecting electrode includes a plurality of second branch structures, and the second branch structures are connected to a second main structure, and one second main structure is connected to one of the N-type semiconductors. The present disclosure also provides a method for preparing a radio frequency switch, which includes the method for preparing the semiconductor device structure described in any one of the above claims.

[0038] The method further comprises the step of forming an inductor.

[0039] Wherein, when the method for preparing the semiconductor device structure includes the steps of forming a first connecting electrode and a second connecting electrode, the inductor and the first connecting electrode and the second connecting electrode are prepared by a single patterning process.

[0040] The method further comprises the step of forming a capacitor.

[0041] Wherein, when the method for preparing the semiconductor device structure includes the steps of forming a first connecting electrode and a second connecting electrode, the first electrode plate of the capacitor and the first connecting electrode and the second connecting electrode are prepared by a single patterning process.

[0042] The present disclosure further provides a radio frequency switch, which includes a transmission line and a semiconductor device structure connected to the transmission line, wherein the semiconductor device structure includes any of the semiconductor device structures described above.

[0043] Wherein, the radio frequency switch further includes an inductor and / or a capacitor electrically connected to the transmission line.

[0044] The present disclosure also provides an electronic device, which includes the above-mentioned radio frequency switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a cross-sectional view of the semiconductor device structure according to an embodiment of the present disclosure.

[0046] Figure 2 A top view of a semiconductor device structure of an embodiment of the present disclosure showing multiple PIN units connected in parallel.

[0047] Figure 3 A top view of a semiconductor device structure according to an embodiment of the present disclosure.

[0048] Figure 4 for Figure 3 A top view of a first connecting electrode and a second connecting electrode of a semiconductor device structure is shown.

[0049] Figure 5 A top view of another semiconductor device structure according to an embodiment of the present disclosure.

[0050] Figure 6 for Figure 5 A top view of a first connecting electrode and a second connecting electrode of a semiconductor device structure is shown.

[0051] Figure 7 The present invention is a process flow chart of a method for preparing a semiconductor device structure according to an embodiment of the present invention.

[0052] Figure 8 This is a process flow chart of step S14 of the method for preparing a semiconductor device according to an embodiment of the present disclosure.

[0053] Fig. 9 This is a process flow chart of step S15 of the method for preparing a semiconductor device according to an embodiment of the present disclosure.

[0054] Fig.10 The figure is a layout of a radio frequency switch according to an embodiment of the present disclosure.

[0055] Fig.11 for Fig.10 A partial diagram of the connection between the first semiconductor device structure / the second semiconductor device structure and the transmission line.

[0056] Fig.12 for Fig.10 Partial diagram of the connection between the first capacitor / first capacitor / third capacitor and the transmission line.

[0057] Fig.13 for Fig.10 A partial diagram of the connection between the first inductor / the second inductor and the transmission line. DETAILED DESCRIPTION

[0058] In order to enable those skilled in the art to better understand the technical solution of the present invention / invention, the present invention / invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0059] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0060] Figure 1 is a cross-sectional view of the semiconductor device structure of an embodiment of the present disclosure; Figure 1 As shown, the semiconductor device structure includes a substrate 1 , at least one PIN unit, a first connection electrode 40 and a second connection electrode 50 arranged on the substrate 1 . Figure 1 Only a cross-sectional view of a PIN unit is shown, which includes a P-type semiconductor 10, an I-type semiconductor 20 and an N-type semiconductor 30 arranged in the same layer and side by side. A first interlayer insulating layer 2 and a second interlayer insulating layer 3 are arranged on the side of the PIN unit away from the substrate 1, and a first connecting electrode 40 is connected to the P-type semiconductor 10 through a via hole penetrating the first interlayer insulating layer 2 and the second interlayer insulating layer 3, and a second connecting electrode 50 is connected to the N-type semiconductor 30 through a via hole penetrating the first interlayer insulating layer 2 and the second interlayer insulating layer 3.

[0061] It should be noted that the two insulating layers are provided between the first connection electrode 40 and the second connection electrode 50 and the layer where the PIN unit is located because a semiconductor active layer of a thin film transistor can be formed while forming the PIN unit on the substrate. That is to say, for a substrate integrated with a semiconductor device structure, it not only includes the device structure but also some other electrical components. Therefore, there may be multiple insulating layers between the first connection electrode 40 and the second connection electrode 50 and the layer where the PIN unit is located. Of course, it should be understood that as long as there is one insulating layer between the first connection electrode 40 and the second connection electrode 50 and the layer where the PIN unit is located. It should also be noted that the semiconductor device structure of the embodiment of the present disclosure can be used in a radio frequency switch, and the application scenario of the semiconductor device structure is not limited here.

[0062] The specific materials of the P-type semiconductor 10, the I-type semiconductor 20, and the N-type semiconductor 30 in the PIN unit are not particularly limited, and those skilled in the art can select them according to the use requirements of the PIN unit. In the embodiment of the present disclosure, the materials of the P-type semiconductor 10, the I-type semiconductor 20, and the N-type semiconductor 30 can all be low temperature polycrystalline silicon (LTPS). In some examples, the P-type semiconductor 10 can be doped with B 3+ The N-type semiconductor 30 may be doped with P 3+ Thus, the on-state current of the semiconductor device structure can be increased by using the P-type semiconductor 10 and the N-type semiconductor 30 made of the above materials.

[0063] In some examples, the number of PIN units in the embodiments of the present disclosure may be one or more. When there are multiple PIN units, the multiple PIN units may be connected in parallel, thereby further reducing the resistance of the device. In the embodiments of the present disclosure, only the case where there are multiple PIN units and the multiple PIN units are connected in parallel is used as an example for description.

[0064] Specifically, Figure 2 FIG. 4 is a top view of a semiconductor device structure of an embodiment of the present disclosure in which a plurality of PIN units are connected in parallel; Figure 2As shown, the number of PIN units is N, and the N PIN units are arranged side by side along the first direction, wherein the P-type semiconductor 10 of the i-th PIN unit is shared with the i-1-th P-type semiconductor 10; the N-type semiconductor 30 of the i-th PIN unit is shared with the i+1-th N-type semiconductor 30; N≥3, and N is a positive integer, and i is 1 to (N-1).

[0065] In some examples, Figure 3 A top view of a semiconductor device structure according to an embodiment of the present disclosure; Figure 4 for Figure 3 A top view of a first connecting electrode and a second connecting electrode of the semiconductor device structure shown; Figure 3 and 4 As shown, when there are multiple PIN units, each P-type semiconductor is connected to the same first connection electrode, and each N-type semiconductor is connected to the same second connection electrode.

[0066] Further, the orthographic projections of the first connection electrode 40 and the second connection electrode 50 on the substrate are located on both sides of the PIN unit in a direction perpendicular to the first direction. That is, the first connection electrode 40 and the second connection electrode 50 are respectively arranged on the left and right sides of the PIN unit. The first connection electrode 40 is connected to each P-type semiconductor through the first via VIA1, and the second connection electrode 50 is connected to each N-type semiconductor through the second via VIA2. The first via VIA1 and the second via VIA2 penetrate the interlayer insulating layer between the layer where the first connection electrode 40 and the second connection electrode 50 are located and the layer where the PIN unit is located.

[0067] In some examples, Figure 5 is a top view of another semiconductor device structure according to an embodiment of the present disclosure; Figure 6 for Figure 5 A top view of a first connecting electrode and a second connecting electrode of the semiconductor device structure shown; Figure 5 and 6 As shown, when there are multiple PIN units, the first connection electrode 40 and the second connection electrode 50 are both comb-shaped electrodes, and the branches of the first connection electrode 40 are arranged corresponding to the P-type semiconductor 10, and the branches of the second connection electrode 50 are arranged corresponding to the N-type semiconductor 30.

[0068] Specifically, the first connection electrode 40 includes a plurality of first branch structures 401 and a first main structure 402 connecting the first branch structures 401; the first branch structure 401 is connected to the P-type semiconductor 10 through a via hole penetrating the first interlayer insulating layer 2 and the second interlayer insulating layer 3. The second connection electrode includes a plurality of second branch structures 501 and a second main structure 502 connecting the second branch structures 501; the second branch structure 501 is connected to the N-type semiconductor 30 through a via hole penetrating the first interlayer insulating layer 2 and the second interlayer insulating layer 3.

[0069] Further, the first branch structure 401 can be connected to the P-type semiconductor 10 through a plurality of vias arranged side by side along the first direction and penetrating the first interlayer insulating layer 2 and the second interlayer insulating layer 3. The second branch structure 501 can be connected to the N-type semiconductor 10 through a plurality of vias arranged side by side along the first direction and penetrating the first interlayer insulating layer 2 and the second interlayer insulating layer 3. In this way, it can be ensured that the first branch structure 401 can be stably connected to the corresponding P-type semiconductor 10, and the second branch structure 501 can be stably connected to the corresponding N-type semiconductor 30.

[0070] Furthermore, the midline of the first branch structure 401 perpendicular to the first direction coincides with the orthographic projection of the midline of the corresponding P-type semiconductor 10 perpendicular to the first direction on the substrate 1; the midline of the second branch structure 501 perpendicular to the first direction coincides with the orthographic projection of the midline of the corresponding N-type semiconductor 30 perpendicular to the first direction on the substrate 1.

[0071] Furthermore, the width of the first branch structure 401 is substantially equal to the width of the corresponding P-type semiconductor 10 , and the width of the second branch structure 501 is substantially equal to the width of the corresponding N-type semiconductor 30 .

[0072] The disclosed embodiments also provide a method for preparing a semiconductor device structure, which can be used to prepare any of the above-mentioned semiconductor device structures. Figure 7 is a process flow chart of a method for preparing a semiconductor device structure according to an embodiment of the present disclosure; Figure 7 As shown, the preparation method specifically comprises the following steps:

[0073] S11, providing a substrate 1.

[0074] S12, forming a pattern of a semiconductor layer 200 including each PIN unit on the base substrate 1 by a patterning process; the semiconductor layer 200 includes a P region, an I region and an N region which are sequentially arranged side by side.

[0075] In some examples, low temperature polysilicon, the material of the semiconductor layer 200, is taken as an example. Step S12 specifically includes: first depositing an amorphous silicon layer on one side of the bottom substrate, and then sequentially performing dehydrogenation treatment and excimer laser annealing (ELA) crystallization treatment on the amorphous silicon layer. In this way, a low temperature polysilicon layer can be formed through a single patterning process, and the specific shape includes the subsequent P-type semiconductor 10, N-type semiconductor 30 and I-type semiconductor 20 parts, and the method only performs deposition, dehydrogenation and crystallization treatment once, thereby avoiding multiple high temperature dehydrogenation treatments that are prone to have functional effects on the PIN unit.

[0076] S13 , forming a first interlayer insulating layer 2 on the side of the semiconductor layer 200 away from the substrate 1 .

[0077] In some examples, step S13 may specifically include forming the first interlayer insulating layer 2 by means including but not limited to plasma enhanced chemical vapor deposition (PECVD). The first interlayer insulating layer 2 may be a single layer of silicon oxide material, silicon nitride material, or a stack of multiple sub-layers of silicon oxide material and silicon nitride material.

[0078] S14. On the side of the first interlayer insulating layer facing away from the base substrate 1, a pattern including a shielding layer 301 is formed by a patterning process; wherein the orthographic projection of the shielding layer 301 on the base substrate 1 coincides with the orthographic projection of region I of the semiconductor layer 200 on the base substrate 1.

[0079] In some examples, the shielding layer 301 may be made of a metal material, including but not limited to metal Mo. In the embodiment of the present disclosure, only the shielding layer 301 using metal Mo is used as an example for description. Figure 8 is a process flow chart of step S14 of the method for preparing a semiconductor device according to an embodiment of the present disclosure; Figure 8 As shown, step S14 may specifically include:

[0080] S141, depositing a first metal film 300 and a first photoresist layer in sequence on a side of the first interlayer insulating layer 2 facing away from the substrate 1; exposing, developing and etching the first photoresist layer to form a first photoresist pattern.

[0081] S142 , forming a shielding layer 301 located in the I region, namely a Mo line, by wet etching, wherein the orthographic projection of the shielding layer 301 on the base substrate 1 coincides with the orthographic projection of the I region of the semiconductor layer 200 on the base substrate 1 .

[0082] S143, removing the first photoresist pattern.

[0083] In this step, the width (DICD) of the first photoresist pattern is 3-4 um through a certain degree of exposure control, the thickness of the Mo layer is about 300 nm, and the FICD of Mo is about 1 um by increasing the amount of wet etching OE.

[0084] S15 , performing ion implantation into the P region and the N region of the semiconductor layer 200 respectively.

[0085] In some examples, Fig. 9 is a process flow chart of step S15 of the method for preparing a semiconductor device according to an embodiment of the present disclosure; Fig. 9 As shown, step S15 may include the following steps:

[0086] S151 , forming a second photoresist layer on a side of the shielding layer 301 away from the substrate 1 ; patterning the second photoresist layer to form a second photoresist pattern 701 , wherein the second photoresist pattern 701 exposes the N region of the semiconductor layer 200 .

[0087] S152, perform ion implantation into the N region.

[0088] In some examples, step S152 may specifically select ion P 3+ as doping ions.

[0089] S153 , removing the second photoresist pattern 701 .

[0090] S154 , forming a third photoresist layer on the side of the semiconductor layer 200 facing away from the substrate 1 after ion implantation in the N region; patterning the third photoresist layer to form a third photoresist pattern 801 , wherein the third photoresist pattern 801 exposes the P region of the semiconductor layer 200 .

[0091] S155, performing ion implantation into the P region.

[0092] In some examples, step S154 may specifically select ion B 3+ as doping ions.

[0093] S156 , removing the third photoresist pattern 801 .

[0094] S16 , removing the shielding layer 301 , and annealing the semiconductor layer 200 after the ion implantation in the P region and the N region, to form a P-type semiconductor 10 , an I-type semiconductor 20 , and an N-type semiconductor 30 .

[0095] In step S16 , the doping elements may be prevented from diffusing while the impurities are activated by rapid annealing (RTA).

[0096] Furthermore, the preparation method may further include forming a first connection electrode 40 and a second connection electrode 50 on a side of the first interlayer insulating layer 2 away from the base substrate 1 , wherein the first connection electrode 40 and the second connection electrode 50 are electrically connected to the P-type semiconductor 10 and the N-type semiconductor 30 , respectively.

[0097] Specifically, a second interlayer insulating layer 3 is formed on a side of the first interlayer insulating layer 2 away from the substrate; a first connecting electrode 40 and a second connecting electrode 50 of each PIN unit are formed on a side of the second interlayer insulating layer 3 away from the substrate through a patterning process, the first connecting electrode 40 is connected to the P-type semiconductor 10 through a first via hole, and the second connecting electrode 50 is connected to the N-type semiconductor 30 through a second via hole; both the first via hole and the second via hole penetrate the first interlayer insulating layer and the second interlayer insulating layer.

[0098] The method for preparing a semiconductor device structure provided in the embodiment of the present disclosure defines the I region by forming a Mo line so that the I region can be less than 1 μm, thereby solving the problem of difficulty in defining the I region with a narrow design.

[0099] Second, Fig.10 A layout of a radio frequency switch according to an embodiment of the present disclosure; Fig.11 for Fig.10 A partial diagram of the connection between the first semiconductor device structure / the second semiconductor device structure and the transmission line; Fig.12 for Fig.10 A partial diagram of the connection between the first capacitor / the first capacitor / the third capacitor and the transmission line; Fig.13 for Fig.10 A partial diagram of the connection between the first inductor / the second inductor and the transmission line; refer to Figure 10-13 An embodiment of the present disclosure provides a radio frequency switch, which includes a transmission line 100 and a semiconductor device structure arranged on the transmission line 100, wherein the semiconductor device structure is any of the semiconductor device structures described above.

[0100] The transmission line 100 may be a coplanar waveguide CPW transmission line 100. That is, the transmission line includes a signal electrode 101, and a first reference electrode 102 and a second reference electrode 103 disposed on both sides of the extending direction of the signal electrode 101. The first reference electrode 102 and the second reference electrode 103 may be ground electrodes. The transmission line 100 may be disposed in the same layer as the first connection electrode 40 and the second connection electrode 50.

[0101] Further, when the first connection electrode 40 and the second connection electrode 50 adopt a double-layer structure, the transmission line 100 can be disposed in the same layer as the second sub-electrode 42 and the fourth sub-electrode 52 .

[0102] In some examples, the RF switch further includes a capacitor C and an inductor L. The coil structure of the inductor L and the first plate of the capacitor C can be disposed in the same layer as the transmission line 100 .

[0103] Specifically, refer to Figure 10-13 The radio frequency switch includes two semiconductor device structures, namely PIN1 and PIN2, three capacitors, namely C1, C2, and C3, and two inductors, L1 and L2. The semiconductor device, capacitors, and inductors are connected in series and parallel through a transmission line to realize a radio frequency switch.

[0104] Accordingly, the embodiment of the present disclosure provides a method for preparing a radio frequency switch, which includes the method for preparing the semiconductor device structure described above, and of course, may also include the steps of forming capacitors, inductors, and transmission lines. The coil structure of the inductor L and the first plate of the capacitor C may be formed in a single patterning process with the transmission line 100 and the first connecting electrode 40 and the second connecting electrode 50 of the semiconductor device structure.

[0105] In a third aspect, an embodiment of the present disclosure provides an electronic device. The above-mentioned radio frequency switch can be used in the electronic device. The electronic device can be an antenna.

[0106] In some examples, the electronic device also includes a transceiver unit, a radio frequency transceiver, a signal amplifier, a power amplifier, and a filtering unit. The antenna in the communication device can be used as a transmitting antenna or a receiving antenna. Among them, the transceiver unit may include a baseband and a receiving end. The baseband provides a signal of at least one frequency band, such as a 2G signal, a 3G signal, a 4G signal, a 5G signal, etc., and sends a signal of at least one frequency band to the radio frequency transceiver. After the antenna in the communication system receives the signal, it can be processed by the filtering unit, the power amplifier, the signal amplifier, and the radio frequency transceiver and then transmitted to the receiving end in the transceiver unit. The receiving end may be, for example, a smart gateway.

[0107] Furthermore, the RF transceiver is connected to the transceiver unit, and is used to modulate the signal sent by the transceiver unit, or to demodulate the signal received by the antenna and transmit it to the transceiver unit. Specifically, the RF transceiver may include a transmitting circuit, a receiving circuit, a modulation circuit, and a demodulation circuit. After the transmitting circuit receives various types of signals provided by the baseband, the modulation circuit can modulate the various types of signals provided by the baseband and then send them to the antenna. The antenna receives the signal and transmits it to the receiving circuit of the RF transceiver. The receiving circuit transmits the signal to the demodulation circuit, and the demodulation circuit demodulates the signal and transmits it to the receiving end.

[0108] Furthermore, the RF transceiver is connected to a signal amplifier and a power amplifier, and the signal amplifier and the power amplifier are connected to a filter unit, and the filter unit is connected to at least one antenna. In the process of sending signals in the communication system, the signal amplifier is used to improve the signal-to-noise ratio of the signal output by the RF transceiver and then transmit it to the filter unit; the power amplifier is used to amplify the power of the signal output by the RF transceiver and then transmit it to the filter unit; the filter unit may specifically include a duplexer and a filter circuit, and the filter unit combines the signals output by the signal amplifier and the power amplifier and filters out the clutter before transmitting them to the antenna, and the antenna radiates the signal. In the process of receiving signals in the communication system, the antenna receives the signal and transmits it to the filter unit, and the filter unit filters out the clutter from the signal received by the antenna and then transmits it to the signal amplifier and the power amplifier, and the signal amplifier amplifies the signal received by the antenna to increase the signal-to-noise ratio; the power amplifier amplifies the power of the signal received by the antenna. The signal received by the antenna is processed by the power amplifier and the signal amplifier and then transmitted to the RF transceiver, and the RF transceiver then transmits it to the transceiver unit.

[0109] In some examples, the signal amplifier may include various types of signal amplifiers, such as a low noise amplifier, which is not limited herein.

[0110] In some examples, the electronic device provided by the embodiments of the present disclosure further includes a power management unit, which is connected to a power amplifier to provide the power amplifier with a voltage for amplifying a signal.

[0111] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A method for preparing a semiconductor device structure, the semiconductor device structure comprising a substrate and at least one PIN unit arranged on the substrate, the PIN unit comprising a P-type semiconductor, an I-type semiconductor and an N-type semiconductor arranged in the same layer and in sequence side by side; The method for preparing the semiconductor device structure comprises: Providing a substrate; On the substrate, a pattern of a semiconductor layer including each of the PIN units is formed by a patterning process; the semiconductor layer includes a P region, an I region and an N region arranged side by side in sequence; forming a first interlayer insulating layer on a side of the semiconductor layer away from the substrate; On a side of the first interlayer insulating layer away from the base substrate, a pattern including a shielding layer is formed by a patterning process; wherein an orthographic projection of the shielding layer on the base substrate coincides with an orthographic projection of the I region of the semiconductor layer on the base substrate; Performing ion implantation on the P region and the N region of the semiconductor layer respectively; The shielding layer is removed, and the semiconductor layer after the ion implantation in the P region and the N region is annealed to form a P-type semiconductor, an I-type semiconductor and an N-type semiconductor.

2. The method for preparing a semiconductor device structure according to claim 1, wherein: The material of the shielding layer includes a metal material; the step of forming a pattern including the shielding layer by a patterning process on a side of the first interlayer insulating layer away from the base substrate includes: On a side of the first interlayer insulating layer away from the base substrate, a first metal film and a first photoresist layer are sequentially formed; Exposing, developing and etching the first photoresist layer to form a first photoresist pattern; By wet etching, the shielding layer located in the I region is formed, and the orthographic projection of the shielding layer on the substrate overlaps with the orthographic projection of the I region of the semiconductor layer on the substrate; The first photoresist pattern is removed.

3. The method for preparing a semiconductor device structure according to claim 2, wherein: The metal material includes molybdenum.

4. The method for preparing a semiconductor device structure according to any one of claims 1 to 3, wherein: The step of respectively implanting ions into the P region and the N region of the semiconductor layer comprises: forming a second photoresist layer on a side of the shielding layer away from the substrate; Patterning the second photoresist layer to form a second photoresist pattern, wherein the second photoresist pattern exposes the N region of the semiconductor layer; Performing ion implantation on the N region; removing the second photoresist pattern; Forming a third photoresist layer on a side of the semiconductor layer away from the substrate substrate after ion implantation in the N region; Patterning the second photoresist layer to form a third photoresist pattern, wherein the third photoresist pattern exposes the P region of the semiconductor layer; Performing ion implantation on the P region; The third photoresist pattern is removed.

5. The method for preparing a semiconductor device structure according to claim 1, wherein: Also includes: forming a second interlayer insulating layer on a side of the first interlayer insulating layer away from the base substrate; On the side of the second interlayer insulating layer away from the base substrate, the first connecting electrode and the second connecting electrode of each PIN unit are formed by a composition process, the first connecting electrode is connected to the P-type semiconductor through a first via hole, and the second connecting electrode is connected to the N-type semiconductor through a second via hole; the first via hole and the second via hole both penetrate the first interlayer insulating layer and the second interlayer insulating layer.

6. The method for preparing a semiconductor device structure according to claim 5, wherein: There are multiple PIN units; the first connection electrodes are connected via a first main body structure, and the second connection electrodes are connected via a second main body structure.

7. The method for preparing a semiconductor device structure according to claim 6, wherein: Each of the first connecting electrodes, each of the second connecting electrodes, the first main structure and the second main structure are formed by a single patterning process.

8. The method for preparing a semiconductor device structure according to claim 5, wherein: The first connection electrode of the PIN unit is connected to the P-type semiconductor through a plurality of first via holes, and the second connection electrode is connected to the P-type semiconductor through a plurality of second via holes.

9. A semiconductor device structure, comprising a substrate and at least one PIN unit arranged on the substrate, wherein the PIN unit comprises a P-type semiconductor, an I-type semiconductor and an N-type semiconductor arranged in the same layer and in sequence side by side.

10. The semiconductor device structure according to claim 9, wherein: There are multiple PIN units, and the P-type semiconductors of the PIN units are connected to the same first connection electrode, and the N-type semiconductors of the PIN units are connected to the same second connection electrode.

11. The semiconductor device structure according to claim 10, wherein: The first connection electrode and the second connection electrode are respectively arranged at two opposite sides of the PIN unit.

12. The semiconductor device structure according to claim 10, wherein: The first connecting electrode includes a plurality of first branch structures and a first main structure connected to the first branch structures; one of the first main structures is connected to one of the P-type semiconductors; and / or, The second connection electrode includes a plurality of second branch structures, the second branch structures and a second main structure, and one second main structure is connected to one of the N-type semiconductors.

13. A method for preparing a radio frequency switch, comprising the method for preparing the semiconductor device structure according to any one of claims 1 to 8.

14. The method for preparing a radio frequency switch according to claim 13, wherein: Also included is the step of forming an inductor.

15. The method for preparing a radio frequency switch according to claim 14, wherein: When the method for preparing the semiconductor device structure includes the steps of forming a first connecting electrode and a second connecting electrode, the inductor and the first connecting electrode and the second connecting electrode are prepared by a single patterning process.

16. The method for preparing a radio frequency switch according to claim 13, wherein: Also included is the step of forming a capacitor.

17. The method for preparing a radio frequency switch according to claim 16, wherein: When the method for preparing the semiconductor device structure includes the steps of forming a first connecting electrode and a second connecting electrode, the first electrode plate of the capacitor and the first connecting electrode and the second connecting electrode are prepared by a single patterning process.

18. A radio frequency switch comprising a transmission line and a semiconductor device structure connected to the transmission line, wherein: The semiconductor device structure comprises the semiconductor device structure according to any one of claims 9 to 12.

19. The radio frequency switch according to claim 18, wherein: The radio frequency switch further includes an inductor and / or a capacitor electrically connected to the transmission line.

20. An electronic device comprising the radio frequency switch according to claim 18 or 19.

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