Semiconductor process method and semiconductor process equipment

Abstract

The invention discloses a semiconductor process method, thin film deposition equipment and a transistor, relates to the technical field of semiconductors, and can avoid additional introduction of annealing equipment and reduce the production cost. Besides, before the metal layer is deposited, the oxide layer on the surface of the wafer can be completely removed, so that a device with small VCE divergence can be formed, and the yield and the product performance can be improved. The semiconductor process method comprises the following steps: ionizing first process gas to form plasma, and cleaning a to-be-deposited surface of a wafer by using the plasma; wherein the first process gas comprises a reducing gas and a physical bombardment gas, and the volume flow rate of the reducing gas introduced in the etching stage is greater than that of the physical bombardment gas introduced in the etching stage; placing the cleaned wafer in a sputtering chamber, and depositing a first metal layer on the to-be-deposited surface; and annealing the wafer on which the first metal layer is deposited in the sputtering chamber.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor process method and semiconductor process equipment. Background Art

[0002] The insulated gate bipolar transistor (IGBT) is a composite, fully controlled, voltage-driven power semiconductor device developed based on the metal oxide field-effect transistor (MOSFET) and bipolar transistor. IGBT devices combine the high voltage, high current, and low loss characteristics of bipolar devices with the low drive power, fast switching response, and excellent thermal stability of MOSFET devices. With the rapid development of high-speed trains, electric vehicles, facial recognition, smart cities, aerospace, defense industry, and smart grids, IGBT devices play a crucial role in the development of these emerging technologies.

[0003] An IGBT device generally includes a substrate, a MOS structure arranged on the front side of the substrate, and a collector structure on the back side of the substrate, wherein the collector structure includes a P-type collector layer and a multi-layer stacked metal layer. Figure 1 As shown, the existing back-side processes include: front-side film lamination, wafer back-side thinning, back-side cleaning, back-side ion implantation, laser annealing, back-side cleaning, back-side metallization and high-temperature annealing; among them, back-side metallization refers to the formation of a multi-layer stacked metal layer.

[0004] The back-side process has the following problems: 1. After the back side is metallized, it needs to be placed in a furnace for high-temperature annealing; this requires the introduction of additional annealing equipment, resulting in increased production costs. 2. The back side cleaning generally uses an acid pickling process to remove the oxide layer on the wafer surface, but the removal capacity of the acid pickling process is limited and cannot guarantee the complete removal of the oxide layer on the wafer surface; in addition, the back side cleaning and back side metallization are not performed in the same equipment, so during the transportation process, the wafer surface is very likely to be exposed to the atmosphere and thus oxidized, resulting in the electrical performance index V of the final IGBT device being low. CE (the voltage between the collector and emitter) is very divergent, which greatly reduces the yield and product performance. Summary of the Invention

[0005] The embodiments of the present application provide a semiconductor process method and a semiconductor process device, which can avoid the introduction of additional annealing equipment and reduce production costs; in addition, before depositing the metal layer, the oxide layer on the surface of the wafer can be completely removed, thereby facilitating the formation of V CE Devices with small divergence are beneficial to improving yield and product performance.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In one aspect, an embodiment of the present application provides a semiconductor process method, comprising:

[0008] Ionizing a first process gas to form a plasma, and using the plasma to clean the surface of the wafer to be deposited; wherein the first process gas includes a reducing gas and a physical bombardment gas, and the volume flow rate of the reducing gas introduced during the etching stage is greater than the volume flow rate of the physical bombardment gas introduced;

[0009] Placing the cleaned wafer in a sputtering chamber and depositing a first metal layer on the surface to be deposited;

[0010] The wafer on which the first metal layer is deposited is annealed in the sputtering chamber.

[0011] Optionally, the volume flow ratio of the introduced reducing gas to the introduced physical bombardment gas is in the range of 2:1 to 6:1.

[0012] Optionally, the volume flow rate of the reducing gas introduced is in the range of 20 sccm to 60 sccm, and the volume flow rate of the physical bombardment gas introduced is in the range of 10 sccm to 30 sccm.

[0013] Optionally, the reducing gas includes hydrogen, and the physical bombardment gas includes argon.

[0014] Optionally, ionizing the first process gas to form plasma, and using the plasma to clean the surface of the wafer to be deposited includes:

[0015] An inductively coupled plasma etching process is adopted in the pre-cleaning chamber to ionize the first process gas to form plasma, and the plasma is used to clean the surface to be deposited on the wafer.

[0016] Optionally, the RF frequency range loaded on the coil of the pre-cleaning chamber is 2 MHz to 15 MHz, the RF power range loaded is 200 W to 1500 W, and the base temperature range is 200° C. to 400° C.

[0017] Optionally, ionizing the first process gas to form plasma, and using the plasma to clean the surface of the wafer to be deposited includes:

[0018] During the ignition stage of the pre-cleaning chamber, the reducing gas is continuously introduced into the pre-cleaning chamber through the reduction ventilation line, and the physical bombardment gas is continuously introduced into the pre-cleaning chamber through the first physical bombardment ventilation line and the second physical bombardment ventilation line, respectively; wherein the volume flow rate of the physical bombardment gas introduced through the second physical bombardment ventilation line is greater than the volume flow rate of the physical bombardment gas introduced through the first physical bombardment ventilation line;

[0019] During the etching stage in the pre-cleaning chamber, the reducing gas is continuously introduced into the pre-cleaning chamber through the reducing ventilation line, the physical bombardment gas is continuously introduced into the pre-cleaning chamber through the first physical bombardment ventilation line, and ventilation through the second physical bombardment ventilation line is stopped; wherein the volume flow rate of the reducing gas introduced through the reducing ventilation line is greater than the volume flow rate of the physical bombardment gas introduced through the first physical bombardment ventilation line.

[0020] Optionally, after ionizing the first process gas to form plasma and using the plasma to clean the surface of the wafer to be deposited, the semiconductor process method further includes:

[0021] During the evacuation phase of the pre-cleaning chamber, the physical bombardment gas is introduced into the pre-cleaning chamber through the second physical bombardment ventilation pipeline, and ventilation through the reduction ventilation pipeline and the first physical bombardment ventilation pipeline is stopped.

[0022] Optionally, before ionizing the first process gas to form plasma and using the plasma to clean the surface of the wafer to be deposited, the semiconductor process method further includes:

[0023] The surface of the wafer to be deposited is wet cleaned.

[0024] Optionally, annealing the wafer on which the first metal layer is deposited in the sputtering chamber includes:

[0025] Annealing gas is introduced into the sputtering chamber, and the cold pump of the sputtering chamber is controlled to be in a closed state to adjust the pressure of the sputtering chamber to a preset pressure and maintain it for a preset time to anneal the wafer deposited with the first metal layer.

[0026] Optionally, the step of introducing annealing gas into the sputtering chamber and controlling a cold pump of the sputtering chamber to be in an off state to adjust the pressure of the sputtering chamber to a preset pressure and maintain the pressure for a preset time to anneal the wafer deposited with the first metal layer includes:

[0027] During a first time period, controlling a cold pump of the sputtering chamber to be in an off state, and introducing the annealing gas into the sputtering chamber to adjust the pressure of the sputtering chamber to the preset pressure; wherein the first time period ranges from 20 seconds to 60 seconds;

[0028] After the first time period ends, the annealing gas is stopped from being introduced, and the cold pump of the sputtering chamber is controlled to remain in a closed state within the preset time period to anneal the wafer deposited with the first metal layer; wherein the preset time period ranges from 30s to 90s, and within the first time period and the preset time period, the base temperature of the sputtering chamber ranges from 300°C to 450°C.

[0029] On the other hand, an embodiment of the present application provides a semiconductor process equipment, including a pre-cleaning chamber, a transfer chamber, a sputtering chamber and a controller, the controller including at least one processor and at least one memory, the memory storing a computer program, and the computer program, when executed by the processor, implements the semiconductor process method as described in any one of the above items.

[0030] The embodiments of the present application provide a semiconductor process method and a semiconductor process device. The semiconductor process method cleans the surface of a wafer to be deposited by plasma formed by ionizing a first process gas, which can completely remove the oxide layer on the surface of the wafer without damaging the surface of the wafer and passivate the defects on the surface of the wafer. Furthermore, after depositing the first metal layer, in-situ annealing can be achieved, thereby avoiding the introduction of additional annealing equipment, shortening the annealing time, and significantly reducing production costs. In addition, it is also conducive to forming V CE Devices with small divergence are beneficial to improving yield and product performance.

[0031] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 A schematic diagram of a backside process provided for related technology;

[0034] Figure 2 One of the flow charts of a semiconductor process method provided in an embodiment of the present application;

[0035] Figure 3 A schematic structural diagram of an IGBT device provided in an embodiment of the present application;

[0036] Figure 4 A schematic structural diagram of a multi-layer metal structure provided in an embodiment of the present application;

[0037] Figure 5 This is a SEM interface image of an Al-Si alloy provided in an embodiment of the present application;

[0038] Figure 6 This is a SEM top view of an Al-Si alloy after pickling provided in an embodiment of the present application;

[0039] Figure 7 A second flow chart of a semiconductor process method provided in an embodiment of the present application;

[0040] Figure 8 The third flow chart of a semiconductor process method provided in an embodiment of the present application;

[0041] Figure 9 Figure (a) is an SEM image of the wafer surface after dry etching (Recipe) using a mixture of H2 and Ar gas and a Coil electrode, and Figure (b) is an SEM image of the unetched wafer surface;

[0042] Figure 10 V provided in the embodiment of this application CE Sample distribution diagram;

[0043] Figure 11 A schematic diagram of a back metal layer process provided for related technology;

[0044] Figure 12 A fourth flow chart of a semiconductor process method provided in an embodiment of the present application;

[0045] Figure 13 A schematic structural diagram of a semiconductor process equipment provided in an embodiment of the present application;

[0046] Figure 14 A schematic structural diagram of a pre-cleaning chamber provided in an embodiment of the present application;

[0047] Figure 15 A schematic structural diagram of a sputtering chamber provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the specific embodiments of this application and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0049] In the embodiments of the present application, words such as "first" and "second" are used to distinguish identical or similar items with substantially the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0050] In the embodiments of the present application, "multi-layer" means two or more layers, and "multiple" means two or more layers, unless otherwise specifically defined. In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the present application.

[0051] The present invention provides a semiconductor process method. Figure 2 As shown, including:

[0052] S1. Ionize the first process gas to form plasma, and use the plasma to clean the surface of the wafer to be deposited; wherein the first process gas includes a reducing gas and a physical bombardment gas, and the volume flow rate of the reducing gas introduced during the etching stage is greater than the volume flow rate of the physical bombardment gas introduced.

[0053] The specific gas components of the above-mentioned reducing gas and physical bombardment gas are not limited. For example, the reducing gas may include hydrogen-containing gases, such as hydrogen (H2), ammonia (NH3), hydrogen sulfide (H2S), hydrogen bromide (HBr) and hydrogen iodide (HI), and methane (CH4), and the physical bombardment gas may include inert gases, such as argon (Ar), helium (He), neon (Ne), krypton (Kr) or xenon (Xe).

[0054] The first process gas is ionized to form a reducing plasma (for example, H + plasma) and physical bombardment plasma (e.g. Ar +The physical impact of the plasma (a type of plasma) can break the silicon-oxygen bonds on the wafer. The oxygen then reacts with the reducing plasma to remove silicon oxide from the surface of the wafer to be deposited, while also passivating Si surface defects. Compared to existing technologies that rely solely on physical bombardment of the gas, this method reduces damage to the wafer surface, facilitating subsequent in-situ annealing processes.

[0055] Step S1 may include at least an ignition stage and an etching stage; in the ignition stage, the first process gas may be ionized to form plasma; in the etching stage, the plasma may etch the surface of the wafer to be deposited, thereby completing cleaning.

[0056] It should be noted that before cleaning, the wafer may include a first side and a second side that are arranged opposite to each other; if the thin film deposition method is applied to the back metallization process of the IGBT device, the wafer may be formed after the front process, thinning process, back cleaning, back ion implantation, and laser annealing, and its thickness is relatively small, ranging from 50μm to 150μm; the first side of the wafer may be formed with a MOS structure, and the MOS structure may include: Figure 3 The gate 5, emitter 6, P- region 7 and N+ region 8 shown in the figure are structures. Of course, the MOS structure can also include other structural types, which are not limited here. The second side can be formed as shown in FIG. Figure 3 The N-type buffer layer 3 and the P-type collector layer 2 are shown, wherein the P-type collector layer is an ion implantation layer. Figure 3 The structure marked 4 in the figure represents a substrate. In the actual production process, multiple IGBT structures can be formed on a wafer. After the corresponding structures are prepared, the wafer is cut to obtain multiple IGBT devices. At this time, part of the wafer in each IGBT device can be called a substrate.

[0057] Step S1 can be performed in a pre-clean chamber, which is part of a semiconductor process equipment, including a PVD (Physical Vapor Deposition) chamber. PVD technology refers to the use of physical methods under vacuum conditions to vaporize the surface of a material source (solid or liquid) into gaseous atoms or molecules, or partially ionize them into ions, and then deposit a thin film with a specific function on the surface of a substrate through a low-pressure gas (or plasma) process. Physical vapor deposition is one of the main surface treatment technologies.

[0058] During cleaning, the wafer to be cleaned can be placed on a susceptor, and the temperature of the susceptor can be controlled according to process requirements, with no specific temperature range being limited.

[0059] S2. Place the cleaned wafer in a sputtering chamber and deposit a first metal layer on the surface to be deposited.

[0060] The sputtering chamber is also part of the semiconductor process equipment; the etched wafer is transferred from the pre-cleaning chamber to the sputtering chamber, all of which are carried out inside the semiconductor process equipment and do not need to be taken out of the semiconductor process equipment, so it will not be exposed to the atmosphere. Then, the deposition surface of the cleaned wafer will not be oxidized again, thereby not affecting the subsequent deposition effect.

[0061] The material of the above-mentioned first metal layer is not limited, and it may include a single metal material. For example, the material of the first metal layer may include a single metal such as aluminum (Al) or copper (Cu); or, the material of the first metal layer may include a mixed metal of multiple conductive materials. For example, the material of the first metal layer may include a mixed metal of aluminum and copper.

[0062] Step S2 uses magnetron sputtering to form the first metal layer. Magnetron sputtering is a type of physical vapor deposition. It is generally used to prepare materials such as metals, semiconductors, and insulators. It has the advantages of simple equipment, easy control, large coating area, and strong adhesion. The working principle of magnetron sputtering is that electrons collide with inert gas atoms (for example, argon atoms) in the process of flying toward the substrate under the action of an electric field, ionizing them to produce positive ions (for example, Ar). + ) and new electrons; new electrons fly to the substrate, inert ions (such as Ar + ) are accelerated towards the cathode target under the action of the electric field and bombard the target surface with high energy, causing the target material to sputter. Among the sputtered particles, neutral target atoms or molecules are deposited on the substrate to form a thin film.

[0063] In step S2, the high-energy metal atoms generated by magnetron sputtering react with the Si on the wafer to form a metal alloy (i.e., a mutually soluble structure between the wafer and the first metal layer after etching). For example, if the material of the first metal layer includes Al, then in step S2, the Al reacts with the Si on the wafer to form an Al-Si alloy.

[0064] The above-mentioned sputtering chamber can be used to implement a magnetron sputtering process, and its specific structure is not limited and can be obtained from related technologies.

[0065] S3. Annealing the wafer deposited with the first metal layer in a sputtering chamber.

[0066] The purpose of the annealing is to form a dense and uniform soluble structure, so as to form a good ohmic contact between the wafer and the first metal layer after etching, thereby reducing the interface contact resistance. The soluble structure formed in step S2 will become even denser and more uniform after the annealing in step S3.

[0067] The specific annealing method is not limited here. For example, the wafer deposited with the first metal layer can be fully annealed by heat conduction and heat radiation.

[0068] An embodiment of the present application provides a semiconductor process method, which cleans the surface of a wafer to be deposited by plasma formed by ionizing a first process gas, and can completely remove the oxide layer on the surface of the wafer with low damage. After depositing the metal layer, in-situ annealing can be achieved, thereby avoiding the introduction of additional annealing equipment, shortening the annealing time, significantly reducing production costs, and being conducive to forming devices with small VCE divergence, which is conducive to improving yield and product performance.

[0069] Optionally, in order to further ensure the cleaning effect, the volume flow ratio of the introduced reducing gas and the introduced physical bombardment gas is in the range of 2:1 to 6:1. For example, the volume flow ratio can be in the range of 2:1, 2.5:1, 3:1, 4:1, 5:1 or 6:1.

[0070] Optionally, according to different process requirements, the volume flow rate of the introduced reducing gas ranges from 20 sccm to 60 sccm, and the volume flow rate of the introduced physical bombardment gas ranges from 10 sccm to 30 sccm.

[0071] On the premise of meeting the above-mentioned volume flow ratio range, the volume flow rate of the reducing gas introduced can be 20sccm, 30sccm, 40sccm, 50sccm or 60sccm, and the volume flow rate of the physical bombardment gas introduced can be 10sccm, 15sccm, 20sccm, 25sccm or 30sccm.

[0072] Optionally, in order to improve the utilization rate of existing equipment and reduce production costs as much as possible, the reducing gas includes hydrogen and the physical bombardment gas includes argon.

[0073] In one or more embodiments, S1, ionizing the first process gas to form plasma, and using the plasma to clean the surface of the wafer to be deposited, includes:

[0074] S1′, using an inductively coupled plasma etching process in a pre-cleaning chamber to ionize a first process gas to form plasma, and using the plasma to clean the surface of the wafer to be deposited.

[0075] In the early days of the inductively coupled plasma (ICP) etching process, etching was performed using a bias power supply and a coil electrode under a single argon atmosphere, which would cause certain damage to the etched surface.

[0076] The present application adopts a mixed gas of reducing gas and physical bombardment gas (such as H2 and Ar mixed gas), and only uses a single coil to excite and form plasma for etching, which can further realize a damage-free etching process, that is, it can further realize the removal of silicon oxide on the surface to be deposited of the wafer without damaging the wafer surface, and at the same time passivate the defects on the Si surface, so as to facilitate the subsequent in-situ annealing process. If the traditional Bias power supply and Coil electrode are used to jointly excite pure argon gas, it will cause certain damage to the surface of the wafer, and a higher annealing temperature and annealing time (60-90 minutes) are required to form an alloy. In the environment of the sputtering chamber, it is impossible to perform in-situ annealing to form an alloy. The main reason is that the annealing temperature of the sputtering chamber is much lower than the annealing furnace used in the prior art, and the sputtering chamber cannot be annealed for such a long time. Reference Figure 9 As shown, Figure (a) is an SEM image of the wafer surface after dry etching (Recipe) using a mixture of H2 and Ar and a Coil electrode, and Figure (b) is an SEM image of the unetched wafer surface. By comparison, it can be found that the Si surface after etching using a mixture of H2 and Ar and a Coil electrode has a cluster morphology of obvious chemical reduction reaction, which is conducive to the subsequent formation of a mutual dissolution structure between the metal layer and the wafer (for example: Al-Si alloy), and is also conducive to the subsequent formation of V CE An IGBT device with small divergence is beneficial to improving the electrical performance of the device.

[0077] Optionally, in step S1 ′, a single Coil electrode is used for etching, the RF frequency range of the coil loaded in the pre-cleaning chamber is 2 MHz to 15 MHz, the RF power range is 200 W to 1500 W, and the susceptor temperature range is 200° C. to 400° C.

[0078] The inductively coupled plasma etching process utilizes a mixed gas and coil electrode. The RF frequency applied to the coil can be 2 MHz, 4 MHz, 8 MHz, 10 MHz, 11 MHz, 12 MHz, 13 MHz, 14 MHz, or 15 MHz; the RF power can be 200 W, 500 W, 800 W, 1100 W, 1300 W, or 1500 W, depending on actual requirements. The susceptor temperature can be 200°C, 300°C, or 400°C.

[0079] In one or more embodiments, S1, ionizing the first process gas to form plasma, and using the plasma to clean the surface of the wafer to be deposited, includes:

[0080] S11. During the ignition stage of the pre-cleaning chamber, reducing gas is continuously introduced into the pre-cleaning chamber through the reduction ventilation line, and physical bombardment gas is continuously introduced into the pre-cleaning chamber through the first physical bombardment ventilation line and the second physical bombardment ventilation line, respectively; wherein the volume flow rate of the physical bombardment gas introduced through the second physical bombardment ventilation line is greater than the volume flow rate of the physical bombardment gas introduced through the first physical bombardment ventilation line.

[0081] The ignition phase is primarily used to apply a certain amount of RF power to the chamber to ionize the process gas and generate plasma. During this phase, a small flow of physical bombardment gas is introduced into the pre-cleaning chamber through the first physical bombardment vent line, while a large flow of physical bombardment gas is introduced into the pre-cleaning chamber through the second physical bombardment vent line. This reduces the ventilation time, and thus the ignition time.

[0082] It should be noted that the ignition stage in step S11 can also be called the pre-ignition stage (to facilitate distinction from the subsequent ignition stage, it can be called the first ignition stage). After this stage, a second ignition stage is also provided. In the second ignition stage, a small flow of physical bombardment gas is continuously introduced into the pre-cleaning chamber through the first physical bombardment ventilation line, the large flow of physical bombardment gas through the second physical bombardment ventilation line is stopped, and reducing gas is continuously introduced into the pre-cleaning chamber through the reduction ventilation line. By setting up two ignition stages, a large amount of physical bombardment gas can be introduced for a short time in the first ignition stage, and a small flow rate can be controlled in the second ignition stage. The two stages work together to shorten the overall ignition time and increase production capacity.

[0083] In addition, a ventilation phase may be provided before the ignition phase in step S11. During the ventilation phase, reducing gas is continuously introduced into the pre-cleaning chamber via the reduction ventilation line, and physical bombardment gas is continuously introduced into the pre-cleaning chamber via the first physical bombardment ventilation line and the second physical bombardment ventilation line, respectively. The volume flow rate of the physical bombardment gas introduced via the second physical bombardment ventilation line is greater than the volume flow rate of the physical bombardment gas introduced via the first physical bombardment ventilation line. That is, during the ventilation phase, the physical bombardment gas is continuously introduced into the pre-cleaning chamber via the first physical bombardment ventilation line and the second physical bombardment ventilation line, respectively, thereby further reducing the gas introduction time.

[0084] S12. During the etching stage in the pre-cleaning chamber, continuously introduce reducing gas into the pre-cleaning chamber through the reduction vent line, continuously introduce physical bombardment gas into the pre-cleaning chamber through the first physical bombardment vent line, and stop venting through the second physical bombardment vent line; wherein the volume flow rate of the reducing gas introduced through the reduction vent line is greater than the volume flow rate of the physical bombardment gas introduced through the first physical bombardment vent line.

[0085] The etching stage is used to etch the surface of the wafer to be deposited using an inductively coupled plasma etching process. In order to facilitate the control of gas flow, during the etching stage, physical bombardment gas is only introduced into the pre-cleaning chamber through the first physical bombardment ventilation pipeline.

[0086] It should be noted that the above-mentioned pre-cleaning chamber includes at least one air inlet; if the pre-cleaning chamber includes one air inlet, the gases in the above-mentioned reduction ventilation line, the first physical bombardment ventilation line and the second physical bombardment ventilation line can be mixed and then introduced into the chamber from the air inlet; if the pre-cleaning chamber includes three air inlets, the gases in the reduction ventilation line, the first physical bombardment ventilation line and the second physical bombardment ventilation line can be introduced into the chamber from the three air inlets respectively, which is not limited here.

[0087] Since the efficiency of the cold pump in extracting reducing gas is much lower than that of extracting physical bombardment gas, in order to improve the efficiency of extracting reducing gas and further shorten the production time, optional reference Figure 7 As shown, after S1, ionizing the first process gas to form plasma, and using the plasma to clean the surface of the wafer to be deposited, the semiconductor process method further includes:

[0088] S10. During the gas extraction stage of the pre-cleaning chamber, physical bombardment gas is introduced into the pre-cleaning chamber through the second physical bombardment ventilation pipeline, and ventilation through the reduction ventilation pipeline and the first physical bombardment ventilation pipeline is stopped.

[0089] In this way, after etching, the concentration of the reducing gas in the pre-cleaning chamber can be diluted by introducing a large amount of physical bombardment gas, thereby facilitating the extraction of the cold pump and improving the efficiency of extracting the reducing gas.

[0090] Taking the reducing gas including hydrogen and the physical bombardment gas including argon as an example, the following provides relevant equipment parameters for non-destructive etching of the deposition surface of the wafer using a mixed gas of hydrogen and argon and a Coil electrode.

[0091] Table 1

[0092] Parameter 1 2 3 4 5 6 7 Step Name Pump1 Gasin Ign1 Ign2 Etch Pump2 End Time 10 10 2 2 30-60 10 15 Pressure 0 0 0 0 0 0 0 Coil RF 0 0 200-1000 200-1000 200-1000 0 0 Coil Match Auto Auto Auto Auto Auto Auto Auto Ar1 0 10 10 10-30 10-30 0 0 Ar2 0 190 190 0 0 100 0 H2 0 10 10 10-60 10-60 0 Gate Valve Full Full Full Full Full Full Full

[0093] In Table 1, the first column represents each process parameter, Parameter 1-7 indicates that there are 7 processes; Step Name represents the name of each step, Pump1 and Pump2 represent two pumping processes, Gasin represents the introduction of physical bombardment gas into the pre-cleaning chamber; Igni represents ignition, that is, the chamber is loaded with a certain DC power to ionize the process gas and generate plasma; Etch represents the etching process; Coil RF represents the loaded coil radio frequency power. In the first ignition stage (Ign1), the second ignition stage (Ign1) and the etching stage (Etch), the power range used is 200W to 1000W; the radio frequency frequency loaded by Coil is 13.56MHz; Ar1 ​​represents the argon gas introduced through the first physical bombardment ventilation pipeline, Ar2 represents the argon gas introduced through the second physical bombardment ventilation pipeline, and H2 represents the hydrogen gas introduced through the reduction ventilation pipeline. In the ventilation stage of the pre-cleaning chamber and the first ignition stage, the volume flow rate of Ar2 is greater than the volume flow rate of Ar1; in the second ignition stage and the etching stage of the pre-cleaning chamber, a small amount of Ar2 is stopped and only Ar1 is introduced; in the Pump2 stage, a large amount of Ar2 is introduced and Ar1 is stopped to facilitate the extraction of the reducing gas.

[0094] In order to further improve the cleaning efficiency and reduce the etching time in the pre-cleaning chamber, optionally, before ionizing the first process gas to form plasma and using the plasma to clean the surface of the wafer to be deposited in step S1, the semiconductor process method further includes:

[0095] S20, wet cleaning the surface of the wafer to be deposited.

[0096] The wet cleaning process can be performed using an acid cleaning process. For example, the wafer can be cleaned with 1:100 hydrofluoric acid for 60 to 90 seconds to remove the oxidized SiO2 layer on the surface. Of course, hydrogen peroxide solution or ozone cleaning solution can also be used for cleaning.

[0097] In one or more embodiments, S3, annealing the wafer on which the first metal layer is deposited in a sputtering chamber, comprises:

[0098] S3', introducing annealing gas into the sputtering chamber, controlling the cold pump of the sputtering chamber to be in a closed state, adjusting the pressure of the sputtering chamber to a preset pressure, and maintaining it for a preset time to anneal the wafer deposited with the first metal layer.

[0099] In order to maximize the utilization rate of existing process equipment, the annealing gas may be an inert gas. For example, the inert gas may include argon (Ar), helium (He), neon (Ne), krypton (Kr), or xenon (Xe).

[0100] The above preset pressure and duration can be selected based on actual requirements and are not limited here. It should be noted that the sputtering chamber pressure is approximately 2.5 mTorr during the deposition of the first metal layer; during the annealing phase, the sputtering chamber pressure needs to be maintained at approximately 1 Torr to improve heat transfer efficiency. To achieve the required pressure, the cold pump needs to be turned off to increase the pressure.

[0101] During the preset time, the cold pump of the sputtering chamber is in a closed state and the pressure of the sputtering chamber is a preset pressure to perform sufficient annealing.

[0102] Optionally, S3′, introducing annealing gas into the sputtering chamber, controlling a cold pump of the sputtering chamber to be in an off state, adjusting the pressure of the sputtering chamber to a preset pressure, and maintaining the pressure for a preset time to anneal the wafer deposited with the first metal layer, includes:

[0103] S301. During a first time period, control the cold pump of the sputtering chamber to be in a closed state, and introduce annealing gas into the sputtering chamber to adjust the pressure of the sputtering chamber to a preset pressure; wherein the first time period ranges from 20s to 60s.

[0104] The first time period can be 20 seconds, 30 seconds, 40 seconds, 50 seconds, or 60 seconds. The volume flow rate of the annealing gas introduced is in the range of 100 sccm to 500 sccm, and can specifically be 100 sccm, 200 sccm, 300 sccm, 400 sccm, or 500 sccm. To achieve rapid annealing, reduce annealing time, and further reduce production costs, the volume flow rate of the annealing gas introduced in step S301 is relatively large.

[0105] S302. After the first time period ends, stop introducing the annealing gas, and control the cold pump of the sputtering chamber to continue to be in a closed state within a preset time period to anneal the wafer deposited with the first metal layer; wherein the preset time period ranges from 30s to 90s, and within the first time period and the preset time period, the base temperature of the sputtering chamber ranges from 300℃ to 450℃.

[0106] The purpose of step S301 is to introduce (Vent) a preset flow rate of annealing gas into the sputtering chamber, and then hold (Hold) it for a period of time to perform annealing after step S302. The annealing principle is that the introduced annealing gas (for example, argon) fully anneals the wafer deposited with the first metal layer through heat conduction and heat radiation to ensure the formation of a dense and uniform miscible structure.

[0107] The above-mentioned preset time length can be 30s, 50s, 70s or 90s. It should be noted that in the related art, the temperature of the base of the sputtering chamber is relatively low. In order to further improve the annealing efficiency, in steps S501 and S502, the temperature of the base of the sputtering chamber can be controlled at a higher temperature, for example: 300℃~450℃, specifically 300℃, 350℃, 400℃ or 450℃, so as to further improve the efficiency of heat conduction and heat radiation, and further improve the annealing effect.

[0108] In addition, the temperature of the base of the sputtering chamber is set relatively high, so annealing can be started while the first metal layer is sputtered in step S2, thereby further shortening the holding time of the subsequent annealing and further reducing the annealing time. In addition, since the plasma formed by the mixed gas and the Coil electrode are used to non-destructively etch the surface of the wafer to be deposited, the first metal layer and the wafer can directly react to form a mutually soluble structure in step S2, and since the surface is intact, the external energy required to form the mutually soluble structure is small and the time required is short, thereby further reducing the annealing time of step S3. In this application, the overall annealing time range in step S3 is 1 min to 3 min, which is much less than the time (60 min to 90 min) of furnace tube annealing after back metallization in the related art.

[0109] Taking the example that the annealing gas includes argon and the material of the first metal layer includes Al as an example, relevant equipment parameters for depositing the first metal layer and in-situ annealing are provided.

[0110] Table 2

[0111]

[0112] As shown in Table 2, the first column represents each process parameter. Parameter 1-7 indicates the seven steps. StepName represents the name of each step. Gasin indicates the introduction of argon, the physical bombardment gas, into the sputtering chamber. Igni indicates ignition, which applies a certain DC power to the chamber to ionize the process gas and generate a plasma. Dep indicates the deposition of the first metal layer. Close indicates stop. Vent indicates the introduction of annealing gas. Hold indicates hold. End indicates end. Time indicates time. As can be seen from Table 2, the deposition time ranges from 10s to 30s, the Vent time (i.e., the first time period) ranges from 20s to 60s, and the Hold time (i.e., the preset duration) ranges from 30s to 90s. Pressure and Backside Pressure represent pressure and backside pressure, respectively, and are both zero in all seven steps. Pressure Source DC indicates the pressure source DC power, and Source DCRamp indicates the applied DC power. Ar1 indicates that the introduced gas is Ar. The Ar volume flow rate during the Vent process is much greater than that during the Dep process, thereby reducing the annealing time. Gate Valve indicates the cold pump, Full indicates open, and Close indicates closed. During Gasin, Igni, Dep, and End, the cold pump is open, and during Close, Vent, and Hold, the cold pump is closed. The Al-Si alloy formed using this process parameter can be referred to Figure 5 and Figure 6 As shown, Figure 5 This is the SEM interface image of Al-Si alloy. Figure 6 This is the SEM top view of Al-Si alloy after pickling. Figure 5 and Figure 6 The area framed by the white dotted line is the Al-Si alloy; Figure 5 and Figure 6 It can be seen that the formed Al-Si alloy is dense, uniform and has good mutual solubility effect.

[0113] In one or more embodiments, after step S3, annealing the wafer on which the first metal layer is deposited in the sputtering chamber, referring to Figure 8 As shown, the semiconductor process method further includes:

[0114] S4. Using a magnetron sputtering process, a second metal layer, a third metal layer and a fourth metal layer are sequentially deposited on the wafer on which the first metal layer is deposited; wherein the first metal layer is arranged between the second metal layer and the wafer.

[0115] There is no limitation on the materials of the second metal layer, the third metal layer and the fourth metal layer. The second metal layer as an adhesion layer mainly connects the first metal layer and the third metal layer to reduce the contact resistance. Its material may include titanium; the third metal layer as a barrier layer prevents the fourth metal layer from diffusing into the interior of the device and prevents the metal layer from being punched through during packaging and bonding. Its material may include nickel or nickel vanadium. The fourth metal layer is mainly used as an electrode, so it can be made of a material with excellent electrical and thermal conductivity. Its material may include silver. The stacked deposited first metal layer, second metal layer, third metal layer and fourth metal layer can be used as the back metal layer of the IGBT device.

[0116] In order to utilize the existing production line as much as possible to reduce production costs, optionally, the material of the wafer includes silicon, the material of the first metal layer includes aluminum, the material of the second metal layer includes titanium, the material of the third metal layer includes nickel, and the material of the fourth metal layer includes silver.

[0117] Aluminum can act as an acceptor impurity, further increasing the surface P-type concentration, reducing the device's on-state voltage drop, and improving device performance. Silver has excellent electrical and thermal conductivity.

[0118] The thickness of the aluminum layer may be in the range of 150 nm to 300 nm, the thickness of the titanium layer may be in the range of 80 nm to 320 nm, the thickness of the nickel layer may be in the range of 150 nm to 600 nm, and the thickness of the silver layer may be in the range of 600 nm to 1200 nm.

[0119] It should be noted that the Al, Ti, Ni and Ag layers are all sputtered in a magnetron sputtering device, that is, after the Al layer is deposited and sputtered, the Ti deposition chamber, Ni deposition chamber, and Ag deposition chamber will be sequentially removed to form the Ti layer, Ni layer, and Ag layer, respectively. Because the thickness of Ag is relatively thick, the sputtering time is the longest (about 5 minutes). The overall annealing time range of the Al layer is 1 minute to 3 minutes; then, when the current wafer completes annealing in the Al deposition chamber, the previous wafer is still sputtering in the Ag chamber. The thin film deposition method provided in this application does not affect the utilization efficiency of the Al chamber, and at the same time can save the time (60 minutes to 90 minutes) of furnace tube annealing after back metallization in the related technology, thereby greatly improving the product capacity (WPH).

[0120] In addition, it should be noted that in the related art, reference Figure 11As shown in the figure, after depositing the back-side Al, Ti, Ni, and Ag metal layers, the device is annealed in a furnace at 350-450°C for 60-90 minutes to form an Al-Si alloy ohmic contact and reduce the device's contact resistance. During the annealing process, the back-side metal layer recrystallizes, causing the Ag grains to grow larger. Oxygen can penetrate the tiny intergranular gaps to reach the Ni metal surface, causing oxidation. Therefore, the annealing process must be maintained in an N2 atmosphere to mitigate oxidation of the Ni and Ag metal layers during annealing. While annealing in an N2 atmosphere can mitigate oxidation of the Ni and Ag metal layers during annealing, the larger Ag grains increase the chance of oxygen in the atmosphere penetrating the grain gaps to reach the Ni metal surface after annealing. This still increases the risk of Ag metal layer delamination and increases interfacial contact resistance, thereby reducing product performance. Furthermore, prolonged high-temperature annealing can negatively impact the pre-formed front-side structures and passivation layer on the wafer, further impacting product performance.

[0121] The semiconductor process method provided by this application refers to Figure 12 As shown, in-situ annealing can be achieved, thus avoiding the risk of Ag metal layer falling off and increased interface contact resistance, thereby significantly improving product performance. In addition, the short annealing time can avoid negative impacts on the front structure and passivation layer already formed on the wafer. Figure 10 As shown, Figure 10 A corresponds to V of the IGBT device formed by the semiconductor process method provided by this application. CE The sample distribution diagram, corresponding to B, is the V of the IGBT device formed by completing the back metal layer and then high-temperature annealing in the related technology. CE Sample distribution diagram, Figure 10 In the figure, the vertical axis Voltage represents V CE , comparing the two sample distribution graphs, we can conclude that V corresponding to A CE The sample distribution is more convergent, and the V CE The fluctuation range is smaller, which is reflected in the products as higher yield and better device performance.

[0122] refer to Figure 3 As shown, the IGBT device formed by the semiconductor process method provided by this application includes: a substrate 4, and a MOS structure 9 and a collector structure 11 disposed on both sides of the substrate 4; the collector structure 11 includes a multi-layer metal structure 1. Figure 4 As shown, the multilayer metal structure 1 includes a first metal layer 11, a second metal layer 12, a third metal layer 13 and a fourth metal layer 14 stacked together, and the first metal layer 11 is arranged between the substrate 4 and the second metal layer 12; the specific structure of the MOS structure is not limited here, for example, refer to Figure 3As shown, the MOS structure may include a gate 5, an emitter 6, a P- region 7 and an N+ region 8, wherein the gate may include a polysilicon gate; of course, referring to Figure 3 As shown, the collector structure 11 may further include a P-type collector layer 2, which is an ion implantation layer; the transistor may further include an N-type buffer layer 3, and the body structure 10 includes a substrate 4 and an N-type buffer layer 3; the MOS structure 9 is generally arranged on the front side of the body structure 10, and the collector structure 11 is generally arranged on the back side of the body structure 10.

[0123] The substrate may include a silicon substrate, the material of the first metal layer may include aluminum, the material of the second metal layer may include titanium, the material of the third metal layer may include nickel or nickel vanadium, and the material of the fourth metal layer may include silver.

[0124] An embodiment of the present application also provides a semiconductor process equipment, including a pre-cleaning chamber, a transfer chamber, a sputtering chamber and a controller, the controller including at least one processor and at least one memory, the memory storing a computer program, and when the computer program is executed by the processor, implementing any of the semiconductor process methods described above.

[0125] refer to Figure 13 As shown, the semiconductor process equipment may include:

[0126] Loading and unloading chamber (Loadport, LP) 40, Figure 13 The following diagram illustrates three loading and unloading chambers, labeled LP1, LP2, and LP3. Each loading and unloading chamber can store one cassette, which contains multiple slots. Each slot can hold one wafer. The three loading and unloading chambers, LP1, LP2, and LP3, can start processes simultaneously or at different times, depending on process requirements.

[0127] The vacuum-atmosphere conversion chamber 42 is used to switch between atmospheric state and vacuum state during film transfer;

[0128] The ATR atmospheric robot 41 is used to transfer wafers between the vacuum atmosphere conversion chamber 42 and the loading and unloading chamber 40;

[0129] The transfer chamber 43 is provided with a vacuum robot (not shown) for transferring wafers between the process gas chamber 44 and the vacuum atmosphere conversion chamber 42;

[0130] Process chamber 44, Figure 13 6 process chambers are illustrated as an example, and are labeled as ChA, ChB, ..., ChF for distinction. For example, process chamber ChA may be a pre-cleaning chamber, and process chamber ChB may be a sputtering chamber.

[0131] The specific structure of the above-mentioned pre-cleaning chamber is not limited, and is for example only. Figure 14 As shown, the pre-cleaning chamber may include: an air inlet 20, an air inlet device 21, an RF Coil 22, a ceramic barrel 23 and a base 24. The wafer to be cleaned may be placed on the base 24. The mixed gas entering from the air inlet is ionized to form a reducing plasma and a physical bombardment plasma. Under the action of the RF Coil, the physical bombardment plasma excites the silicon-oxygen bond to break; then, the oxygen reacts with the reducing plasma to undergo a reduction reaction, thereby removing the silicon oxide on the surface to be deposited on the wafer with low damage, and at the same time passivating the Si surface defects.

[0132] The specific structure of the sputtering chamber is not limited, and is for example only. Figure 15 As shown, the sputtering chamber may include: a rotating shaft 27, a magnetron 28, a target 29, an air inlet 30, a protective cover 31, a cover ring (Cover The sputtering chamber comprises a cover ring 32, a deposition ring 33, a base 34, a rotating arm 35 and a shielding layer 36; the base 34 is a liftable base. When a thin film needs to be deposited, it is raised to the height of the cover ring 32. The protective cover 31, the cover ring 32 and the deposition ring 33 cooperate with each other to prevent the target atoms from being deposited on the side walls and bottom walls of the chamber during sputtering. The physical bombardment gas introduced from the gas inlet 30 bombards the target 29 under the action of the voltage and the magnetic field generated by the magnetron 28, causing atoms on the surface of the target 29 to fall off and deposit on the surface of the wafer to be deposited on the base 34 to form a thin film to be deposited. If the sputtering chamber is used to deposit a first metal layer, the first metal layer is deposited on the surface to be deposited of the cleaned wafer. Then, annealing gas is introduced through the gas inlet 30, and the cold pump of the sputtering chamber is controlled to be in a closed state to adjust the pressure of the sputtering chamber to a preset pressure and maintain it for a preset time to anneal the wafer deposited with the first metal layer.

[0133] The controller can be either a host computer or a slave computer. For example, the controller can control the opening of a valve on an air inlet assembly to introduce a corresponding process gas into the process chamber 44. The controller can also control the opening and closing of the valve on the air inlet assembly to control the flow rate of the process gas. The controller can also control the exhaust assembly to exhaust air from the process chamber 44, thereby controlling the pressure inside the process chamber 44 and discharging reaction byproducts.

[0134] The type of the above-mentioned memory is not limited. For example, the memory may include ROM (Read-Only Memory), RAM (Random Access Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory, magnetic card or optical card.

[0135] It should be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0136] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A semiconductor process method, characterized in that: include: Ionizing a first process gas to form a plasma, and using the plasma to clean the surface of the wafer to be deposited; wherein the first process gas includes a reducing gas and a physical bombardment gas, and the volume flow rate of the reducing gas introduced during the etching stage is greater than the volume flow rate of the physical bombardment gas introduced; Placing the cleaned wafer in a sputtering chamber, and depositing a first metal layer on the surface to be deposited; The wafer on which the first metal layer is deposited is annealed in the sputtering chamber.

2. The semiconductor process method according to claim 1, characterized in that: The volume flow ratio of the introduced reducing gas to the introduced physical bombardment gas is in the range of 2:1 to 6:

1.

3. The semiconductor process method according to claim 2, characterized in that: The volume flow rate of the reducing gas introduced is in the range of 20 sccm to 60 sccm, and the volume flow rate of the physical bombardment gas introduced is in the range of 10 sccm to 30 sccm.

4. The semiconductor process method according to claim 1, characterized in that: The reducing gas includes hydrogen, and the physical bombardment gas includes argon.

5. The semiconductor process method according to claim 1, characterized in that: The step of ionizing the first process gas to form plasma and using the plasma to clean the surface of the wafer to be deposited comprises: An inductively coupled plasma etching process is adopted in the pre-cleaning chamber to ionize the first process gas to form plasma, and the plasma is used to clean the surface to be deposited on the wafer.

6. The semiconductor process method according to claim 5, characterized in that: The RF frequency range loaded by the coil of the pre-cleaning chamber is 2 MHz to 15 MHz, the RF power range loaded is 200 W to 1500 W, and the base temperature range is 200° C. to 400° C.

7. The semiconductor process method according to claim 1, characterized in that: The step of ionizing the first process gas to form plasma and using the plasma to clean the surface of the wafer to be deposited comprises: During the ignition stage of the pre-cleaning chamber, the reducing gas is continuously introduced into the pre-cleaning chamber through the reduction ventilation pipeline, and the physical bombardment gas is continuously introduced into the pre-cleaning chamber through the first physical bombardment ventilation pipeline and the second physical bombardment ventilation pipeline, respectively; wherein the volume flow rate of the physical bombardment gas introduced through the second physical bombardment ventilation pipeline is greater than the volume flow rate of the physical bombardment gas introduced through the first physical bombardment ventilation pipeline; During the etching stage of the pre-cleaning chamber, the reducing gas is continuously introduced into the pre-cleaning chamber through the reducing ventilation line, the physical bombardment gas is continuously introduced into the pre-cleaning chamber through the first physical bombardment ventilation line, and ventilation through the second physical bombardment ventilation line is stopped; wherein the volume flow rate of the reducing gas introduced through the reducing ventilation line is greater than the volume flow rate of the physical bombardment gas introduced through the first physical bombardment ventilation line.

8. The semiconductor process method according to claim 7, characterized in that: After ionizing the first process gas to form plasma and using the plasma to clean the surface of the wafer to be deposited, the semiconductor process method further includes: During the evacuation phase of the pre-cleaning chamber, the physical bombardment gas is introduced into the pre-cleaning chamber through the second physical bombardment ventilation pipeline, and ventilation through the reduction ventilation pipeline and the first physical bombardment ventilation pipeline is stopped.

9. The semiconductor process method according to claim 1, characterized in that: Before ionizing the first process gas to form plasma and using the plasma to clean the surface to be deposited on the wafer, the semiconductor process method further includes: The surface of the wafer to be deposited is wet cleaned.

10. The semiconductor process method according to claim 1, characterized in that: Annealing the wafer on which the first metal layer is deposited in the sputtering chamber comprises: Annealing gas is introduced into the sputtering chamber, and a cold pump of the sputtering chamber is controlled to be in a closed state to adjust the pressure of the sputtering chamber to a preset pressure and maintain it for a preset time to anneal the wafer deposited with the first metal layer.

11. The semiconductor process method according to claim 10, characterized in that: The step of introducing annealing gas into the sputtering chamber and controlling a cold pump of the sputtering chamber to be in a closed state to adjust the pressure of the sputtering chamber to a preset pressure and maintain the pressure for a preset time to anneal the wafer deposited with the first metal layer comprises: In a first time period, the cold pump of the sputtering chamber is controlled to be in a closed state, and the annealing gas is introduced into the sputtering chamber to adjust the pressure of the sputtering chamber to the preset pressure; wherein the first time period ranges from 20s to 60s; After the first time period ends, the annealing gas is stopped from being introduced, and the cold pump of the sputtering chamber is controlled to remain in a closed state within the preset time period to anneal the wafer deposited with the first metal layer; wherein the preset time period ranges from 30s to 90s, and within the first time period and the preset time period, the base temperature of the sputtering chamber ranges from 300°C to 450°C.

12. A semiconductor process equipment, characterized in that: The invention comprises a pre-cleaning chamber, a transfer chamber, a sputtering chamber and a controller, wherein the controller comprises at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the semiconductor process method as described in any one of claims 1 to 11 is implemented.

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