Semiconductor device and manufacturing method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. The manufacturing method comprises the steps of forming a semiconductor body; a first mask layer is formed on the first surface of the semiconductor body, the first mask layer comprises a first through hole, and the first through hole exposes the gate trench and at least part of the first area; forming a first oxide layer in the gate trench; forming an inversion layer in the semiconductor body by taking the first mask layer as a mask; removing the first mask layer and the first oxide layer; and forming an insulating layer and a trench gate in the gate trench. The invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, which can reduce the process steps of manufacturing the semiconductor device and reduce the manufacturing cost of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Common MOS (metal oxide semiconductor, metal oxide field effect transistor) devices are enhancement-mode devices, which are normally non-conductive. To conduct, a positive voltage needs to be directly applied to Vgs (gate-source voltage) to form a channel conduction in the MOS device.

[0003] The depletion-mode MOS device is normally conductive. In the cut-off state, a negative voltage needs to be applied to Vgs to cut off the MOS device channel. Therefore, it can respond and control the current flow faster, with small conduction loss, and is more suitable for high-frequency circuits and switching circuits.

[0004] However, the existing depletion-mode MOS device manufacturing process is complex and the manufacturing cost is high, which limits the further development of the depletion-mode MOS device. Summary of the Invention

[0005] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, which can reduce the process steps for manufacturing the semiconductor device and lower the manufacturing cost of the semiconductor device.

[0006] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising:

[0007] forming a semiconductor body, wherein the semiconductor body includes a first surface and a second surface disposed opposite to each other, the semiconductor body further including a well region and a first region, the first region being configured as a first conductivity type and located on the first surface; the well region being configured as a second conductivity type and located on a side of the first region away from the first surface; the first surface further including a gate trench extending from the first surface into the semiconductor body, the first region being adjacent to the gate trench;

[0008] forming a first mask layer on the first surface of the semiconductor body, wherein the first mask layer comprises a first through hole, and the first through hole exposes the gate trench and at least a portion of the first region;

[0009] forming a first oxide layer in the gate trench;

[0010] forming an inversion layer in the semiconductor body using the first mask layer as a mask, wherein the inversion layer is adjacent to a sidewall of the gate trench; and the inversion layer is set to be of a first conductivity type;

[0011] removing the first mask layer and the first oxide layer;

[0012] An insulating layer and a trench gate are formed in the gate trench, wherein the insulating layer is located on the bottom surface and sidewalls of the gate trench, and the trench gate is located on a side of the insulating layer in the gate trench away from the inversion layer.

[0013] Optionally, forming a semiconductor body includes:

[0014] forming a semiconductor transition body, wherein the semiconductor transition body comprises a first surface and a second surface disposed opposite to each other, the semiconductor transition body further comprising a transition well region and a first transition region, the transition well region comprising a first sub-well region and a second sub-well region, the first sub-well region being adjacent to the first transition region and located on the first surface, and the second sub-well region being located on a side of the first sub-well region and the first transition region away from the first surface;

[0015] forming a second mask layer on the first surface of the semiconductor transition body, wherein the second mask layer comprises a second through hole, and the second through hole at least exposes the first sub-well region;

[0016] Using the second mask layer as a mask, etching the semiconductor transition body to form the gate trench, and the etched semiconductor transition body serves as the semiconductor body;

[0017] The forming of a first mask layer on the first surface comprises:

[0018] The second mask layer is processed to form the first mask layer.

[0019] Optionally, processing the second mask layer to form the first mask layer includes:

[0020] oxidizing a portion of the second mask layer to form a second oxide layer;

[0021] The second oxide layer is removed to form the first mask layer.

[0022] Optionally, forming a first oxide layer in the gate trench includes:

[0023] Oxide is filled in the gate trench and the first through hole, and at least a portion of the oxide outside the gate trench is removed to form the first oxide layer.

[0024] Optionally, the inversion layer has a thickness of 100 Å to 500 Å.

[0025] Optionally, the material of the second mask layer includes polysilicon.

[0026] Optionally, after forming the insulating layer and the trench gate in the gate trench, the method further includes:

[0027] An interlayer insulating layer and a metal layer are formed in sequence; wherein the interlayer insulating layer is located on the first surface and covers at least the trench gate; the metal layer is located on the first surface and covers the first region and the interlayer insulating layer.

[0028] Optionally, a length of the inversion layer in a thickness direction of the semiconductor body is smaller than a depth of the gate trench.

[0029] According to another aspect of the present invention, there is provided a semiconductor device, wherein the semiconductor device is manufactured using the method for manufacturing a semiconductor device provided by any embodiment of the present invention;

[0030] The semiconductor device comprises:

[0031] A semiconductor body comprising a first surface and a second surface disposed opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being configured as a first conductivity type and located on the first surface; the well region being configured as a second conductivity type and located on a side of the first region away from the first surface; a gate trench being further disposed on the first surface, the gate trench extending from the first surface into the semiconductor body, the first region being adjacent to the gate trench;

[0032] an inversion layer, the inversion layer being adjacent to a sidewall of the gate trench; the inversion layer being of a first conductivity type;

[0033] an insulating layer, the insulating layer being located on the bottom surface and sidewalls of the gate trench;

[0034] A trench gate is located in the gate trench on a side of the insulating layer away from the inversion layer.

[0035] According to another aspect of the present invention, a power module is provided. The power module includes a substrate and at least one semiconductor device provided by any embodiment of the present invention, wherein the substrate is used to support the semiconductor device.

[0036] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0037] The power conversion circuit includes a circuit board and at least one semiconductor device provided by any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0038] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as provided in any embodiment of the present invention, wherein the power conversion circuit is configured to convert alternating current (AC) into direct current (DC), convert DC into DC, or convert DC into AC, and then input the converted DC into AC, and then input the converted DC into the load.

[0039] An embodiment of the present invention provides a method for fabricating a semiconductor device. The method comprises: first forming a semiconductor body, then forming a first mask layer on one side of the semiconductor body, then forming a first oxide layer within a gate trench of the semiconductor body, then forming an inversion layer within the semiconductor body using the first mask layer as a mask, then removing the first mask layer and the first oxide layer, and finally forming an insulating layer and a trench gate within the gate trench, thereby forming a semiconductor device. In this embodiment, during the fabrication of the semiconductor device, the inversion layer is formed by fabricating the first mask layer, eliminating the need for photolithography to fabricate the inversion layer. This reduces the number of process steps required to fabricate the semiconductor device and lowers the manufacturing cost of the semiconductor device.

[0040] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0043] Figure 2 is a schematic structural diagram of a semiconductor body provided according to an embodiment of the present invention;

[0044] Figure 3 is a schematic diagram of the structure after forming the first mask layer;

[0045] Figure 4 Schematic diagram of the structure after the first oxide layer is formed;

[0046] Figure 5 Schematic diagram of the structure after the inversion layer is formed;

[0047] Figure 6 is a schematic diagram of the structure after removing the first mask layer and the first oxide layer;

[0048] Figure 7 A schematic diagram of a structure in which an insulating layer and a trench gate are formed in a gate trench;

[0049] Figure 8 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0050] Figure 9 This is a schematic structural diagram of a semiconductor transition body provided according to an embodiment of the present invention;

[0051] Figure 10 is a schematic diagram of the structure after forming the second mask layer;

[0052] Figure 11 is a schematic diagram of the structure of the semiconductor body formed after etching;

[0053] Figure 12 A schematic structural diagram of oxidizing a portion of the second mask layer to form a second oxide layer;

[0054] Figure 13 is a schematic diagram of the structure after the gate trench and the first through hole are filled with oxide;

[0055] Figure 14 is a schematic structural diagram of another semiconductor device provided according to an embodiment of the present invention;

[0056] Figure 15 is a structural schematic diagram of a substrate transition structure provided according to an embodiment of the present invention;

[0057] Figure 16 Schematic diagram of the structure after the third area is formed;

[0058] Figure 17 and Figure 18 A schematic diagram of the process structure after the first transition region is formed;

[0059] Figure 19 A schematic diagram of the structure for forming a trench gate transition layer. DETAILED DESCRIPTION

[0060] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0061] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0062] Figure 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, with reference to Figure 1 The manufacturing method provided in this embodiment includes the following steps:

[0063] S110 , forming a semiconductor body.

[0064] in, Figure 2 is a schematic structural diagram of a semiconductor body provided according to an embodiment of the present invention, with reference to Figure 2 The semiconductor body 100 includes a first surface and a second surface disposed opposite each other. The semiconductor body 100 also includes a well region 130 and a first region 140. The first region 140 is configured as a first conductivity type and is located on the first surface. The well region 130 is configured as a second conductivity type and is located on a side of the first region 140 away from the first surface. The first surface is also provided with a gate trench 170, which extends from the first surface into the semiconductor body 100. The first region 140 is adjacent to the gate trench 170. The semiconductor body 100 may further include a second region 150. The second region 150 is configured as a second conductivity type and is located on the first surface. The second region 150 surrounds the first region 140.

[0065] Specifically, the semiconductor body 100 further includes a substrate layer 110 and an epitaxial layer 120. The epitaxial layer 120 is located on one side of the substrate layer 110, and the well region 130 is located on a side of the epitaxial layer 120 away from the substrate layer 110. The first region 140 and the second region 150 may be adjacent in a set direction, with the plane of the set direction being parallel to the surface of the substrate layer 110 supporting the epitaxial layer 120. The semiconductor device includes an N-type MOSFET semiconductor device or a P-type MOSFET semiconductor device. Taking an N-type MOSFET semiconductor device as an example, the first conductivity type is N-type and the second conductivity type is P-type. The semiconductor body is an N-type semiconductor body, the first region 140 is an N+ doped region, the second region 150 is a P+ doped region, the well region 130 is a P-well region, and the substrate layer 110 is an N+ substrate.

[0066] S120 , forming a first mask layer on the first surface of the semiconductor body.

[0067] in, Figure 3 The schematic diagram of the structure after forming the first mask layer is shown in FIG. Figure 3 The first mask layer 160 includes a first through hole 161 , and the first through hole 161 exposes the gate trench 170 and at least a portion of the first region 140 .

[0068] Specifically, the vertical projection of the first through hole 161 on the well region 130 covers the inner boundary of the vertical projection of the first region 140 on the well region 130 and the vertical projection of at least part of the first region 140 adjacent to the inner boundary, and covers the vertical projection of the gate trench 170 on the well region 130.

[0069] A vertical projection of the first region 140 on the well region 130 includes an inner boundary and an outer boundary. Compared to the inner boundary of the first region 140 , the outer boundary of the first region 140 is closer to the second region 150 .

[0070] The first through hole 161 may expose at least a portion of the surface of the first region 140 adjacent to the sidewall of the gate trench 170 .

[0071] S130 , forming a first oxide layer in the gate trench.

[0072] in, Figure 4 For the structural diagram after forming the first oxide layer, refer to Figure 4 , the thickness of the first oxide layer 171 is less than or equal to the depth of the gate trench.

[0073] Specifically, the bottom of the gate trench may be located in the epitaxial layer 120, and the first oxide layer 171 may cover the epitaxial layer 120 exposed by the gate trench. The first oxide layer 171 does not cover the surface of the first region 140 away from the substrate layer 110, and the material of the first oxide layer 171 may be silicon dioxide.

[0074] S140 , forming an inversion layer in the semiconductor body using the first mask layer as a mask.

[0075] in, Figure 5 For the structural diagram after the inversion layer is formed, refer to Figure 5 The inversion layer 180 is adjacent to the sidewall of the gate trench and is configured to be of the first conductivity type.

[0076] Specifically, the first mask layer 160 can be used as a mask to vertically downwardly inject ions having a first conductivity type into the semiconductor body to form an inversion layer 180. Vertical injection facilitates the control of the concentration of doped ions in the inversion layer 180. The concentration of doped ions in the inversion layer 180 can be set according to actual needs. The height of the inversion layer 180 is less than the depth of the gate trench. The inversion layer 180 is arranged in a direction perpendicular to the surface of the substrate layer 110 supporting the epitaxial layer 120. In this embodiment, the inversion layer 180 is formed using the first mask layer 160 as a mask. There is no need to use a photolithography process to form the inversion layer 180, which reduces the process steps for forming the inversion layer 180 and reduces the cost of forming the inversion layer 180. Since the first oxide layer 171 is located in the gate trench, the doped ions injected during the formation of the inversion layer 180 will not be deposited at the bottom of the gate trench.

[0077] S150 , removing the first mask layer and the first oxide layer.

[0078] Specifically, Figure 6 It is a schematic diagram of the structure after removing the first mask layer and the first oxide layer.

[0079] S160 , forming an insulating layer and a trench gate in the gate trench.

[0080] in, Figure 7 Schematic diagram of the structure of forming an insulating layer and a trench gate in the gate trench. Figure 7 A schematic diagram of the structure of a semiconductor device provided by this embodiment can be referred to as Figure 7 The insulating layer 181 is located on the bottom surface and sidewalls of the gate trench, and the trench gate 182 is located on a side of the insulating layer 181 in the gate trench away from the inversion layer 180 .

[0081] Specifically, the insulating layer 181 and the trench gate 182 fill the gate trench. A thermal oxidation process can be used to oxidize the inner wall surface of the gate trench to form the insulating layer 181. The temperature range of the thermal oxidation process can be 1000°C to 1500°C. The material of the insulating layer 181 can be silicon oxide. Before forming the insulating layer 181, a protective layer can be formed on the first surface side of the semiconductor body. The protective layer can be a carbon film, and then high-temperature annealing is performed to activate the implanted ions. After removing the carbon film, a sacrificial oxide layer is formed and then the sacrificial oxide layer is removed to eliminate the surface damage caused by annealing. The material of the trench gate 182 can be a conductive material, such as doped polysilicon. The semiconductor device provided in this embodiment can be a depletion-type MOS device.

[0082] This embodiment provides a method for fabricating a semiconductor device. The method includes: first forming a semiconductor body, then forming a first mask layer on one side of the semiconductor body, then forming a first oxide layer within a gate trench of the semiconductor body, then forming an inversion layer within the semiconductor body using the first mask layer as a mask, then removing the first mask layer and the first oxide layer, and finally forming an insulating layer and a trench gate within the gate trench, thereby forming a semiconductor device. In this embodiment, during the process of fabricating the semiconductor device, the inversion layer is formed by fabricating the first mask layer, eliminating the need for photolithography to form the inversion layer, thereby reducing the process steps required to fabricate the semiconductor device and lowering the manufacturing cost of the semiconductor device.

[0083] Figure 8 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention, with reference to Figure 8 The manufacturing method provided in this embodiment includes the following steps:

[0084] S210, forming a semiconductor transition body.

[0085] in, Figure 9 is a schematic structural diagram of a semiconductor transition body provided according to an embodiment of the present invention, with reference to Figure 9 Semiconductor transition body 101 includes a first surface and a second surface disposed opposite each other. Semiconductor transition body 101 also includes a transition well region and a first transition region 141. The transition well region includes a first sub-well region 131 and a second sub-well region 132. First sub-well region 131 is adjacent to first transition region 141 and located on the first surface. Second sub-well region 132 is located on a side of first sub-well region 131 and first transition region 141 away from the first surface. Semiconductor transition body 101 may also include a second region 150, which surrounds first transition region 141.

[0086] Specifically, in the same direction parallel to the surface of the substrate layer 110 supporting the epitaxial layer 120 , the length of the first transition region 141 is greater than or equal to the length of the first region.

[0087] S220 , forming a second mask layer on the first surface of the semiconductor transition body.

[0088] in, Figure 10 For a schematic diagram of the structure after forming the second mask layer, refer to Figure 10 The second mask layer 162 includes a second through hole 163 , and the second through hole 163 at least exposes the first sub-well region 131 .

[0089] Specifically, in the same direction parallel to the surface of the substrate layer 110 supporting the epitaxial layer 120 , the length of the second through hole 163 is smaller than the length of the first through hole.

[0090] S230 , etching the semiconductor transition body using the second mask layer as a mask to form a gate trench, and the etched semiconductor transition body serves as the semiconductor body.

[0091] Specifically, Figure 11 This is a schematic diagram of the structure of the semiconductor body formed after etching, refer to Figure 11 The bottom of the gate trench 170 is located in the epitaxial layer 120. Part of the sidewall of the gate trench 170 exposes the inner boundary of the first region 140. When forming the gate trench 170, the semiconductor body is etched using the second mask layer 162 as a mask to form the gate trench 170. Figure 11 The structure of the semiconductor body shown is similar to Figure 2 The structure of the semiconductor body shown is the same except that Figure 11 Compare Figure 2 A second mask layer is applied to cover the film.

[0092] S240 , processing the second mask layer to form a first mask layer.

[0093] For details, please refer to Figure 4 , after processing the second mask layer, a Figure 4 In the structure shown, the first mask layer in this embodiment is obtained by appropriately processing the second mask layer, rather than removing the second mask layer and then separately making the first mask layer. It can be seen that the manufacturing method of the semiconductor device provided in this embodiment can reduce the manufacturing process steps and reduce the manufacturing cost.

[0094] S250 , forming a first oxide layer in the gate trench.

[0095] Specifically, the content of step S250 is the same as that of step S130. For the description of step S250, please refer to the description of step S130, which will not be repeated here.

[0096] S260 , forming an inversion layer in the semiconductor body using the first mask layer as a mask.

[0097] Specifically, the content of step S260 is the same as that of step S140. For the description of step S260, please refer to the description of step S140, which will not be repeated here.

[0098] S270 , removing the first mask layer and the first oxide layer.

[0099] Specifically, the content of step S270 is the same as that of step S150. For the description of step S270, please refer to the description of step S150, which will not be repeated here.

[0100] S280 , forming an insulating layer and a trench gate in the gate trench.

[0101] Specifically, the content of step S280 is the same as that of step S160. For the description of step S280, please refer to the description of step S160, which will not be repeated here.

[0102] Optionally, processing the second mask layer to form the first mask layer includes: oxidizing a portion of the second mask layer to form a second oxide layer; and removing the second oxide layer to form the first mask layer.

[0103] Specifically, Figure 12 For a schematic diagram of a structure in which a portion of the second mask layer is oxidized to form a second oxide layer, refer to Figure 12 The thickness of the second oxide layer 164 can be 200A to 1000A. The schematic diagram of the structure after removing the second oxide layer 164 can be referred to Figure 3 .

[0104] Optionally, forming the first oxide layer in the gate trench includes: filling the gate trench and the first through hole with oxide, and removing at least a portion of the oxide outside the gate trench to form the first oxide layer.

[0105] Specifically, Figure 13 This is a schematic diagram of the structure after the gate trench and the first through hole are filled with oxide, refer to Figure 3 and Figure 13 , available in Figure 3 In the structure shown, an oxide material is deposited to form an oxide 172. The material of the oxide 172 is the same as the material of the first oxide layer. The oxide 172 can be wet-etched to form the first oxide layer. The schematic diagram of the structure after removing part of the oxide 172 to form the first oxide layer can be referred to. Figure 4 .

[0106] Optionally, the thickness of the inversion layer ranges from 100 Å to 500 Å.

[0107] Specifically, the thickness of the inversion layer refers to the length of the inversion layer in the direction from the second region to the first region. In this embodiment, the thickness of the inversion layer is set in the range of 100 Å to 500 Å, which can ensure that the inversion layer forms a conductive channel, so that the semiconductor device provided by this embodiment is conductive under normal conditions.

[0108] Optionally, the material of the second mask layer includes polysilicon; the material of the substrate layer and the material of the epitaxial layer include silicon carbide.

[0109] Specifically, polysilicon can be consumed by oxidation and removal, and the thickness of the oxidation can be controlled to precisely control the thickness of the inversion layer without adding a new photolithography layer, thereby reducing overlay deviation.

[0110] Silicon carbide material has the characteristics of large band gap, strong critical breakdown electric field, high thermal conductivity, high temperature resistance and excellent heat dissipation performance. Semiconductor devices made of silicon carbide material operate in high temperature environments without the need for additional heat dissipation devices, greatly reducing the size and cost of the system including the semiconductor device provided by this embodiment.

[0111] Optionally, after forming the insulating layer and the trench gate in the gate trench, the method further includes: sequentially forming an interlayer insulating layer and a metal layer.

[0112] in, Figure 14 is a schematic structural diagram of another semiconductor device provided according to an embodiment of the present invention. Figure 14 The semiconductor device shown is manufactured using the manufacturing method of the semiconductor device provided in this embodiment, referring to Figure 14 The interlayer insulating layer 183 is located on the first surface, and the interlayer insulating layer 183 at least covers the trench gate 182 ; the metal layer 184 is located on the first surface, and the metal layer 184 covers the first region 140 and the interlayer insulating layer 183 .

[0113] Specifically, the metal layer 184 is electrically connected to the second region 150 and the first region 140. The metal layer 184 is a source of the semiconductor device.

[0114] Optionally, the length of the inversion layer in the thickness direction of the semiconductor body is smaller than the depth of the gate trench, so that the formed channel region can form a conductive channel with the epitaxial layer 120 .

[0115] Optionally, forming a semiconductor body includes: forming a semiconductor body including a silicon carbide semiconductor body.

[0116] Specifically, the semiconductor body includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. Silicon carbide MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance, and high frequency, which can further improve the performance of semiconductor devices.

[0117] Optionally, forming a semiconductor transition body includes the following steps:

[0118] S111. Provide a substrate transition structure.

[0119] in, Figure 15 is a schematic structural diagram of a substrate transition structure provided according to an embodiment of the present invention, with reference to Figure 15 The substrate transition structure includes a substrate layer 110 and an epitaxial transition layer 121 .

[0120] S112 , implanting ions of the second conductivity type into a side of the epitaxial transition layer away from the substrate layer to form a third region.

[0121] Specifically, Figure 16 For the structural diagram after the third area is formed, refer to Figure 16 The region of the epitaxial transition layer not doped with ions of the second conductivity type may be the epitaxial layer 120 . The vertical projection of the third region 133 on the substrate layer 110 covers the vertical projection of the epitaxial layer 120 on the substrate layer 110 .

[0122] S113 , implanting ions of the first conductivity type into a first set region of the third region to form a first transition region.

[0123] Specifically, a photoresist may be coated on the side of the third region away from the substrate layer, and then photolithography and development are performed. The structural diagram of the developed photoresist 134 can be referred to as Figure 17 After development, ions with the first conductivity type are injected to form the first transition region 141, and then the remaining photoresist is removed. The structural diagram after removing the photoresist can be referred to Figure 18 .

[0124] S114 , implanting ions of the second conductivity type into a second set region of the third region to form a second region.

[0125] Specifically, the forming process of the second region may be the same as the forming process of the first transition region 141 . Figure 9 It can be a schematic diagram of the structure after the second region is formed.

[0126] Optionally, forming an insulating layer and a trench gate in the gate trench includes the following steps:

[0127] S181 , forming an insulating layer on the sidewalls and the bottom of the gate trench.

[0128] The insulating layer does not fill the trench completely.

[0129] S182, forming a trench gate transition layer covering the gate trench, the first region and the second region.

[0130] Specifically, Figure 19 For a schematic diagram of the structure of the trench gate transition layer, refer to Figure 19 , a trench gate material may be deposited into the gate trench to form a trench gate transition layer 185 .

[0131] S183, etching the trench gate transition layer outside the gate trench to form a trench gate.

[0132] Specifically, Figure 7 FIG. 1 is a schematic structural diagram of the trench gate 182 formed in step S183 .

[0133] This embodiment also provides a semiconductor device, which is manufactured using the method for manufacturing a semiconductor device provided by any embodiment of the present invention. Figure 7 The semiconductor device includes: a semiconductor body, an inversion layer, an insulating layer, and a trench gate. The semiconductor body includes a first surface and a second surface arranged opposite to each other. The semiconductor body also includes a well region 130 and a first region 140. The first region 140 is set to the first conductivity type and is located on the first surface; the well region 130 is set to the second conductivity type and is located on the side of the first region 140 away from the first surface; the first surface is also provided with a gate trench 170, which extends from the first surface into the semiconductor body 100, and the first region 140 is adjacent to the gate trench 170. The inversion layer 180 is adjacent to the sidewall of the gate trench. The inversion layer 180 is set to the first conductivity type. The insulating layer 181 is located on the bottom surface and sidewalls of the gate trench, and the trench gate 182 is located in the gate trench on the side of the insulating layer 181 away from the inversion layer 180.

[0134] An embodiment of the present invention provides a power module comprising a substrate and at least one semiconductor device as described in any of the embodiments of the present invention, wherein the substrate is configured to support the semiconductor device. Therefore, the beneficial effects of the power module including the semiconductor device as described in any of the embodiments of the present invention are not further elaborated here.

[0135] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0136] Therefore, the beneficial effects of the power conversion circuit including any semiconductor device described in the embodiments of the present invention will not be repeated here.

[0137] An embodiment of the present invention further provides a vehicle including a load and a power conversion circuit according to any embodiment of the present invention. The power conversion circuit is configured to convert AC power to DC power, AC power to AC power, DC power to DC power, or DC power to AC power, and then input the converted power to the load. Therefore, the beneficial effects of the power conversion circuit described in any embodiment of the present invention in the vehicle are not further elaborated here.

[0138] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0139] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Forming a semiconductor body, wherein the semiconductor body includes a first surface and a second surface arranged opposite to each other, and the semiconductor body further includes a well region and a first region, the first region is set to a first conductivity type and is located on the first surface; the well region is set to a second conductivity type and is located on a side of the first region away from the first surface; the first surface is further provided with a gate trench, the gate trench extends from the first surface into the semiconductor body, and the first region is adjacent to the gate trench; forming a first mask layer on the first surface of the semiconductor body, wherein the first mask layer comprises a first through hole, and the first through hole exposes the gate trench and at least a portion of the first region; forming a first oxide layer in the gate trench; Using the first mask layer as a mask, forming an inversion layer in the semiconductor body, wherein the inversion layer is adjacent to the sidewall of the gate trench; and the inversion layer is set to be a first conductivity type; removing the first mask layer and the first oxide layer; An insulating layer and a trench gate are formed in the gate trench, wherein the insulating layer is located on the bottom surface and sidewalls of the gate trench, and the trench gate is located on a side of the insulating layer in the gate trench away from the inversion layer.

2. The method according to claim 1, characterized in that: The forming of the semiconductor body comprises: forming a semiconductor transition body, wherein the semiconductor transition body comprises a first surface and a second surface arranged opposite to each other, the semiconductor transition body further comprises a transition well region and a first transition region, the transition well region comprises a first sub-well region and a second sub-well region, the first sub-well region is adjacent to the first transition region and is located on the first surface, and the second sub-well region is located on a side of the first sub-well region and the first transition region away from the first surface; forming a second mask layer on the first surface of the semiconductor transition body, wherein the second mask layer comprises a second through hole, and the second through hole at least exposes the first sub-well region; Using the second mask layer as a mask, etching the semiconductor transition body to form the gate trench, and the etched semiconductor transition body serves as the semiconductor body; The forming of a first mask layer on the first surface comprises: The second mask layer is processed to form the first mask layer.

3. The method according to claim 2, characterized in that: The step of processing the second mask layer to form the first mask layer includes: oxidizing a portion of the second mask layer to form a second oxide layer; The second oxide layer is removed to form the first mask layer.

4. The method according to claim 1, characterized in that: The forming of a first oxide layer in the gate trench comprises: Oxide is filled in the gate trench and the first through hole, and at least a portion of the oxide outside the gate trench is removed to form the first oxide layer.

5. The method according to claim 1, characterized in that: The thickness of the inversion layer is 100 Å to 500 Å.

6. The method according to claim 2, characterized in that: The material of the second mask layer includes polysilicon.

7. The manufacturing method according to claim 1, characterized in that: After forming an insulating layer and a trench gate in the gate trench, the method further includes: An interlayer insulating layer and a metal layer are formed in sequence; wherein the interlayer insulating layer is located on the first surface and covers at least the trench gate; the metal layer is located on the first surface and covers the first region and the interlayer insulating layer.

8. The manufacturing method according to claim 1, characterized in that: A length of the inversion layer in a thickness direction of the semiconductor body is smaller than a depth of the gate trench.

9. A semiconductor device, characterized in that: Made by the method for making a semiconductor device according to any one of claims 1 to 8; The semiconductor device comprises: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being set to a first conductivity type and being located on the first surface; the well region being set to a second conductivity type and being located on a side of the first region away from the first surface; the first surface further being provided with a gate trench, the gate trench extending from the first surface into the semiconductor body, the first region being adjacent to the gate trench; an inversion layer, the inversion layer being adjacent to a sidewall of the gate trench; the inversion layer being set to be of a first conductivity type; an insulating layer, the insulating layer being located on the bottom surface and sidewalls of the gate trench; A trench gate is located in the gate trench on a side of the insulating layer away from the inversion layer.

10. A power module, characterized in that: The method comprises a substrate and at least one semiconductor device according to claim 9, wherein the substrate is used for carrying the semiconductor device.

11. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as claimed in claim 9, wherein the semiconductor device is electrically connected to the circuit board.

12. A vehicle, characterized in that: It includes a load and a power conversion circuit as claimed in claim 11, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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