Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device includes a drain layer formed of one of n-type or p-type silicon carbide, and a drift layer formed on the drain layer and formed of one of n-type or p-type silicon carbide. In the terminal structure of the chip, the side wall part of the drift layer is bent or inclined inwards, and at least the upper part of the side wall part is in an inverted cone shape. According to the terminal structure, under the condition that the process of the semiconductor device is not complicated, withstand voltage can be ensured, and miniaturization can be realized.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, in particular to semiconductor devices. Background Art

[0002] Patent document 1 (Japanese Patent Laying-Open No. 2018-186160) discloses a semiconductor device in which a plurality of surrounding patterns are arranged near the chip end on the surface in order to alleviate electric field distribution in a vertical high voltage element of the semiconductor device.

[0003] Patent document 2 (Japanese Patent Publication No. 2018-206914) discloses a semiconductor device in which an insulating film is arranged on the side of a second semiconductor layer located at a lateral end among a plurality of second semiconductor layers, or on the side of a third semiconductor layer located at an end among a plurality of third semiconductor layers. A semiconductive film is arranged on the side of the insulating film. The semiconductive film is electrically connected to the first electrode and the second electrode. The resistivity of the semiconductive film is higher than the resistivity of the second semiconductor layer and the third semiconductor layer, but lower than the resistivity of the insulating film. With this structure, a semiconductor device can be provided that does not affect the withstand voltage at the terminal cutting position.

[0004] However, in the semiconductor device described in Patent 1, the terminal structure is configured with many surrounding patterns. Such a terminal structure occupies a large proportion of the chip area. Therefore, it is difficult to achieve miniaturization of the terminal structure of the semiconductor device. Summary of the invention

[0005] The present application is made to overcome the above-mentioned problems. The purpose of the present application is to provide a semiconductor device that can achieve miniaturization and does not use complicated processes while ensuring withstand voltage in a terminal structure.

[0006] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising: a drain layer formed of either n-type or p-type silicon carbide; and a drift layer formed on the drain layer and made of n-type or p-type silicon carbide; In the termination structure, the side wall portion of the drift layer is bent or inclined inwardly, and at least the upper portion of the side wall portion has an inverted tapered shape.

[0007] In some of the embodiments, in the side wall portion, the curvature of the upper portion is greater than the curvature of the lower portion.

[0008] In some of the embodiments, in the side wall portion, an inclination angle of an upper portion is greater than an inclination angle of a lower portion.

[0009] In some of the embodiments, in the sidewall portion, a side surface of the drain layer is vertical.

[0010] In some of the embodiments, in the sidewall portion, a side surface of the drain layer is in a forward tapered shape.

[0011] In some of the embodiments, the device further includes another n-type or p-type doping layer formed on the surface of the sidewall portion, and the impurity concentration of the doping layer is higher than that of the drift layer.

[0012] In some of the embodiments, the device further includes an insulating layer formed on the surface of the doped layer, and the insulating breakdown strength of the insulating layer is not less than that of silicon carbide.

[0013] In some of the embodiments, the device further comprises an insulating layer formed on a surface of the sidewall portion, the insulating layer having a dielectric breakdown strength not lower than that of silicon carbide.

[0014] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0016] Figure 1 It is a cross-sectional view of the main part of the semiconductor device in Example 1 of the present application.

[0017] Figure 2 This is a diagram for explaining a method for forming a terminal structure of a semiconductor device in the first embodiment.

[0018] Figure 3 This is a diagram for explaining a method for forming a terminal structure of a semiconductor device in the first embodiment.

[0019] Figure 4 This is a schematic diagram of the electric field distribution of the semiconductor device in Example 1.

[0020] Figure 5 It is a schematic diagram of the electric field distribution in comparison.

[0021] Figure 6 This is a cross-sectional view of the main part of the semiconductor device in Example 2.

[0022] Figure 7 This is a schematic diagram of the electric field distribution of the semiconductor device in Example 2.

[0023] Figure 8 This is a cross-sectional view of the main part of the semiconductor device in Example 3.

[0024] Fig. 9 This is a schematic diagram of the electric field distribution of the semiconductor device in Example 3.

[0025] 1-semiconductor device; 2-drain layer; 3-drift layer; 4-body layer; 5-source layer; 7-gate insulating layer; 8-gate electrode layer; 10-source electrode layer; 12-drain electrode layer; 13-doping layer; 14-insulating layer. DETAILED DESCRIPTION

[0026] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0027] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0028] Embodiment 1: Figure 1 It is a cross-sectional view of the main part of the semiconductor device in Example 1 of the present application.

[0029] exist Figure 1 , the semiconductor device 1 is a silicon carbide MOSFET. The semiconductor device 1 includes a drain layer 2, a drift layer 3, a plurality of body layers 4, a plurality of source layers 5, a plurality of gate insulating layers 7, a plurality of gate electrode layers 8, a plurality of interlayer insulating layers (not shown), a plurality of source electrode layers 10, a wiring electrode layer (not shown), and a drain electrode layer 12. Figure 1Only one gate insulating layer 7 and one gate electrode layer 8 are shown.

[0030] The drain layer 2 is formed of silicon carbide of the first conductivity type. For example, the drain layer 2 is formed of 4H silicon carbide of n+ type. For example, the drain layer 2 is formed with nitrogen as an impurity. The drift layer 3 is formed on the drain layer 2. The drift layer 3 is formed of silicon carbide of the first conductivity type having a lower impurity concentration than the drain layer 2. For example, the drift layer 3 is an n-type layer.

[0031] A plurality of body layers 4 are formed above the drift layer 3. The plurality of body layers 4 are formed of silicon carbide of the second conductivity type. For example, the plurality of body layers 4 may be p-type layers. A plurality of source layers 5 are respectively formed above the plurality of body layers 4. The plurality of source layers 5 are formed of silicon carbide of the first conductivity type having a higher impurity concentration than the drift layer 3. For example, the plurality of source layers 5 are n+ type layers.

[0032] Each of the plurality of gate insulating layers 7 spans across the adjacent body layer 4. For example, the plurality of gate insulating layers 7 may be formed of silicon dioxide. For example, the plurality of gate insulating layers 7 may be formed of aluminum oxide. The plurality of gate electrode layers 8 are formed on the plurality of gate insulating layers 7, respectively.

[0033] A plurality of interlayer insulating layers respectively cover the plurality of gate electrode layers 8. A plurality of source electrode layers 10 are respectively formed corresponding to the plurality of body layers 4. The source electrode layer 10 is formed to contact the source layer 5. A wiring electrode layer is formed to cover the plurality of source electrode layers 10. A drain electrode layer 12 is formed below the drain layer 2.

[0034] In the terminal structure outside the active area of ​​the semiconductor device 1 of Example 1, the drain layer 2 and the drift layer 3 extend to the side wall of the chip. The side wall portion W of the drift layer 3 is bent inward. In the side wall portion W, at least the upper portion is in an inverted cone shape. In the upper curved portion of the side wall portion W, the curvature gradually decreases from the upper portion to the lower portion. Therefore, in the curved portion of the side wall portion W, the curvature of the upper portion is greater than the curvature of the lower portion. In the side wall portion W, one side of the drain layer 2 is continuously connected to the lower portion of the curved portion. In the side wall portion W, one side of the drain layer 2 is vertical.

[0035] A doping layer 13 is formed on the surface of the side wall portion W. The doping layer 13 is formed of silicon carbide of a second conductivity type having a higher impurity concentration than the drift layer 3. For example, the doping layer 13 is a p-type layer. The insulating layer 14 is formed on the surface of the doping layer 13. The doping layer 13 is formed of a material having an insulation breakdown strength not lower than that of silicon carbide. For example, the doping layer 13 is formed of silicon dioxide.

[0036] Next, through Figure 2 and Figure 3 A method for forming the terminal structure of the semiconductor device 1 will be described. Figure 2 and Figure 3This is a diagram for explaining a method for forming a terminal structure of a semiconductor device in the first embodiment.

[0037] First, if Figure 2 As shown in A, by cutting the structure of the manufacturing process, the side wall portion W of the drain layer 2 and the drift layer 3 in the terminal structure of the semiconductor device 1 are exposed. Figure 2 B, the shape of the side wall portion W is controlled. Specifically, isotropic dry etching and anisotropic dry etching are performed on the side wall portion W. Therefore, at least the upper portion of the side wall portion W is in an inverted cone shape. At this time, in the curved portion of the side wall portion W, the curvature of the upper portion is greater than the curvature of the lower portion. In the side wall portion W, one side of the drain layer 2 is vertical.

[0038] Next, if Figure 3 As shown in A, P-type ions are injected into the side wall portion W from the upper side to form a doping layer 13. Figure 3 As shown in FIG. 1B , a plurality of gate insulating layers 7, a plurality of gate electrode layers 8, a plurality of source electrode layers 10 and a drain electrode layer 12 are formed. Then, as shown in FIG. Figure 3 As shown in FIG. 3C , an insulating layer 14 is formed on the surface of the doping layer 13 .

[0039] Next, through Figure 4 and Figure 5 The electric field distribution of the semiconductor device 1 in Example 1 and the comparative example will be described. Figure 4 This is a schematic diagram of the electric field distribution of the semiconductor device in Example 1. Figure 5 It is a schematic diagram of the electric field distribution of the comparative example.

[0040] Figure 4 A is a cross-sectional view showing the simulation result of the electric field distribution of the semiconductor device 1 in the first embodiment. Figure 4 B is a perspective view showing the simulation result of the electric field distribution of the semiconductor device 1 in the first embodiment. Figure 5 A is a cross-sectional view showing the simulation result of the electric field distribution of the comparative example. Figure 5 B is a perspective view of the simulation result of the electric field distribution of the comparative example.

[0041] like Figure 4 As shown, in the semiconductor device 1 in the first embodiment, in the curved portion of the side wall portion W of the drift layer 3, the curvature gradually decreases from the upper portion to the lower portion. One side of the drain layer 2 is continuously connected to the lower portion of the curved portion. One side of the drain layer 2 is vertical. Therefore, in the side wall portion W of the drift layer 3, the electric field concentration phenomenon is not easy to occur. In particular, the electric field concentration phenomenon is not easy to occur at the upper end of the side wall of the drift layer 3. For example, even if a voltage of 2000V is applied to the drift layer 3, according to Figure 4 The simulation results shown show that the maximum electric field value is only 2.417 MV / cm.

[0042] like Figure 5 As shown in FIG. 1 , in the comparative example, the side wall portion X of the drift layer 3 is vertical. In the comparative example, the electric field is concentrated at the upper and lower ends of the side wall portion X of the drift layer 3. For example, when a voltage of 2000 V is applied to the drift layer 3, according to Figure 5 The simulation results shown show that the maximum electric field value reaches 3.087 MV / cm. In the semiconductor device 1 of Example 1, the maximum electric field value is 20% lower than that of the comparative example.

[0043] In the semiconductor device 1 in the first embodiment, the electric field at the upper end of the side wall portion W of the drift layer 3 is smaller than the electric field at the upper end of the side wall portion X of the drift layer 3 in the comparative example. In addition, in the semiconductor device 1 in the first embodiment, the maximum electric field of the side wall portion W of the drift layer 3 is much smaller than the maximum electric field of the side wall portion X of the drift layer 3 in the comparative example. And, considering the space charge effect, the structure of the side wall portion W of the drift layer 3 in the first embodiment is an optional embodiment.

[0044] According to the first embodiment, the side wall portion W of the drift layer 3 is bent inward. In the side wall portion W, at least the upper portion is in an inverted cone shape. Therefore, in the side wall portion W, electric field concentration is not likely to occur. Thus, in the terminal structure, miniaturization can be achieved while ensuring withstand voltage without complicating the process. In addition, by reducing the proportion of the terminal structure in the active region, miniaturization of the semiconductor device 1 can be achieved.

[0045] Furthermore, in the side wall portion W, the curvature of the upper portion is greater than that of the lower portion. Therefore, in the terminal structure, the withstand voltage can be more reliably ensured.

[0046] Furthermore, one side of the drain layer 2 is vertical in the side wall portion W. Therefore, in the terminal structure, the withstand voltage can be more reliably ensured.

[0047] Furthermore, the doping layer 13 is formed on the surface of the side wall portion W. Therefore, in the termination structure, the withstand voltage can be ensured more reliably.

[0048] In addition, an insulating layer 14 is formed on the surface of the doping layer 13. Therefore, by thickening the insulating layer 14, the side wall portion W can be reliably protected. Therefore, even if the semiconductor device 1 is encapsulated by a molding resin, the insulation breakdown of the molding resin can be suppressed. The molding resin can use polyimide, for example. For example, when the semiconductor device 1 is mounted in a module and encapsulated with polyimide, a similar effect can be expected.

[0049] Embodiment 2: Figure 6 It is a cross-sectional view of the main part of the semiconductor device in Example 2. In addition, the same or corresponding parts as those in Example 1 are denoted by the same reference numerals, and the description of these parts will be omitted.

[0050] like Figure 6 As shown, in the terminal structure outside the active region of the semiconductor device 1 in Example 2, the side wall portion W of the drift layer 3 is inclined inward. In the side wall portion W, the upper portion is in an inverted cone shape. In the inclined portion of the side wall portion W, the inclination angle of the upper portion is greater than the inclination angle of the lower portion. In the side wall portion W, one side of the drain layer 2 is vertical.

[0051] Next, through Figure 7 The electric field distribution of the semiconductor device 1 in the second embodiment will be described. Figure 7 This is a schematic diagram of the electric field distribution of the semiconductor device in Example 2.

[0052] Figure 7 A is a cross-sectional view showing the simulation result of the electric field distribution of the semiconductor device 1 in the second embodiment. Figure 7 B is a perspective view showing the simulation result of the electric field distribution of the semiconductor device 1 in the second embodiment.

[0053] like Figure 7 As shown in FIG. 1 , in the side wall portion W of the semiconductor device 1 in Example 2, the electric field is concentrated at the position where the tilt angle changes. Specifically, the electric field is concentrated at the intersection of the inclined portion and the vertical portion of the side wall portion W. However, compared to Figure 5 For example, even if a voltage of 2000 V is applied to the drift layer 3, according to Figure 7 The simulation results shown show that the maximum electric field value is only 2.618 MV / cm.

[0054] According to the above-mentioned embodiment 2, the side wall portion W of the drift layer 3 is inclined inward. Therefore, electric field concentration is less likely to occur in the side wall portion W. Therefore, in the terminal structure, miniaturization can be achieved while ensuring withstand voltage without complicating the process.

[0055] Furthermore, in the side wall portion W, the inclination angle of the upper portion is larger than the inclination angle of the lower portion. Therefore, in the terminal structure, the withstand voltage can be more reliably ensured.

[0056] Embodiment 3: Figure 8 It is a cross-sectional view of the main part of the semiconductor device in Example 3. In addition, the same or corresponding parts as those in Example 1 and Example 2 are denoted by the same reference numerals, and the description of these parts will be omitted.

[0057] like Figure 8 As shown, in the termination structure outside the active region of the semiconductor device 1 in Example 3, the side wall portion W of the drift layer 3 is inclined inward. In the side wall portion W, the upper portion is in an inverted cone shape. In the side wall portion W, the lower portion (the side of the drain layer 2) is in a forward cone shape.

[0058] Next, through Fig. 9 The electric field distribution of the semiconductor device 1 in the third embodiment will be described. Fig. 9 This is a schematic diagram of the electric field distribution of the semiconductor device in Example 3.

[0059] like Fig. 9 As shown, Fig. 9 A is an oblique view showing the simulation result of the electric field distribution of the semiconductor device 1 in Example 3, Fig. 9 B is a perspective view showing the simulation result of the electric field distribution of the semiconductor device 1 in Example 3.

[0060] In the side wall portion W of the semiconductor device 1 in the third embodiment, the electric field is concentrated at the intersection of the upper portion of the inverted cone shape and the lower portion of the forward cone shape. Figure 8 For example, even if a voltage of 2000 V is applied to the drift layer 3, according to Fig. 9 The simulation results shown show that the maximum electric field value is only 2.815 MV / cm.

[0061] According to the third embodiment described above, one side of the drain layer 2 has a forward tapered shape in the side wall portion W. In this case, in the terminal structure, miniaturization can be achieved while ensuring withstand voltage without complicating the process.

[0062] In the first to third embodiments, the insulating layer 14 may be formed directly on the surface of the side wall portion W without passing through the doping layer 13. In this case, in the terminal structure, miniaturization can be achieved while ensuring withstand voltage without complicating the process.

[0063] In Embodiments 1 to 3, the first conductivity type may be set to p-type and the second conductivity type may be set to n-type. In this case, in the terminal structure, miniaturization can be achieved while ensuring withstand voltage without complicating the process.

[0064] In Embodiments 1 to 3, the structure of the side wall portion W is suitable for the semiconductor device 1 that does not use the body diode current, in which the surface electric field of the side wall portion W is larger than the electric field at other positions. Therefore, the structure of the side wall portion W in Embodiments 1 to 3 can be applied to the Schottky barrier diode. In this case, in the terminal structure, miniaturization can be achieved while ensuring the withstand voltage without complicating the process.

[0065] Although certain aspects of at least one embodiment have been described, various modifications, changes and improvements will be readily apparent to those skilled in the art, and these modifications, changes and improvements are intended to constitute a part of this application and are within the scope of this application.

[0066] It should be understood that the embodiments of the methods and apparatus described herein should not be limited to the detailed description of the structures and arrangements shown in the above description and drawings. The methods and apparatus can be implemented in other embodiments and can be implemented or performed in a variety of ways.

[0067] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: include: a drain layer formed of either n-type or p-type silicon carbide; as well as a drift layer formed on the drain layer and made of n-type or p-type silicon carbide; In the termination structure, the side wall portion of the drift layer is bent or inclined inwardly, and at least the upper portion of the side wall portion has an inverted tapered shape.

2. The semiconductor device according to claim 1, wherein: In the side wall portion, a curvature of an upper portion is greater than a curvature of a lower portion.

3. The semiconductor device according to claim 1, wherein: In the side wall portion, an inclination angle of an upper portion is greater than an inclination angle of a lower portion.

4. The semiconductor device according to claim 1, wherein: In the side wall portion, the side surface of the drain layer is vertical.

5. The semiconductor device according to claim 1, wherein: In the side wall portion, a side surface of the drain layer has a forward tapered shape.

6. The semiconductor device according to claim 1, wherein: The device further includes another doping layer of n type or p type formed on the surface of the sidewall portion, the doping layer having an impurity concentration higher than that of the drift layer.

7. The semiconductor device according to claim 6, wherein: The device also includes an insulating layer formed on the surface of the doping layer, and the insulating breakdown strength of the insulating layer is not lower than that of silicon carbide.

8. The semiconductor device according to claim 1, wherein: The device further includes an insulating layer formed on a surface of the side wall portion, the insulating breakdown strength of which is not lower than that of silicon carbide.

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