Semiconductor device and forming method thereof, power semiconductor module and vehicle

Abstract

The embodiment of the invention relates to a semiconductor device and a forming method thereof, a power semiconductor module and a vehicle. The semiconductor device includes a semiconductor layer, a floating shielding region, and a first gate structure. The semiconductor layer includes a gate current conduction region. The floating shielding region is located in the semiconductor layer of the gate current conduction region. A first gate structure is located on the floating shielding region. Therefore, the floating shielding region plays a role in shielding an electric field applied to the first gate structure, the stress borne by the first gate structure is reduced, the reliability of the first gate structure is improved, and the reliability of the semiconductor device is further improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same, a power semiconductor module and a vehicle. Background Art

[0002] Silicon carbide has the advantages of large bandgap, high thermal conductivity, high breakdown field strength, high electron saturation velocity and strong radiation resistance. Silicon carbide power semiconductor devices made of silicon carbide materials can be better applied to high temperature, high pressure and high frequency environments, and have been widely used in new energy fields such as electric vehicles, wind power generation, and photovoltaic power generation.

[0003] Among them, silicon carbide insulated gate field effect transistors (SiC MOSFETs) dominate silicon carbide power semiconductor devices. However, the reliability of silicon carbide insulated gate field effect transistors needs to be improved. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor device and a method for forming the same, a power semiconductor module and a vehicle, which improve the reliability of the semiconductor device and at least partially solve the above-mentioned technical problems.

[0005] In order to achieve the above object, according to a first aspect of the present application, a semiconductor device is provided, comprising:

[0006] a semiconductor layer including a gate current conducting region;

[0007] A floating shielding region located inside the semiconductor layer of the gate current conducting region;

[0008] The first gate structure is located on the floating shielding region.

[0009] According to a second aspect of the present application, a method for forming a semiconductor device is provided, comprising:

[0010] providing a semiconductor layer, the semiconductor layer comprising a gate current conducting region;

[0011] forming a floating shielding region inside the semiconductor layer in the gate current conducting region;

[0012] A first gate structure is formed, wherein the first gate structure is located on the floating shielding region.

[0013] According to a third aspect of the present application, a power semiconductor module is also provided, and the power semiconductor module includes the above-mentioned semiconductor device.

[0014] According to a fourth aspect of the present application, a vehicle is also provided, the vehicle comprising the above-mentioned power semiconductor module.

[0015] In the semiconductor device and its formation method, power semiconductor module and vehicle of the embodiments of the present application, the floating shielding area shields the electric field applied to the first gate structure, reduces the stress borne by the first gate structure, improves the reliability of the first gate structure, and thereby improves the reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic cross-sectional structure diagram of a semiconductor device provided in an exemplary embodiment of the present disclosure;

[0017] Figure 2 A schematic flow chart of a method for forming a semiconductor device provided in an exemplary embodiment of the present disclosure;

[0018] Figures 3 to 7 Schematic diagram of a structure of a semiconductor device provided in an exemplary embodiment of the present disclosure.

[0019] Description of reference numerals:

[0020] 100. Semiconductor devices;

[0021] 1. Semiconductor layer; 1A, cell region; 1B, gate current conduction region; 1C, terminal region; 1D, drift region; 1E, substrate region; 1G1, front side; 1G2, back side;

[0022] 10. first semiconductor layer; 11. second semiconductor layer;

[0023] 121, floating shielding area; 122, ohmic contact area; 1221, first ohmic contact area; 1222, second ohmic contact area; 123, field limiting ring;

[0024] 131A, initial shielding doping region; 131, shielding doping region; 132A, initial active region; 132, active region; 1321A, first initial active region; 1321, first active region; 1322A, second initial active region; 1322, second active region;

[0025] 141A, initial floating isolation region; 141, floating isolation region; 142, source region; 1421, first source region; 1422, second source region;

[0026] 15, gate oxide layer; 151, second gate oxide portion; 152, first gate oxide portion;

[0027] 16, gate layer; 161, second gate; 162, first gate; GS1, first gate structure; GS2, second gate structure;

[0028] 17, dielectric layer; 171, first dielectric portion; 172, second dielectric portion;

[0029] 18. Insulating dielectric layer; 19. Field stop structure;

[0030] 2. Front metal layer; 21. Source metal; 22. Third gate;

[0031] 3. Drain metal;

[0032] X, first direction; Y, second direction. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0034] According to the first aspect of the present application, referring to Figure 1 As shown, an embodiment of the present application provides a semiconductor device 100. The semiconductor device 100 includes a semiconductor layer 1, a floating shielding region 121 and a first gate structure GS1. The semiconductor layer 1 includes a gate current conduction region 1B. The gate current conduction region 1B is provided with a first gate structure GS1 to conduct the gate current to the device structure of the semiconductor device 100 and control the device structure to be turned on or off. The floating shielding region 121 is located inside the semiconductor layer 1 of the gate current conduction region 1B. The first gate structure GS1 is located on the floating shielding region 121. The floating shielding region 121 shields the electric field applied to the first gate structure GS1, reduces the stress borne by the first gate structure GS1, improves the reliability of the first gate structure GS1, and thereby improves the reliability of the semiconductor device 100.

[0035] It should be noted that the floating shielding region 121 refers to a region that is in a floating state without being connected to an electric potential, and the region can play a role in shielding the electric field.

[0036] In some embodiments, the semiconductor layer 1 may include at least one of silicon, a compound semiconductor material, and an alloy semiconductor material. The compound semiconductor material includes at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide. The alloy semiconductor material includes at least one of silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium indium arsenide phosphide. Exemplarily, the semiconductor layer 1 includes silicon carbide, and therefore, the semiconductor device is a silicon carbide power semiconductor device, so that the semiconductor device 100 has the advantages of large bandgap, high thermal conductivity, high breakdown field strength, high electron saturation velocity, and strong radiation resistance.

[0037] In some embodiments, the first gate structure GS1 includes a first gate 162 and a first gate oxide portion 152. The first gate 162 is located on the semiconductor layer 1 of the gate current conduction region 1B. The first gate oxide portion 152 is located between the semiconductor layer 1 and the first gate 162, and serves to isolate the semiconductor layer 1 from the first gate 162. Since the first gate oxide portion 152 is located between the semiconductor layer 1 and the first gate 162, the first gate oxide portion 152 is also located between the first gate 162 and the floating shielding region 121. When the semiconductor device 100 is in a reverse working state, when a negative voltage is applied to the first gate 162, the floating shielding region 121 shields the electric field applied by the first gate 162 to the first gate oxide portion 152, reduces the stress borne by the first gate oxide portion 152 under the action of the electric field, improves the reliability of the first gate oxide portion 152, and further improves the reliability of the semiconductor device 100.

[0038] It should be noted that the first gate 162 is located on the semiconductor layer 1 in the gate current conducting region 1B, which may mean that the first gate 162 is located on the surface of the semiconductor layer 1, or the first gate 162 is located inside the semiconductor layer 1, or the first gate 162 is located on the surface of the semiconductor layer 1 and inside the conductor layer. When other structures in the present application are located on the semiconductor layer 1, they can also be explained by analogy, and will not be repeated here.

[0039] In some embodiments, reference Figure 1 As shown, the first gate oxide portion 152 may be located on the surface of the semiconductor layer 1. In other embodiments, when the first gate 162 may be located in the trench of the semiconductor layer 1, the first gate oxide portion 152 may also be located in the trench of the semiconductor layer 1 to isolate the first gate 162 from the semiconductor layer 1. Exemplarily, when the first gate 162 may be located on the surface of the semiconductor layer 1, the first gate oxide portion 152 may be located on the surface of the semiconductor layer 1 and between the first gate 162 and the semiconductor layer 1.

[0040] In some embodiments, reference Figure 1 As shown, the first gate 162 may be located on the surface of the semiconductor layer 1. In other embodiments, the first gate 162 may be located in a trench of the semiconductor layer 1.

[0041] In some embodiments, the semiconductor layer 1 further includes a cell region 1A, and the cell region 1A is adjacent to the gate current conduction region 1B. The cell region 1A is provided with a cell structure, and the cell structure may include at least one of a field effect transistor and an insulated gate bipolar transistor. Exemplarily, the cell structure includes a field effect transistor.

[0042] In some embodiments, the cell structure includes a second gate structure GS2. The second gate structure GS2 includes a second gate 161, which serves as a control electrode of the cell structure. The second gate 161 is located on the semiconductor layer 1 of the cell region 1A and is connected to the first gate 162. In this way, the first gate 162 is connected to the second gate 161 of the cell region 1A to conduct the gate current to the second gate 161 of the cell region 1A.

[0043] In some embodiments, reference Figure 1 As shown, the second gate 161 may be a planar gate located on the surface of the semiconductor layer 1. In other embodiments, the second gate 161 may also be a trench gate located inside the semiconductor layer 1.

[0044] In some embodiments, the second gate 161 and the first gate 162 may both include the same material, so that both are formed at the same time, simplifying the formation process of the semiconductor device 100. In some embodiments, the second gate 161 and the first gate 162 may include conductive materials such as polysilicon. The second gate 161 and the first gate 162 may also be doped with doping ions to improve the conductivity of the second gate 161 and the first gate 162. Exemplarily, the second gate 161 and the first gate 162 both include polysilicon.

[0045] In some embodiments, reference Figure 1 As shown, the second gate structure GS2 further includes a second gate oxide portion 151. The second gate oxide portion 151 is located between the second gate 161 and the semiconductor layer 1 to isolate the second gate 161 from the semiconductor layer 1.

[0046] In some embodiments, the second gate oxide portion 151 and the first gate oxide portion 152 have the same thickness, so that the two can be formed at the same time, simplifying the formation process of the semiconductor device 100 .

[0047] In some embodiments, the second gate oxide portion 151 and the first gate oxide portion 152 may include the same material so as to form both at the same time, simplifying the formation process of the semiconductor device 100. In some embodiments, the second gate oxide portion 151 and the first gate oxide portion 152 may include an insulating material. The insulating material includes but is not limited to at least one of silicon oxide, silicon nitride, and silicon oxynitride. Exemplarily, the second gate oxide portion 151 and the first gate oxide portion 152 include silicon oxide.

[0048] In some embodiments, the semiconductor device 100 further includes an insulating dielectric layer 18. The insulating dielectric layer 18 is adjacent to the first gate oxide portion 152 and is located between the first gate 162 and the floating shielding region 121. In this way, the floating shielding region 121 is located below the connection between the insulating dielectric layer 18 and the first gate oxide portion 152, reducing the stress of the first gate oxide portion 152 at the connection between the insulating dielectric layer 18 and the first gate oxide portion 152 under the action of the electric field generated by the negative voltage of the first gate 162, and further improving the reliability of the first gate oxide portion 152.

[0049] It should be noted that, at the connection between the insulating dielectric layer 18 and the first gate oxide portion 152, the first gate oxide portion 152 prepared due to process reasons may be thinner, which becomes the weakest position of the first gate oxide portion 152. Therefore, the floating shielding region 121 is located below the connection between the insulating dielectric layer 18 and the first gate oxide portion 152, which can reduce the stress borne by the first gate oxide portion 152 at the connection between the insulating dielectric layer 18 and the first gate oxide portion 152, and further improve the reliability of the first gate oxide portion 152.

[0050] In some embodiments, the semiconductor layer 1 further includes a terminal region 1C. The terminal region 1C is adjacent to the gate current conducting region 1B and is located at the edge of the semiconductor device 100. The terminal region 1C is used to set a terminal structure to improve the voltage resistance of the edge of the semiconductor device 100.

[0051] Reference Figure 1 As shown, in the first direction X, the gate current conducting region 1B is located between the terminal region 1C and the cell region 1A. The gate current conducting region 1B, the terminal region 1C and the cell region 1A constitute a device region.

[0052] In some embodiments, reference Figure 1 As shown, at least a portion of the insulating dielectric layer 18 is located in the terminal region 1C to isolate the semiconductor layer 1 from other conductive structures in the terminal region 1C.

[0053] In an exemplary embodiment, referring to Figure 1 As shown, the insulating dielectric layer 18 extends from the terminal region 1C to the gate current conducting region 1B and is adjacent to the first gate oxide portion 152. In another exemplary embodiment, the insulating dielectric layer 18 may be located in the terminal region 1C.

[0054] In some embodiments, reference Figure 1 As shown, the thickness of the insulating dielectric layer 18 is greater than the thickness of the first gate oxide portion 152. In this way, the insulating performance of the insulating dielectric layer 18 in the terminal region 1C is improved, the reliability of the insulating dielectric layer 18 is improved, and the reliability of the semiconductor device 100 is further improved.

[0055] In some embodiments, the insulating dielectric layer 18 may include, but is not limited to, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0056] In some embodiments, reference Figure 1 As shown, the semiconductor device 100 further includes a shielding doping region 131. The shielding doping region 131 is located inside the semiconductor layer 1. The shielding doping region 131 is located on the side of the floating shielding region 121 away from the first gate oxide portion 152, and is isolated from the floating shielding region 121. In this way, when the semiconductor device 100 is in a reverse working state, the shielding doping region 131 plays a better shielding role for the electric field generated by the positive voltage loaded by the drain metal 3 below, can better alleviate the electric field of the gate current conduction region 1B, and improve the reliability of the gate current conduction region 1B.

[0057] In some embodiments, the shielding doping region 131 is located inside the semiconductor layer 1 of the gate current conducting region 1B.

[0058] In some embodiments, reference Figure 1 As shown, the semiconductor device 100 further includes an ohmic contact region 122. The ohmic contact region 122 is located inside the semiconductor layer 1 and is connected to the shielding doping region 131. In this way, the shielding doping region 131 is connected to the ohmic contact region 122, and the ohmic contact region 122 continuously increases carriers for the shielding doping region 131, thereby improving the shielding capability of the shielding doping region 131.

[0059] It should be noted that the shielding doping region 131 is connected to the ohmic contact region 122, so that the shielding doping region 131 will be connected to the potential. In addition, when the shielding doping region 131 is connected to the ohmic contact region 122, when the semiconductor device 100 is in a reverse working state, the first gate 162 is connected to a negative voltage, which is equivalent to the ohmic contact region 122 being connected to a positive voltage, and the shielding doping region 131 is also connected to a positive voltage, and the first gate oxide portion 152 will be subjected to the stress corresponding to the electric field generated by the positive voltage of the shielding doping region 131. In the present application, by adding a floating shielding region 121 between the first gate oxide portion 152 and the shielding doping region 131, the floating shielding region 121 plays a shielding role on the electric field generated by the shielding doping region 131, reduces the stress inside the first gate oxide portion 152, and improves the reliability of the first gate oxide portion 152.

[0060] In some other embodiments, the shielding doping region 131 may also be connected to other conductive structures to access the potential. In some other embodiments, the shielding doping region 131 may not be connected to the ohmic contact region 122 .

[0061] In some embodiments, the ohmic contact region 122 is a part of the cellular structure and is located inside the semiconductor layer 1 of the cellular region 1A to improve the performance of the cellular structure.

[0062] Exemplarily, the ohmic contact region 122 includes a first ohmic contact region 1221 and a second ohmic contact region 1222 which are spaced apart from each other, and the second ohmic contact region 1222 is adjacent to the gate current conducting region 1B and adjacent to the shielding doping region 131 .

[0063] In some embodiments, the ohmic contact region 122 and the floating shield region 121 have doping ions of the same conductivity type. Thus, the ohmic contact region 122 and the floating shield region 121 can be obtained by a doping process using doping ions of the same conductivity type, thereby simplifying the manufacturing process of the semiconductor device 100 .

[0064] Exemplarily, the ohmic contact region 122 has P-type doping ions, and the floating shield region 121 also has P-type doping ions. It is understood that in the case where the ohmic contact region 122 has N-type doping ions, the floating shield region 121 also has N-type doping ions. The P-type doping ions may include, but are not limited to, boron ions and boron fluoride ions. The N-type doping ions may include, but are not limited to, at least one of phosphorus ions and arsenic ions.

[0065] In some embodiments, when the ohmic contact region 122 and the floating shield region 121 have doping ions of the same conductivity type, the concentration of the doping ions in the ohmic contact region 122 is the same as the concentration of the doping ions in the floating shield region 121. In this way, the ohmic contact region 122 and the floating shield region 121 have the same doping ion concentration, and the two can be formed at the same time, simplifying the manufacturing process of the semiconductor device 100.

[0066] It should be noted that in the present application, the same concentration of doped ions can cover the case where the concentration of doped ions is exactly the same, and can also cover the case where there is a small deviation in concentration due to process reasons, for example, the ratio of the difference is within ±5%.

[0067] In some embodiments, the shielding doping region 131 and the floating shielding region 121 have doping ions of the same conductivity type. In this way, the shielding doping region 131 and the floating shielding region 121 can achieve a shielding function by doping doping ions of the same conductivity type.

[0068] Exemplarily, in the case where the floating shielding region 121 has P-type doping ions, the shielding doping region 131 also has P-type doping ions.

[0069] In some embodiments, when the shielding doping region 131 and the floating shielding region 121 have doping ions of the same conductivity type, the concentration of doping ions in the shielding doping region 131 is less than the concentration of doping ions in the floating shielding region 121. In this way, the concentration of doping ions in the floating shielding region 121 is higher, thereby improving the shielding capability of the floating shielding region 121.

[0070] In other embodiments, when the shielding doping region 131 and the floating shielding region 121 have doping ions of the same conductivity type, the concentration of the doping ions in the shielding doping region 131 may also be equal to the concentration of the doping ions in the floating shielding region 121. In this way, the shielding doping region 131 and the floating shielding region 121 may be formed at the same time, simplifying the manufacturing process of the semiconductor device 100.

[0071] In some other embodiments, when the shielding doping region 131 and the floating shielding region 121 have doping ions of the same conductivity type, the concentration of doping ions in the shielding doping region 131 may also be greater than the concentration of doping ions in the floating shielding region 121. In this way, the concentration of doping ions in the shielding doping region 131 is higher, thereby improving the shielding capability of the shielding doping region 131.

[0072] In some embodiments, reference Figure 1 As shown, the semiconductor device 100 further includes a floating isolation region 141. The floating isolation region 141 is located between the shielding doping region 131 and the floating shielding region 121. Thus, the floating isolation region 141 plays a role in isolating the shielding doping region 131 from the floating shielding region 121.

[0073] In some embodiments, the floating isolation region 141 is located inside the semiconductor layer 1 in the gate current conducting region 1B to isolate the shielding doping region 131 and the floating shielding region 121 in the gate current conducting region 1B.

[0074] In some embodiments, the floating isolation region 141 and the floating shielding region 121 include doping ions of opposite conductivity types, respectively, so that the floating isolation region 141 can play an isolation role.

[0075] Exemplarily, in the case where the floating shielding region 121 has P-type doping ions, the floating isolation region 141 has N-type doping ions.

[0076] In some embodiments, the shielding doping region 131 and the floating isolation region 141 include doping ions of opposite conductivity types, respectively, so that the floating isolation region 141 can play an isolation role.

[0077] In some other embodiments, the floating isolation region 141 may be an insulating region, so as to isolate the shielding doped region 131 from the floating shielding region 121 .

[0078] In some embodiments, reference Figure 1 As shown, the semiconductor device 100 further includes a source region 142 . The source region 142 is located inside the semiconductor layer 1 of the cell region 1A. In the case where the semiconductor device 100 includes the ohmic contact region 122 , the source region 142 is adjacent to the ohmic contact region 122 .

[0079] For example, refer to Figure 1 As shown, the source region 142 includes a first source region 1421 and a second source region 1422 that are spaced apart. The second source region 1422 is adjacent to the gate current conducting region 1B. In the case where the ohmic contact region 122 includes a first ohmic contact region 1221 and a second ohmic contact region 1222 that are spaced apart and the second ohmic contact region 1222 is adjacent to the gate current conducting region 1B, in the first direction X, the first source region 1421 and the second source region 1422 are located between the first ohmic contact region 1221 and the second ohmic contact region 1222. The first source region 1421 is adjacent to the first ohmic contact region 1221, and the second source region 1422 is adjacent to the second ohmic contact region 1222.

[0080] In some embodiments, the source region 142 and the floating isolation region 141 have doping ions of the same conductivity type. Thus, the source region 142 and the floating isolation region 141 can be formed by doping doping ions of the same conductivity type, thereby simplifying the formation process of the semiconductor device 100 .

[0081] Exemplarily, the floating isolation region 141 has N-type doping ions, and the source region 142 also has N-type doping ions.

[0082] In some embodiments, when the source region 142 and the floating isolation region 141 have doping ions of the same conductivity type, the concentration of the doping ions in the source region 142 is the same as the concentration of the doping ions in the floating isolation region 141. In this way, the source region 142 and the floating isolation region 141 can be formed in one doping process, that is, the two can be formed at the same time, further simplifying the formation process of the semiconductor device 100.

[0083] In some embodiments, the semiconductor device 100 further includes a source metal 21. The source metal 21 is located on the surface of the semiconductor layer 1 of the cell region 1A and contacts the source region 142. The source metal 21 also contacts the ohmic contact region 122. In this way, the source voltage is transmitted through the source region 142 via the source metal 21.

[0084] In some embodiments, when the semiconductor device 100 includes a second gate 161 and a source metal 21 located on the semiconductor layer 1 of the cell region 1A, the second gate 161 is insulated from the source metal 21. In some embodiments, the semiconductor device 100 may further include a first dielectric portion 171, which is located between the second gate 161 and the source metal 21. In this way, the first dielectric portion 171 serves to isolate the second gate 161 from the source metal 21, so that the source metal 21 is insulated from the second gate 161.

[0085] In some embodiments, reference Figure 1As shown, the semiconductor layer 1 further includes a terminal region 1C. In the first direction X, the terminal region 1C is adjacent to the gate current conducting region 1B. The semiconductor device 100 further includes a field limiting ring 123. The field limiting ring 123 is located inside the semiconductor layer 1 in the terminal region 1C. In this way, the field limiting ring 123 can alleviate the edge electric field of the semiconductor device 100 and improve the withstand voltage performance of the terminal region 1C.

[0086] In an exemplary embodiment, a plurality of field limiting rings 123 are located inside the semiconductor layer 1 of the termination region 1C.

[0087] In some embodiments, reference Figure 1 As shown, the adjacent field limiting rings 123 are connected to the shielding doping region 131. Thus, the shielding doping region 131 can provide carriers for the field limiting rings 123 adjacent to the gate current conducting region 1B, thereby improving the withstand voltage performance of the field limiting rings 123 adjacent to the gate current conducting region 1B.

[0088] In some other embodiments, the field limiting ring 123 adjacent to the gate current conducting region 1B may be spaced apart from the shielding doping region 131 .

[0089] In some embodiments, the field limiting ring 123 and the floating shield region 121 have doping ions of the same conductivity type. Thus, the field limiting ring 123 and the floating shield region 121 can be formed by doping doping ions of the same conductivity type, thereby simplifying the formation process of the semiconductor device 100 .

[0090] Exemplarily, when the floating shielding region 121 has P-type doping ions, the field limiting ring 123 also has P-type doping ions.

[0091] In some embodiments, when the field limiting ring 123 and the floating shield region 121 have doping ions of the same conductivity type, the concentration of the doping ions in the field limiting ring 123 is the same as the concentration of the doping ions in the floating shield region 121. In this way, the field limiting ring 123 and the floating shield region 121 can be formed in one doping process, that is, the two can be formed at the same time, further simplifying the formation process of the semiconductor device 100.

[0092] In some embodiments, reference Figure 1 As shown, the semiconductor device 100 further includes an active region 132. The active region 132 is located in the semiconductor layer 1 of the cell region 1A. The active region 132 is connected to the source region 142 and the ohmic contact region 122, and is located below the second gate 161. In this way, when the active region 132 forms an inversion layer under the action of the positive voltage of the second gate 161, the source region 142 and the drift region 1D are turned on, so that the cell structure is turned on.

[0093] Exemplarily, the active region 132 includes a first active region 1321 and a second active region 1322 disposed at intervals to provide a dual channel and improve the density of the conduction current of the cell structure. When the source region 142 includes a first source region 1421 and a second source region 1422 disposed at intervals, and the ohmic contact region 122 includes a first ohmic contact region 1221 and a second ohmic contact region 1222 disposed at intervals, the second source region 1422 and the second ohmic contact region 1222 are adjacent to the gate current conduction region 1B. The first ohmic contact region 1221 is adjacent to the first source region 1421 and both are embedded in the first active region 1321. The second ohmic contact region 122 and the second source region 1422 are adjacent to each other and both are embedded in the second active region 1322. A second gate oxide portion 151 is disposed between the second gate 161 and the first active region 1321 and the second active region 1322.

[0094] In some embodiments, the active region 132 and the shielding doping region 131 have doping ions of the same conductivity type. Thus, the active region 132 and the shielding doping region 131 can be formed by doping doping ions of the same conductivity type, thereby simplifying the formation process of the semiconductor device 100 .

[0095] Exemplarily, in the case where the shielding doping region 131 has P-type doping ions, the active region 132 also has P-type doping ions.

[0096] In some embodiments, when the active region 132 and the shielding doping region 131 have doping ions of the same conductivity type, the concentration of the doping ions in the active region 132 is the same as the concentration of the doping ions in the shielding doping region 131. In this way, the active region 132 and the shielding doping region 131 can be formed in one doping process, that is, both can be formed at the same time, further simplifying the formation process of the semiconductor device 100.

[0097] In some embodiments, the semiconductor device 100 further includes a third gate 22. The third gate 22 is located on a side of the first gate 162 away from the semiconductor layer 1, and is connected to the first gate 162. In this way, the third gate 22 is connected to the second gate 161 through the first gate 162, thereby reducing the overall impedance of the entire gate and improving the speed of opening the cell structure and the consistency of the start time.

[0098] In some embodiments, the third gate 22 may be located in the gate current conducting region 1B, but is not limited thereto.

[0099] In some embodiments, the conductivity of the third gate 22 is greater than the conductivity of the first gate 162 and the second gate 161 .

[0100] In some embodiments, the third gate 22 and the source metal 21 include the same metal material. In this way, the third gate 22 and the source metal 21 can be made of the same metal material, and can even be formed by patterning a metal layer, thereby simplifying the formation process of the semiconductor device 100. The metal material may include but is not limited to at least one of copper, aluminum, titanium and tungsten.

[0101] In some embodiments, when the third gate 22 and the source metal 21 include the same metal material, the third gate 22 has the same thickness as the source metal 21. In this way, the third gate 22 and the source metal 21 can be formed by patterning one metal layer, simplifying the formation process of the semiconductor device 100.

[0102] In some embodiments, the semiconductor device 100 further includes a second dielectric portion 172. At least a portion of the second dielectric portion 172 is located between the third gate 22 and the first gate 162 and includes a contact hole. The third gate 22 is connected to the first gate 162 through the contact hole. In this way, the second dielectric portion 172 protects the first gate 162, and the third gate 22 can also be connected to the first gate 162 through the contact hole of the second dielectric portion 172.

[0103] Exemplarily, the second dielectric portion 172 extends from the gate current conducting region 1B to the terminal region 1C.

[0104] It should be noted that, refer to Figure 2 As shown, when the terminal region 1C further includes an insulating dielectric layer 18, when the second dielectric portion 172 extends to the terminal region 1C, the insulating dielectric layer 18 is located between the second dielectric portion 172 and the semiconductor layer 1. In this way, the thickness of the insulating layer in the terminal region 1C is increased, and the reliability of the terminal region 1C is improved.

[0105] In some embodiments, the second dielectric portion 172 and the first dielectric portion 171 may include the same insulating material. Thus, the second dielectric portion 172 and the first dielectric portion 171 may be made of the same insulating material and may even be formed simultaneously, thereby simplifying the formation process of the semiconductor device 100. The insulating material may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0106] In some embodiments, reference Figure 1 As shown, the semiconductor device 100 also includes a drift region 1D. The drift region 1D is located inside the semiconductor layer 1, and the floating shielding region 121 is away from the side of the first gate structure GS1. In this way, the ability of the semiconductor device 100 to withstand high voltage is improved. In addition, by adjusting the thickness of the drift region 1D and the concentration of the doped ions, the breakdown voltage and on-resistance of the semiconductor device 100 can be adjusted.

[0107] Exemplarily, in the second direction Y, the drift region 1D is adjacent to the gate current conducting region 1B, the cell region 1A and the terminal region 1C.

[0108] In some embodiments, the drift region 1D and the floating shield region 121 respectively contain doping ions of opposite conductivity types, so as to ensure that the floating shield region 121 has good shielding capability.

[0109] In some embodiments, reference Figure 1 As shown, the semiconductor device 100 further includes a substrate region 1E and a drain metal 3. The substrate region 1E is located inside the semiconductor layer 1 and on the side of the drift region 1D away from the floating shielding region 121. The drain metal 3 is located on the surface of the semiconductor layer 1, on the side away from the substrate region 1E, and in contact with the substrate region 1E.

[0110] It should be noted that the active region 132 , the source region 142 , the ohmic contact region 122 , the second gate structure GS2 , the source metal 21 , and the drain metal 3 constitute a cell structure, and the cell structure is a metal oxide semiconductor field effect transistor.

[0111] In some embodiments, reference Figure 1 As shown, the semiconductor device 100 further includes a field stop structure 19, which is located inside the semiconductor layer 1 of the terminal region 1C. In this way, the field stop structure 19 plays a role in further improving the withstand voltage performance of the terminal region 1C of the semiconductor device 100. In the case where the semiconductor device 100 further includes a field limiting ring 123 located in the terminal region 1C, the field limiting ring 123 is located between the field stop structure 19 and the cell region 1A.

[0112] According to a second aspect of the present disclosure, a method for forming a semiconductor device 100 is provided. Figure 2 As shown, the method for forming the semiconductor device 100 includes:

[0113] Step S101: forming a semiconductor layer, wherein the semiconductor layer includes a gate current conducting region;

[0114] Step S102: forming a floating shielding region inside the semiconductor layer of the gate current conducting region;

[0115] Step S103: forming a first gate structure, wherein the first gate structure is located on the floating shielding region.

[0116] In some embodiments of the present application, the floating shielding region shields the electric field applied to the first gate structure, reduces the stress borne by the first gate structure, improves the reliability of the first gate structure, and further improves the reliability of the semiconductor device.

[0117] The following combination Figures 3 to 7The formation process of the semiconductor device 100 according to the embodiment of the present application is described in detail.

[0118] In some embodiments, reference Figure 3 As shown, the above step S101 is performed. The semiconductor layer 1 has a gate current conducting region 1B. The semiconductor layer 1 also includes a cell region 1A adjacent to the gate current conducting region 1B in the first direction X.

[0119] In some embodiments, the semiconductor layer 1 further has a terminal region 1C. In the first direction X, the gate current conducting region 1B is located between the terminal region 1C and the cell region 1A.

[0120] Reference Figure 3 As shown, the semiconductor layer 1 has a front side 1G1 and a back side 1G2 which are arranged opposite to each other in the second direction Y. The front side 1G1 is used to form a device structure.

[0121] In some embodiments, the step S101 of forming the semiconductor layer 1 includes:

[0122] Step S1011: providing a first semiconductor layer 10;

[0123] Step S1012 : forming a second semiconductor layer 11 on the first semiconductor layer 10 , wherein the second semiconductor layer 11 and the first semiconductor layer 10 are stacked in the second direction Y.

[0124] The surface of the second semiconductor layer 11 facing away from the first semiconductor layer 10 is a front surface 1G1 , and the surface of the first semiconductor layer 10 facing away from the second semiconductor layer 11 is a back surface 1G2 .

[0125] In some embodiments, the second semiconductor layer 11 may be formed on the first semiconductor layer 10 by an epitaxial process, but is not limited thereto. The region corresponding to the second semiconductor layer 11 is an initial drift region.

[0126] In some embodiments, the first semiconductor layer 10 and the second semiconductor layer 11 may have doping ions of the same conductivity type. For example, both the first semiconductor layer 10 and the second semiconductor layer 11 have N-type doping ions.

[0127] In some embodiments, the concentration of doping ions in the first semiconductor layer 10 is greater than the concentration of doping ions in the second semiconductor layer 11 .

[0128] In some embodiments, the second direction Y is perpendicular to the first direction X, but is not limited thereto.

[0129] Reference Figures 4 to 6 As shown, the above step S102 is executed.

[0130] In some embodiments, reference Figures 4 to 6As shown, the method for forming the semiconductor device 100 further includes: forming a shielding doping region 131 inside the semiconductor layer 1 , wherein the shielding doping region 131 is located on a side of the floating shielding region 121 away from the first gate structure GS1 and is isolated from the floating shielding region 121 .

[0131] In some embodiments, reference Figure 4 and Figure 5 As shown, a shielding doping region 131 is formed in the semiconductor layer 1, including:

[0132] forming an initial shielding doping region 131A inside the semiconductor layer 1 of the gate current conducting region 1B;

[0133] An initial floating isolation region 141A is formed in a portion of the initial shielding doping region 131A, and the remaining initial shielding doping region 131A constitutes the shielding doping region 131 .

[0134] In some embodiments, the initial floating isolation region 141A and the initial shielding doping region 131A have doping ions of opposite conductivity types.

[0135] In some embodiments, reference Figure 4 As shown, the method for forming the semiconductor device 100 further includes: forming an initial active region 132A inside the semiconductor layer 1 of the cell region 1A during the process of forming the initial shielding doping region 131A inside the semiconductor layer 1 of the gate current conducting region 1B. In this way, the initial active region 132A is formed during the process of forming the initial shielding doping region 131A, thereby simplifying the manufacturing process of the semiconductor device 100.

[0136] In some embodiments, the initial active region 132A and the initial shielding doping region 131A have doping ions of the same conductivity type, so that the initial active region 132A and the initial shielding doping region 131A can be formed simultaneously by the same ion doping process, simplifying the manufacturing process of the semiconductor device 100 .

[0137] For example, refer to Figure 4 As shown, a first ion doping process is performed from the front side 1G1 of the semiconductor layer 1 to form an initial active region 132A and an initial shielding doping region 131A. The conductivity type of the doped ions in the first ion doping process is opposite to the conductivity type of the doped ions in the second semiconductor layer 11. Exemplarily, the doped ions in the first ion doping process are P-type doped ions.

[0138] For example, refer to Figure 4 As shown, the initial active region 132A includes a first initial active region 1321A and a second initial active region 1322A which are spaced apart from each other. The second initial active region 1322A is adjacent to the gate current conducting region 1B.

[0139] In some embodiments, reference Figure 5 As shown, in the process of forming the initial floating isolation region 141A in part of the initial shielding doping region 131A, the source region 142 is formed in the initial active region 132A. As follows, the source region 142 is formed in the process of forming the initial floating isolation region 141A, simplifying the manufacturing process of the semiconductor device 100.

[0140] In some embodiments, the source region 142 and the initial floating isolation region 141A have doping ions of the same conductivity type, so that the source region 142 and the initial floating isolation region 141A can be formed simultaneously by the same ion doping process, simplifying the manufacturing process of the semiconductor device 100 .

[0141] In some embodiments, reference Figure 5 As shown, a second ion doping process is performed from the front side 1G1 of the semiconductor layer 1 to form an initial floating isolation region 141A and a source region 142. The conductivity type of the doped ions in the second ion doping process is opposite to the conductivity type of the doped ions in the first ion doping process. Exemplarily, the doped ions in the second ion doping process are N-type doped ions.

[0142] For example, refer to Figure 5 As shown, the source region 142 includes a first source region 1421 and a second source region 1422 which are spaced apart. The second source region 1422 is embedded in the second initial active region 1322A. The first source region 1421 is embedded in the first initial active region 1321A.

[0143] In some embodiments, reference Figure 5 and Figure 6 As shown, the method for forming the semiconductor device 100 further includes: forming a floating isolation region 141 , wherein the floating isolation region 141 is located inside the semiconductor layer 1 of the gate current conducting region 1B and between the shielding doping region 131 and the floating shielding region 121 .

[0144] In some embodiments, reference Figure 6 As shown, a floating isolation region 141 is formed, including:

[0145] A floating shielding region 121 is formed in a portion of the initial floating isolation region 141A, and the remaining initial floating isolation region 141A constitutes a floating isolation region 141 .

[0146] In some embodiments, the floating shield region 121 and the initial floating isolation region 141A have doping ions of opposite conductivity types.

[0147] In some embodiments, reference Figure 6 As shown, the method for forming the semiconductor device 100 further includes:

[0148] During the process of forming the floating shielding region 121, an ohmic contact region 122 is formed in the initial active region 132A, and the ohmic contact region 122 is adjacent to the source region 142. Thus, during the process of forming the floating shielding region 121, the ohmic contact region 122 is formed, simplifying the manufacturing process of the semiconductor device 100.

[0149] In some embodiments, reference Figure 6 As shown, the ohmic contact region 122 includes a first ohmic contact region 1221 and a second ohmic contact region 1222. The first ohmic contact region 1221 is embedded in the first initial active region 1321A and is adjacent to the first source region 1421 in the first direction X. The second ohmic contact region 1222 is embedded in the second initial active region 1322A and is adjacent to the second source region 1422 in the first direction X.

[0150] In some embodiments, Figure 6 As shown, the ohmic contact region 122 is connected to the floating shield region 121. Exemplarily, the second ohmic contact region 1222 is connected to the floating shield region 121.

[0151] In some embodiments, reference Figure 6 As shown, the method for forming the semiconductor device 100 further includes: forming a field limiting ring 123 in the semiconductor layer 1 of the terminal region 1C during the process of forming the floating shielding region 121. Forming the field limiting ring 123 during the process of forming the floating shielding region 121 simplifies the manufacturing process of the semiconductor device 100.

[0152] In some embodiments, Figure 6 As shown, adjacent field limiting rings 123 are connected to the shielding doping region 131 .

[0153] In some embodiments, the field limiting ring 123, the ohmic contact region 122, and the floating shield region 121 have doping ions of the same conductivity type, and the doping ions have the same concentration, so that the three can be formed by the same ion doping process.

[0154] For example, refer to Figure 6 As shown, a third ion doping process is performed from the front side 1G1 of the semiconductor layer 1 to form a floating shielding region 121, an ohmic contact region 122, and a field limiting ring 123. The conductivity type of the doped ions in the third ion doping process is opposite to the conductivity type of the doped ions in the second ion doping process. Exemplarily, the doped ions in the third ion doping process are P-type doped ions.

[0155] In some embodiments, reference Figure 7 As shown, execute the above step S103.

[0156] In some embodiments, reference Figure 7As shown, the method for forming the semiconductor device 100 also includes: forming an insulating dielectric layer 18, the insulating dielectric layer 18 extends from the terminal area 1C to the gate current conduction area 1B, and is located on the floating shielding area 121, the shielding doping area 131 and the floating isolation area 141 inside the semiconductor layer 1.

[0157] In some embodiments, reference Figure 7 As shown, the method for forming the semiconductor device 100 further includes: forming a gate oxide layer 15 on the semiconductor layer 1, the gate oxide layer 15 including a second gate oxide portion 151 and a first gate oxide portion 152. The first gate oxide portion 152 is located on the floating shielding region 121, the shielding doping region 131 and the floating isolation region 141 of the gate current conduction region 1B, and is in contact with the floating shielding region 121, the shielding doping region 131 and the floating isolation region 141. The first gate oxide portion 152 is also adjacent to the insulating dielectric layer 18. The second gate oxide portion 151 is located on the source region 142 and the active region 132 of the cell region 1A, and is in contact with the source region 142 and the active region 132. The first gate oxide portion 152 is also adjacent to the insulating dielectric layer 18. In this way, the second gate oxide portion 151 and the first gate oxide portion 152 are formed at the same time, simplifying the formation process of the semiconductor device 100.

[0158] In some embodiments, reference Figure 7 As shown, the method for forming the semiconductor device 100 further includes: forming a gate layer 16, the gate layer 16 including a second gate 161 and a first gate 162 connected. The first gate 162 is located on the first gate oxide portion 152 and the insulating dielectric layer 18 and is in contact with the first gate oxide portion 152 and the insulating dielectric layer 18. A portion of the insulating dielectric layer 18 is located between the first gate 162 and the floating shielding region 121. The second gate 161 is located on the second gate oxide portion 151 and is in contact with the second gate oxide portion 151. In this way, the second gate 161 and the first gate 162 are formed at the same time, simplifying the formation process of the semiconductor device 100.

[0159] In some embodiments, reference Figure 7 As shown, the method for forming the semiconductor device 100 further includes: forming a dielectric layer 17, the dielectric layer 17 including a first dielectric portion 171 and a second dielectric portion 172. The first dielectric portion 171 covers the second gate 161. The second dielectric portion 172 covers the first gate 162 and extends from the gate current conducting region 1B to the terminal region 1C. The second dielectric portion 172 also includes a contact hole exposing the first gate 162. In this way, the first dielectric portion 171 and the second dielectric portion 172 are formed at the same time, simplifying the formation process of the semiconductor device 100.

[0160] In some embodiments, reference Figure 7As shown, the method for forming the semiconductor device 100 further includes: forming a front metal layer 2. The front metal layer 2 includes a source metal 21 and a third gate 22. The source metal 21 is located on the first dielectric portion 171 and contacts the ohmic contact region 122 and the source region 142. The third gate 22 is located on the second dielectric portion 172 and connected to the first gate 162 through a contact hole. In this way, the source metal 21 and the third gate 22 are formed at the same time, simplifying the formation process of the semiconductor device 100.

[0161] In some embodiments, reference Figure 7 As shown, the method for forming the semiconductor device 100 further includes:

[0162] A drift region 1D is formed, and the drift region 1D is located at one side of the floating shield region 121 and the cell region 1A in the second direction Y.

[0163] It should be noted that after the front side 1G1 of the initial drift region forms various doping regions located in the cell region 1A, the gate current conduction region 1B and the terminal region 1C through a doping process, the remaining initial drift region constitutes the drift region 1D.

[0164] In some embodiments, reference Figure 7 As shown, the method for forming the semiconductor device 100 further includes:

[0165] A substrate region 1E is formed. In the second direction Y, the substrate region 1E is located on a side of the drift region 1D away from the floating shield region 121 and the cell region 1A.

[0166] It should be noted that the first semiconductor layer 10 is the initial substrate region 1E. After the back surface 1G2 of the first semiconductor layer 10 is thinned, the remaining first semiconductor layer 10 constitutes the substrate region 1E.

[0167] In some embodiments, reference Figure 7 As shown, the method for forming the semiconductor device 100 further includes:

[0168] A drain metal 3 is formed, and the drain metal 3 is located on and in contact with the substrate region 1E.

[0169] According to a third aspect of the present disclosure, an embodiment of the present application further provides a power semiconductor module. The power semiconductor module includes the semiconductor device 100 described above. The reliability of the semiconductor device 100 is improved, thereby improving the reliability of the power semiconductor module.

[0170] According to a fourth aspect of the present disclosure, a vehicle is provided. The vehicle may be a fuel vehicle, a plug-in hybrid vehicle, or a new energy vehicle, etc., which is not specifically limited in the embodiments of the present application. The vehicle includes the above-mentioned power semiconductor module. The reliability of the power semiconductor module is improved, thereby improving the safety performance of the vehicle.

[0171] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0172] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0173] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0174] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. Although the descriptions of various embodiments in the embodiments of the present application have different focuses, for the parts not described in detail in a certain embodiment, reference can be made to the relevant contents of other embodiments. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A semiconductor device (100), characterized in that include: A semiconductor layer (1) including a gate current conducting region (1B); A floating shielding region (121) located inside the semiconductor layer (1) of the gate current conducting region (1B); A first gate structure (GS1) is located on the floating shielding region (121).

2. The semiconductor device (100) according to claim 1, characterized in that The first gate structure (GS1) comprises: A first gate (162) is located on the semiconductor layer (1) in the gate current conducting region (1B); The first gate oxide portion (152) is located between the first gate (162) and the floating shielding region (121).

3. The semiconductor device (100) according to claim 2, characterized in that Also includes: An insulating dielectric layer (18) is adjacent to the first gate oxide portion (152) and is located between the first gate (162) and the floating shielding region (121).

4. The semiconductor device (100) according to claim 3, characterized in that The semiconductor layer (1) further comprises a terminal region (1C), the terminal region (1C) being adjacent to the gate current conduction region (1B), and at least a portion of the insulating dielectric layer (18) being located in the terminal region (1C).

5. The semiconductor device (100) according to claim 3, characterized in that The thickness of the insulating dielectric layer (18) is greater than the thickness of the first gate oxide portion (152).

6. The semiconductor device (100) according to claim 2, characterized in that Also includes: A shielding doping region (131) is located on a side of the floating shielding region (121) away from the first gate oxide portion (152) and is isolated from the floating shielding region (121).

7. The semiconductor device (100) according to claim 6, characterized in that Also includes: An ohmic contact region (122) is located inside the semiconductor layer (1) and is connected to the shielding doping region (131).

8. The semiconductor device (100) according to claim 7, characterized in that The ohmic contact region (122) and the floating shielding region (121) have doping ions of the same conductive type.

9. The semiconductor device (100) according to claim 8, characterized in that The concentration of the doped ions in the ohmic contact region (122) is the same as the concentration of the doped ions in the floating shielding region (121).

10. The semiconductor device (100) according to claim 6, characterized in that The shielding doping region (131) and the floating shielding region (121) have doping ions of the same conductive type.

11. The semiconductor device (100) according to claim 10, characterized in that The concentration of doped ions in the shielding doping region (131) is lower than the concentration of doped ions in the floating shielding region (121).

12. The semiconductor device (100) according to claim 6, characterized in that Also includes: A floating isolation region (141) is located between the shielding doping region (131) and the floating shielding region (121).

13. The semiconductor device (100) according to claim 12, characterized in that The floating isolation region (141) and the floating shielding region (121) respectively include doping ions of opposite conductive types.

14. The semiconductor device (100) according to claim 12, characterized in that The shielding doping region (131) and the floating isolation region (141) respectively include doping ions of opposite conductivity types.

15. The semiconductor device (100) according to claim 12, characterized in that Also includes: The source region (142) is located inside the semiconductor layer (1) and has doping ions of the same conductivity type as the floating isolation region (141).

16. The semiconductor device (100) according to claim 15, characterized in that The concentration of the doped ions in the source region (142) is the same as the concentration of the doped ions in the floating isolation region (141).

17. The semiconductor device (100) according to claim 6, characterized in that The semiconductor layer (1) further includes a terminal region (1C) adjacent to the gate current conducting region (1B); The semiconductor device (100) further comprises a field limiting ring (123) located inside the semiconductor layer (1) in the terminal region (1C).

18. The semiconductor device (100) according to claim 17, characterized in that The adjacent field limiting rings are connected to the shielding doping region (131).

19. The semiconductor device (100) according to claim 17, characterized in that The field limiting ring (123) and the floating shielding region (121) have doping ions of the same conductive type.

20. The semiconductor device (100) according to claim 19, wherein the concentration of doped ions in the field limiting ring (123) is the same as the concentration of doped ions in the floating shielding region (121).

21. The semiconductor device (100) according to claim 6, characterized in that Also includes: The active region (132) is located in the semiconductor layer (1) and has doping ions of the same conductivity type as the shielding doping region (131).

22. The semiconductor device (100) according to claim 21, characterized in that The concentration of the doping ions in the active region (132) is the same as the concentration of the doping ions in the shielding doping region (131).

23. The semiconductor device (100) according to any one of claims 2 to 22, characterized in that Also includes: A cell region (1A) adjacent to the gate current conducting region (1B); A second gate (161) is located on the semiconductor layer (1) of the cell region (1A) and is connected to the first gate (162).

24. The semiconductor device (100) according to claim 23, characterized in that The cellular structure further includes: A source metal (21) is located on the semiconductor layer (1) and is insulated from the second gate (161).

25. The semiconductor device (100) according to any one of claims 2 to 22, characterized in that Also includes: The third gate (22) is located on a side of the first gate (162) away from the semiconductor layer (1) and is connected to the first gate (162).

26. The semiconductor device (100) according to claim 25, characterized in that Also includes: The second dielectric portion (172) is located between the first grid (162) and the third grid (22) and includes a contact hole, and the third grid (22) and the first grid (162) are connected through the contact hole.

27. The semiconductor device (100) according to any one of claims 1 to 22, characterized in that Also includes: A drift region (1D) is located on a side of the floating shielding region (121) away from the first gate structure (GS1).

28. The semiconductor device (100) according to claim 27, characterized in that The drift region (1D) and the floating shielding region (121) respectively contain doping ions of opposite conductivity types.

29. The semiconductor device (100) according to claim 27, characterized in that Also includes: a substrate region (1E) located on a side of the drift region (1D) away from the floating shielding region (121); A drain metal (3) is located on a side of the substrate region (1E) away from the drift region (1D).

30. A method for forming a semiconductor device (100), characterized in that: include: forming a semiconductor layer (1), wherein the semiconductor layer includes a gate current conducting region (1B); forming a floating shielding region (121) inside the semiconductor layer (1) of the gate current conduction region (1B); A first gate structure (GS1) is formed, wherein the first gate structure (GS1) is located on the floating shielding region (121).

31. The method for forming a semiconductor device (100) according to claim 30, characterized in that: Also includes: A shielding doping region (131) is formed, wherein the shielding doping region (131) is located on a side of the floating shielding region (121) away from the first gate structure (GS1) and is isolated from the floating shielding region (121).

32. The method for forming a semiconductor device (100) according to claim 31, characterized in that: Also includes: A floating isolation region (141) is formed, wherein the floating isolation region (141) is located between the shielding doping region (131) and the floating shielding region (121).

33. The method for forming a semiconductor device (100) according to claim 32, characterized in that: The forming of the shielding doping region (131) comprises: forming an initial shielding doping region (131A) inside the semiconductor layer (1); An initial floating isolation region (141A) is formed in a portion of the initial shielding doping region (131A), and the remaining initial shielding doping region (131A) constitutes the shielding doping region (131).

34. The method for forming a semiconductor device (100) according to claim 33, characterized in that: The forming of the floating isolation region (141) comprises: The floating shielding region (121) is formed in a portion of the initial floating isolation region (141A), and the remaining initial floating isolation region (141A) constitutes the floating isolation region (141).

35. The method for forming a semiconductor device (100) according to claim 34, characterized in that: The semiconductor layer (1) further includes a cell region (1A), and the gate current conduction region (1B) is adjacent to the cell region (1A); the method further includes: In the process of forming an initial shielding doping region (131A) inside the semiconductor layer (1), an initial active region (132A) is formed inside the semiconductor layer (1) of the cell region (1A).

36. The method for forming a semiconductor device (100) according to claim 35, characterized in that: The method further comprises: In the process of forming an initial floating isolation region (141A) in a portion of the initial shielding doping region (131A), a source region (142) is formed in the initial active region (132A).

37. The method for forming a semiconductor device (100) according to claim 35, characterized in that: The method further comprises: In the process of forming the floating shielding region (121) in part of the initial floating isolation region (141A), an ohmic contact region (122) is formed in the initial active region (132A), and the remaining initial active region (132A) constitutes an active region (132).

38. The method for forming a semiconductor device (100) according to claim 35 or 37, characterized in that: The semiconductor layer (1) further includes a terminal region (1C), and the gate current conducting region (1B) is adjacent to the terminal region (1C); the method further includes: During the process of forming the floating shielding region (121) in part of the initial floating isolation region (141A), a field limiting ring (123) is formed in the semiconductor layer (1) of the terminal region (1C).

39. The method for forming a semiconductor device (100) according to claim 30, characterized in that: The forming of the first gate structure (GS1) comprises: forming a first gate oxide portion (152), wherein the first gate oxide portion (152) is located on the semiconductor layer (1) in the gate current conducting region (1B); A first gate (162) is formed, and the first gate (162) is located on a side of the first gate oxide portion (152) away from the floating shielding region (121).

40. The method for forming a semiconductor device (100) according to claim 39, characterized in that: The method further comprises: An insulating dielectric layer (18) is formed, the insulating dielectric layer (18) is adjacent to the first gate oxide portion (152), and the insulating dielectric layer (18) is located between the first gate (162) and the floating shielding region (121).

41. A power semiconductor module, characterized in that: A semiconductor device (100) comprising any one of claims 1 to 29.

42. A vehicle, characterized in that: Comprising the power semiconductor module according to claim 41.

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