Semiconductor device and electronic equipment

Abstract

The invention discloses a semiconductor device and electronic equipment, the semiconductor device comprises a semiconductor substrate, a first barrier layer, a metal silicide layer, a gate stack structure and a gate side wall, the semiconductor substrate comprises a channel region, a source region and a drain region, the source region and the drain region are located on two sides of the channel region, the first barrier layer is located on the source region and the drain region, and the metal silicide layer is located on the gate side wall. The metal silicide layer covers one side, opposite to the semiconductor substrate, of the first barrier layer on the source electrode region and the drain electrode region. Grooves are formed in the source electrode region and the drain electrode region respectively, and the grooves are filled with first semiconductor materials. The first barrier layer comprises a second semiconductor material doped with first doping ions, and the lattice structure of the material of the metal silicide layer is different from the lattice structure of the first semiconductor material. According to the arrangement, the first barrier layer is arranged between the metal silicide layer and the first semiconductor material, so that material agglomeration and precipitation caused by direct contact between the first semiconductor material and the metal silicide layer can be avoided, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and an electronic device. Background Art

[0002] In semiconductor manufacturing, for metal oxide semiconductor field effect transistor (MOSFET) devices, the carriers of N-type metal oxide semiconductor field effect transistor (NMOS) are electrons, and the carriers of P-type metal oxide semiconductor field effect transistor (PMOS) are holes, and the effective mass of holes is greater than the effective mass of electrons, so the mobility of holes is much smaller than that of electrons. In order to maintain the carrier balance of MOSFET and increase the speed of PMOS, it is necessary to increase the mobility of holes. Based on this, by epitaxially growing SiGe material in the source / drain region of the semiconductor substrate, compressive stress will be generated laterally, thereby squeezing the channel, making the lattice constant in the channel smaller, thereby increasing the mobility of holes.

[0003] In addition, in order to avoid non-ohmic contact caused by direct contact between metal and semiconductor parts (such as source / drain regions) in transistors, metal silicide is usually used as a transition layer for contact between metal and semiconductor parts (such as source / drain regions). For example, metal is covered on the SiGe material in the source / drain region, and then metal silicide is formed by thermal reaction to achieve interconnection. However, some metal silicides have different crystal structures from SiGe materials, resulting in agglomeration and precipitation of Ge after these metal silicides are formed on SiGe materials, resulting in stress loss in SiGe materials, which seriously affects the performance of semiconductor devices. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor device and an electronic device to prevent material agglomeration and precipitation and improve the performance of the semiconductor device.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor device, which includes: a semiconductor substrate, a first barrier layer, a metal silicide layer, a gate stack structure, and a gate sidewall, wherein the semiconductor substrate includes a channel region and a source region and a drain region located on both sides of the channel region, the first barrier layer is located on the source region and the drain region, the metal silicide layer covers the side of the first barrier layer on the source region and the drain region that faces away from the semiconductor substrate, the gate stack structure is located on the channel region, and the gate stack structure includes a gate dielectric layer and a gate, and the gate dielectric layer is located between the gate and the channel region. The gate sidewall is located on both sides of the gate stack structure, and the positive projection of the gate sidewall on the semiconductor substrate does not overlap with the opening of the groove. In addition, the source region and the drain region are respectively formed with grooves, and the grooves are filled with a first semiconductor material, and the positive projection of the first barrier layer on the semiconductor substrate covers the positive projection of the opening of the groove in the source region and the drain region on the semiconductor substrate. In addition, the first barrier layer includes a second semiconductor material doped with a first doping ion, and the lattice structure of the material of the metal silicide layer is different from the lattice structure of the first semiconductor material. Thus, by arranging the first barrier layer between the metal silicide layer and the first semiconductor material, it is possible to avoid the first semiconductor material from directly contacting the metal silicide layer to generate material agglomeration and precipitation, thereby improving the performance of the semiconductor device. In addition, by arranging the first barrier layer and the metal silicide layer on the source region and the drain region in sequence, the source metal connection line and the drain metal connection line are electrically connected to the source region and the drain region respectively through the first barrier layer and the metal silicide layer, thereby reducing the contact resistance.

[0006] In some embodiments, the second semiconductor material includes Si. In addition, the semiconductor device is a P-type transistor, and the first doping ion is a B ion. Alternatively, the first doping ion is a B ion and a C ion. The doping concentration (body density) of the B ion is about 1e 21 ~8e 21 ions per cubic centimeter.

[0007] In some embodiments, the metal silicide layer includes one or more of cobalt silicide, nickel silicide, and titanium silicide.

[0008] In some embodiments, the semiconductor device is a P-type transistor, and the first semiconductor material includes a germanium silicon material, which can increase the hole migration rate of the P-type transistor.

[0009] In some embodiments, a second barrier layer is further included, wherein the second barrier layer is located between the first barrier layer and the metal silicide layer on the source region and the drain region. In addition, the second barrier layer includes a third semiconductor material doped with second doping ions. In this way, the second barrier layer can further hinder the growth of the metal silicide in the direction of the first semiconductor material, and improve the thermal stability of the semiconductor device.

[0010] In some embodiments, the third semiconductor material is the same as the second semiconductor material.

[0011] In some embodiments, the second doping ions include C ions.

[0012] In some embodiments, the gate stack structure further includes a metal silicide layer covering the side of the gate facing away from the semiconductor substrate. Thus, when forming a gate metal connection line, the gate metal connection line can be electrically connected to the gate through the metal silicide layer, thereby reducing contact resistance.

[0013] In some embodiments, in order to achieve the effect of squeezing the channel and improve the mobility of the holes of the P-type transistor, the cross-sectional area of ​​the groove in the first cross-section gradually increases to a target cross-sectional area in the direction from the bottom of the groove to the opening of the groove, and then gradually decreases from the target cross-sectional area. The first cross-section is parallel to the plane where the opening of the groove is located, and the first cross-section is located between the opening and the bottom of the groove.

[0014] In the second aspect, an embodiment of the present application further provides an electronic device, which includes a circuit board and a semiconductor device, and the semiconductor device is arranged on the circuit board and electrically connected to the circuit board. The semiconductor device is a semiconductor device as in the first aspect or various embodiments of the first aspect. Since the performance of the above-mentioned semiconductor device is good, the performance of the electronic device including the above-mentioned semiconductor device is also good. In addition, the principle of solving the problem by the electronic device is similar to that of the aforementioned semiconductor device, so the implementation of the electronic device can refer to the implementation of the aforementioned semiconductor device, and the repeated parts will not be repeated.

[0015] In a third aspect, an embodiment of the present application also provides a method for preparing a semiconductor device, the method comprising: forming a gate stack structure and gate sidewalls on both sides of the gate stack structure on a channel region of a semiconductor substrate, the gate stack structure comprising a gate dielectric layer and a gate, the gate dielectric layer being located between the gate and the channel region, and the gate sidewalls having an orthographic projection on the semiconductor substrate that does not overlap with the opening of the groove. Etching the source region and the drain region in the semiconductor substrate to form grooves respectively. Epitaxially growing a first semiconductor material in the grooves. Ion doping is performed in the source region and the drain region of the semiconductor substrate and a first barrier layer and a metal silicide are formed on the source region and the drain region, the orthographic projection of the first barrier layer on the semiconductor substrate respectively covering the orthographic projection of the opening of the groove in the source region and the drain region on the semiconductor substrate, the first barrier layer comprising a second semiconductor material doped with a first doping ion, and the metal silicide layer covers the side of the first barrier layer on the source region and the drain region that faces away from the semiconductor substrate.

[0016] For forming a metal silicide layer, for example, ion doping is performed in the source region and the drain region of the semiconductor substrate and a first barrier layer and a metal silicide are formed on the source region and the drain region, including the following process: epitaxially forming a silicon capping layer doped with B ions on the source region and the drain region, the orthographic projection of the silicon capping layer on the semiconductor substrate respectively covering the orthographic projection of the opening of the groove in the source region and the drain region on the semiconductor substrate; wherein the doping concentration of B ions in the silicon capping layer after this doping is 8e 20 ions per cubic centimeter to 8e 21 ions per cubic centimeter. B ion doping is performed in the source region, drain region and silicon cover layer of the semiconductor substrate, wherein the doping concentration of B ions in the silicon cover layer after this doping is 1e 21 ions per cubic centimeter to 8e 21 ions per cubic centimeter. The rare gas ions are used to pre-amorphize at least one side of the silicon cover layer facing away from the semiconductor substrate, so that an amorphous silicon layer is formed on the side of the silicon cover layer facing away from the semiconductor substrate. The self-aligned silicide process is used to form a metal silicide layer from the amorphous silicon layer.

[0017] In order to further hinder the growth of metal silicide and improve the thermal stability of semiconductor devices, the preparation method, after using rare gas ions to pre-amorphize at least one side of the silicon cover layer facing away from the semiconductor substrate, so that an amorphous silicon layer is formed on the side of the silicon cover layer facing away from the semiconductor substrate, further includes the following process: injecting C ions into the amorphous silicon layer. In addition, for using a self-aligned silicide process to form a metal silicide layer on the amorphous silicon layer, the following process is included: using a self-aligned silicide process to form a metal silicide on the amorphous silicon layer, and forming a second barrier layer between the metal silicide and the first barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of the structure of an electronic device in an embodiment of the present application;

[0019] Figure 2 A schematic diagram of the structure of a semiconductor device in an embodiment of the present application;

[0020] Figure 3 It is another structural schematic diagram of the semiconductor device in the embodiment of the present application;

[0021] Figures 4a to 4f A schematic diagram of the structure of a semiconductor device in an embodiment of the present application during the preparation process;

[0022] Figure 5 It is another structural schematic diagram of the semiconductor device in the embodiment of the present application;

[0023] Figure 6a and Figure 6bThey are respectively another structural schematic diagram of the semiconductor device in the embodiment of the present application during the preparation process.

[0024] Reference numerals:

[0025] 100-housing; 200-circuit board; 300-semiconductor device; 310-semiconductor substrate; 320-first semiconductor material; 320'-germanium silicon material; 330-first barrier layer; 331 / 332-amorphous silicon layer; 330'-silicon cap layer; 340 / 353-metal silicide layer; 350-gate stack structure; 351-gate dielectric layer; 352-gate; 360-gate sidewall; 370-metal layer; 371-source metal connecting line; 372-drain metal connecting line; 373-gate metal connecting line; 374-isolation layer; GB-channel region; SB-source region; DB-drain region; AX1 / AX2-groove. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The specific operating methods in the method embodiments can also be applied to device embodiments or system embodiments. It should be noted that in the description of the present application, "multiple" can be understood as "at least two". In addition, it should be understood that in the description of the present application, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0027] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be changed as needed, and the changes are included in the protection scope of this application. The drawings of this application are only used to illustrate the relative position relationship and do not represent the true proportion.

[0028] In order to facilitate the understanding of the semiconductor device, preparation method and electronic device provided in the embodiment of the present application, the application scenario is first introduced below. The semiconductor device provided in the embodiment of the present application can be widely used in various electronic devices, and the electronic devices include various terminal devices and electronic devices. For example, the terminal device includes but is not limited to smart phones, smart TVs, smart TV set-top boxes, smart watches, personal computers (personal computers, PCs), wearable devices, smart broadband and other devices. Electronic devices include but are not limited to wireless networks, fixed networks, servers and other communication equipment and device modules, memories, static random access memories, digital logic circuits and other devices, which are not listed one by one here. It is understandable that the specific implementation of the semiconductor device can be determined according to the actual application scenario, and is not limited here.

[0029] Figure 1 Schematic diagram of a structure of an electronic device in an embodiment of the present application. Figure 1 The electronic device includes: a housing 100, a circuit board 200 disposed in the housing 100, and a semiconductor device 300 fixed on the circuit board 200. The semiconductor device 300 and the circuit board 200 can be connected by bonding, bonding, etc. to achieve electrical connection between the semiconductor device 300 and the circuit board 200, so that signals can be transmitted between the semiconductor device 300 and the circuit board 200.

[0030] Figure 2 A schematic diagram of the structure of a semiconductor device in an embodiment of the present application, referring to Figure 2The semiconductor device 300 includes: a semiconductor substrate 310 and a first barrier layer 330, a metal silicide layer 340, a gate stack structure 350 and a gate spacer 360 located on the same side of the semiconductor substrate 310. The semiconductor substrate 310 includes a channel region GB and a source region SB and a drain region DB located on both sides of the channel region GB. The gate stack structure 350 is located on the channel region GB, and the gate spacer 360 is located on both sides of the gate stack structure 350. In order to improve the performance of the semiconductor device, a groove AX1 is formed in the source region SB, and a groove AX2 is formed in the drain region DB. The grooves AX1-AX2 are respectively filled with a first semiconductor material 320 to generate compressive stress in the lateral direction and achieve the effect of squeezing the channel. In addition, the gate stack structure 350 includes a gate dielectric layer 351 and a gate 352. The gate dielectric layer 351 is located between the gate 352 and the channel region GB, and the orthographic projection of the gate spacer 360 on the semiconductor substrate 310 does not overlap with the opening of the groove. Furthermore, the first barrier layer 330 is located on the source region SB and the drain region DB, and the orthographic projection of the first barrier layer 330 on the semiconductor substrate 310 covers the orthographic projection of the opening of the groove in the source region SB and the drain region DB on the semiconductor substrate 310. The metal silicide layer 340 covers the side of the first barrier layer 330 on the source region SB and the drain region DB facing away from the semiconductor substrate 310. Since the lattice structure of the material of the metal silicide layer 340 is different from the lattice structure of the first semiconductor material 320, by arranging the first barrier layer 330 between the metal silicide layer 340 and the first semiconductor material 320, and by making the first barrier layer 330 include the second semiconductor material doped with the first doping ions, it is possible to avoid the first semiconductor material 320 from directly contacting the metal silicide layer 340 to generate material agglomeration and precipitation, thereby improving the performance of the semiconductor device. In addition, by sequentially arranging the first barrier layer 330 and the metal silicide layer 340 on the source region SB and the drain region DB, the source metal connecting line and the drain metal connecting line can be electrically connected to the source region SB and the drain region DB through the first barrier layer 330 and the metal silicide layer 340, respectively, thereby reducing the contact resistance.

[0031] Continue to refer to Figure 2 The gate stack structure 350 further includes a metal silicide layer 353 covering the side of the gate 352 facing away from the semiconductor substrate 310. Thus, when a gate metal connection line is formed, the gate metal connection line can be electrically connected to the gate 352 through the metal silicide layer 340, thereby reducing contact resistance.

[0032] Continue to refer to Figure 2 , the orthographic projection of the gate 352 on the semiconductor substrate 310 is located within the orthographic projection of the channel region GB on the semiconductor substrate 310 . Alternatively, the orthographic projection of the gate 352 on the semiconductor substrate 310 overlaps with the orthographic projection of the channel region GB on the semiconductor substrate 310 .

[0033] Continue to refer to Figure 2 , the orthographic projection of the gate sidewall 360 close to the source region SB on the semiconductor substrate 310 also covers a portion of the orthographic projection of the source region SB on the semiconductor substrate 310 close to the orthographic projection of the gate on the semiconductor substrate 310, and the orthographic projection of the gate sidewall 360 close to the drain region DB on the semiconductor substrate 310 also covers a portion of the orthographic projection of the drain region DB on the semiconductor substrate 310 close to the orthographic projection of the gate on the semiconductor substrate 310. Alternatively, the orthographic projection of the gate sidewall 360 close to the source region SB on the semiconductor substrate 310 may be located within the orthographic projection of the channel region GB on the semiconductor substrate 310, and the orthographic projection of the gate sidewall 360 close to the drain region DB on the semiconductor substrate 310 may be located within the orthographic projection of the channel region GB on the semiconductor substrate 310.

[0034] The semiconductor device in the embodiment of the present application can be configured as a P-type transistor (eg, PMOS). In order to improve the mobility of holes in the P-type transistor, due to the lattice constant of Ge Larger than Si's lattice constant Epitaxial growth of silicon germanium (SiGe) material in the grooves in the source region SB and the drain region DB of the semiconductor substrate 310 will produce compressive stress in the lateral direction, thereby squeezing the channel, reducing the lattice constant in the channel, and thus improving the mobility of holes. Based on this, the first semiconductor material 320 can be set to silicon germanium material. Especially in the chip manufacturing process below 45nm, by filling the groove with silicon germanium material, the hole migration rate of the P-type transistor can be improved. Of course, in specific applications, the first semiconductor material 320 can also be other materials that can achieve squeezing the channel, which is not limited here.

[0035] In a specific implementation, the metal silicide layer 340 includes cobalt silicide (CoSi 2 ), nickel silicide (NiSi), titanium silicide (TiSi) or more. It is understandable that nickel silicide has poor thermal stability and will degrade at temperatures greater than 500 degrees Celsius, limiting the use of nickel silicide in certain processes that require high temperatures. Cobalt silicide has the advantages of good conductivity and low mismatch with silicon, and CoSi 2 It is the final phase of cobalt silicide, and its thermal stability is about 150 degrees Celsius higher than that of NiSi. It has good applications in certain scenarios where semiconductor devices need to be applied to high-temperature thermal stability. Based on this, in the embodiment of the present application, when semiconductor devices need to be applied to high-temperature thermal stability, the material of the metal silicide layer 340 can be preferably selected from cobalt silicide (CoSi 2 ). Furthermore, in the chip manufacturing process below 45nm, by using cobalt silicide (CoSi 2) forms a metal silicide layer 340, which can enable the prepared semiconductor device to be used for a long time at high temperature and avoid the degradation of NiSi material at high temperature.

[0036] In the present application, the second semiconductor material is set to Si, wherein the first doping ion is set to B ion, and the first barrier layer 330 is a film layer doped with B ions in Si. Alternatively, the first doping ion is set to B ion and C ion, and the first barrier layer 330 is a film layer doped with B ions and C ions in Si. In addition, the B ions can have a higher doping concentration, so as to hinder the growth of metal silicide during the preparation process, and further avoid the contact between the metal silicide and the first semiconductor material 320. Of course, the specific doping concentrations of B ions and C ions can be determined according to the actual process requirements and are not limited here.

[0037] Continue to refer to Figure 2 In order to achieve the effect of squeezing the channel and improve the mobility of the holes of the P-type transistor, taking the groove AX2 as an example, the cross-sectional area of ​​the groove AX2 in the first cross-section CS can be gradually increased to the target cross-sectional area S0 in the direction F0 from the bottom of the groove AX2 to the opening of the groove AX2 (i.e., the direction pointed by the arrow F0), and then gradually reduced from the target cross-sectional area S0. In addition, the first cross-section CS is parallel to the plane where the opening of the groove AX2 is located, and the first cross-section CS is located between the opening and the bottom of the groove AX2. With this arrangement, the cross-sectional area of ​​the groove AX2 in the first cross-section CS can show a trend of first increasing and then shrinking in the direction F0 from the bottom of the groove AX2 to the opening of the groove (i.e., the direction pointed by the arrow F0). The groove AX1 can be arranged in the same way, which will not be described in detail here.

[0038] Figure 3 is another structural schematic diagram of a semiconductor device in an embodiment of the present application, referring to Figure 3In order to realize interconnection, the semiconductor device 300 further includes: an isolation layer 374, a source metal connection line 371, a drain metal connection line 372 and a gate metal connection line 373, wherein the isolation layer 374 covers the side of the semiconductor substrate 310 having the gate stack structure 350, and the isolation layer 374 includes a source contact hole, a drain contact hole and a gate contact hole penetrating therethrough, the source contact hole is used to expose the metal silicide layer 340 on the source region SB, the drain contact hole is used to expose the metal silicide layer 340 on the drain region DB, and the gate contact hole is used to expose the metal silicide layer 340 on the gate. Moreover, the source metal connection line 371 contacts the metal silicide layer 340 on the source region SB through the source contact hole, so that the source metal connection line 371 can be connected to the source region SB through the first barrier layer 330 of the metal silicide layer 340 on the source region SB, thereby realizing the reduction of contact resistance and signal transmission. Furthermore, the drain metal connection line 372 contacts the metal silicide layer 340 on the drain region DB through the drain contact hole, so that the drain metal connection line 372 can be connected to the drain region DB through the metal silicide layer 340 and the first barrier layer 330 on the drain region DB, thereby reducing the contact resistance and signal transmission. Furthermore, the gate metal connection line 373 contacts the metal silicide on the gate through the gate contact hole, so that the gate metal connection line 373 can be connected to the gate through the metal silicide, thereby reducing the contact resistance and signal transmission.

[0039] The following is prepared Figure 2 Taking the structure of the semiconductor device shown as an example, the method for preparing the semiconductor device provided by the embodiment of the present application is described. Specifically, the method for preparing the semiconductor device provided by the embodiment of the present application may include the following contents:

[0040] Reference Figure 4a , Figure 4aThis is a structural schematic diagram of a semiconductor device in an embodiment of the present application during the preparation process. For example, a semiconductor substrate 310 is provided, and a gate stack structure 350 and gate sidewalls 360 located on both sides of the gate stack structure 350 are formed on the channel region GB of the semiconductor substrate 310. Then, gate sidewalls 360 are formed on both sides of the gate 352. Among them, the materials of the gate dielectric layer 351 and the gate sidewalls 360 include but are not limited to one or more of silicon dioxide and silicon nitride. The material of the gate 352 includes but is not limited to polysilicon. Then, through an etching process, grooves are etched in the source region SB and the drain region DB respectively. For example, a dry etching machine and a selective wet etching solution can be used, and the etching solution includes but is not limited to tetramethylammonium hydroxide (TMAH), and the source region SB and the drain region DB are dry-etched and wet-etched respectively, so as to form grooves in the source region SB and the drain region DB. In addition, the semiconductor substrate 310 includes but is not limited to a silicon substrate.

[0041] Reference Figure 4b , Figure 4b This is another structural schematic diagram of the semiconductor device in the embodiment of the present application during the preparation process. For example, the first semiconductor material 320 is epitaxially grown in the groove. For example, the first semiconductor material 320 is a germanium silicon material, and an epitaxial growth device can be used to epitaxially grow the germanium silicon material 320' in the groove.

[0042] Reference Figure 4c , Figure 4c FIG. 1 is another structural schematic diagram of a semiconductor device in an embodiment of the present application during the preparation process. For example, an epitaxial growth device can be used, and when the silicon cap layer 330' is epitaxially grown, a boride (such as borane B 2 H 6 ), doping B ions in the silicon capping layer 330', and making the orthogonal projection of the formed silicon capping layer 330' on the semiconductor substrate 310 cover the orthogonal projection of the opening of the groove in the source region SB and the drain region DB on the semiconductor substrate 310. In addition, by increasing the addition ratio of boride, the concentration of B ions in the silicon capping layer 330' is increased, so that the doping concentration of B ions in the silicon capping layer 330' is within 8e 20 To 8e 21 ions per cubic centimeter. In addition, the thickness of the silicon cover layer 330' can be in the range of 15nm to 30nm. It is understandable that when the silicon cover layer 330' is epitaxially grown, C ions can also be doped when B ions are doped in the silicon cover layer 330', or C ions can be directly doped in the silicon cover layer 330'. And by adjusting the concentration of C ions, the concentration of C ions in the silicon cover layer 330' is increased.

[0043] Reference Figure 4d , Figure 4d This is another structural schematic diagram of the semiconductor device in the embodiment of the present application during the preparation process. For example, ion implantation equipment can be used to implant B ions into the source region SB and the drain region DB of the semiconductor substrate 310 to form the source region SB and the drain region DB doped with B ions. Since B ions are further implanted into the silicon capping layer 330' when the source region SB and the drain region DB are implanted, the concentration of B ions in the silicon capping layer 330' is increased, thereby further increasing the content of B ions at the bottom of the silicon capping layer 330' to form a boron barrier layer. Moreover, in this step, the implantation energy of the B ions is approximately 2 to 4 kiloelectron volts, and the implantation dose is 2e 15 To 5e 15 ions per square centimeter, so that the doping concentration of B ions in the silicon cap layer 330' after this step is within 1e 21 To 8e 21 ions per cubic centimeter. Afterwards, a spike annealing process is performed using a spike annealing device and a laser surface annealing is performed using a laser annealing device to achieve diffusion activation of the B ions injected into the source region SB and the drain region DB. In addition, the region between the source region SB and the drain region DB is formed as a channel region GB.

[0044] Reference Figure 4e , Figure 4e This is another structural schematic diagram of the semiconductor device in the embodiment of the present application during the preparation process. For example, ion implantation equipment can be used to use rare gas ions to perform pre-amorphization (PAI) treatment on the side of the silicon capping layer 330' facing away from the semiconductor substrate 310 through ion implantation, so that a more stable amorphous silicon layer 331 is formed in the area on the side of the silicon capping layer 330' facing away from the semiconductor substrate 310, and there is also a silicon capping layer 330' doped with B ions between the amorphous silicon layer 331 and the semiconductor substrate 310 to promote the formation of metal silicide in the subsequent steps, and the PAI treatment by rare gas ions can also help improve the compactness and continuity of the metal silicide film formed in the subsequent steps, improve the interface morphology, reduce defects, and effectively improve the agglomeration of the germanium silicon material 320'. In addition, the rare gas ions can also be used to perform pre-amorphization treatment on the side of the gate facing away from the semiconductor substrate 310 through ion implantation, so that a more stable amorphous silicon layer 332 is formed in the area on the side of the gate facing away from the semiconductor substrate 310. In a specific implementation, the rare gas ions include, for example, Xe ions and / or Ar ions. If the amorphous implantation source uses Xe ions, the implantation energy of the Xe ions is about 2 to 10 kiloelectron volts, and the implantation dose is about 1e 14 To 5e 14ions per square centimeter. It is understandable that using Xe ions instead of conventional Ge ions in the pre-amorphization treatment can avoid agglomeration caused by the incompatibility of Ge and cobalt germanium materials.

[0045] Reference Figure 4f , Figure 4f This is another structural schematic diagram of the semiconductor device in the embodiment of the present application during the preparation process. Exemplarily, a self-aligned silicide process is used to form a metal silicide layer 340 from the amorphous silicon layer 331. Specifically, a deposition process (for example, a physical vapor deposition process based on a physical vapor deposition device) is used to deposit a metal layer 370 on the side of the silicon cap layer 330' away from the semiconductor substrate 310, and the thickness of the metal layer 370 is approximately in the range of 40 to 80 nanometers. Afterwards, a rapid thermal annealing device is used to form a high-resistance phase metal silicide layer through low-temperature rapid thermal annealing. Afterwards, a wet etcher is used to remove the remaining unreacted metal layer through selective etching (the selective etching solution is sulfuric acid). Afterwards, a rapid thermal annealing device is used to form a low-resistance phase metal silicide layer through high-temperature rapid thermal annealing. Wherein, if the metal layer is a cobalt metal layer, the metal silicide is cobalt silicide, and the annealing temperature corresponding to low-temperature rapid thermal annealing is about 380 to 540 degrees Celsius, and the annealing time is about 30 to 120 seconds, and the annealing temperature corresponding to high-temperature rapid thermal annealing is about 700 to 900 degrees Celsius, and the annealing time is about 5 to 30 seconds. If the metal layer is a nickel metal layer, the metal silicide is nickel silicide, and the annealing temperature corresponding to low-temperature rapid thermal annealing is about 200 to 300 degrees Celsius, and the annealing time is about 30 to 60 seconds, and the annealing temperature corresponding to high-temperature rapid thermal annealing is about 300 to 550 degrees Celsius, and the annealing time is about 5 to 30 seconds. If the metal layer is a titanium metal layer, the metal silicide is titanium silicide, and the annealing temperature and annealing time corresponding to low-temperature rapid thermal annealing and high-temperature rapid thermal annealing can be determined according to process requirements.

[0046] It is understandable that, taking the metal silicide as cobalt silicide as an example, since B ions are doped in the silicon capping layer 330', when the cobalt silicide is formed, the growth of the cobalt silicide will be hindered, the thickness of the cobalt silicide layer will be reduced, and the cobalt silicide layer will be prevented from directly contacting with the silicon germanium material in the groove to produce agglomeration and precipitation, thereby improving the performance of the semiconductor device. In addition, when the silicon capping layer 330' is epitaxially grown, by increasing the doping concentration of B ions in the silicon capping layer 330', the growth of the cobalt silicide can be further hindered, and the cobalt silicide layer can be prevented from directly contacting with the silicon germanium material in the groove. Furthermore, when ion implantation is performed in the source region SB and the drain region DB, the concentration of B ions in the silicon capping layer 330' can be further increased, which can further inhibit the growth of the cobalt silicide toward the side of the semiconductor substrate 310, and further prevent the cobalt silicide layer from directly contacting with the silicon germanium material in the groove.

[0047] Figure 5is another structural schematic diagram of a semiconductor device in an embodiment of the present application, referring to Figure 5 , the semiconductor device 300 includes: a semiconductor substrate 310 and a first barrier layer 330, a metal silicide layer 340, a gate stack structure 350, a gate spacer 360 and a second barrier layer 380 located on the same side of the semiconductor substrate 310. Among them, the second barrier layer 380 is located between the first barrier layer 330 and the metal silicide layer 340 on the source region SB and the drain region DB, and the second barrier layer 380 includes a third semiconductor material doped with a second doping ion. Exemplarily, the third semiconductor material is the same as the second semiconductor material, for example, the second semiconductor material and the third semiconductor material are both Si, and the second doping ions include but are not limited to C ions. With this arrangement, the second barrier layer 380 can further hinder the growth of the metal silicide in the direction of the first semiconductor material 320, and improve the thermal stability of the semiconductor device.

[0048] The following is prepared Figure 5 Taking the structure of the semiconductor device shown in FIG. 1 as an example, the method for preparing the semiconductor device provided in the embodiment of the present application is described. The method for preparing the semiconductor device provided in the embodiment of the present application not only includes: Figures 4a to 4e The process shown also includes the following:

[0049] Reference Figure 6a , Figure 6a FIG. 1 is another structural diagram of a semiconductor device in an embodiment of the present application during the preparation process. For example, an ion implantation device is used to implant C ions into the source region SB, the drain region DB and the amorphous silicon layer 331 on the gate to form an amorphous silicon layer 331 doped with C ions. The implantation energy of the C ions is about 2 to 5 kiloelectron volts, and the implantation dose is about 2e 14 To 1e 15 Based on this, the second barrier layer 380 further prevents metal silicide (such as cobalt silicide) from growing downward, thereby further improving the thermal stability of the device.

[0050] Reference Figure 6b , Figure 6bThis is another structural schematic diagram of the semiconductor device in the embodiment of the present application during the preparation process. For example, a self-aligned silicide process is used to form a metal silicide layer on the amorphous silicon layer 331, and a second barrier layer 380 is formed between the metal silicide and the first barrier layer 330. Specifically, a deposition process (for example, a physical vapor deposition process based on a physical vapor deposition device) is used to deposit a metal layer on the side of the silicon cap layer 330' away from the semiconductor substrate 310, and the thickness of the metal layer is about 40 to 80 nanometers. Afterwards, a rapid thermal annealing device is used to form a high-resistance metal silicide layer through low-temperature rapid thermal annealing. Due to metal ion implantation, C ions are squeezed, thereby forming a second barrier layer 380 doped with C ions between the metal silicide and the first barrier layer 330. Afterwards, a wet etcher is used to remove the remaining unreacted metal layer through selective etching (the selective etching solution is sulfuric acid). Afterwards, a rapid thermal annealing device is used to form a low-resistance metal silicide layer through high-temperature rapid thermal annealing. Wherein, if the metal layer is a cobalt metal layer, the metal silicide is cobalt silicide, and the annealing temperature corresponding to low-temperature rapid thermal annealing is about 380 to 540 degrees Celsius, and the annealing time is about 30 to 120 seconds, and the annealing temperature corresponding to high-temperature rapid thermal annealing is about 700 to 900 degrees Celsius, and the annealing time is about 5 to 30 seconds. If the metal layer is a nickel metal layer, the metal silicide is nickel silicide, and the annealing temperature corresponding to low-temperature rapid thermal annealing is about 200 to 300 degrees Celsius, and the annealing time is about 30 to 60 seconds, and the annealing temperature corresponding to high-temperature rapid thermal annealing is about 300 to 550 degrees Celsius, and the annealing time is about 5 to 30 seconds. If the metal layer is a titanium metal layer, the metal silicide is titanium silicide, and the annealing temperature and annealing time corresponding to low-temperature rapid thermal annealing and high-temperature rapid thermal annealing can be determined according to process requirements.

[0051] The embodiment of the present application also provides an electronic device, which includes: a circuit board and a semiconductor device, wherein the semiconductor device is arranged on the circuit board and electrically connected to the circuit board. Among them, the semiconductor device is any semiconductor device in the embodiment of the present application. In addition, the electronic device includes various terminal devices and electronic devices. For example, the terminal device includes but is not limited to smart phones, smart TVs, smart TV set-top boxes, smart watches, personal computers (personal computers, PCs), wearable devices, smart broadband and other devices. Electronic devices include but are not limited to wireless networks, fixed networks, servers and other communication equipment, as well as device modules, memories, static random access memories, digital logic circuits and other devices, which are not listed one by one here. It is understandable that the specific implementation of the semiconductor device can be determined according to the actual application scenario and is not limited here.

[0052] The above contents are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate, the semiconductor substrate comprising a channel region and a source region and a drain region located at both sides of the channel region, the source region and the drain region are respectively formed with grooves, and the grooves are filled with a first semiconductor material; A first barrier layer, located on the source region and the drain region, and the orthographic projection of the first barrier layer on the semiconductor substrate covers the orthographic projection of the openings of the grooves in the source region and the drain region on the semiconductor substrate, respectively, and the first barrier layer comprises a second semiconductor material doped with first doping ions; A metal silicide layer, covering the side of the first barrier layer on the source region and the drain region facing away from the semiconductor substrate; the lattice structure of the material of the metal silicide layer is different from the lattice structure of the first semiconductor material; A gate stack structure, located on the channel region, the gate stack structure comprising a gate dielectric layer and a gate, the gate dielectric layer being located between the gate and the channel region; The gate spacers are located at two sides of the gate stack structure, and the orthographic projection of the gate spacers on the semiconductor substrate does not overlap with the opening of the groove.

2. The semiconductor device according to claim 1, wherein The second semiconductor material includes Si; The semiconductor device is a P-type transistor, the first doping ions are B ions, or the first doping ions are B ions and C ions.

3. The semiconductor device according to claim 1 or 2, characterized in that The metal silicide layer includes one or more of cobalt silicide, nickel silicide, and titanium silicide; and / or, The semiconductor device is a P-type transistor, and the first semiconductor material includes germanium silicon material.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: It also includes a second barrier layer, which is located between the first barrier layer and the metal silicide layer on the source region and the drain region; the second barrier layer includes a third semiconductor material doped with second doping ions.

5. The semiconductor device according to claim 4, wherein: The second doping ions include C ions.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that: The gate stack structure further includes the metal silicide layer covering a side of the gate facing away from the semiconductor substrate.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that: The cross-sectional area of ​​the groove in the first cross-section gradually increases to a target cross-sectional area in a direction from the bottom of the groove to the opening of the groove, and then gradually decreases from the target cross-sectional area; wherein the first cross-section is parallel to the plane where the opening of the groove is located, and the first cross-section is located between the opening and the bottom of the groove.

8. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in any one of claims 1 to 7, wherein the semiconductor device is arranged on the circuit board.

9. A method for preparing a semiconductor device, characterized in that: include: A gate stack structure and gate sidewalls located on both sides of the gate stack structure are formed on the channel region of the semiconductor substrate, wherein the gate stack structure includes a gate dielectric layer and a gate, the gate dielectric layer is located between the gate and the channel region, and the orthographic projection of the gate sidewalls on the semiconductor substrate does not overlap with the opening of the groove; Etching the source region and the drain region in the semiconductor substrate to form grooves respectively; epitaxially growing a first semiconductor material in the groove; Ion doping is performed in the source region and the drain region of the semiconductor substrate, and a first barrier layer and a metal silicide are formed on the source region and the drain region, the first barrier layer covers the orthographic projection of the semiconductor substrate of the openings of the grooves in the source region and the drain region respectively, the first barrier layer includes a second semiconductor material doped with first doping ions, and the metal silicide layer covers the side of the first barrier layer on the source region and the drain region facing away from the semiconductor substrate.

10. The preparation method according to claim 9, characterized in that: The step of performing ion doping in the source region and the drain region of the semiconductor substrate and forming a first barrier layer and a metal silicide on the source region and the drain region comprises: A silicon capping layer doped with B ions is epitaxially formed on the source region and the drain region, wherein the orthographic projection of the silicon capping layer on the semiconductor substrate respectively covers the orthographic projection of the opening of the groove in the source region and the drain region on the semiconductor substrate; wherein the doping concentration of B ions in the silicon capping layer is 8e 20 ions per cubic centimeter to 8e 21 ions per cubic centimeter; B ion doping is performed in the source region, the drain region and the silicon cover layer of the semiconductor substrate; wherein the doping concentration of B ions in the silicon cover layer is 1e 21 ions per cubic centimeter to 8e 21 ions per cubic centimeter; Performing a pre-amorphization treatment on at least one side of the silicon cover layer facing away from the semiconductor substrate using rare gas ions, so that an amorphous silicon layer is formed on the side of the silicon cover layer facing away from the semiconductor substrate; The self-aligned silicide process is used to form a metal silicide layer from the amorphous silicon layer.

11. The preparation method according to claim 10, characterized in that: After performing a pre-amorphization treatment on at least one side of the silicon cover layer facing away from the semiconductor substrate by using rare gas ions to form an amorphous silicon layer on the side of the silicon cover layer facing away from the semiconductor substrate, the method further includes: implanting C ions into the amorphous silicon layer; The method of using the self-aligned silicide process to form a metal silicide layer from an amorphous silicon layer includes: using the self-aligned silicide process to form a metal silicide from an amorphous silicon layer, and forming a second barrier layer between the metal silicide and the first barrier layer.

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