Separation gate super-junction IGBT device and preparation method thereof
By designing a separation gate superjunction structure in the SJ-I GBT device, including setting a deep trench and separation gate above the N column, and setting a P-base area, N-base area and P+ area above the P column, the problem of high loss during hole outflow and shutdown during conduction is solved, and the effect of reducing the on-voltage drop, shutdown loss and switching losses is achieved.
Patent Information
- Application Number
- CN202510154774.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-12
- Publication Date
- 2025-05-02
AI Technical Summary
When the existing SJ-I GBT devices are turned on, holes are easily flowed through the P column to the emitter, resulting in insufficient hole storage, weakening of the conduction modulation effect, and increasing the conduction voltage drop; when turned off, the depletion of the PN junction accelerates the depletion of the carrier, but the conduction efficiency is low and the shutdown loss increases.
A separation gate super junction IGBT device is designed, by setting two deep trenches above the N-pillar, setting up a separation gate of the upper and lower structures in the deep trenches, and setting the P-base area, the N-base area and the P+ area in turn between the two deep trenches directly above the P-pillar.
When conducting, the P-base region acts as a hole barrier to block hole outflow, enhancing the conductivity modulation effect and reducing the conduction voltage drop; when shutting down, the additional hole extraction channel accelerates the current shutdown and reduces the shutdown loss. At the same time, the separation gate structure reduces Miller capacitance, reduces switching losses, and eliminates a layer of dielectric layer and tungsten plugs, enlarges the process window.
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Figure CN119922958A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor devices, and in particular relates to a split-gate superjunction IGBT device and a preparation method thereof. Background Art
[0002] Compared with traditional silicon-based IGBT devices, SJ-IGBT introduces alternating N and P columns in the drift region, and uses the lateral depletion of N and P columns to improve the electric field distribution, so as to have higher withstand voltage and higher current density under the same drift region length. When the device is turned off, the depletion of the PN junction between the N column and the P column will accelerate the extraction of carriers, thereby reducing the turn-off loss, but when it is turned on, holes can easily flow to the emitter through the P column and the P well region, resulting in insufficient hole storage, weakened conductivity modulation effect, and increased on-state voltage drop. Summary of the invention
[0003] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a split-gate super junction IGBT device and a method for preparing the same.
[0004] In order to solve the above technical problems, the present invention provides the following technical solutions:
[0005] A split-gate superjunction IGBT device comprises a first P+ layer and an epitaxial layer arranged on the first P+ layer, wherein a P-type base region is formed on the upper part of the epitaxial layer by injection, and P columns and N columns are periodically arranged along a first direction below the P-type base region, and the upper ends of the P columns and the N columns are both connected to the P-type base region, and the doping concentration of the P-type base region is greater than the doping concentration of the P columns; a split gate structure is arranged above the N column, and an N-type base region and a second P+ region are sequentially injected on the P-type base region between two adjacent split gate structures; a back metal is arranged at the lower end of the first P+ layer, and an emitter metal is arranged at the upper ends of the split gate structure and the second P+ region.
[0006] Furthermore, the separation gate structure includes two deep trenches, a separation gate arranged in the deep trenches, and an N+ region and a third P+ region periodically arranged between the two deep trenches along a second direction perpendicular to the first direction; the deep trench penetrates downward through the P-type base region and extends into the N column.
[0007] Furthermore, the separation gate includes a gate oxide layer covering the trench wall of the deep trench, a gate arranged at the bottom of the deep trench, a cathode arranged at the top of the deep trench, and a gate dielectric layer arranged between the gate and the cathode.
[0008] Furthermore, the depth of the third P+ region is the same as the depth of the second P+ region.
[0009] Furthermore, the lower end surface of the N+ region is lower than the upper end surface of the gate.
[0010] Furthermore, the upper ends of the second P+ region, the third P+ region, the N+ region and the cathode are directly connected to the emitter metal.
[0011] A method for preparing a split-gate superjunction IGBT device comprises the following steps:
[0012] S100, providing an N-type doped silicon substrate;
[0013] S200, epitaxially growing N-type doped silicon on the silicon substrate to form an epitaxial layer, and forming a plurality of P columns periodically arranged along a first direction in the epitaxial layer by implantation, and forming N columns in the epitaxial layer between adjacent P columns;
[0014] S300, implanting a P-type base region at the upper part of the epitaxial layer, and opening two deep trenches above the N-pillars that penetrate downward through the P-type base region and extend into the N-pillars;
[0015] S400, between the two deep trenches above the same N column, an N+ region and a third P+ region periodically arranged along the second direction are formed at the upper end of the P-type base region by implantation; between two adjacent deep trenches located above two adjacent N columns, an N-type base region and a second P+ region are formed at the upper end of the P-type base region by implantation;
[0016] S500, forming a separation gate in the deep trench;
[0017] S600, fabricating an emitter metal on the upper end of the epitaxial layer; forming a first P+ layer on the silicon substrate by implantation; and fabricating a back metal on the lower end of the first P+ layer.
[0018] Furthermore, in the step S200, an epitaxial layer is formed by epitaxially growing multiple layers of N-type doped silicon, and in the region of the P column, a P column is implanted once for each epitaxial layer of N-type doped silicon, thereby forming a P column segment.
[0019] Furthermore, the step S400 includes the following sub-steps:
[0020] S410, forming an N-type base region on the upper part of the P-type base region between two adjacent deep trenches located above two adjacent N pillars by N-type implantation, forming an N+ region periodically arranged along the second direction on the upper part of the P-type base region between the two deep trenches above the same N pillar, and exposing the upper surface of the N+ region;
[0021] S420, forming a second P+ region on the upper portion of the N-type base region by P-type implantation, forming a third P+ region on the upper portion of the P-type base region between adjacent N+ regions, and exposing upper surfaces of the second P+ region and the third P+ region.
[0022] Furthermore, the step S500 includes the following sub-steps:
[0023] S510, etching the first polysilicon in the deep trench, and retaining the first polysilicon at the bottom of the deep trench to form a gate;
[0024] S520, depositing a layer of oxide on the upper end of the gate to form a gate dielectric layer;
[0025] S530, forming a cathode by growing a second polysilicon on the upper portion of the deep trench and etching back.
[0026] In the present invention, by setting two deep trenches above the N column, setting a separation gate of an upper and lower structure in the deep trench, and sequentially setting a P-base region, an N-base region, and a P+ region between the two deep trenches directly above the P column, it is possible to block the outflow of holes when the device is turned on, enhance the conductivity modulation effect, and reduce the on-state voltage drop; when the device is turned off, an additional hole extraction channel is formed to accelerate the current shutoff and further reduce the shutoff loss. It can also reduce the Miller capacitance and the switching loss; and it can save a layer of dielectric layer and tungsten plugs, and increase the process window, which has the potential to produce smaller products. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0028] Figure 1 FIG. 1 is a schematic structural diagram of an embodiment of a split-gate superjunction IGBT device according to the present invention.
[0029] Figure 2 for Figure 1 Schematic diagram of the structure after removing the emitter metal.
[0030] Figure 3 for Figure 2 Schematic diagram of the AA' section.
[0031] Figure 4 for Figure 2 Schematic diagram of the BB' section.
[0032] Figure 5 for Figure 2 Schematic diagram of the CC' section.
[0033] Figure 6 for Figure 2 DD' section diagram.
[0034] Figure 7 The flowchart is a method for manufacturing a split-gate super junction IGBT device according to an embodiment of the present invention.
[0035] Figure 8 It is a cross-sectional schematic diagram of epitaxial N-type doped silicon and implantation to form a P column segment.
[0036] Fig. 9 It is a cross-sectional schematic diagram after forming a deep trench and filling the first polysilicon.
[0037] Fig.10 It is a cross-sectional schematic diagram after forming the N+ region, the third P+ region, the N-type base region and the second P+ region.
[0038] Fig.11 This is a cross-sectional diagram after the emitter metal and back metal are made.
[0039] The accompanying drawings in the specification are as follows:
[0040] Silicon substrate-100; first P+ layer-110; epitaxial layer-200; N column-210; P column-220; P column segment-221; P type base region-230; N type base region-240; second P+ region-250; N+ region-260; third P+ region-270; separated gate-300; deep trench-310; gate oxide layer-320; gate-330; first polysilicon-331; gate dielectric layer-340; cathode-350; emitter metal-400; back metal-500. DETAILED DESCRIPTION
[0041] The following describes the implementation methods of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other without conflict.
[0042] The traditional SJ-I GBT structure uses alternating N-columns and P-columns. The P-columns are usually connected to the P_base region, and the lateral depletion of the N-columns and P-columns is used to improve the electric field distribution. Its advantages are: it has a higher withstand voltage and a higher current density under the same drift region length. The depletion of the PN junction between the N-column and the P-column of the superjunction structure accelerates the extraction of carriers and the turn-off speed is faster. The limitations are: the P-column region provides a hole extraction channel directly connected to the P_base, which affects the conductivity modulation level of the traditional superjunction I GBT under forward conduction, making the SJ-I GBT show a larger Vcesat, and the Miller capacitance of the traditional SJ-I GBT is larger. Therefore, the traditional SJ-I GBT structure needs to reduce Vcesat and switching losses.
[0043] Some devices in the prior art use a floating P-column SJ-I GBT structure, using alternating N-columns and P-columns, and using the lateral depletion of the N-columns and P-columns to improve the electric field distribution, but the P-columns are no longer connected to the P_base region. Its advantages are: since the P-columns no longer extract holes, the injected carriers increase and Vcesat decreases. The limitations are: holes can only be extracted from the P-base region, the extraction efficiency is reduced, resulting in a longer turn-off time and increased turn-off loss; there is a large Miller capacitance and a large switching loss; when developing to a smaller size, the process window is smaller.
[0044] To solve the above problems, the present invention proposes a split-gate superjunction IGBT device. Figure 1 , Figure 1 Schematic diagram of the structure of an embodiment of a split-gate superjunction IGBT device of the present invention. The split-gate superjunction IGBT device of this embodiment includes a first P+ layer 110 and an epitaxial layer 200 disposed on the first P+ layer 110, and a P-type base region 230 (i.e., a P-base region) is formed on the upper portion of the epitaxial layer 200 by implantation. The lower portion of the P-type base region 230 is along a first direction (i.e., Figure 1 and Figure 2 In the x-axis direction, P columns 220 and N columns 210 are periodically arranged, and the upper ends of the P columns 220 and the N columns 210 are connected to the P-type base region 230, and the doping concentration of the P-type base region 230 is greater than the doping concentration of the P column 220.
[0045] See also Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 A separation gate structure is disposed above the N column 210, and the separation gate structure includes two deep trenches 310, a separation gate 300 disposed in the deep trenches 310, and a separation gate 300 disposed in the deep trenches 310, and a separation gate 300 disposed in the deep trenches 310 along a second direction perpendicular to the first direction (i.e., Figure 1 and Figure 2 The N+ region 260 and the third P+ region 270 are periodically arranged at intervals (in the y-axis direction in FIG. 1 ). The lower end surface of the N+ region 260 is lower than the upper end surface of the gate 330, and the depth of the third P+ region 270 can be the same as the depth of the second P+ region 250. The deep trench 310 penetrates downward through the P-type base region 230 and extends into the N column 210. The separation gate 300 includes a gate oxide layer 320 covering the groove wall of the deep trench 310, a gate 330 arranged at the bottom of the deep trench 310, a cathode 350 arranged at the top of the deep trench 310, and a gate dielectric layer 340 arranged between the gate 330 and the cathode 350, and the gate 330 and the cathode 350 are both formed of polysilicon.
[0046] Between two adjacent separation gate structures (i.e., between two adjacent deep trenches 310 of different separation gate structures), an N-type base region 240 (i.e., N-base region) and a second P+ region 250 are sequentially implanted on the P-type base region 230. Figure 1 A back metal 500 is provided at the lower end of the first P+ layer 110, an emitter metal 400 is provided at the upper end of the separated gate structure and the second P+ region 250, and the upper ends of the second P+ region 250, the third P+ region 270, the N+ region 260 and the cathode 350 are directly connected to the emitter metal 400.
[0047] In this embodiment, the P column 220 and the N column 210 are alternately arranged to form an SJ structure, and two deep trenches 310 are arranged above the N column 210, and a separation gate 300 of an upper and lower structure is arranged in the deep trench 310, wherein the lower part is connected to the gate and the upper part is connected to the emitter, and a P-base region, an N+ region 260 and a third P+ region 270 are arranged between the two deep trenches 310, and a P-base region, an N-base region and a second P+ region 250 are arranged directly above the P column 220. The above structure has the following beneficial effects:
[0048] 1. It can reduce the on-state voltage drop and turn-off loss. When the device is turned on, the dense N-base region directly above the P column 220 acts as a hole barrier to block the outflow of holes, enhance the conductivity modulation effect, and reduce the on-state voltage drop Vcesat; when turned off, since the upper part of the separation gate 300 is connected to the emitter, as the collector voltage increases, the PMOS composed of the P-base, N-base and P+ above the P column 220 will be turned on, forming an additional hole extraction channel, accelerating the current shutdown, and further reducing the turn-off loss.
[0049] 2. It can reduce Miller capacitance and switching loss. The split gate structure reduces the area of the gate 330, and the upper part of the split gate 300 is connected to the emitter, converting part of the gate-collector capacitance Cgc into the gate-emitter capacitance Cge, so the Miller capacitance Cgc is reduced, and the switching loss is also reduced.
[0050] 3. Since the upper ends of the second P+ region 250, the third P+ region 270, the N+ region 260 and the cathode 350 are directly connected to the emitter metal 400, a dielectric layer and a tungsten plug can be omitted.
[0051] See also Figure 7 , Figure 7 1 is a schematic diagram of a method for preparing a split-gate super junction IGBT device according to an embodiment of the present invention. The method for preparing a split-gate super junction IGBT device according to this embodiment comprises the following steps:
[0052] S100 , providing an N-type doped silicon substrate 100 .
[0053] S200, epitaxially grow N-type doped silicon on the silicon substrate 100 to form an epitaxial layer 200, and form a plurality of P columns 220 periodically arranged along a first direction in the epitaxial layer 200 by implantation, and form N columns 210 in the epitaxial layer 200 between adjacent P columns 220. Figure 8 In this embodiment, the epitaxial layer 200 is formed by epitaxially growing multiple layers of N-type doped silicon. In the region of the P column 220, the P column 220 is implanted once each time a layer of N-type doped silicon is epitaxially grown, thereby forming a P column segment 221. Through multiple epitaxy and multiple implantation, multiple P column segments 221 are connected to form a P column 220.
[0054] S300, see Fig. 9 A P-type base region 230 is implanted in the upper part of the epitaxial layer 200, and two deep trenches 310 are opened above the N column 210, penetrating downward through the P-type base region 230 and extending into the N column 210. A layer of oxide is deposited on the wall of the deep trench 310 to form a gate oxide layer 320, and then the first polysilicon 331 is filled in the deep trench 310.
[0055] S400, see Fig.10 , between the two deep trenches 310 above the same N column 210, an N+ region 260 and a third P+ region 270 arranged periodically along the second direction are formed by implantation at the upper end of the P-type base region 230; between two adjacent deep trenches 310 located above two adjacent N columns 210, an N-type base region 240 and a second P+ region 250 are formed by implantation at the upper end of the P-type base region 230. This step may include the following sub-steps:
[0056] S410, forming an N-type base region 240 on the upper part of the P-type base region 230 between two adjacent deep trenches 310 located above two adjacent N columns 210 through N-type implantation, and forming an N+ region 260 periodically arranged along the second direction on the upper part of the P-type base region 230 between the two deep trenches 310 above the same N column 210, and exposing the upper surface of the N+ region 260.
[0057] S420 , forming a second P+ region 250 on the N-type base region 240 by P-type implantation, forming a third P+ region 270 on the P-type base region 230 between adjacent N+ regions 260 , and exposing the upper surfaces of the second P+ region 250 and the third P+ region 270 .
[0058] S500, please refer to Fig.11 , forming a separation gate 300 in the deep trench 310; specifically, the process may include the following sub-steps:
[0059] S510 , etching the first polysilicon 331 in the deep trench 310 to retain the first polysilicon 331 at the bottom of the deep trench 310 , thereby forming a gate 330 .
[0060] S520 , depositing a layer of oxide on the upper end of the gate 330 to form a gate dielectric layer 340 .
[0061] S530 , forming a cathode 350 by growing a second polysilicon on the upper portion of the deep trench 310 and etching back.
[0062] S600, please continue to read Fig.11 , an emitter metal 400 is formed on the upper end of the epitaxial layer 200, a first P+ layer 110 is formed on the silicon substrate 100 by injection, and a back metal 500 is formed on the lower end of the first P+ layer 110. Since the upper surfaces of the N+ region 260, the second P+ region 250, the third P+ region 270 and the cathode 350 are all exposed on the surface of the wafer, the emitter can be formed by a self-aligned contact hole process, thereby saving a layer of dielectric layer and tungsten plugs, and increasing the process window. This process has the potential to produce products with smaller pitch sizes (minimum repeating unit size, i.e., the size of one N column 210 + one P column 220) (at small sizes, the process window of the process related to the active area contact hole connected to the P-base region in the traditional structure is narrow). Of course, the structure of this embodiment can still choose to grow a dielectric layer on the wafer, etch contact holes on the dielectric layer, and form tungsten plugs in the contact holes, so that the emitter metal 400 is connected to the N+ region 260, the second P+ region 250, the third P+ region 270 and the cathode 350 through the tungsten plugs.
[0063] The super junction IGBT device manufactured by the method of this embodiment can reduce the on-state voltage drop and turn-off loss, and can also reduce the Miller capacitance and switch loss. In addition, a dielectric layer and a tungsten plug can be omitted, and the process window can be increased, which has the potential to produce smaller products.
[0064] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.
Claims
1. A split-gate superjunction IGBT device, characterized in that: It includes a first P+ layer and an epitaxial layer arranged on the first P+ layer, wherein a P-type base region is formed on the upper part of the epitaxial layer by injection, and P columns and N columns are periodically arranged along a first direction below the P-type base region, and the upper ends of the P columns and the N columns are connected to the P-type base region, and the doping concentration of the P-type base region is greater than the doping concentration of the P columns; a separation gate structure is arranged above the N column, and an N-type base region and a second P+ region are sequentially injected on the P-type base region between two adjacent separation gate structures; a back metal is arranged at the lower end of the first P+ layer, and an emitter metal is arranged at the upper ends of the separation gate structure and the second P+ region.
2. The split-gate super junction IGBT device according to claim 1, characterized in that: The separation gate structure includes two deep trenches, a separation gate arranged in the deep trenches, and an N+ region and a third P+ region periodically arranged between the two deep trenches along a second direction perpendicular to the first direction; the deep trench penetrates downward through the P-type base region and extends into the N column.
3. The split-gate super junction IGBT device according to claim 2, characterized in that: The separation gate comprises a gate oxide layer covering the groove wall of the deep groove, a gate arranged at the lower part of the deep groove, a cathode arranged at the upper part of the deep groove, and a gate dielectric layer arranged between the gate and the cathode.
4. The split-gate super junction IGBT device according to claim 3, characterized in that: The depth of the third P+ region is the same as that of the second P+ region.
5. The split-gate super junction IGBT device according to claim 4, characterized in that: The lower end surface of the N+ region is lower than the upper end surface of the gate.
6. The split-gate super junction IGBT device according to claim 3, characterized in that: The upper ends of the second P+ region, the third P+ region, the N+ region and the cathode are directly connected to the emitter metal.
7. A method for preparing a split-gate super junction IGBT device, characterized in that: The following steps are involved: S100, providing an N-type doped silicon substrate; S200, epitaxially growing N-type doped silicon on the silicon substrate to form an epitaxial layer, and forming a plurality of P columns periodically arranged along a first direction in the epitaxial layer by implantation, and forming N columns in the epitaxial layer between adjacent P columns; S300, implanting a P-type base region at the upper part of the epitaxial layer, and opening two deep trenches above the N-pillars that penetrate downward through the P-type base region and extend into the N-pillars; S400, between the two deep trenches above the same N column, an N+ region and a third P+ region periodically arranged along the second direction are formed at the upper end of the P-type base region by implantation; between two adjacent deep trenches located above two adjacent N columns, an N-type base region and a second P+ region are formed at the upper end of the P-type base region by implantation; S500, forming a separation gate in the deep trench; S600, fabricating an emitter metal on the upper end of the epitaxial layer; forming a first P+ layer on the silicon substrate by implantation; and fabricating a back metal on the lower end of the first P+ layer.
8. The method for preparing a split-gate super junction IGBT device according to claim 7, characterized in that: In the step S200, an epitaxial layer is formed by epitaxially growing multiple layers of N-type doped silicon. In the region of the P column, a P column is implanted once for each epitaxial layer of N-type doped silicon, thereby forming a P column segment.
9. The method for preparing a split-gate super junction IGBT device according to claim 7, characterized in that: The step S400 includes the following sub-steps: S410, forming an N-type base region on the upper part of the P-type base region between two adjacent deep trenches located above two adjacent N pillars by N-type implantation, forming an N+ region periodically arranged along the second direction on the upper part of the P-type base region between the two deep trenches above the same N pillar, and exposing the upper surface of the N+ region; S420, forming a second P+ region on the upper portion of the N-type base region by P-type implantation, forming a third P+ region on the upper portion of the P-type base region between adjacent N+ regions, and exposing upper surfaces of the second P+ region and the third P+ region.
10. The method for preparing a split-gate super junction IGBT device according to claim 7, characterized in that: The step S500 includes the following sub-steps: S510, etching the first polysilicon in the deep trench, and retaining the first polysilicon at the bottom of the deep trench to form a gate; S520, depositing a layer of oxide on the upper end of the gate to form a gate dielectric layer; S530, forming a cathode by growing a second polysilicon on the upper portion of the deep trench and etching back.