Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate; the first passivation layer is formed on the substrate; the grid electrode is formed in the first passivation layer, and the grid electrode penetrates through the first passivation layer; the source electrode and the drain electrode are formed in the portions, on the two sides of the grid electrode, of the first passivation layer, the source electrode and the drain electrode penetrate through the first passivation layer, and at least one groove is formed in the portion, between the grid electrode and the drain electrode, of the first passivation layer; and the first field plate is formed on the first passivation layer, and the at least one groove is filled with the first field plate. According to the technical scheme, the breakdown voltage of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In the existing GaN HEMT (High Electron Mobility Transistor) field plate technology, due to the electric field concentration at the edge of the field plate, the edge is the breakdown point, which limits the further increase of the breakdown voltage and the field plate fails to effectively play the role of balancing the electric field.

[0003] Therefore, how to improve the breakdown voltage of the device is an urgent problem to be solved. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so that the breakdown voltage of the device is improved.

[0005] To achieve the above object, the present invention provides a semiconductor device, comprising:

[0006] substrate;

[0007] A first passivation layer formed on the substrate;

[0008] A gate is formed in the first passivation layer, and the gate penetrates the first passivation layer;

[0009] A source electrode and a drain electrode are formed in the first passivation layer on both sides of the gate electrode, the source electrode and the drain electrode penetrate the first passivation layer, and at least one groove is formed in the first passivation layer between the gate electrode and the drain electrode;

[0010] A first field plate is formed on the first passivation layer, and the first field plate fills the at least one groove.

[0011] Optionally, the base includes, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer.

[0012] Optionally, the nucleation layer, the buffer layer, the channel layer and the barrier layer are retracted relative to the substrate to form steps.

[0013] Optionally, the first field plate is electrically connected to the gate or the source, or the first field plate is not electrically connected to the gate and the source.

[0014] Optionally, the semiconductor device further includes:

[0015] an interlayer dielectric layer, formed on the first passivation layer, and the interlayer dielectric layer covers the gate, the source, the drain and the first field plate;

[0016] A metal interconnect structure is formed in the interlayer dielectric layer on the gate, the source and the drain, respectively, and the metal interconnect structure also extends onto the interlayer dielectric layer;

[0017] A second passivation layer is formed on the interlayer dielectric layer, and the second passivation layer also extends to a portion of the surface of the metal interconnection structure.

[0018] Optionally, the semiconductor device further includes:

[0019] A second field plate is formed in the interlayer dielectric layer above the first field plate.

[0020] The present invention also provides a method for manufacturing a semiconductor device, comprising:

[0021] providing a substrate;

[0022] A first passivation layer, a gate, a source, a drain and a first field plate are formed, wherein the first passivation layer is formed on the substrate, the gate is formed in the first passivation layer, the source and the drain are formed in the first passivation layer on both sides of the gate, the gate, the source and the drain all penetrate the first passivation layer, at least one groove is formed in the first passivation layer between the gate and the drain, the first field plate is formed on the first passivation layer, and the first field plate fills the at least one groove.

[0023] Optionally, the base includes, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer.

[0024] Optionally, the nucleation layer, the buffer layer, the channel layer and the barrier layer are retracted relative to the substrate to form steps.

[0025] Optionally, the first field plate is electrically connected to the gate or the source, or the first field plate is not electrically connected to the gate and the source.

[0026] Optionally, the method for manufacturing the semiconductor device further includes:

[0027] An interlayer dielectric layer and a metal interconnection structure are formed, wherein the interlayer dielectric layer is formed on the first passivation layer, and the interlayer dielectric layer covers the gate, the source, the drain and the first field plate; the metal interconnection structure is formed in the interlayer dielectric layer on the gate, the source and the drain, respectively, and the metal interconnection structure also extends onto the interlayer dielectric layer;

[0028] A second passivation layer is formed on the interlayer dielectric layer, and the second passivation layer also extends to a portion of the surface of the metal interconnection structure.

[0029] Optionally, before forming the second passivation layer on the interlayer dielectric layer, the method for manufacturing the semiconductor device further includes:

[0030] A second field plate is formed in the interlayer dielectric layer above the first field plate.

[0031] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0032] 1. The semiconductor device of the present invention comprises: a substrate; a first passivation layer formed on the substrate; a gate formed in the first passivation layer, the gate penetrating the first passivation layer; a source and a drain formed in the first passivation layer on both sides of the gate, the source and the drain penetrating the first passivation layer, at least one groove formed in the first passivation layer between the gate and the drain; a first field plate formed on the first passivation layer, and the first field plate filling the at least one groove. The breakdown voltage of the device is improved.

[0033] 2. The manufacturing method of the semiconductor device of the present invention comprises: providing a substrate; forming a first passivation layer, a gate, a source, a drain and a first field plate, wherein the first passivation layer is formed on the substrate, the gate is formed in the first passivation layer, the source and the drain are formed in the first passivation layer on both sides of the gate, the gate, the source and the drain all penetrate the first passivation layer, at least one groove is formed in the first passivation layer between the gate and the drain, the first field plate is formed on the first passivation layer, and the first field plate fills the at least one groove. The breakdown voltage of the device is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a schematic structural diagram of a semiconductor device according to a first embodiment of the present invention;

[0035] Figure 2 is a schematic structural diagram of a semiconductor device according to a second embodiment of the present invention;

[0036] Figure 3 is a schematic structural diagram of a semiconductor device according to a third embodiment of the present invention;

[0037] Figure 4 is a schematic structural diagram of a semiconductor device according to a fourth embodiment of the present invention;

[0038] Figure 5 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0039] Figure 6a to Figure 6i yes Figure 5 FIG. 1 is a schematic diagram of a device in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0040] Among them, Figure 1 to Figure 6i The reference numerals are described as follows:

[0041] 101-substrate; 102-nucleation layer; 103-buffer layer; 104-channel layer; 105-barrier layer; 106-groove; 11-first passivation layer; 121-first gate; 1211-first gate material layer; 1212-patterned photoresist layer; 122-second gate; 13-source; 131-first opening; 14-drain; 141-second opening; 15-first field plate; 151-groove; 16-interlayer dielectric layer; 171-via plug; 172-metal interconnect; 173-pad; 18-second passivation layer; 19-second field plate. DETAILED DESCRIPTION

[0042] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0043] An embodiment of the present invention provides a semiconductor device, comprising: a substrate; a first passivation layer formed on the substrate; a gate formed in the first passivation layer, the gate penetrating the first passivation layer; a source and a drain formed in the first passivation layer on both sides of the gate, the source and the drain penetrating the first passivation layer, and at least one groove is formed in the first passivation layer between the gate and the drain; a first field plate formed on the first passivation layer, and the first field plate fills the at least one groove.

[0044] See below Figure 1 to Figure 4 Describe in detail the semiconductor device provided by this embodiment, Figure 1 to Figure 4 A schematic diagram of the longitudinal section of the device.

[0045] In one embodiment, the base may include, from bottom to top, a substrate 101 , a nucleation layer 102 , a buffer layer 103 , a channel layer 104 , and a barrier layer 105 .

[0046] The substrate 101 may be made of semiconductor materials such as silicon carbide, silicon, germanium or sapphire.

[0047] The material of the channel layer 104 may be at least one of GaN, AlGaN, InGaN and the like, and the material of the barrier layer 105 may be at least one of AlGaN, InAlGaN, AlScN, InScN and the like.

[0048] The channel layer 104 and the barrier layer 105 may form a heterojunction, thereby forming a two-dimensional electron gas (2DEG).

[0049] The nucleation layer 102 , the buffer layer 103 , the channel layer 104 , and the barrier layer 105 are retracted relative to the substrate 101 to form steps.

[0050] like Figure 1 to Figure 4 As shown, a groove 106 is formed at the edge of the barrier layer 105, the channel layer 104, the buffer layer 103, the nucleation layer 102 and the substrate 101. The groove 106 is annular and serves as an isolation. The sidewall and bottom wall of the groove 106 constitute a step.

[0051] The groove 106 may penetrate the barrier layer 105, the channel layer 104 and the buffer layer 103 and enter the nucleation layer 102, or the groove 106 may penetrate the barrier layer 105, the channel layer 104, the buffer layer 103 and the nucleation layer 102 and enter the substrate 101, that is, the bottom of the step may be located in the nucleation layer 102 or in the substrate 101.

[0052] The first passivation layer 11 is formed on the substrate.

[0053] like Figure 1 to Figure 4 As shown, the first passivation layer 11 is formed on the barrier layer 105 at the periphery of the trench 106 .

[0054] The gate is formed in the first passivation layer 11 , and the gate penetrates the first passivation layer 11 .

[0055] In one embodiment, the gate may include a first gate 121 and a second gate 122 from bottom to top, and the upper surface of the second gate 122 may be higher or lower than the upper surface of the first passivation layer 11, or the upper surface of the second gate 122 may be flush with the upper surface of the first passivation layer 11.

[0056] The source electrode 13 and the drain electrode 14 are formed in the first passivation layer 11 on both sides of the gate electrode. The source electrode 13 and the drain electrode 14 penetrate the first passivation layer 11. At least one groove (i.e., Figure 6f The groove 151 in the embodiment of the present invention.

[0057] The source electrode 13 and the drain electrode 14 are in ohmic contact with the substrate respectively.

[0058] The source electrode 13 may further extend to a portion of the upper surface of the first passivation layer 11 , and the drain electrode 14 may further extend to a portion of the upper surface of the first passivation layer 11 .

[0059] The first field plate 15 is formed on the first passivation layer 11 , and the first field plate 15 fills the at least one groove 151 .

[0060] The first field plate 15 extends from the upper surface of the first passivation layer 11 into the first passivation layer 11 , so that the first field plate 15 is an interdigitated embedded field plate.

[0061] The groove 151 may penetrate the first passivation layer 11 or may not penetrate the first passivation layer 11 , that is, the first field plate 15 may be in contact with the substrate or may not be in contact with the substrate.

[0062] When the number of the grooves 151 is at least two, the grooves 151 may be connected or not connected.

[0063] Preferably, the distance between the at least one groove 151 and the gate is smaller than the distance between the at least one groove 151 and the drain 14 .

[0064] In one embodiment, if Figure 1 , Figure 2 and Figure 3 As shown, the source 13, the drain 14 and the first field plate 15 are made of the same material, and the material of the source 13, the drain 14 and the first field plate 15 and the material of the second gate 122 may be the same or different; or, in another embodiment, as Figure 4 As shown, the source 13 and the drain 14 are made of the same material, the first field plate 15 and the second gate 122 are made of the same material, and the source 13 and the drain 14 may be made of the same material or different from the first field plate 15 and the second gate 122 .

[0065] The material of the first passivation layer 11 may include at least one of insulating materials such as aluminum nitride, aluminum oxide, silicon dioxide and silicon nitride. The material of the first gate 121 may include at least one of p-type doped gallium nitride, nickel oxide, stannous oxide, cuprous oxide, tungsten oxide and boron nitride. The material of the second gate 122 and the first field plate 15 may include at least one of metal (such as titanium, aluminum or tungsten), metal nitride (titanium nitride or tungsten nitride) and metal silicide. The material of the source 13 and the drain 14 may include metal material (such as titanium, aluminum or tungsten).

[0066] The first field plate 15 is electrically connected to the source 13, and the first field plate 15 is not electrically connected to the gate, that is, the first field plate 15 is a common source field plate. Figure 2 and Figure 3 As shown, the portion of the first field plate 15 located on the first passivation layer 11 extends toward the source 13 until it is connected to the source 13; or, the first field plate 15 is electrically connected to the gate, and the first field plate 15 is not electrically connected to the source 13, that is, the first field plate 15 is a common-gate field plate, such as Figure 4 As shown, the portion of the first field plate 15 located on the first passivation layer 11 extends to the upper surface of the second gate 122; or Figure 1 As shown, the first field plate 15 is not electrically connected to the gate and the source 13 , that is, the first field plate 15 is a floating field plate.

[0067] The semiconductor device further comprises:

[0068] An interlayer dielectric layer 16 is formed on the first passivation layer 11, and the interlayer dielectric layer 16 covers the gate, the source 13, the drain 14 and the first field plate 15;

[0069] A metal interconnect structure is formed in the interlayer dielectric layer 16 on the gate, the source 13 and the drain 14, respectively, and the metal interconnect structure also extends onto the interlayer dielectric layer 16;

[0070] The second passivation layer 18 is formed on the interlayer dielectric layer 16 , and the second passivation layer 18 also extends to a portion of the surface of the metal interconnection structure.

[0071] The metal interconnection structures on the gate, the source 13 and the drain 14 are not electrically connected. The metal interconnection structure may include a through-hole plug 171, a metal interconnection line 172 and a pad 173, wherein the through-hole plug 171 and the metal interconnection line 172 are located in the interlayer dielectric layer 16, the pad 173 is located on the upper surface of the interlayer dielectric layer 16, and the second passivation layer 18 extends to a portion of the surface of the pad 173; the metal interconnection lines 172 of adjacent layers and the metal interconnection lines 172 on the top layer and the pad 173 are electrically connected through the through-hole plug 171, and the metal interconnection lines 172 on the bottom layer and the gate, the source 13 and the drain 14 are all electrically connected through the through-hole plug 171.

[0072] The second passivation layer 18 may be made of polyimide or polyamide.

[0073] like Figure 3As shown, preferably, the semiconductor device further includes: a second field plate 19 formed in the interlayer dielectric layer 16 above the first field plate 15 .

[0074] The second field plate 19 may be at least one layer.

[0075] The second field plate 19 may be a planar field plate parallel to the upper surface of the substrate; or Figure 3 As shown, the second field plate 19 may include a planar field plate and a portion extending from a portion of the lower surface of the planar field plate toward the first field plate 15 , that is, the second field plate 19 may be an interdigitated embedded field plate.

[0076] The second field plate 19 can be electrically connected to the metal interconnection structure on the source 13, and the second field plate 19 is not electrically connected to the metal interconnection structure on the gate, that is, the second field plate 19 is a common source field plate. Figure 3 As shown, the second field plate 19 extends toward the metal interconnect structure on the source 13 until it is connected to the metal interconnect line 172 on the source 13; or, the second field plate 19 is electrically connected to the metal interconnect structure on the gate, and the second field plate 19 is not electrically connected to the metal interconnect structure on the source 13, that is, the second field plate 19 is a common-gate field plate; or, the second field plate 19 is not electrically connected to the metal interconnect structures on the gate and the source 13, that is, the second field plate 19 is a floating field plate.

[0077] The material of the second field plate 19 may include at least one of metal (such as titanium, aluminum or tungsten), metal nitride (titanium nitride or tungsten nitride) and metal silicide.

[0078] In the existing HEMT (High Electron Mobility Transistor) device, the field plate is only located on the upper surface of the passivation layer, resulting in electric field concentration between the gate and the drain (including the edge of the field plate close to the gate and other parts of the area between the gate and the drain); in the present invention, since the first field plate 15 is not only formed on the first passivation layer 11, but also formed in the at least one groove 151 in the first passivation layer 11 between the gate and the drain 14, the strong electric field area between the gate and the drain 14 is dispersed, and the electric field is widened in the direction of the groove 151, that is, the first field plate 15 can effectively balance the electric field distribution between the gate and the drain 14 (especially the electric field distribution close to the gate), thereby making the electric field distribution between the gate and the drain 14 more uniform, and the electric field concentration phenomenon is improved, thereby achieving an increase in breakdown voltage and improving dynamic resistance characteristics, thereby improving device performance and reliability.

[0079] In summary, the present invention provides a semiconductor device, comprising: a substrate; a first passivation layer formed on the substrate; a gate formed in the first passivation layer, the gate penetrating the first passivation layer; a source and a drain formed in the first passivation layer on both sides of the gate, the source and the drain penetrating the first passivation layer, at least one groove formed in the first passivation layer between the gate and the drain; a first field plate formed on the first passivation layer, and the first field plate filling the at least one groove. The semiconductor device provided by the present invention improves the breakdown voltage of the device.

[0080] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 5 ,from Figure 5 It can be seen that the method for manufacturing the semiconductor device includes:

[0081] Step S1, providing a substrate;

[0082] Step S2, forming a first passivation layer, a gate, a source, a drain and a first field plate, wherein the first passivation layer is formed on the substrate, the gate is formed in the first passivation layer, the source and the drain are formed in the first passivation layer on both sides of the gate, the gate, the source and the drain all penetrate the first passivation layer, at least one groove is formed in the first passivation layer between the gate and the drain, the first field plate is formed on the first passivation layer, and the first field plate fills the at least one groove.

[0083] See below Figure 2 to Figure 4 , Figure 6a to Figure 6i The method for manufacturing the semiconductor device provided in this embodiment is described in detail. Figure 2 to Figure 4 , Figure 6a to Figure 6i A schematic diagram of the longitudinal section of the device.

[0084] Follow step S1, refer to Figure 6a , providing a substrate.

[0085] In one embodiment, the base may include, from bottom to top, a substrate 101 , a nucleation layer 102 , a buffer layer 103 , a channel layer 104 , and a barrier layer 105 .

[0086] The substrate 101 may be made of semiconductor materials such as silicon carbide, silicon, germanium or sapphire.

[0087] The material of the channel layer 104 may be at least one of GaN, AlGaN, InGaN and the like, and the material of the barrier layer 105 may be at least one of AlGaN, InAlGaN, AlScN, InScN and the like.

[0088] The channel layer 104 and the barrier layer 105 may form a heterojunction, thereby forming a two-dimensional electron gas (2DEG).

[0089] According to step S2, a first passivation layer 11, a gate, a source 13, a drain 14 and a first field plate 15 are formed, wherein the first passivation layer 11 is formed on the substrate, the gate is formed in the first passivation layer 11, the source 13 and the drain 14 are formed in the first passivation layer 11 on both sides of the gate, the gate, the source 13 and the drain 14 all penetrate the first passivation layer 11, at least one groove 151 is formed in the first passivation layer 11 between the gate and the drain 14, the first field plate 15 is formed on the first passivation layer 11, and the first field plate 15 fills the at least one groove 151.

[0090] In one embodiment, the gate may include a first gate 121 and a second gate 122 from bottom to top, and the upper surface of the second gate 122 may be higher or lower than the upper surface of the first passivation layer 11, or the upper surface of the second gate 122 may be flush with the upper surface of the first passivation layer 11.

[0091] The source electrode 13 and the drain electrode 14 are in ohmic contact with the substrate respectively.

[0092] The first field plate 15 extends from the upper surface of the first passivation layer 11 into the first passivation layer 11 , so that the first field plate 15 is an interdigitated embedded field plate.

[0093] The groove 151 may penetrate the first passivation layer 11 or may not penetrate the first passivation layer 11 , that is, the first field plate 15 may be in contact with the substrate or may not be in contact with the substrate.

[0094] When the number of the grooves 151 is at least two, the grooves 151 may be connected or not connected.

[0095] Preferably, the distance between the at least one groove 151 and the gate is smaller than the distance between the at least one groove 151 and the drain 14 .

[0096] In one embodiment, the steps of forming the first passivation layer 11, the gate, the source 13, the drain 14 and the first field plate 15 may include: Figure 6a As shown, a first gate material layer 1211 is formed on the substrate; then, as shown Figure 6d As shown, photolithography and etching processes are performed to form the first gate material layer 1211 into a first gate 121, and the first gate 121 is formed on a portion of the upper surface of the substrate; then, as shown Figure 6eAs shown, a first passivation layer 11 is formed on the substrate, and the first passivation layer 11 covers the first gate 121; then, as shown Figure 6e As shown, the first passivation layer 11 on both sides of the first gate 121 is etched to form a first opening 131 and a second opening 141 in the first passivation layer 11 on both sides of the first gate 121, respectively. The first opening 131 and the second opening 141 both penetrate the first passivation layer 11 to expose a portion of the upper surface of the substrate; then, as shown Figure 6f As shown, the first passivation layer 11 between the first gate 121 and the second opening 141 is etched to form at least one groove 151; then, as shown Figure 6g As shown, a metal material is deposited on the first passivation layer 11, and the metal material fills the first opening 131, the second opening 141 and the at least one groove 151, and the metal material is etched to form a source 13, a drain 14 and a first field plate 15, wherein the source 13 extends from the first opening 131 to a portion of the upper surface of the first passivation layer 11, the drain 14 extends from the second opening 141 to a portion of the upper surface of the first passivation layer 11, and the first field plate 15 extends from the at least one groove 151 to a portion of the upper surface of the first passivation layer 11; then, as shown Figure 6h As shown, the first passivation layer 11 above the first gate 121 is etched to form an opening (not shown) exposing at least a portion of the upper surface of the first gate 121 , and a metal material is filled into the opening to form a second gate 122 .

[0097] It should be noted that the steps of forming the first passivation layer 11 , the gate, the source 13 , the drain 14 and the first field plate 15 are not limited to the above embodiments.

[0098] In other embodiments, the first passivation layer 11 may be formed first, and then the first gate 121 and the second gate 122 may be formed.

[0099] In other embodiments, the at least one groove 151 may be formed first, and then the first opening 131 and the second opening 141 may be formed; when the groove 151 penetrates the first passivation layer 11, the at least one groove 151, the first opening 131 and the second opening 141 may be formed by etching at the same time.

[0100] In one embodiment, if Figure 6h , Figure 2 and Figure 3As shown, the source 13, the drain 14 and the first field plate 15 can be formed by the same deposition process and the same etching process, and the second gate 122 is formed by another deposition process and another etching process. At this time, the material of the source 13, the drain 14 and the first field plate 15 is the same, and the material of the source 13, the drain 14 and the first field plate 15 can be the same as or different from the material of the second gate 122; or, in another embodiment, as Figure 4 As shown, the source 13 and the drain 14 are formed by the same deposition process and the same etching process, and the first field plate 15 and the second gate 122 are formed by the same deposition process and the same etching process. At this time, the material of the source 13 and the drain 14 is the same, and the material of the first field plate 15 and the second gate 122 is the same. The material of the source 13 and the drain 14 can be the same as or different from the material of the first field plate 15 and the second gate 122.

[0101] The material of the first passivation layer 11 may include at least one of insulating materials such as aluminum nitride, aluminum oxide, silicon dioxide and silicon nitride. The material of the first gate 121 may include at least one of p-type doped gallium nitride, nickel oxide, stannous oxide, cuprous oxide, tungsten oxide and boron nitride. The material of the second gate 122 and the first field plate 15 may include at least one of metal (such as titanium, aluminum or tungsten), metal nitride (titanium nitride or tungsten nitride) and metal silicide. The material of the source 13 and the drain 14 may include metal material (such as titanium, aluminum or tungsten).

[0102] The first field plate 15 is electrically connected to the source 13, and the first field plate 15 is not electrically connected to the gate, that is, the first field plate 15 is a common source field plate. Figure 2 and Figure 3 As shown, the portion of the first field plate 15 located on the first passivation layer 11 extends toward the source 13 until it is connected to the source 13; or, the first field plate 15 is electrically connected to the gate, and the first field plate 15 is not electrically connected to the source 13, that is, the first field plate 15 is a common-gate field plate, such as Figure 4 As shown, the portion of the first field plate 15 located on the first passivation layer 11 extends to the upper surface of the second gate 122; or Figure 6h As shown, the first field plate 15 is not electrically connected to the gate and the source 13 , that is, the first field plate 15 is a floating field plate.

[0103] like Figure 6c As shown, the nucleation layer 102 , the buffer layer 103 , the channel layer 104 and the barrier layer 105 are retracted relative to the substrate 101 to form steps.

[0104] In one embodiment, the step of forming the step may include: Figure 6b As shown, after forming the first gate material layer 1211 on the substrate, a patterned photoresist layer 1212 is formed on the first gate material layer 1211; then, as shown in Figure 6c As shown, the first gate material layer 1211, the barrier layer 105, the channel layer 104, the buffer layer 103, the nucleation layer 102 and a partial thickness of the substrate 101 are etched using a patterned photoresist layer 1212 as a mask to form a groove 106, wherein the groove 106 is located at the edge of the first gate material layer 1211, the barrier layer 105, the channel layer 104, the buffer layer 103, the nucleation layer 102 and a partial thickness of the substrate 101, and the groove 106 is annular and serves as an isolation layer, and the sidewalls and bottom walls of the groove 106 constitute a step; then, the patterned photoresist layer 1212 is removed.

[0105] In other embodiments, the step may be formed before forming the first gate material layer 1211 , or may be formed after any step after forming the first gate 121 and before subsequently forming the interlayer dielectric layer 16 .

[0106] The groove 106 may penetrate the barrier layer 105, the channel layer 104 and the buffer layer 103 and enter the nucleation layer 102, or the groove 106 may penetrate the barrier layer 105, the channel layer 104, the buffer layer 103 and the nucleation layer 102 and enter the substrate 101, that is, the bottom of the step may be located in the nucleation layer 102 or in the substrate 101.

[0107] like Figure 6i , Figure 2 to Figure 4 As shown, the method for manufacturing the semiconductor device further includes:

[0108] An interlayer dielectric layer 16 and a metal interconnection structure are formed, wherein the interlayer dielectric layer 16 is formed on the first passivation layer 11, and the interlayer dielectric layer 16 covers the gate, the source 13, the drain 14 and the first field plate 15; the metal interconnection structure is formed in the interlayer dielectric layer 16 on the gate, the source 13 and the drain 14, respectively, and the metal interconnection structure also extends onto the interlayer dielectric layer 16;

[0109] A second passivation layer 18 is formed on the interlayer dielectric layer 16 , and the second passivation layer 18 also extends to a portion of the surface of the metal interconnection structure.

[0110] The metal interconnection structures on the gate, the source 13 and the drain 14 are not electrically connected. The metal interconnection structure may include a through-hole plug 171, a metal interconnection line 172 and a pad 173, wherein the through-hole plug 171 and the metal interconnection line 172 are located in the interlayer dielectric layer 16, the pad 173 is located on the upper surface of the interlayer dielectric layer 16, and the second passivation layer 18 extends to a portion of the surface of the pad 173; the metal interconnection lines 172 of adjacent layers and the metal interconnection lines 172 on the top layer and the pad 173 are electrically connected through the through-hole plug 171, and the metal interconnection lines 172 on the bottom layer and the gate, the source 13 and the drain 14 are all electrically connected through the through-hole plug 171.

[0111] The second passivation layer 18 may be made of polyimide or polyamide.

[0112] like Figure 3 As shown, preferably, before forming the second passivation layer 18 on the interlayer dielectric layer 16 , the method for manufacturing the semiconductor device further includes: forming a second field plate 19 in the interlayer dielectric layer 16 above the first field plate 15 .

[0113] The second field plate 19 may be at least one layer.

[0114] The second field plate 19 may be a planar field plate parallel to the upper surface of the substrate; or Figure 3 As shown, the second field plate 19 may include a planar field plate and a portion extending from a portion of the lower surface of the planar field plate toward the first field plate 15 , that is, the second field plate 19 may be an interdigitated embedded field plate.

[0115] The second field plate 19 can be electrically connected to the metal interconnection structure on the source 13, and the second field plate 19 is not electrically connected to the metal interconnection structure on the gate, that is, the second field plate 19 is a common source field plate. Figure 3 As shown, the second field plate 19 extends toward the metal interconnect structure on the source 13 until it is connected to the metal interconnect line 172 on the source 13; or, the second field plate 19 is electrically connected to the metal interconnect structure on the gate, and the second field plate 19 is not electrically connected to the metal interconnect structure on the source 13, that is, the second field plate 19 is a common-gate field plate; or, the second field plate 19 is not electrically connected to the metal interconnect structures on the gate and the source 13, that is, the second field plate 19 is a floating field plate.

[0116] The material of the second field plate 19 may include at least one of metal (such as titanium, aluminum or tungsten), metal nitride (titanium nitride or tungsten nitride) and metal silicide.

[0117] In the existing HEMT (High Electron Mobility Transistor) device, the field plate is only located on the upper surface of the passivation layer, resulting in electric field concentration between the gate and the drain (including the edge of the field plate close to the gate and other parts of the area between the gate and the drain); in the present invention, by forming the first field plate 15 not only on the first passivation layer 11, but also in the at least one groove 151 in the first passivation layer 11 between the gate and the drain 14, the strong electric field area between the gate and the drain 14 is dispersed, and the electric field is widened in the direction of the groove 151, that is, the first field plate 15 can effectively balance the electric field distribution between the gate and the drain 14 (especially the electric field distribution close to the gate), thereby making the electric field distribution between the gate and the drain 14 more uniform, and improving the electric field concentration phenomenon, thereby achieving an increase in breakdown voltage and improving dynamic resistance characteristics, thereby improving device performance and reliability.

[0118] In summary, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate; forming a first passivation layer, a gate, a source, a drain and a first field plate, wherein the first passivation layer is formed on the substrate, the gate is formed in the first passivation layer, the source and the drain are formed in the first passivation layer on both sides of the gate, the gate, the source and the drain all penetrate the first passivation layer, at least one groove is formed in the first passivation layer between the gate and the drain, the first field plate is formed on the first passivation layer, and the first field plate fills the at least one groove. The method for manufacturing a semiconductor device provided by the present invention improves the breakdown voltage of the device.

[0119] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A first passivation layer formed on the substrate; A gate is formed in the first passivation layer, and the gate penetrates the first passivation layer; A source electrode and a drain electrode are formed in the first passivation layer on both sides of the gate electrode, the source electrode and the drain electrode penetrate the first passivation layer, and at least one groove is formed in the first passivation layer between the gate electrode and the drain electrode; A first field plate is formed on the first passivation layer, and the first field plate fills the at least one groove.

2. The semiconductor device according to claim 1, wherein The base comprises, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer.

3. The semiconductor device according to claim 2, wherein: The nucleation layer, the buffer layer, the channel layer, and the barrier layer are retracted relative to the substrate to form steps.

4. The semiconductor device according to claim 1, wherein The first field plate is electrically connected to the gate or the source, or the first field plate is not electrically connected to the gate and the source.

5. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: an interlayer dielectric layer, formed on the first passivation layer, and the interlayer dielectric layer covers the gate, the source, the drain and the first field plate; A metal interconnect structure is formed in the interlayer dielectric layer on the gate, the source and the drain, respectively, and the metal interconnect structure also extends onto the interlayer dielectric layer; A second passivation layer is formed on the interlayer dielectric layer, and the second passivation layer also extends to a portion of the surface of the metal interconnection structure.

6. The semiconductor device according to claim 5, characterized in that The semiconductor device further comprises: A second field plate is formed in the interlayer dielectric layer above the first field plate.

7. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; A first passivation layer, a gate, a source, a drain and a first field plate are formed, wherein the first passivation layer is formed on the substrate, the gate is formed in the first passivation layer, the source and the drain are formed in the first passivation layer on both sides of the gate, the gate, the source and the drain all penetrate the first passivation layer, at least one groove is formed in the first passivation layer between the gate and the drain, the first field plate is formed on the first passivation layer, and the first field plate fills the at least one groove.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The base comprises, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The nucleation layer, the buffer layer, the channel layer, and the barrier layer are retracted relative to the substrate to form steps.

10. The method for manufacturing a semiconductor device according to claim 7, wherein: The first field plate is electrically connected to the gate or the source, or the first field plate is not electrically connected to the gate and the source.

11. The method for manufacturing a semiconductor device according to claim 7, wherein: The method for manufacturing the semiconductor device further includes: An interlayer dielectric layer and a metal interconnection structure are formed, wherein the interlayer dielectric layer is formed on the first passivation layer, and the interlayer dielectric layer covers the gate, the source, the drain and the first field plate; the metal interconnection structure is formed in the interlayer dielectric layer on the gate, the source and the drain, respectively, and the metal interconnection structure also extends onto the interlayer dielectric layer; A second passivation layer is formed on the interlayer dielectric layer, and the second passivation layer also extends to a portion of the surface of the metal interconnection structure.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: Before forming the second passivation layer on the interlayer dielectric layer, the method for manufacturing the semiconductor device further includes: A second field plate is formed in the interlayer dielectric layer above the first field plate.

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