Semiconductor structure and forming method thereof

Abstract

Semiconductor structures and methods of forming the same are provided. A method according to the present invention includes providing an intermediate structure including an opening, conformally depositing a metal gasket over the opening, depositing a dummy fill material over the metal gasket, recessing the dummy fill material to expose a portion of the metal gasket, removing the exposed portion of the metal gasket, removing the recessed dummy fill material, and removing the dummy fill material over the opening. And after removal of the recessed dummy fill material, depositing a metal fill layer over the opening.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits than the previous one. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or wire) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of handling and manufacturing ICs.

[0003] The stacked transistor structure can provide further density reduction for advanced integrated circuit (IC) technology nodes (particularly as it advances to 3nm (N3) and below), especially when the stacked transistor structure includes multi-gate devices such as fin field effect transistors (FinFETs), full-circle-alone (GAA) transistors including nanowires and / or nanosheets, other types of multi-gate devices, etc. The stacked transistor structure stacks transistors vertically. For example, a transistor stack may include a first transistor (e.g., a top transistor) disposed above a second transistor (e.g., a bottom transistor). When the first transistor and the second transistor are of opposite conductivity types (i.e., an n-type transistor and a p-type transistor), the transistor stack may provide a complementary field effect transistor (CFET). Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a method for forming a semiconductor structure is provided, comprising: providing an intermediate structure including an opening; conformally depositing a metal liner above the opening; depositing a dummy filling material above the metal liner; recessing the dummy filling material to expose a portion of the metal liner; removing the exposed portion of the metal liner; removing the recessed dummy filling material; and after the removal of the recessed dummy filling material, depositing a metal filling layer above the opening.

[0005] According to another aspect of an embodiment of the present application, a method for forming a semiconductor structure is provided, comprising: providing an intermediate structure including an opening; depositing a dummy filling material above the opening; recessing the dummy filling material to expose the sidewalls of the opening; selectively depositing an inhibitor layer above the exposed sidewalls of the opening; selectively removing the dummy filling material; after the selective removal, depositing a metal catalyst above the opening; after the deposition of the metal catalyst, selectively removing the inhibitor layer; and after the removal of the inhibitor layer, depositing a metal filling layer above the metal catalyst in the opening.

[0006] According to another aspect of an embodiment of the present application, a semiconductor structure is provided, comprising: a substrate; a first base fin and a second base fin rising from the substrate; an isolation component arranged above the substrate and located between the first base fin and the second base fin; a first plurality of nanostructures located above the first base fin; a second plurality of nanostructures located above the second base fin; a gate dielectric layer located above the first base fin, the first plurality of nanostructures, the second plurality of nanostructures, the second base fin, and the isolation component; a metal nitride layer located above the gate dielectric layer; and a gate fill layer located above the metal nitride layer, wherein an upper portion of the gate fill layer is in direct contact with the metal nitride layer, and a lower portion of the gate fill layer is separated from the metal nitride layer by a metal pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A flow chart showing a method 100 for depositing a metal filling layer in an opening according to one or more aspects of the present invention;

[0009] Figure 2-Figure 10 The present invention shows one or more aspects of the Figure 1 A partial cross-sectional view of a work-in-progress (WIP) structure of various manufacturing processes in the method;

[0010] Fig.11 A flow chart showing a method 300 for depositing a metal filling layer in an opening according to one or more aspects of the present invention;

[0011] Figure 12-Figure 20 The present invention shows one or more aspects of the Fig.10A partial cross-sectional view of a WIP structure of various manufacturing processes in the method;

[0012] Figure 21-Figure 28 The present invention shows one or more aspects of the Figure 1 or Fig.11 Representative partial cross-sectional views of different WIP structures for various manufacturing processes in the method. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] For ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] In addition, when "about," "approximately," etc. are used to describe a number or a range of numbers, the term is intended to encompass numbers within a reasonable range that take into account variations inherently caused during manufacturing as understood by a person of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing a component having the features associated with the number, the number or range of numbers encompasses a reasonable range that includes the described number, for example, within + / - 10% of the described number. For example, a material layer having a thickness of "about 5 nm" may encompass a size range from 4.25 nm to 5.75 nm, where a person of ordinary skill in the art knows that the manufacturing tolerance associated with depositing material layers is + / - 15%.

[0016] The gate structure for multi-gate devices and stacked multi-gate devices can be formed using a gate last process. In an exemplary gate last process, a dummy gate stack or a placeholder gate stack is first formed above the channel region of the active region of the multi-gate device and the stacked multi-gate device. A gate spacer is formed along the sidewall of the dummy gate stack. After forming the source / drain components, the dummy gate stack is removed, and the remaining gate spacer defines the gate trench. For GAA transistors or stacked multi-gate devices, the channel component is released from the sacrificial semiconductor layer by selective etching. Then, a functional gate structure having a gate dielectric layer, at least one work function layer, and a gate filling layer is deposited in the gate trench. Since the gate filling layer is deposited in a high aspect ratio opening, the gate filling layer may merge prematurely and block the line of sight, resulting in gaps and gaps in the gate structure. These gaps and gaps not only increase the resistance, but also may cause defects when the gate structure is etched back for further process steps.

[0017] The present invention provides a bottom-up deposition method for depositing a metal fill layer in a high aspect ratio opening. The high aspect ratio opening may include a partially filled gate trench for a multi-gate transistor or a stacked multi-gate transistor, or even a contact opening for a back-end of line (BEOL) structure. The method of the present invention can selectively deposit a metal liner or a metal catalyst above the lower portion of the high aspect ratio opening. Then, a metal fill layer is deposited over the metal liner or the metal catalyst in a bottom-up manner using chemical plating.

[0018] Various aspects of the present invention will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 and Fig.11 1 is a flow chart illustrating methods 100 and 300 for depositing a metal fill layer in a high aspect ratio opening according to various aspects of the present invention. Methods 100 and 300 are merely examples and are not intended to limit the present invention to what is explicitly shown in methods 100 and 300. Additional steps may be provided before, during, and after methods 100 and 300, and some of the steps described may be replaced, eliminated, or relocated for additional embodiments of the method. For simplicity, not all steps are described in detail. Figure 2-Figure 10 To describe method 100, Figure 2-Figure 10 is a partial cross-sectional view of a work-in-progress (WIP) structure 200 at different stages of manufacture according to an embodiment of the method 100. Figure 12-Figure 19 To describe method 300, Figure 12-Figure 193 is a partial cross-sectional view of a WIP structure 200 at different stages of manufacturing according to an embodiment of the method 300. When performing various processes of the present invention, the WIP structure 200 may also be referred to as a workpiece or an intermediate structure. Since the WIP structure 200 will be manufactured into a semiconductor device 200 at the end of the manufacturing process, the WIP structure 200 may be referred to as a semiconductor device 200 as required by the context. In addition, throughout the present application and in different embodiments, unless otherwise specified, the same reference numerals represent the same components with similar structures and compositions. The source / drain region may refer to the source or the drain, individually or collectively depending on the context.

[0019] The method 100 deposits a metal fill layer over a high aspect ratio opening in a bottom-up manner by selectively depositing a metal liner over a bottom of the high aspect ratio opening and then depositing a metal fill layer over the metal liner.

[0020] refer to Figure 1 , Figure 2 ,and Figure 3 , the method 100 includes block 102, wherein a work in process (WIP) structure 200 including an opening 215 is provided. Figure 2 In some of the embodiments represented, the WIP structure 200 is intended for use in the fabrication of stacked multi-gate transistors. Figure 3 Shows the crossing Figure 2A partial cross-sectional view of the line A-A' in FIG. The WIP structure 200 includes a substrate 202 and a fin structure 210 disposed above the substrate 202. In one embodiment, the substrate 202 may be a silicon (Si) substrate. In some other embodiments, the substrate 202 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 may also include an insulating layer, such as a silicon oxide layer, to have a silicon on insulator (SOI) structure. The fin structure 210 may be patterned from the substrate 202 and a semiconductor stack disposed above the substrate 202. Each of the fin structures 210 includes a substrate fin 204, a bottom channel component 208B located above the substrate fin 204, an intermediate insulating layer 209 located above the bottom channel component 208B, and a top channel component 208T. The substrate fin 204 rises continuously from the substrate 202 and shares the same composition with the substrate 202. Each of the substrate fins 204 is surrounded by an isolation component 206 to insulate each other laterally. In some embodiments, the bottom channel component 208B and the top channel component 208T may include silicon (Si). The intermediate insulating layer 209 is vertically sandwiched between the topmost one of the bottom channel component 208B and the bottommost one of the top channel component 208T. Please note that for the purpose of illustration, the drawings of the present invention only show two bottom channel components 208B and two top channel components 208T. The present invention is fully contemplated to have additional bottom channel components 208B or top channel components 208T.

[0021] The isolation feature 206 may also be referred to as a shallow trench isolation (STI) feature 206. In an exemplary process, a dielectric material for the isolation feature 206 is deposited over the WIP structure 200 including the fin structure 210 using CVD, sub-atmospheric pressure CVD (SACVD), flowable CVD (FCVD), spin coating, and / or other suitable processes. The deposited dielectric material is then planarized and recessed to form the isolation feature 206. The dielectric material for the isolation feature may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. Figure 2 As shown in FIG. 2 , after the recess, the substrate fin 204 rises above the isolation feature 206. The intermediate insulating layer 209 may include silicon oxide, silicon nitride, or a combination thereof. Figure 3 When viewed in the X direction shown in FIG. 2 , the isolation feature 206 may not be visible.

[0022] refer to Figure 3 . The bottom channel member 208B extends longitudinally along the Y direction between the two bottom source / drain features 250, and the top channel member 208T extends longitudinally along the Y direction between the two top source / drain features 260. The bottom source / drain feature 250 may be formed using an epitaxial process, such as vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The epitaxial growth process may use gaseous and / or liquid precursors that interact with the composition of the substrate fin 204, the bottom channel member 208B, and the top channel member 208T. The epitaxial growth of the bottom source / drain feature 250 may be performed from the top surface of the substrate fin 204 and the exposed sidewalls of the bottom channel member 208B. The epitaxial growth of the top source / drain feature 260 may be performed from the exposed sidewalls of the top channel member 208T. In the embodiment represented in the figure, the bottom source / drain feature 250 is p-type and can include silicon germanium (SiGe) doped with a p-type dopant such as boron (B). The top source / drain feature 260 is n-type and can include silicon (Si) doped with an n-type dopant such as phosphorus (P) or arsenic (As). Each of the bottom channel member 208B and the top channel member 208T includes a channel width direction ( Figure 2 The width of the bottom channel member 208B and the top channel member 208T is greater than the height, and each of the bottom channel member 208B and the top channel member 208T can be referred to as a nanosheet or a nanostructure.

[0023] Still reference Figure 3, the top source / drain feature 260 is spaced apart from at least the bottom source / drain feature 250 by a bottom contact etch stop layer (CESL) 252 and a bottom interlayer dielectric (ILD) layer 254. The bottom CESL 252 may include silicon nitride, silicon oxynitride, and / or other materials known in the art. The bottom ILD layer 254 may include materials such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials, and may be formed by CVD, ALD, plasma enhanced chemical vapor deposition (PECVD) processes, and / or other suitable deposition or oxidation processes. In some embodiments, the bottom CESL 252 is first conformally deposited on the WIP structure 200 using CVD, ALD, PECVD, and the bottom ILD layer 254 is deposited over the bottom CESL 252 by spin coating, FCVD, CVD, or other suitable deposition techniques. In some embodiments, after forming the bottom ILD layer 254, the WIP structure 200 may be annealed to improve the integrity of the bottom ILD layer 254. Figure 3 , after depositing the bottom CESL 252 and the bottom ILD layer 254, the bottom CESL 252 and the bottom ILD layer 254 are etched back to the exposed sidewalls of the top channel member 208T. Similarly, a top contact etch stop layer (CESL) 262 and a top interlayer dielectric (ILD) layer 264 are deposited over the top source / drain features 260. The top CESL 262 may share a similar composition and a similar formation process with the bottom CESL 252. The top ILD layer 264 may share a similar composition and a similar formation process with the bottom ILD layer 252.

[0024] In the depicted embodiment, Figure 2 and Figure 3 The WIP structure 200 in FIG. 1 is formed using a gate last process, wherein a dummy gate stack (or a replacement gate stack) is formed over the channel region of the fin structure 210. After the gate spacer 242 is deposited along the sidewalls of the fin structure 210, a source / drain trench now filled with a bottom source / drain feature 250 and a top source / drain feature 260 is formed by anisotropic etching. After the dummy gate stack is removed and the bottom channel feature 208B and the top channel feature 208T are released, the gate spacer 242 and the inner spacer feature 248 define a gate trench now filled with an interface layer 211, a high-k dielectric layer 212, and a metal nitride layer 214. The gate spacer 242 and the inner spacer feature 248 may include silicon oxycarbon nitride, silicon carbonitride, or silicon nitride.

[0025] exist Figure 2 In the WIP structure 200 in, the interface layer 211 is formed over the exposed surfaces of the substrate fin 204, the bottom channel member 208B, and the top channel member 208T. A high-k dielectric layer 212 is disposed over the interface layer 211. In some embodiments, the interface layer 211 includes silicon oxide or hafnium silicate and can be formed in a pre-cleaning process. An exemplary pre-cleaning process may include using RCA SC-1 (ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). A high-k dielectric layer 212 is then deposited over the interface layer 211 using atomic layer deposition (ALD), CVD, and / or other suitable methods. The dielectric material included in the high-k dielectric material as used and described herein has a high dielectric constant, for example, a dielectric constant greater than that of thermal silicon oxide (~3.9). In one embodiment, the high-k dielectric layer 212 may include hafnium oxide. Alternatively, the high-k dielectric layer 212 may include other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or other suitable materials. Figure 2 As shown in , since the intermediate insulating layer 209 covers the top surface of the topmost bottom channel component 208B and the bottom surface of the bottommost channel component 208T, the interface layer 211 is spaced apart from the top surface of the topmost bottom channel component 208B and the bottom surface of the bottommost channel component 208T. Since the pre-cleaning process does not oxidize the isolation feature 206, the interface layer 211 is not formed above the surface of the isolation feature 206. The high-k dielectric layer 212 is deposited on the isolation feature 206, around the base fin 204, and around at least one bottom channel component 208B and at least one top channel component 208T. Figure 2 In the embodiment represented in FIG. 1 , the high-k dielectric layer 212 surrounds the topmost bottom channel component 208B, the middle insulating layer 209, and the bottommost top channel component 208T as a whole. The high-k dielectric layer 212 does not extend between the topmost bottom channel component 208B and the middle insulating layer 209, or between the bottommost top channel component 208T and the middle insulating layer 209.

[0026] As the gate structure 240 (eg Fig. 9 and Fig.10As shown in FIG. 2 , a metal nitride layer 214 is deposited over the WIP structure 200. Figure 2 As shown in , the metal nitride layer 214 is deposited over the high-k dielectric layer 212 to surround the bottom channel member 208B and the top channel member 208T. In the depicted embodiment, the metal nitride layer 214 completely fills the space between the bottom channel member 208B and the space between the top channel member 208T. The metal nitride layer 214 is also disposed over the high-k dielectric layer 212 over the isolation feature 206. In some embodiments, the metal nitride layer 214 may include titanium nitride and may be used as a work function metal layer, such as a p-type work function metal layer. The fin structure 210 and the metal nitride layer 214 define an opening 215 between the two fin structures 210. The opening 215 includes a first width (W1) along the X direction and a first height (H1) along the Z direction. In some embodiments, the ratio of the first height (H1) to the first width (W1) defines a first aspect ratio, which is between 3 and 10. The opening 215 can be considered a high aspect ratio opening.

[0027] refer to Figure 1 and Figure 4 , method 100 includes block 104, where a metal liner 220 is deposited over opening 215. In some embodiments, metal liner 220 may include ruthenium (Ru), cobalt (Co), molybdenum (Mo), palladium (Pd), platinum (Pt), gold (Au), or iridium (Ir). At block 104, metal liner 220 may be conformally deposited over metal nitride layer 214 using atomic layer deposition (ALD). In some cases, metal liner 220 is deposited to have a thickness of about 100 mm / s. Peace The thickness between.

[0028] refer to Figure 1 and Figure 5 , the method 100 includes block 106, where a dummy fill material 222 is deposited over the metal liner 220. In some embodiments, the dummy fill material 222 may include a bottom anti-reflective coating (BARC) layer. In some cases, the BARC layer may include a silicon-containing polymer, a carbon-containing polymer, or spin-on carbon (SOC). The dummy fill material 222 may be deposited using flowable CVD (FCVD) or spin coating. In the depicted embodiment, the top surface of the dummy fill material 222 is higher than the top surface of the metal nitride layer 214 to completely fill the opening 215.

[0029] refer to Figure 1 and Figure 6 , the method 100 includes block 108, wherein the dummy fill material 222 is recessed. At block 108, the dummy fill material 222 is anisotropically etched back or recessed to have a reduced height. Figure 5 and Figure 6 As shown in FIG. 1 , the height of the dummy fill material 222 decreases from completely covering the opening 215 to covering the bottom of the opening 215. In some embodiments, the anisotropic etch back at block 108 may include using a dry etching process using nitrogen plasma, hydrogen plasma, argon (Ar), or a combination thereof. Figure 6 As shown in FIG. 2 , after etching back the dummy filling material, the top of the metal liner 220 is exposed, while the bottom of the metal liner 220 is still covered by the etched back dummy filling material 222 .

[0030] refer to Figure 1 and Figure 7 , the method 100 includes block 110, wherein the top of the metal liner 220 is removed using the recessed dummy fill material 222 as an etch mask. In some embodiments, a selective wet etching process may be used to selectively remove the exposed top of the metal liner 220 that is not covered by the recessed dummy fill material 222. The selective wet etching at block 110 may include using hydrochloric acid (HCl), nitric acid (HNO3), hydrogen peroxide (H2O2), or a mixture thereof. Figure 7 As shown in FIG. 1 , after selectively removing the top of the metal liner 220, the recessed dummy filling material 222 covering the bottom of the metal liner 220 may have a second width (W2) along the X direction, and a second height (H2) along the Y direction. The aspect ratio of the recessed dummy filling material 222 is the ratio of the second height H2 to the second width W2, and is between 1 and 2.

[0031] refer to Figure 1 and Figure 8 , the method 100 includes block 112, wherein the dummy fill material 222 is completely removed. At block 112, the dummy fill material 222 is removed by a dry etching process, the dry etching process including using nitrogen plasma, hydrogen plasma, argon (Ar), or a combination thereof. Figure 8 As shown in FIG. 1 , the dry etching process at block 112 etches the metal liner 220 at a slower rate and leaves the bottom of the metal liner 220 after the dummy fill material 222 is completely removed from the WIP structure 200 .

[0032] refer to Figure 1 and Figure 9-10, the method 100 includes a frame 114, depositing a metal fill layer 230 above the metal liner 220. In some embodiments, the metal fill layer 230 is deposited using chemical plating at frame 114. In an exemplary process, a pre-cleaning process including both dry cleaning and wet cleaning is performed to remove surface oxidation, organic debris, and metal debris. The WIP structure 200 is then immersed in a plating solution containing a metal precursor, an organic chelating agent, a reducing agent, a stabilizer, a pH adjusting agent, or a wetting agent. The reducing agent reacts with the metal precursor to deposit the metal of the metal precursor to form the metal fill layer 230. The deposition of the metal fill layer 230 starts from the bottom of the metal liner 220 and is performed in a bottom-up manner. In some embodiments, the metal fill layer 230 includes nickel (Ni), copper (Cu), silver (Ag), gold (Au), palladium (Pd), ruthenium (Ru), platinum (Pt), or iridium (Ir), or an alloy such as nickel phosphorus (NiP) or cobalt nickel phosphorus (CoNiP). Fig. 9 As shown in FIG. 1 , after the metal filling layer 230 is deposited, the top surface of the metal filling layer 230 is higher than the top surface of the metal nitride layer 214. In some embodiments, a post annealing process may be performed after the metal filling layer 230 is deposited to promote the regrowth and reflow of the metal filling layer 230. It has been observed that the metal filling layer 230 formed using the method 100 tends to be seamless and provide low resistance. Fig. 9 and Fig.10 As shown in FIG. 2 , with the deposition of the metal fill layer 230, a gate structure 240 is substantially formed. The gate structure 240 includes the metal fill layer 230, the metal nitride layer 214, the bottom of the metal liner 220, the high-k dielectric layer 212, and the interface layer 211. The gate structure 240 completely surrounds at least one bottom channel member 208B and at least one top channel member 208T.

[0033] The method 300 deposits a metal fill layer over a high aspect ratio opening in a bottom-up manner by selectively depositing a metal catalyst over a bottom portion of the high aspect ratio opening and then depositing a metal fill layer over the metal catalyst.

[0034] refer to Fig.11 , Fig.12 ,and Fig.13 , the method 300 includes block 302 , where a work in process (WIP) structure 200 including an opening 215 is provided. Figure 12-13 The WIP structure shown in Figure 2-Figure 3 For the sake of brevity, the Fig.12 and Fig.13 Detailed description of the WIP structure 200 in FIG.

[0035] refer to Fig.11 and Fig.14 , method 300 includes block 304, where a dummy fill material 222 is deposited over opening 215. In some embodiments, dummy fill material 222 may include a bottom anti-reflective coating (BARC) layer or silicon oxycarbide (SiOC). In some cases, the BARC layer may include a silicon-containing polymer, a carbon-containing polymer, or spin-on carbon (SOC). Dummy fill material 222 may be deposited using flowable CVD (FCVD) or spin coating. In the depicted embodiment, a top surface of dummy fill material 222 is higher than a top surface of metal nitride layer 214 to completely fill opening 215.

[0036] refer to Fig.11 and Fig.15 , the method 300 includes block 306, where the dummy fill material 222 is recessed. At block 306, the dummy fill material 222 is anisotropically etched back or recessed to have a reduced height. Fig.14 and Fig.15 As shown in FIG. 3 , the height of the dummy fill material 222 decreases from completely covering the opening 215 to covering the bottom of the opening 215. In some embodiments, the anisotropic etch back at block 306 may include using a dry etching process using nitrogen plasma, hydrogen plasma, argon (Ar), or a combination thereof. Fig.15 As shown in FIG. 2 , after etching back the dummy filling material 222 , the top of the metal nitride layer 214 is exposed, while the bottom of the metal nitride layer 214 is still covered by the etched back dummy filling material 222 .

[0037] refer to Fig.11 and Fig.16 , method 300 includes block 308, wherein an inhibitor coating 224 is deposited over the exposed portion of the metal nitride layer 214. The inhibitor coating 224 includes a small molecule inhibitor (SMI) or a self-assembled monolayer (SAM). In some embodiments, the inhibitor coating 224 includes a molecule including a head group that interacts with the metal nitride layer 214 and a bulky tail group that inhibits the deposition of materials on the metal nitride layer 214. The SMI may include silane, aniline, pyridine, toluidine, phenylenediamine, toluenediamine, naphthylamine, or aminopyridine. The SAM may include chlorosilane or alkoxysilane. In some cases, the SAM may include various functional groups. In one embodiment, the inhibitor coating 224 includes silane. Since the bottom of the metal nitride layer 214 is covered by the dummy fill material 222, the inhibitor coating 224 is only deposited over the exposed surface of the metal nitride layer 214, including the top surface of the metal nitride layer 214.

[0038] refer to Fig.11 and Fig.17, the method 300 includes block 310, in which the dummy fill material 222 is completely removed. After depositing the inhibitor coating 224, the dummy fill material 222 is removed by a dry etching process including using nitrogen plasma, hydrogen plasma, argon (Ar), or a combination thereof. The removal of the dummy fill material 222 exposes the surface of the bottom of the metal nitride layer 214. The exposed surface of the bottom of the metal nitride layer 214 is not protected or covered by the inhibitor coating 224.

[0039] refer to Fig.11 and Fig.18 , the method 300 includes a frame 312, wherein a metal catalyst 226 is deposited above the surface not covered by the inhibitor coating 224. In some embodiments, the metal catalyst 226 may include nanoparticles of ruthenium (Ru), palladium (Pd), platinum (Pt), or gold (Au). In one embodiment, the metal catalyst 226 includes nanoparticles of palladium (Pd). In some cases, the nanoparticles of the metal catalyst 226 may be about 1 nm to 2 nm in size. At frame 312, the metal catalyst 226 may be deposited using spin coating or dip coating. The coverage density of the metal catalyst 226 on the exposed surface of the metal nitride layer 214 is related to the deposition of the metal fill layer 230 at frame 316. In most cases, a greater coverage density is preferred because it can obtain a denser and faster deposition of the metal fill layer 230. The operation at frame 312 may also be referred to as metal catalyst decoration.

[0040] refer to Fig.11 and Fig.19 , the method 300 includes block 314, where the inhibitor coating 224 is removed from the WIP structure 200. In some embodiments, the inhibitor coating 224 can be removed by thermal activation. In an exemplary thermal activation process, the WIP structure 200 is heated until the bond between the inhibitor coating 224 and the metal nitride layer 214 is weakened, and the inhibitor coating 224 is removed by activation. Here, the bottom of the metal nitride layer 214 is covered by the metal catalyst 226, and the top of the metal nitride layer 214 is exposed.

[0041] refer to Fig.11 and Fig. 20, the method 100 includes a block 316, depositing a metal fill layer 230 over the metal catalyst 226. In some embodiments, at block 316, the metal fill layer 230 is deposited using chemical plating. In an exemplary process, a pre-cleaning process including both dry cleaning and wet cleaning can be performed to remove surface oxidation, organic debris, and metal debris, as long as the pre-cleaning process does not interfere with or remove the metal catalyst 226. The WIP structure 200 is then immersed in a plating solution containing a metal precursor, an organic chelating agent, a reducing agent, a stabilizer, a pH adjuster, or a wetting agent. The reducing agent reacts with the metal precursor to deposit the metal of the metal precursor to form the metal fill layer 230. The deposition of the metal fill layer 230 starts from the metal catalyst 226 at the bottom of the metal nitride layer 214 and is performed in the opening 215 in a bottom-up manner. In some embodiments, the metal fill layer 230 includes nickel (Ni), copper (Cu), silver (Ag), gold (Au), palladium (Pd), ruthenium (Ru), platinum (Pt), or iridium (Ir), or an alloy such as nickel phosphorus (NiP) or cobalt nickel phosphorus (CoNiP). Fig. 20 As shown in , after depositing the metal fill layer 230, the top surface of the metal fill layer 220 is higher than the top surface of the metal nitride layer 214. That is, the metal fill layer 230 completely fills the opening 215. In some embodiments, a post annealing process can be performed to increase the density of the metal fill layer 230, or to remove voids in the metal fill layer 230. It has been observed that the metal fill layer 230 formed using the method 300 tends to be seamless and provide low resistance. With the deposition of the metal fill layer 230, a gate structure 240 is basically formed. The gate structure 240 includes the metal fill layer 230, the metal nitride layer 214, the metal catalyst 226, the high-k dielectric layer 212, and the interface layer 211. The gate structure 240 completely surrounds at least one bottom channel member 208B and at least one top channel member 208T.

[0042] In addition to being used to manufacture Figure 2-Figure 10 and Figure 12-Figure 20 In addition to the stacked multi-gate device shown in FIG. 1 , the methods 100 and 300 can also be applied to Figure 21-23 In the fin field effect transistor (FinFET) shown in Figure 24-26 In the GAA transistor shown in Figure 27-Figure 28 Although not explicitly described here, it should be obvious to those skilled in the art that the method of the present invention can also be applied to planar devices when a metal fill layer needs to be deposited in a high aspect ratio opening.

[0043] First reference Figure 21-23, which shows a work-in-progress (WIP) structure 400 intended for use in fabricating a FinFET structure. Fig.21 , the WIP structure 400 includes a fin 404 rising from the top surface of the substrate 402. The fin 404 is patterned from a portion of the substrate 402 and is laterally insulated from each other by an isolation feature 406. A gate dielectric layer 412 is deposited over the fin 404 and the isolation feature 406. The gate dielectric layer 412 includes an interface layer and a high-k dielectric layer located above the interface layer. A metal nitride layer 414 is deposited over the gate dielectric layer 412 by ALD. In one embodiment, the substrate 402 may be a silicon (Si) substrate. In some other embodiments, the substrate 402 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. The substrate 402 may also include an insulating layer, such as a silicon oxide layer, to have a silicon on insulator (SOI) structure. The fin 404 rises continuously from the substrate 402 and shares the same composition as the substrate 402. The isolation feature 406 may also be referred to as a shallow trench isolation (STI) feature 406. The isolation features 406 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials.

[0044] In some embodiments, the interfacial layer in the gate dielectric layer 412 includes silicon oxide or hafnium silicate and can be formed in a pre-cleaning process. The high-k dielectric layer in the gate dielectric layer 412 includes hafnium oxide. Alternatively, the high-k dielectric layer may include other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (Hf-SiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or other suitable materials. In some embodiments, the metal nitride layer 414 may include titanium nitride and may be used as a work function metal layer, such as a p-type work function metal layer. Fig.21 In the embodiment, between the fins 404 , the fins 404 and the metal nitride layer 414 define openings 415 .

[0045] By using method 100 or method 300, a metal nucleation layer 420 is formed to cover the bottom of the metal nitride layer 414. When using method 100, the metal nucleation layer 420 can be similar to the metal liner 220. When using method 300, the metal nucleation layer 420 can be similar to the metal catalyst 226. Like the metal liner 220 or the metal catalyst 226, the metal nucleation layer 420 helps to deposit the metal filling layer 430 from the bottom up, such as Fig. 22 . The metal fill layer 430 may be deposited using the techniques described above with respect to the operations in block 114. That is, the metal fill layer 430 may be deposited using electroless plating. In some embodiments, the metal fill layer 430 includes nickel (Ni), copper (Cu), silver (Ag), gold (Au), palladium (Pd), ruthenium (Ru), platinum (Pt), or iridium (Ir), or an alloy such as nickel phosphorus (NiP) or cobalt nickel phosphorus (CoNiP).

[0046] Fig.23 Shown along Fig. 22 Partial cross-sectional view along the center line BB'. Along the Y direction, the fin 404 extends between the two source / drain components 450. The source / drain components 450 can be n-type or p-type. When they are n-type, they can include silicon (Si), and n-type dopants such as phosphorus (P) or arsenic (As). When they are p-type, they can include silicon germanium (SiGe), and p-type dopants such as boron (B). The gate structure 440 surrounds the channel region of the fin 404. The gate structure 440 includes a metal fill layer 430, a metal nitride layer 414, a metal nucleation layer 420, and a gate dielectric layer 412. Since the line BB' cuts through the fin 404, Fig.23 4. The metal nucleation layer 420 is not shown in FIG. The sidewalls of the top of the gate structure 440 above the fin 404 are lined by gate spacers 442. A contact etch stop layer (CESL) 452 is deposited over the source / drain features 450, and an interlayer dielectric (ILD) layer 454 is disposed over the CESL 452. The composition of the CESL 452 can be similar to that of the bottom CESL 252. The composition of the ILD layer 454 can be similar to that of the bottom ILD layer 254.

[0047] Then refer to Figure 24-26 , which shows a work-in-progress (WIP) structure 500 intended for use in manufacturing a GAA structure. Fig.24, the WIP structure 500 includes a plurality of channel members 508 disposed above a base fin 504. The base fin 504 rises continuously from the top surface of the substrate 502. The base fins 504 are patterned from portions of the substrate 502 and are insulated from each other by isolation features 506. A gate dielectric layer 512 is deposited to surround each channel member 508 and to be located above the top surface of the isolation features 506. The base fin 504 and the channel member 508 disposed directly thereon may be collectively referred to as a fin structure 510. The gate dielectric layer 512 includes an interface layer and a high-k dielectric layer located above the interface layer. A metal nitride layer 514 is deposited above the gate dielectric layer 512 by ALD. The metal nitride layer 514 is disposed along the sidewalls of the channel member 508 and defines an opening 515 disposed between the two fin structures 510. Each of the fin structures 510 includes a base fin 504 , and a vertical stack of channel members 508 disposed directly above the base fin 502 .

[0048] In one embodiment, substrate 502 may be a silicon (Si) substrate. In some other embodiments, substrate 502 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Substrate 502 may also include an insulating layer, such as a silicon oxide layer, to have a silicon on insulator (SOI) structure. Fin structure 510 may be patterned from substrate 502 and a semiconductor stack disposed above substrate 502. Base fin 504 rises continuously from substrate 502 and shares the same composition with substrate 502. Channel member 508 may include silicon (Si). Note that for purposes of illustration, the accompanying drawings of the present invention show three bottom channel members 508. It should be understood that WIP structure 500 may include fewer or more channel members. Isolation component 506 may also be referred to as shallow trench isolation (STI) component 506. Isolation component 506 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials.

[0049] The interfacial layer in the gate dielectric layer 512 may include silicon oxide or hafnium silicate and may be formed in a pre-cleaning process. The high-k dielectric layer in the gate dielectric layer 512 may include hafnium oxide. Alternatively, the high-k dielectric layer may include other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (Hf-SiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or other suitable materials. The metal nitride layer 514 may include titanium nitride and may be used as a work function metal layer, such as a p-type work function metal layer.

[0050] By using method 100 or method 300, a metal nucleation layer 520 is formed to cover the bottom of the metal nitride layer 514. When using method 100, the metal nucleation layer 520 can be similar to the metal liner 220. When using method 300, the metal nucleation layer 520 can be similar to the metal catalyst 226. Like the metal liner 220 or the metal catalyst 226, the metal nucleation layer 520 helps to deposit the metal filling layer 530 from the bottom up, such as Fig.25 As shown in .

[0051] Fig.26 Shown along Fig.25 A partial cross-sectional view of the center line CC'. Along the Y direction, the channel component 508 extends between the two source / drain components 550. The source / drain components 550 can be n-type or p-type. When they are n-type, they can include silicon (Si), and n-type dopants such as phosphorus (P) or arsenic (As). When they are p-type, they can include silicon germanium (SiGe), and p-type dopants such as boron (B). A gate structure 540 surrounds each channel component 508. The gate structure 540 includes a metal fill layer 530, a metal nitride layer 514, a metal nucleation layer 520, and a gate dielectric layer 512. Since the line CC' cuts through the channel component 508, Fig.26 5. The metal nucleation layer 520 is not shown in FIG. The sidewalls of the top of the gate structure 540 above the channel member 508 are lined by gate spacers 542. A contact etch stop layer (CESL) 552 is deposited over the source / drain features 550, and an interlayer dielectric (ILD) layer 554 is disposed over the CESL 552. The composition of the CESL 552 can be similar to that of the bottom CESL 252. The composition of the ILD layer 554 can be similar to that of the bottom ILD layer 254.

[0052] Finally, now refer to Figure 27-Figure 28 , which shows a work-in-progress (WIP) structure 600 intended for a contact structure. The WIP structure 600 includes a contact feature 604 disposed in a first dielectric layer 602. Over the contact feature 604 and the top surface of the first dielectric layer 602, an etch stop layer (ESL) 606 is disposed. A second dielectric layer 608 is disposed over the ESL 606. An opening 615 is formed through the second dielectric layer 608 and the ESL 606. A barrier layer 614 is deposited over the opening 615. In some embodiments, the first dielectric layer 602 and the second dielectric layer 608 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, a combination thereof, and / or other suitable materials. The ESL 606 may include silicon nitride, oxygen-doped silicon carbide, nitrogen-doped silicon carbide, silicon oxynitride, aluminum oxide, or aluminum nitride. Contact feature 604 may include copper (Cu), cobalt (Co), nickel (Ni), ruthenium (Ru), or tungsten (W), and may represent source / drain contacts, source / drain contact vias, gate contact vias, or metal lines. Barrier layer 614 may include titanium nitride (TiN).

[0053] By using method 100 or method 300, a metal nucleation layer 620 is formed to cover the bottom of the barrier layer 614 in the opening 615. When using method 100, the metal nucleation layer 620 can be similar to the metal liner 220. When using method 300, the metal nucleation layer 620 can be similar to the metal catalyst 226. Like the metal liner 220 or the metal catalyst 226, the metal nucleation layer 620 helps to deposit the metal filling layer 630 from the bottom up, such as Fig.28 After the deposition of the metal fill layer 630 , a planarization process, such as a chemical mechanical polishing (CMP) process, is performed to provide a planar top surface for the WIP structure 600 .

[0054] In one exemplary aspect, the present invention relates to a method of forming a semiconductor structure. The method includes providing an intermediate structure including an opening, conformally depositing a metal liner over the opening, depositing a dummy fill material over the metal liner, recessing the dummy fill material to expose a portion of the metal liner, removing the exposed portion of the metal liner, removing the recessed dummy fill material, and depositing a metal fill layer over the opening after removal of the recessed dummy fill material.

[0055] In some embodiments, the opening is defined between two fin structures covered by a metal nitride layer. In some embodiments, the metal nitride layer includes titanium nitride. In some embodiments, each of the two fin structures includes a plurality of bottom channel members, and a plurality of top channel members disposed above the plurality of bottom channel members. In some embodiments, each of the two fin structures also includes an insulating layer sandwiched between the topmost bottom channel member in the plurality of bottom channel members and the bottommost top channel member in the plurality of top channel members. In some cases, the metal liner includes Ru, Co, Mo, Pd, Pt, Au, or Ir. In some embodiments, the conformal deposition of the metal liner includes the use of atomic layer deposition (ALD). In some embodiments, the dummy fill material includes a bottom anti-reflective coating (BARC) material. In some embodiments, the metal fill layer includes Ni, Cu, Ag, Au, Pd, Ru, Pt, Ir, NiP, or CoNiP. In some embodiments, the deposition of the metal fill layer includes the use of chemical plating.

[0056] In another exemplary aspect, the present invention relates to a method of forming a semiconductor structure. The method includes providing an intermediate structure including an opening, depositing a dummy fill material over the opening, recessing the dummy fill material to expose sidewalls of the opening, selectively depositing an inhibitor layer over the exposed sidewalls of the opening, selectively removing the dummy fill material, depositing a metal catalyst over the opening after the selective removal, selectively removing the inhibitor layer after the deposition of the metal catalyst, and depositing a metal fill layer over the metal catalyst in the opening after the removal of the inhibitor layer.

[0057] In some embodiments, the selective removal of the inhibitor layer comprises using thermal excitation. In some embodiments, the selective deposition of the inhibitor layer comprises using silane. In some embodiments, the metal catalyst comprises Pd. In some embodiments, the deposition of the metal filler layer comprises using chemical plating.

[0058] In another exemplary aspect, the present invention relates to a semiconductor structure. The semiconductor structure includes: a substrate; a first base fin and a second base fin rising from the substrate; an isolation component disposed above the substrate and between the first base fin and the second base fin; a first plurality of nanostructures located above the first base fin; a second plurality of nanostructures located above the second base fin; a gate dielectric layer located above the first base fin, the first plurality of nanostructures, the second plurality of nanostructures, the second base fin, and the isolation component; a metal nitride layer located above the gate dielectric layer; and a gate fill layer located above the metal nitride layer. The upper portion of the gate fill layer is in direct contact with the metal nitride layer, and the lower portion of the gate fill layer is separated from the metal nitride layer by a metal liner.

[0059] In some embodiments, the metal nitride layer comprises titanium nitride. In some embodiments, the metal liner comprises Ru, Co, Mo, Pd, Pt, Au, or Ir. In some embodiments, the metal filler layer comprises Ni, Cu, Ag, Au, Pd, Ru, Pt, Ir, NiP, or CoNiP. In some embodiments, the metal liner comprises Pd.

[0060] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: providing an intermediate structure including an opening; conformally depositing a metal liner over the opening; depositing a dummy fill material over the metal pad; recessing the dummy fill material to expose a portion of the metal pad; removing the exposed portion of the metal liner; removing the recessed dummy filling material; as well as After said removal of said dummy fill material of the recess, a metal fill layer is deposited over said opening.

2. The method according to claim 1, wherein: The opening is defined between two fin structures covered by the metal nitride layer.

3. The method according to claim 2, wherein: The metal nitride layer includes titanium nitride.

4. The method according to claim 2, wherein: Each of the two fin structures includes a plurality of bottom channel members, and a plurality of top channel members disposed above the plurality of bottom channel members.

5. The method according to claim 4, wherein: Each of the two fin structures further includes an insulating layer sandwiched between a topmost bottom channel member of the plurality of bottom channel members and a bottommost top channel member of the plurality of top channel members.

6. A method of forming a semiconductor structure, comprising: providing an intermediate structure including an opening; depositing a dummy fill material over the opening; recessing the dummy filling material to expose sidewalls of the opening; selectively depositing an inhibitor layer over the exposed sidewalls of the opening; selectively removing the dummy fill material; depositing a metal catalyst over the opening after the selectively removing; selectively removing said inhibitor layer after said depositing of said metal catalyst; as well as After the removal of the inhibitor layer, a metal fill layer is deposited over the metal catalyst in the opening.

7. The method according to claim 6, wherein: The selective removal of the inhibitor layer includes using thermal activation.

8. The method according to claim 6, wherein: The selective deposition of the inhibitor layer includes using silane.

9. A semiconductor structure comprising: substrate; a first base fin and a second base fin rising from the substrate; an isolation component disposed above the substrate and between the first base fin and the second base fin; a first plurality of nanostructures disposed above the first substrate fin; a second plurality of nanostructures disposed above the second substrate fin; a gate dielectric layer over the first substrate fin, the first plurality of nanostructures, the second plurality of nanostructures, the second substrate fin, and the isolation feature; a metal nitride layer, located above the gate dielectric layer; as well as a gate filling layer, located above the metal nitride layer, The upper portion of the gate filling layer is in direct contact with the metal nitride layer, and the lower portion of the gate filling layer is separated from the metal nitride layer by a metal liner.

10. The semiconductor structure according to claim 9, wherein: The metal liner includes Ru, Co, Mo, Pd, Pt, Au, or Ir.

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