Semiconductor device and integrated circuit including same

Abstract

A semiconductor device may include a diode pattern including a first conductive region and a second conductive region having opposite conductive types on a base insulating layer; an insulating layer covering the diode pattern on the base insulating layer; a wiring portion on the insulating layer; and a through connector extending through the insulating layer at a periphery of the diode pattern to electrically connect the diode pattern and the wiring portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0145953 filed in the Korean Intellectual Property Office on October 27, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device and an integrated circuit including the semiconductor device. Background Art

[0004] Semiconductor devices can be miniaturized and perform various functions, so they are used in various electronic devices such as storage devices that store data and processors that calculate and process data. With the development of the electronics industry, various studies continue to improve various performances of semiconductor devices such as integration, reliability, speed and functionality.

[0005] Conventionally, in an integrated circuit including various semiconductor devices, there is a limit to improving the performance of the various semiconductor devices due to limitations of a manufacturing process. Summary of the invention

[0006] Some example embodiments provide a semiconductor device capable of improving performance and productivity and an integrated circuit including the semiconductor device.

[0007] According to an example embodiment of the present disclosure, a semiconductor device may include: a diode pattern on a base insulating layer, the diode pattern including a first conductive region and a second conductive region having conductivity types opposite to each other; an insulating layer covering the diode pattern on the base insulating layer; a wiring portion on the insulating layer; and a through connector extending through the insulating layer at the periphery of the diode pattern to electrically connect the diode pattern and the wiring portion.

[0008] According to an example embodiment of the present disclosure, a semiconductor device may include: a diode pattern, on a base insulating layer, the diode pattern including a first conductive region and a second conductive region having conductivity types opposite to each other; an insulating layer, covering the diode pattern on the base insulating layer; a wiring portion, on the insulating layer; and a connector, electrically connecting a side surface or a rear surface of the diode pattern with the wiring portion.

[0009] According to an example embodiment of the present disclosure, an integrated circuit may include: a base insulating layer having a first region and a second region; a first semiconductor device in the first region; and a second semiconductor device in the second region, the second semiconductor device including a back side power distribution network (BSPDN) structure, the BSPDN structure including a rear wiring portion, the rear wiring portion including a rear contact via extending through the base insulating layer. The first semiconductor device includes: a diode pattern on the base insulating layer, the diode pattern including a first conductive region and a second conductive region having conductive types opposite to each other; an insulating layer covering the diode pattern on the base insulating layer; a wiring portion on the insulating layer; and a through connector extending through the insulating layer at the periphery of the diode pattern and electrically connecting the diode pattern to the wiring portion.

[0010] According to example embodiments, the performance of a semiconductor device can be improved by simplifying the structure of a semiconductor device including a diode having a body-less structure and improving resistance. In addition, the semiconductor device can be manufactured through a relatively easy manufacturing process, thereby improving the productivity of the semiconductor device.

[0011] Furthermore, the structure of an integrated circuit including the above-described semiconductor device and the semiconductor device having a back-side power distribution network structure can be simplified, and the integrated circuit can be formed through a relatively easy manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a plan view illustrating a first semiconductor device according to example embodiments.

[0013] Figure 2 is along Figure 1 A cross-sectional view taken along line II′.

[0014] Figure 3 is shown along Figure 1 XX′ in FIG. 5 is a cross-sectional view of the first semiconductor device and the second semiconductor device.

[0015] Figure 4 is shown along Figure 1 2 is a cross-sectional view of the first semiconductor device and the second semiconductor device taken along line YY′ in FIG.

[0016] Figures 5 to 17 is a cross-sectional view illustrating a method of manufacturing an integrated circuit including a first semiconductor device according to example embodiments.

[0017] Fig.18 is a plan view illustrating a first semiconductor device according to example embodiments.

[0018] Fig.19 is along Fig.18A cross-sectional view taken along line AA.

[0019] Fig. 20 is shown along Fig.18 BB′ is a cross-sectional view of the first semiconductor device and the second semiconductor device.

[0020] Figure 21 to Figure 24 is a cross-sectional view illustrating a method of manufacturing an integrated circuit including a first semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0021] Hereinafter, some exemplary embodiments of the present disclosure will be described more fully with reference to the accompanying drawings so that those skilled in the art to which the present disclosure belongs can easily practice the present disclosure. The present disclosure can be implemented in various different forms and is not limited to the exemplary embodiments provided herein.

[0022] In order to clearly describe the present disclosure, parts irrelevant to the description are omitted, and the same or similar components are denoted by the same reference numerals throughout the specification.

[0023] In addition, since the sizes and thicknesses of the parts, regions, components, units, layers, films, etc. shown in the drawings may be arbitrarily shown for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of the parts, regions, components, units, layers, films, etc. may be enlarged or exaggerated for ease of description and / or simple illustration.

[0024] It should be understood that when a component such as a layer, film, region, or substrate is referred to as being "on" another component, it can be directly on the other component or intervening components may also be present. In contrast, when a component is referred to as being "directly on" another component, there are no intervening components. Furthermore, when a component is referred to as being "on" or "above" a reference component, the component may be located above or below the reference component and is not necessarily "on" or "above" the reference component in an opposite direction of gravity.

[0025] In addition, unless explicitly described to the contrary, the words “comprise,” “include,” or “contain,” and variations such as “comprising,” “including,” “comprising,” “including,” and the like, will be understood to imply the inclusion of other components rather than the exclusion of any other components.

[0026] Furthermore, throughout the specification, the phrases "on a plane," "in a plane," "on a plan view," or "in a plan view" may indicate a situation where a part is viewed from above or from the top, and the phrases "on a section" or "in a section view" may indicate a vertical section viewed from the side.

[0027] Although the terms "same", "equal" or "identical" are used in the description of the exemplary embodiments, it should be understood that some imprecision may exist. Therefore, when an element is referred to as being the same as another element, it should be understood that the element or value is the same as the other element within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0028] When the terms "about," "substantially," or "approximately" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "about," "substantially," or "approximately" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the tolerance for the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified to "about" or "substantially," it should be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape.

[0029] As used herein, expressions such as "at least one of..." when following a list of elements modify the entire list of elements and do not modify the individual elements of the list. Thus, for example, "at least one of A, B, or C" and "at least one of A, B, and C" both mean A, B, C, or any combination thereof. Likewise, A and / or B means A, B, or A and B.

[0030] In the following, reference will be made to Figures 1 to 4 A semiconductor device and an integrated circuit including the semiconductor device according to example embodiments are described.

[0031] Figure 1 is a plan view showing a first semiconductor device 100 according to example embodiments, and Figure 2 is along Figure 1 For simple illustration and clear understanding, Figure 1 (a) shows the diode pattern 14 and the through connector 50, and Figure 1 (b) shows the diode pattern 14 , the through connector 50 , and the wiring portion 60 .

[0032] Reference Figure 1 and Figure 2 , the first semiconductor device 100 according to the example embodiment includes a diode pattern 14 on a base insulating layer 10, an insulating layer 40 (e.g., a first insulating layer 44), a through connector 50, and a wiring portion 60. As an example, the first semiconductor device 100 may be a pn diode having a bodyless structure. This will be described in more detail.

[0033] In example embodiments, the base insulating layer 10 may be in the lower portion of the first semiconductor device 100 to support the diode pattern 14, the insulating layer 40, the through connector 50, and the wiring portion 60. In example embodiments, the base insulating layer 10 may be in the entire lower portion of the first semiconductor device 100. For example, the base insulating layer 10 may have a plane (XY plane in the figure) extending in a first direction (X-axis direction in the figure) and a second direction (Y-axis direction in the figure) that are transverse or cross each other (e.g., perpendicular to each other), and may have a desired (or alternatively, predetermined) thickness in a third direction (Z-axis direction in the figure).

[0034] The diode pattern 14 on the base insulating layer 10 may have a structure separated in the second direction (the Y-axis direction in the figure). For example, in the case where a plurality of diode patterns 14 are arranged along the second direction, the diode patterns 14 may be on the base insulating layer 10, but may have individual patterns separated from each other. That is, after removing the semiconductor substrate 10p having the diode pattern 14 (see Figure 6 ) of the main part 12 (see Figure 6 ), a base insulating layer 10 is formed in a region where the body portion 12 has been removed, so that the first semiconductor device 100 has a body-less structure.

[0035] The base insulating layer 10 may include any of various insulating materials. For example, the base insulating layer 10 may include silicon oxide (SiO x ), silicon nitride (SiN x ), Silicon Oxynitride (SiON x ) or a combination thereof, but example embodiments are not limited thereto.

[0036] The rear insulating layer 78 (see Figure 3 ) may also be on one surface (eg, the lower surface) of the base insulating layer 10. When referring to Figure 3 When describing the second semiconductor device 200 , the rear insulating layer 78 will be described. However, example embodiments are not limited thereto, and the rear insulating layer 78 may not be provided.

[0037] The diode pattern 14 including the first conductive region 14 a and the second conductive region 14 b having opposite conductivity types may be on the second surface (eg, the front surface or the top surface) of the base insulating layer 10 .

[0038] The first conductive region 14a and the second conductive region 14b may each include a semiconductor substrate including a semiconductor material. For example, the first conductive region 14a or the second conductive region 14b may include at least one of a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the first conductive region 14a or the second conductive region 14b may include at least one of Si, Ge, SiGe, SiC, GaAs, InAs, or InP.

[0039] At this time, the first conductive region 14a or the second conductive region 14b may include a crystalline semiconductor substrate (e.g., a single crystal semiconductor substrate or a polycrystalline semiconductor substrate). As another example, the first conductive region 14a or the second conductive region 14b may include an epitaxial semiconductor layer. In this way, when the first conductive region 14a and the second conductive region 14b constituting the diode pattern 14 include a crystalline semiconductor material, the electrical characteristics of the first semiconductor device 100 may be improved.

[0040] The first conductive region 14a may include a semiconductor material doped with a dopant of a first conductive type (e.g., one of a p-type or an n-type) to have a first conductive type (e.g., one of a p-type or an n-type), and the second conductive region 14b may include a semiconductor material doped with a dopant of a second conductive type (e.g., the other of the n-type or the p-type) to have a second conductive type (e.g., the other of the n-type or the p-type). The first conductive region 14a and the second conductive region 14b adjacent to each other may form a unit diode pattern, which forms a pn diode.

[0041] In example embodiments, the diode pattern 14 may have a shape extending longitudinally in a first direction (X-axis direction in the figure), and a plurality of diode patterns 14 may be spaced apart from each other at regular intervals in a second direction (Y-axis direction in the figure) transverse to the first direction. For example, a plurality of diode patterns 14 each having a constant width in the first direction and a desired (or alternatively, predetermined) thickness in a third direction (Z-axis direction in the figure) may be spaced apart from each other in the second direction on the base insulating layer 10.

[0042] In each diode pattern 14, the first conductive region 14a and the second conductive region 14b may be adjacent to each other in the first direction. As an example, each diode pattern 14 may include a plurality of first conductive regions 14a and a plurality of second conductive regions 14b alternating in the first direction. That is, each diode pattern 14 may include a plurality of unit diode patterns.

[0043] In the drawings and the above description, each diode pattern 14 includes a plurality of unit diode patterns, and a plurality of diode patterns 14 are provided. In some example embodiments, the diode pattern 14 may include one unit diode pattern or one diode pattern 14 .

[0044] In the accompanying drawings, it is shown that the plurality of first conductive regions 14a included in each diode pattern 14 have the same area, and the plurality of second conductive regions 14b included in each diode pattern 14 have the same area. In addition, in the plurality of diode patterns 14 in the second direction, the first conductive regions 14a and the second conductive regions 14b have the same area and are at the same position. However, example embodiments are not limited thereto. In some example embodiments, the first conductive regions 14a included in each diode pattern 14 may have different areas, and / or the second conductive regions 14b included in each diode pattern 14 may have different areas. In some example embodiments, in the plurality of diode patterns 14 in the second direction, the first conductive regions 14a and / or the second conductive regions 14b may have different areas, or be at different positions. Many other variations are possible.

[0045] In the drawings, it is shown that the length of the first conductive region 14a or the second conductive region 14b in the first direction (the X-axis direction in the drawings) is greater than the width of the first conductive region 14a or the second conductive region 14b in the second direction (the Y-axis direction in the drawings). Accordingly, the through connector 50 may have a relatively large pitch. However, example embodiments are not limited thereto, and the length of the first conductive region 14a or the second conductive region 14b may be equal to or less than the width of the first conductive region 14a or the second conductive region 14b.

[0046] An insulating layer 40 (more specifically, a first insulating layer 44 ) covering the diode pattern 14 may be on the base insulating layer 10 . Figure 4 as well as Figure 1 and Figure 2 In example embodiments, the first insulating layer 44 may include a first insulating portion 44a and a second insulating portion 44b. The first insulating portion 44a may be on the base insulating layer 10, and the second insulating portion 44b may be on the diode pattern 14. The second insulating portion 44b may also be referred to as an upper insulating portion.

[0047] The first insulating portion 44a and the second insulating portion 44b may be formed by different processes. For example, the second insulating portion 44b may be formed by removing a layer (eg, stacked structure 20 (see FIG. 1 )) on the diode pattern 14. Figure 6 , the same below)) and an insulating material is formed in the corresponding portion. The stacked structure 20 can be used to form a second semiconductor device 200 (see Figure 3 ). In the first semiconductor device 100 according to example embodiments, an undesirable current path may be formed by the stack structure 20, and therefore, the stack structure 20 may be removed and the second insulating portion 44b may be formed. The boundary between the first insulating portion 44a and the second insulating portion 44b may be seen, or may not be clearly seen.

[0048] The first insulating portion 44a and the second insulating portion 44b may include one or more layers. The multiple layers included in the first insulating portion 44a or the second insulating portion 44b may include the same material or different materials. The boundaries between the multiple layers included in the first insulating portion 44a or the second insulating portion 44b may be seen, or may not be clearly seen. The first insulating portion 44a and the second insulating portion 44b may have the same material or different materials. For example, the first insulating portion 44a or the second insulating portion 44b may include at least one of silicon oxide, silicon nitride, silicon oxynitride or a low dielectric constant material. However, example embodiments are not limited to the above-mentioned structures or materials of the first insulating layer 44, the first insulating portion 44a or the second insulating portion 44b.

[0049] In example embodiments, the second insulating portion 44b may have portions with different widths, and the side surface of the second insulating portion 44b may have a step. For example, the width in the second direction (the Y-axis direction in the figure) may be greater in the upper portion than in the lower portion, and a step in which the width in the second direction changes may be provided between the lower portion and the lower portion at the side surface of the second insulating portion 44b. This may be due to the formation of the opening 42c (see Fig.12 ) process. This will be described in more detail later in the method for manufacturing the first semiconductor device 100. However, example embodiments are not limited thereto. The side surface of the second insulating portion 44b may be an inclined surface or a vertical surface that extends continuously, and a step may not be provided at the side surface.

[0050] The wiring portion 60 may be on the first insulating layer 44. Since the wiring portion 60 is at an upper portion of the first semiconductor device 100, the wiring portion 60 may also be referred to as an upper wiring portion or a front wiring portion.

[0051] The wiring portion 60 may include a first wiring layer 64, a contact via 62 connecting the through connector 50 and the first wiring layer 64, and an upper insulating layer 68 at least at the periphery of the contact via 62 and the first wiring layer 64 in a portion where the contact via 62 and the first wiring layer 64 are not arranged.

[0052] For simple illustration and clear understanding, the figure shows that the first wiring layer 64 includes a first layer connected to the through connector 50 through the contact via 62. In the accompanying drawings, it is shown that the upper insulating layer 68 is on the insulating layer 40, and the upper insulating layer 68 includes a first upper insulating layer 68a on the same layer as the contact via 62, and a second upper insulating layer 68b on the first upper insulating layer 68a and on the same layer as the first wiring layer 64. However, the example embodiments are not limited to this. The first wiring layer 64 may also include one or more additional wiring layers connected to the first layer through the contact via 62, with an insulating layer disposed therebetween. Alternatively, the stacking structure and shape of the upper insulating layer 68 may be modified in various ways.

[0053] For example, the first upper insulating layer 68a or the second upper insulating layer 68b may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant material. However, example embodiments are not limited to the foregoing, and the first upper insulating layer 68a or the second upper insulating layer 68b may include any of various materials or have any of various structures. The boundary between the first upper insulating layer 68a and the second upper insulating layer 68b may be seen, or may not be clearly seen.

[0054] The through connector 50 may be at the periphery of the diode pattern 14 to extend through the insulating layer 40 (more specifically, the first insulating layer 44) and electrically connect the diode pattern 14 and the first wiring layer 64. For example, the through connector 50 may contact the diode pattern 14 and the contact via 62. In this case, the through connector 50 may include a first through connector 50a connected to the first conductive region 14a, and a second through connector 50b connected to the second conductive region 14b.

[0055] In example embodiments, the first conductive region 14a and the second conductive region 14b may be adjacent to each other in the first direction (the X-axis direction in the figure). In addition, the first through connector 50a may be located at a portion where the first conductive region 14a is located when viewed in the first direction, and may be located at a first side ( 14b ) of the diode pattern 14 in the second direction (the Y-axis direction in the figure). Figure 1 The second through connector 50b may be located at a portion where the second conductive region 14b is located when viewed in the first direction, and may be located at a second side ( 100 ) of the diode pattern 14 opposite to the first side of the diode pattern 14 in the second direction (the Y-axis direction in the figure). Figure 1 That is, when viewed in the second direction, the first through connector 50a and the second through connector 50b may be on two sides opposite to each other while positioning the diode pattern 14 at the center.

[0056] For example, the first through connector 50a may correspond to the center portion of the first conductive region 14a in the first direction, and the second through connector 50b may correspond to the center portion of the second conductive region 14b in the first direction. Accordingly, the first through connector 50a and the first conductive region 14a may be stably connected, and the second through connector 50b and the second conductive region 14b may be stably connected.

[0057] In this case, a plurality of first through connectors 50 a electrically connected to the plurality of first conductive regions 14 a may be disposed at a first side of the diode pattern 14 , and a plurality of second through connectors 50 b electrically connected to the second conductive regions 14 b may be disposed at a second side of the diode pattern 14 .

[0058] In the first direction, the first through connector 50a and the second through connector 50b at opposite sides can be connected from the first end ( Figure 1 ) to the second end ( Figure 1 For example, the first through connector 50a and the second through connector 50b may be arranged in a zigzag shape.

[0059] In example embodiments, a voltage or power for operating the first semiconductor device 100 may be applied through the first wiring layer 64. The first wiring layer 64 may include a first wiring portion 64a extending along a first direction at a first side of the diode pattern 14 to be electrically connected to the plurality of first through connectors 50a, and a second wiring portion 64b extending along the first direction at a second side of the diode pattern 14 to be electrically connected to the plurality of second through connectors 50b.

[0060] For example, the plurality of first through connectors 50a and the first wiring portions 64a may be electrically connected through the plurality of contact vias 62, each contact via 62 overlapping with a corresponding one of the first through connectors 50a and the first wiring portions 64a. Similarly, the plurality of second through connectors 50b and the second wiring portions 64b may be connected through the plurality of contact vias 62, each contact via 62 overlapping with a corresponding one of the second through connectors 50b and the second wiring portions 64b.

[0061] Because the plurality of first through connectors 50 a and the plurality of second through connectors 50 b are on opposite sides of the diode pattern 14 , the first wiring portions 64 a connected to the plurality of first through connectors 50 a and the second wiring portions 64 b connected to the plurality of second through connectors 50 b may be located on opposite sides of each other based on the diode pattern 14 .

[0062] For example, the diode pattern 14, the first wiring portion 64a and the second wiring portion 64b may all have a straight or linear shape extending in the first direction (X-axis direction in the figure). Therefore, the connection structure of the first wiring layer 64 connected to the through connector 50 can be simplified.

[0063] For example, the contact vias 62 or the first wiring layers 64 included in the wiring portion 60 may include at least one of titanium, tungsten, nickel, cobalt, tantalum, molybdenum, copper, aluminum, gold, tin, manganese, ruthenium, beryllium or an alloy thereof. Each first wiring layer 64 may include one or more layers.

[0064] For example, the first through connector 50a or the second through connector 50b included in the through connector 50 may include at least one of titanium, tungsten, nickel, cobalt, tantalum, molybdenum, copper, aluminum, gold, tin, manganese, ruthenium, beryllium, or alloys thereof.

[0065] In example embodiments, the side surface of the through connector 50 may have an inclined surface such that the width of the through connector 50 decreases from the front surface to the rear surface of the through connector 50. However, example embodiments are not limited thereto, and the side surface of the through connector 50 may have a vertical surface or other shapes.

[0066] For example, the length of the first conductive region 14a in the first direction may be greater than the width of the first through connector 50a in the first direction, and the length of the second conductive region 14b in the first direction may be greater than the width of the second through connector 50b in the first direction. The width of the first through connector 50a in the second direction may be greater than the width of the contact via 62 or the first wiring portion 64a connected to the first through connector 50a, and the width of the second through connector 50b in the second direction may be greater than the width of the contact via 62 or the second wiring portion 64b connected to the second through connector 50a. Therefore, the first through connector 50a or the second through connector 50b may be stably formed, and the electrical connection characteristics may be improved, but example embodiments are not limited thereto. In some example embodiments, the length of the first conductive region 14a or the second conductive region 14b in the first direction may be equal to or less than the width of the first through connector 50a or the second through connector 50b in the first direction. In some example embodiments, the width of the first through connector 50a or the second through connector 50b in the second direction may be equal to or smaller than the width of the contact via 62 connected to the first through connector 50a or the second through connector 50b, or the first wiring portion 64a or the second wiring portion 64b.

[0067] In example embodiments, the side surface of the diode pattern 14 and the side surface of the through connector 50 may be connected to each other (e.g., in contact with each other). More specifically, in the second direction, the first side surface 141 (e.g., the first conductive region 14a) of the diode pattern 14 and the side surface of the first through connector 50a may be connected to each other (e.g., in contact with each other). In addition, in the second direction, the second side surface 142 (e.g., the second conductive region 14b) of the diode pattern 14 and the side surface of the second through connector 50b may be connected to each other (e.g., in contact with each other). Therefore, the current path may be effectively reduced.

[0068] The center of the first through connector 50a may be at a distance from the center of the diode pattern 14 in the second direction, and the side surface of the first through connector 50a may be in contact with the first side surface 141 of the first conductive region 14a. For example, in a plan view, a recessed portion 14r may be provided on the first side surface 141 of the first conductive region 14a, and the first through connector 50a may fill the recessed portion 14r. This is because the first through portion for forming the first through connector 50a is formed to overlap with a portion of the first conductive region 14a, and then, the first through portion is filled with a metal material to form the first through connector 50a. That is, the first through connector 50a may be formed so that the recessed portion 14r is provided on the first side surface 141 of the first conductive region 14a to stably connect the first side surface 141 of the first conductive region 14a and the side surface of the first through connector 50a.

[0069] Similarly, the center of the second through connector 50b is located at a distance from the center of the diode pattern 14 in the second direction, and the side surface of the second through connector 50b may be in contact with the second side surface 142 of the second conductive region 14b. For example, in a plan view, a recessed portion 14r may be provided on the second side surface 142 of the second conductive region 14b, and the second through connector 50b may fill the recessed portion 14r.

[0070] For example, the distance between the center of the first through connector 50a or the second through connector 50b and the center of the diode pattern 14 in the second direction may be about 100 nm or less (e.g., about 1 nm to about 100 nm), but example embodiments are not limited thereto. While maintaining the connection between the first through connector 50a or the second through connector 50b and the diode pattern 14, the distance between the center of the first through connector 50a or the second through connector 50b and the center of the diode pattern 14 may exceed about 100 nm.

[0071] In this case, the metal-semiconductor compound layer 14s may be at a boundary between the first side surface 141 of the first conductive region 14a and the side surface of the first through connector 50a. That is, the first through connector 50a may be electrically connected to the first conductive region 14a through the metal-semiconductor compound layer 14s. Similarly, the metal-semiconductor compound layer 14s may be at a boundary between the second side surface 142 of the second conductive region 14b and the side surface of the first through connector 50a. That is, the second through connector 50b may be electrically connected to the second conductive region 14b through the metal-semiconductor compound layer 14s.

[0072] The metal-semiconductor compound layer 14s may include a compound of a metal and a semiconductor material included in the diode pattern 14. For example, the metal-semiconductor compound layer 14s may include a metal silicide, for example, at least one of titanium silicide, tungsten silicide, nickel silicide, cobalt silicide, tantalum silicide, or molybdenum silicide. The metal included in the metal-semiconductor compound layer 14s may be the same as or different from the metal included in the through connector 50. Therefore, example embodiments are not limited to the materials of the above-described metal-semiconductor compound layer 14s.

[0073] The metal-semiconductor compound layer 14s at the boundary between the first side surface 141 of the first conductive region 14a and the side surface of the first through connector 50a, and the metal-semiconductor compound layer 14s at the boundary between the second side surface 142 of the second conductive region 14b and the side surface of the second through connector 50b may include the same material as each other. However, example embodiments are not limited thereto. The metal-semiconductor compound layer 14s at the boundary between the first side surface 141 of the first conductive region 14a and the side surface of the first through connector 50a, and the metal-semiconductor compound layer 14s at the boundary between the second side surface 142 of the second conductive region 14b and the side surface of the second through connector 50b may include different materials.

[0074] The first semiconductor device 100 may form a pn diode. In this case, the first semiconductor device 100 may have a bodyless structure in which the diode pattern 14 is on the base insulating layer 10. The first semiconductor device 100 having a bodyless structure may be connected to a second semiconductor device 200 having a back side power distribution network (BSPDN) structure (see Figure 3 ) are set together in an integrated circuit. This will be referred to later Figure 3 and Figure 4 Describe in more detail.

[0075] According to example embodiments, the first semiconductor device 100 having a body-less structure may include a diode pattern 14, a through connector 50, and a wiring portion 60, and may not include a gate electrode 32a included in the second semiconductor device 200 (see Figure 3 ), and source and drain patterns 34 (see Figure 3 ). Therefore, the structure can be simplified to have a short current path, and the diode pattern 14 and the through-connection portion 50 can have a sufficient connection area, and therefore, the resistance of the first semiconductor device 100 can be improved. In addition, the first semiconductor device 100 can be manufactured by a simple manufacturing process. Therefore, the performance and productivity of the first semiconductor device 100 can be improved.

[0076] On the contrary, if the pn diode with a non-main structure includes a gate structure and a source and drain pattern included in the second semiconductor device 200, the current path of the pn diode may include a source and drain pattern. Therefore, the source and drain pattern may be on the current path of the pn diode, thereby increasing the resistance due to the resistance of the source and drain pattern. In addition, the pn diode and the wiring layer may be electrically connected through the source and drain pattern and the first contact portion connected to the source and drain pattern. Then, the connection area between the source and drain pattern and the first contact portion is small, so reducing the resistance of the pn diode is limited. In addition, due to the change in the energy band gap caused by the gate electrode, tunneling leakage may occur. In order to reduce or prevent this problem, a process of replacing the gate electrode provided in the pn diode with an insulating layer may be performed, and then, the manufacturing process may be more complicated.

[0077] As described above, the first semiconductor device 100 having a bodyless structure may be provided in an integrated circuit together with the second semiconductor device 200 having a back side power distribution network (BSPDN) structure. Figure 3 and Figure 4 as well as Figure 1 and Figure 2 An integrated circuit including a first semiconductor device 100 and a second semiconductor device 200 is described.

[0078] Figure 3 is shown along Figure 1 A cross-sectional view of the first semiconductor device and the second semiconductor device taken along line XX′ in FIG. Figure 4 is shown along Figure 1 The first semiconductor device is a cross-sectional view of the first semiconductor device and the second semiconductor device taken along the line YY′ in FIG. Figure 3 (a) and Figure 4 As shown in (a), and the second semiconductor device is as shown in Figure 3 (b) and Figure 4In this case, Figure 3 A cross section (XZ plane in the figure) perpendicular to the second direction (Y-axis direction in the figure) is shown, and Figure 4 is a cross section (YZ plane in the figure) perpendicular to the first direction (X axis direction in the figure). Figure 4 In (b), the source and drain pattern 34 is shown in a cross section (YZ plane of the figure) perpendicular to the first direction (X-axis direction in the figure), and the second wiring layer 66 and the third through connector 50c connected to the source and drain pattern 34 are conceptually shown.

[0079] Reference Figure 3 and Figure 4 In example embodiments, the base insulating layer 10 may have a first region A1 and a second region A2. Herein, the first region A1 may refer to a region where the first semiconductor device 100 is located, and the second region A2 may refer to a region where the second semiconductor device 200 is located.

[0080] The base insulating layer 10 in the first area A1 and the second area A2 may include the same material. For example, the base insulating layer 10 in the first area A1 and the second area A2 may be the same layer formed by the same process. However, example embodiments are not limited thereto. In some example embodiments, the base insulating layer in the first area A1 and the base insulating layer in the second area A2 may include different materials or may be formed by different processes.

[0081] The above description may be applied to the first semiconductor device 100 in the first area A1 .

[0082] The second semiconductor device 200 in the second area A2 may include active patterns 16 and 26, a gate structure 32, source and drain patterns 34, an insulating layer 40 (e.g., a second insulating layer 46), a through connector 50, a wiring portion 60, and a rear wiring portion 70 on the base insulating layer 10. In this case, the rear wiring portion 70 may include a rear contact via 72 extending through the base insulating layer 10. As an example, the second semiconductor device 200 may have a bodyless structure and a BSPDN structure.

[0083] The active patterns 16 and 26 may be on the base insulating layer 10. Portions of the active patterns 16 and 26 overlapping the gate structure 32 may form a channel region of the transistor.

[0084] The active patterns 16 and 26 may include a lower pattern 16 , and a plurality of channel layers 26 on the lower pattern 16 .

[0085] In example embodiments, at least a portion of the active patterns 16 and 26 (e.g., the lower pattern 16) may have a shape that extends longitudinally along a first direction (X-axis direction in the figure) on the base insulating layer 10. As an example, a plurality of channel layers 26 may be spaced apart from each other in the first direction. In addition, the active patterns 16 and 26 may be spaced apart from each other at regular intervals in a second direction (Y-axis direction in the figure).

[0086] A plurality of channel layers 26 may be on the lower pattern 16 and spaced apart from each other in the thickness direction (Z-axis direction in the figure). Each of the plurality of channel layers 26 may have a nanosheet-shaped channel pattern having a thickness of nanometer scale (e.g., 1 nm to 10 nm), and may be a semiconductor pattern containing a semiconductor material. The embodiment is not limited thereto, and the shape of the channel layer 26 may be modified in various ways, and the thickness of the channel layer 26 may be less than 1 nm or greater than 10 nm.

[0087] The lower pattern 16 may include a crystalline semiconductor substrate (e.g., a single crystal semiconductor substrate or a polycrystalline semiconductor substrate) including a semiconductor material. In some example embodiments, the lower pattern 16 may include a crystalline semiconductor substrate (e.g., a single crystal semiconductor substrate or a polycrystalline semiconductor substrate), and an epitaxial layer grown from the crystalline semiconductor substrate and including a semiconductor material. The channel layer 26 may include an epitaxial layer including a semiconductor material.

[0088] For example, the semiconductor substrate disposed in the lower pattern 16 may include at least one of a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the semiconductor substrate disposed in the lower pattern 16 may include at least one of Si, Ge, SiGe, SiC, GaAs, InAs, or InP. The semiconductor substrate and / or the epitaxial layer disposed in the lower pattern 16 may include the same semiconductor material as the semiconductor substrate and / or the epitaxial layer disposed in the diode pattern 14.

[0089] For example, the channel layer 26 may include at least one of a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. In this case, the channel layer 26 may include at least one of Si, Ge, SiGe, SiC, GaAs, InAs, or InP, for example, at least one of Si, Ge, or SiGe. Each channel layer 26 may include the same material as the lower pattern 16, or a different material from the lower pattern 16.

[0090] For example, the lower pattern 16 and the channel layer 26 may include Si or SiGe. In some example embodiments, the lower pattern 16 may include Si, and the channel layer 26 may include SiGe. Many other variations are possible.

[0091] The material of the lower pattern 16 , the shape, thickness or material of the channel layer 26 , or the number of the plurality of channel layers 26 constituting one channel structure may be changed in various ways.

[0092] The gate structures 32 may cross the active patterns 16 and 26 and may extend in the second direction (the Y-axis direction in the drawing). A plurality of gate structures 32 may be spaced apart from each other in the first direction (the X-axis direction in the drawing).

[0093] The gate structure 32 may include a gate electrode 32 a , a gate insulating layer 32 b , a gate spacer 32 c , and a gate capping layer 32 d .

[0094] The gate electrode 32a may be on the active patterns 16 and 26 including the plurality of channel layers 26 while completely surrounding each of the plurality of channel layers 26. The gate electrodes 32a may be separated from each other in the second direction (the Y-axis direction in the figure) according to the circuit configuration of the first semiconductor device 100. For example, the gate electrode 32a may be separated into a plurality of gate electrodes 32a in the second direction by a separate gate separation portion (not shown) in the gate electrode 32a.

[0095] The gate insulating layer 32b may be between the gate electrode 32a and the channel layer 26. In example embodiments, the gate insulating layer 32b may be between the active patterns 16 and 26 and the gate electrode 32a, and may also be between the gate electrode 32a and the gate spacer 32c.

[0096] The gate spacer 32c may be on the side surface of the gate electrode 32a to insulate the gate electrode 32a from the source and drain pattern 34 and / or the first contact portion 52. For example, the gate spacer 32c may be on the side surface of the gate electrode 32a at the upper portion of the active patterns 16 and 26, but may not be on the side surface of the channel layer 26 constituting the active patterns 16 and 26. The gate spacer 32c may extend in the second direction (the Y-axis direction in the figure) at both side surfaces of the gate electrode 32a in the first direction (the X-axis direction in the figure).

[0097] The gate capping layer 32d may be on the gate electrode 32a. Figure 3 In (b), it is shown that the gate spacer 32c is on the side surface of the gate capping layer 32d. In some example embodiments, the gate capping layer 32d may be on the gate spacer 32c. In example embodiments, the front surface of the gate capping layer 32d may be on the same plane as the front surface of the first contact portion 52 or the insulating layer 40. However, example embodiments are not limited thereto. Therefore, the front surface of the gate capping layer 32d may be on a different plane from the front surface of the first contact portion 52 or the insulating layer 40.

[0098] The gate electrode 32a may include a conductive material. For example, the gate electrode 32a may include at least one of a metal, a metal alloy, a metal nitride, a metal silicide, or a doped semiconductor material. Here, the metal or metal alloy included in the gate electrode 32a may include at least one of tungsten, molybdenum, aluminum, copper, or cobalt, and the metal nitride included in the gate electrode 32a may include at least one of tungsten nitride, molybdenum nitride, titanium nitride, or tantalum nitride. The gate electrode 32a may also include an oxidized metal oxide or metal oxynitride including the above materials, or the gate electrode 32a may include multiple layers.

[0099] The gate insulating layer 32b may include oxide, nitride or high dielectric constant material. The high dielectric constant material may refer to a dielectric material having a higher dielectric constant than silicon oxide. For example, the gate insulating layer 32b may include at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide layer, aluminum oxide layer or tantalum oxide layer. The gate insulating layer 32b may include multiple insulating layers.

[0100] The gate spacer 32c may include at least one of silicon oxide, silicon nitride or silicon oxynitride, or may further include carbon. For example, the gate spacer 32c may include a low dielectric constant material. The gate spacer 32c may include multiple layers. The gate capping layer 32d may include at least one of silicon oxide, silicon nitride or silicon oxynitride.

[0101] However, example embodiments are not limited to the above, and the gate electrode 32 a , the gate insulating layer 32 b , the gate spacer 32 c , or the gate capping layer 32 d may include any of various materials or may have any of various structures.

[0102] The source and drain patterns 34 may be on both sides of the active patterns 16 and 26 and / or the gate structure 32. In this case, the source and drain patterns 34 may be adjacent to both sides of the active patterns 16 and 26 in a first direction (X-axis direction in the figure) and may constitute a source region or a drain region of a transistor.

[0103] The source and drain pattern 34 may include an epitaxial layer formed by a selective epitaxial growth (SEG) process at recessed portions of the active patterns 16 and 26. The source and drain pattern 34 may have an angular shape, but example embodiments are not limited thereto and may have various shapes such as polygonal, circular, elliptical, and circular shapes.

[0104] For example, the source and drain pattern 34 may include at least one of Si, Si-Ge, or SiC, and may further include a dopant such as arsenic (As) or phosphorus (P). In some example embodiments, the source and drain pattern 34 may include a plurality of portions having different materials or different compositions. However, example embodiments are not limited to the foregoing, and the source and drain pattern 34 may include any of various materials, or have any of various structures.

[0105] An insulating layer 40 (eg, a second insulating layer 46 ) covering at least portions of the active patterns 16 and 26 and the source and drain patterns 34 may be on the base insulating layer 10 .

[0106] For example, the second insulating layer 46 may include a third insulating portion 46a and a fourth insulating portion 46b. The third insulating portion 46a may be on the base insulating layer 10, and the fourth insulating portion 46b may be between the source and drain pattern 34 and the through connector 50. The fourth insulating portion 46b may be a diffusion interruption, for example, a single diffusion interruption (SDB). The boundary between the third insulating portion 46a and the fourth insulating portion 46b may be seen, or may not be clearly seen. In some example embodiments, an etch stop layer (not shown) may be provided between the source and drain pattern 34 and the second insulating layer 46.

[0107] The third insulating portion 46a or the fourth insulating portion 46b may include one or more layers. The multiple layers included in the third insulating portion 46a or the fourth insulating portion 46b may include the same material or different materials. The boundaries between the multiple layers included in the third insulating portion 46a or the fourth insulating portion 46b may be seen, or may not be clearly seen. The third insulating portion 46a and the fourth insulating portion 46b may have the same material or different materials. For example, the third insulating portion 46a or the fourth insulating portion 46b may include at least one of silicon oxide, silicon nitride, silicon oxynitride or a low dielectric constant material. However, example embodiments are not limited to the above, and the third insulating portion 46a or the fourth insulating portion 46b may include any of various materials, or have any of various structures.

[0108] The second insulating layer 46 (eg, the third insulating portion 46a or the fourth insulating portion 46b) and the first insulating layer 44 (eg, the first insulating portion 44a or the second insulating portion 44b) may include the same material as each other, or may include different materials.

[0109] The wiring portion 60 on the second insulating layer 46 in the second area A2 may include the second wiring layer 66, and the contact via 62 and the upper insulating layer 68. For the contact via 62 and the upper insulating layer 68, the above description of the contact via 62 and the upper insulating layer 68 included in the wiring portion 60 on the first insulating layer 44 in the first area A1 may be applied.

[0110] For the sake of simplicity of illustration and clear understanding, the figure shows that the second wiring layer 66 includes a first layer connected to the through connector 50 through the contact via 62. However, example embodiments are not limited thereto. The second wiring layer 66 may also include one or more additional wiring layers connected to the first layer through the contact via, with an insulating layer disposed therebetween.

[0111] In this case, the first contact portion 52 may extend through the second insulating layer 46 to electrically connect the source and drain pattern 34 with the second wiring layer 66. For example, the first contact portion 52 may contact the source and drain pattern 34 and the contact via 62. The second contact portion 54 may extend through the first upper insulating layer 68a, the second insulating layer 46, and the gate capping layer 32d to electrically connect the gate electrode 32a with the second wiring layer 66. For example, the second contact portion 54 may contact the gate electrode 32a and the contact via 62.

[0112] The first contact portion 52 or the second contact portion 54 may include a single layer or multiple layers. The first contact portion 52 or the second contact portion 54 may include various conductive materials. For example, the first contact portion 52 or the second contact portion 54 may include at least one of a metal, a metal alloy, a metal nitride, a metal silicide, or a doped semiconductor material. Here, the metal or metal alloy included in the first contact portion 52 or the second contact portion 54 may include at least one of titanium, tungsten, nickel, cobalt, tantalum, molybdenum, copper, aluminum, gold, tin, manganese, ruthenium, beryllium, or an alloy thereof. The metal nitride included in the first contact portion 52 or the second contact portion 54 may include at least one of titanium nitride, tungsten nitride, tantalum nitride, or molybdenum nitride. The first contact portion 52 or the second contact portion 54 may also include an oxidized metal oxide or metal nitride including the above-mentioned metal oxide or metal nitride. According to some example embodiments, the first contact portion 52 or the second contact portion 54 may include multiple layers. However, example embodiments are not limited to the above, and the first contact portion 52 or the second contact portion 54 may include any of various materials or may have any of various structures.

[0113] The through connector 50 may be at the periphery of the source and drain pattern 34 to extend through the insulating layer 40 (e.g., the second insulating layer 46), and electrically connect the source and drain pattern 34 with the rear wiring portion 70 via the wiring portion 60. For example, the through connector 50 may contact the contact via 62 and the rear contact via 72 to connect the contact via 62 and the rear contact via 72. In the drawings, it is shown that the through connector 50 in the second area A2 includes a third through connector 50c at one side of the source and drain pattern 34 with the fourth insulating portion 46b interposed therebetween, but example embodiments are not limited thereto.

[0114] The third through connector 50c may be at the periphery of the source and drain pattern 34 and spaced apart from the source and drain pattern 34. The third through connector 50c may be connected to the source and drain pattern 34 through the wiring portion 60.

[0115] The third through connector 50c may be spaced apart a certain distance from the source and drain pattern 34. In some example embodiments, the fourth insulating portion 46b may be located between the third through connector 50c and the source and drain pattern 34 in the first direction. For example, the third through connector 50c may include at least one of titanium, tungsten, nickel, cobalt, tantalum, molybdenum, copper, aluminum, gold, tin, manganese, ruthenium, beryllium, or an alloy thereof.

[0116] The third through-connector 50c may include the same material as the first through-connector 50a or the second through-connector 50b, or may include materials different from each other.

[0117] The second semiconductor device 200 may include a rear wiring portion 70 at one side (more specifically, at a rear surface) where the base insulating layer 10 is formed. The rear wiring portion 70 may include a rear contact via 72 extending through the base insulating layer 10.

[0118] The rear wiring portion 70 as a part of the BSPDN structure supplying power to the second semiconductor device 200 may be included separately from the wiring portion 60 at the front surface of the second semiconductor device 200 .

[0119] The rear wiring portion 70 may include a rear contact via 72, a rear wiring layer 76, and a rear insulating layer 78. The rear contact via 72 may extend through the base insulating layer 10 to be connected to the third through connector 50c. Therefore, power supplied through the rear wiring layer 76 may be supplied to the source and drain pattern 34 via the rear contact via 72, the third through connector 50c, the contact via 62, the second wiring layer 66, the contact via 62, and the first contact portion 52.

[0120] For the sake of simplicity of illustration and clear understanding, the figure shows that the rear wiring layer 76 includes a first layer connected to the through connector 50 through the rear contact via 72. However, example embodiments are not limited thereto. The rear wiring layer 76 may also include one or more additional wiring layers connected to the first layer through the contact via, with an insulating layer disposed therebetween.

[0121] For example, the rear contact via 72 or the rear wiring layer 76 included in the rear wiring portion 70 may include at least one of titanium, tungsten, nickel, cobalt, tantalum, molybdenum, copper, aluminum, gold, tin, manganese, ruthenium, beryllium or its alloy. Each rear wiring layer 76 may include one or more layers. The rear insulating layer 78 may include at least one of silicon oxide, silicon nitride, silicon oxynitride or a low dielectric constant material. However, example embodiments are not limited to the foregoing, and the rear insulating layer 78 may include any of various materials, or have any of various structures.

[0122] In example embodiments, a side surface of the rear contact via 72 may have an inclined surface such that a width of the rear contact via 72 increases from a front surface (eg, top or upper end) toward a rear surface (eg, bottom or lower end).

[0123] In the drawings, the rear insulating layer 78 is shown to be located at a lower portion of the base insulating layer 10 in the first area A1, but example embodiments are not limited thereto. The rear insulating layer 78 may not be located at a lower portion of the base insulating layer 10 in the first area A1. Many other variations are possible.

[0124] According to example embodiments, the first semiconductor device 100 having a bodyless structure and the second semiconductor device 200 having a BSPDN structure have an electrical connection structure through the through connector 50. Therefore, the electrical connection structure can be simplified. That is, the structure of the integrated circuit including the first semiconductor device 100 having a bodyless structure and the second semiconductor device 200 having a BSPDN structure can be simplified, and the integrated circuit can be formed by a simple manufacturing process.

[0125] The second semiconductor device 200 above may be an example, and the example embodiments are not limited thereto. That is, in the above description and the accompanying drawings, the second semiconductor device 200 has been shown as a gate-all-around (GAA) structure or a multi-bridge channel (MBC) structure having four surfaces of the channel layer 26 surrounded by the gate electrode 32a. However, the example embodiments are not limited thereto, and the second semiconductor device 200 may have a finFET structure, a 3D stacked field effect transistor (3DSFET) structure, or a complementary field effect transistor (CFET) structure. Many other variations are possible.

[0126] Will refer to Figures 5 to 17 A first semiconductor device 100 having a bodyless structure is described in detail (see Figure 1 As described above, the first semiconductor device 100 and the second semiconductor device 200 having a BSPDN structure (see Figure 3 ) together form an integrated circuit. Hereinafter, a method for manufacturing the first semiconductor device 100 will be described while describing a method for manufacturing an integrated circuit including the first semiconductor device 100 and the second semiconductor device 200.

[0127] Figures 5 to 17 is a cross-sectional view illustrating a method of manufacturing an integrated circuit including a first semiconductor device according to example embodiments.

[0128] like Figure 5 and Figure 6 As shown, a semiconductor substrate 10 p and a stack structure 20 for forming a first semiconductor device 100 and a second semiconductor device 200 may be formed. Figure 5 and Figure 6 Shown with Figure 4 The corresponding part.

[0129] like Figure 5 As shown, a plurality of sacrificial layers 28 and a plurality of channel layers 26 may be alternately formed on the semiconductor substrate 10 p .

[0130] The semiconductor substrate 10p may be a bulk substrate including a semiconductor material or a semiconductor on an insulator. For example, the semiconductor substrate 10p may include at least one of a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the semiconductor substrate 10p may include at least one of Si, Ge, SiGe, SiC, GaAs, InAs, or InP. For example, the semiconductor on an insulator may be a silicon on insulator (SOI) or a silicon germanium on an insulator (SGOI).

[0131] The channel layer 26 and the sacrificial layer 28 may be formed by epitaxial growth. The channel layer 26 may include a semiconductor material. The sacrificial layer 28 may be removed in a subsequent process to provide a gate insulating layer 32b (see Fig. 9 ) and the gate electrode 32a (see Fig. 9 ) is located in a space. The sacrificial layer 28 may include a material having an etching selectivity to the channel layer 26 relative to the etching material of the channel layer 26. For example, the channel layer 26 may include Si, and the sacrificial layer 28 may include SiGe. However, the channel layer 26 or the sacrificial layer 28 may include any of a variety of materials.

[0132] like Figure 6As shown, the stack structure 20 and the semiconductor substrate 10p including the body portion 12 and the pattern portions 14p and 16p may be formed by forming a trench 20t that partially removes the channel layer 26, the sacrificial layer 28, and the semiconductor substrate 10p.

[0133] In a plan view, each trench 20t may extend in a first direction (X-axis direction in the figure), and a plurality of trenches 20t may be spaced apart from each other at regular intervals in a second direction (Y-axis direction in the figure). In a cross-sectional view, the trench 20t may completely remove the channel layer 26 and the sacrificial layer 28, and may partially remove the semiconductor substrate 10p in a third direction (Z-axis direction in the figure).

[0134] The main body portion 12 of the semiconductor substrate 10p may be a portion where the groove 20t is not formed. The main body portion 12 of the semiconductor substrate 10p may have a desired (or alternatively, predetermined) thickness in the third direction (Z-axis direction in the figure), and may have an area connected as a whole to contain a plane (XY plane in the figure) having a desired (or alternatively, predetermined) size in the first direction (X-axis direction in the figure) and the second direction (Y-axis direction in the figure) in the plan view. In the plan view, each of the pattern portions 14p and 16p may extend along the first direction (X-axis direction in the figure), and a plurality of pattern portions 14p and 16p may be spaced apart from each other at regular intervals in the second direction (Y-axis direction in the figure). In the cross-sectional view, the pattern portions 14p and 16p of the semiconductor substrate 10p may have a shape that partially protrudes upward from the upper portion of the main body portion 12 in the third direction (Z-axis direction in the figure).

[0135] The pattern portions 14p and 16p may constitute the diode pattern 14 (see FIG. 1 ) included in the first semiconductor device 100 in the first area A1. Figure 1 ), and the lower pattern 16 of the active pattern included in the second semiconductor device 200 in the second area A2 (see Figure 1 ).

[0136] The diode pattern 14 may include first conductive regions 14a adjacent to each other in a first direction (X-axis direction in the figure) (see Figure 1 ) and the second conductive region 14b (see Figure 1 ). The lower pattern 16 may include a region having a first conductivity type or a region having a second conductivity type. The first conductive region 14a, the second conductive region 14b, the region having the first conductivity type, and the region having the second conductivity type may be disposed on the semiconductor substrate 10p before forming the trench 20t (e.g., before forming the sacrificial layer 28 and the channel layer 26).

[0137] The stacked structure 20 may include a plurality of sacrificial layers 28 and a plurality of channel layers 26 on the pattern portions 14p and 16p of the semiconductor substrate 10p. The stacked structure 20 may be located on the upper portion of the pattern portions 14p and 16p in a third direction (Z-axis direction in the figure). In a plan view, each stacked structure 20 may extend along a first direction (X-axis direction in the figure), and a plurality of stacked structures 20 may be spaced apart from each other at regular intervals in a second direction (Y-axis direction in the figure).

[0138] The trench 20t may be formed by an etching process performed from a front surface (e.g., a top surface) of the stack structure 20 including the plurality of sacrificial layers 28 and the plurality of channel layers 26. However, example embodiments are not limited thereto, and the formation process of the trench 20t, the pattern portions 14p and 16p, or the stack structure 20 may be modified in various ways.

[0139] As described above, the semiconductor substrate 10 p for forming the first semiconductor device 100 as a diode device and the second semiconductor device 200 as a transistor device are formed together with the stack structure 20 , and thus, the stack structure 20 may be disposed on the diode pattern 14 .

[0140] Then, if Figure 7 As shown, a first insulating portion 44a of the first insulating layer 44 may be formed in the first region A1 (see Fig.13 ). Figure 7 Shown with Figure 4 The corresponding part.

[0141] In example embodiments, the first insulating portion 44a in the first region A1 may fill the trench 20t on the semiconductor substrate 10p and the stacked structure 20. A front surface (e.g., a top surface) of the first insulating portion 44a may be located higher than a front surface (e.g., a top surface) of the stacked structure 20. In some example embodiments, the front surface of the first insulating portion 44a may be located on the same plane as the front surface of the stacked structure 20.

[0142] In this case, the first insulating portion 44a may not be formed in the second region A2, and thus the semiconductor substrate 10p and the stacked structure 20 in the second region A2 may be exposed. Figure 8 and Fig. 9 As shown, a portion included in the second semiconductor device 200 may be formed in the second region A2, while the first insulating portion 44a protects the diode pattern 14 in the first region A1 (see Figure 1 ) or pattern portion 14p.

[0143] For example, the first insulating portion 44a covering the first region A1 while exposing the second region A2 may be the first insulating portion 44a in the first semiconductor device 100. Therefore, by using the first insulating portion 44a covering the first region A1 as it is, the manufacturing process may be easily performed. However, example embodiments are not limited thereto. In some example embodiments, at least a portion of the insulating layer covering the first region A1 while exposing the second region A2 may be replaced with another insulating layer to form the first insulating portion 44a in the first semiconductor device 100.

[0144] Then, if Figures 8 to 10 As shown, the gate structure 32, the source and drain patterns 34, and the third insulating portion 46a of the second semiconductor device 200 may be formed in the second region A2. For clear understanding and brief description, Figure 8 and Fig. 9 Mainly shown are the gate structure 32 and the source and drain patterns 34 . Figure 8 (a) and Fig. 9 (a) shows the Figure 3 The corresponding part of (b), and Figure 8 (b) and Fig. 9 (b) shows the Figure 4 The corresponding part of (b). Fig.10 Shown with Figure 4 The corresponding part.

[0145] like Figure 8 As shown, a dummy gate 32s may be formed on the active patterns 16 and 26. The dummy gate 32s may be replaced by the gate electrode 32 (see FIG. Fig. 9 ) replaced by a layer. For example, the dummy gate 32s may include polysilicon, but example embodiments are not limited thereto. In some example embodiments, gate spacers 32c may also be formed on both sides of the dummy gate 32s. In example embodiments, the dummy gate 32s and / or the gate spacer 32c may extend in a direction intersecting with an extension direction of the active patterns 16 and 26. For example, the dummy gate 32s and / or the gate spacer 32c may extend in a second direction (Y-axis direction in the figure), and a plurality of dummy gates 32s and / or a plurality of gate spacers 32c may be spaced apart from each other in a first direction (X-axis direction in the figure).

[0146] The stacked structure 20 may be etched by an etching process using the dummy gate 32s and / or the gate spacer 32c as a mask, and the lower pattern 16 may be exposed to the outside of the dummy gate 32s and the gate spacer 32c. In some example embodiments, portions of the sacrificial layer 28 exposed to the side surfaces of the dummy gate 32s and the gate spacer 32c are removed to form an internal spacer space, and an internal spacer (not shown) may be formed by filling the internal spacer space with an insulating material. The internal spacer may include the same material as the gate spacer 32c, but example embodiments are not limited thereto.

[0147] The source and drain patterns 34 may be formed from the front surface of the exposed lower pattern 16 using a selective epitaxial growth process. The thickness of the source and drain patterns 34 may vary. For example, the front surface (e.g., top surface) of the source and drain patterns 34 may be located higher than the front surfaces (e.g., top surfaces) of the active patterns 16 and 26, or the front surfaces of the source and drain patterns 34 and the front surfaces of the active patterns 16 and 26 may be located on the same plane.

[0148] like Fig. 9 As shown, the dummy gate electrode 32s can be replaced by the gate electrode 32a (see Figure 8 ) to form a gate structure 32.

[0149] For example, the dummy gate 32s may be removed using an etching material that can selectively etch the dummy gate 32s without etching the source and drain patterns 34 and the gate spacer 32c. When the dummy gate 32s is removed, the channel layer 26 and the sacrificial layer 28 (see FIG. 2 ) at the lower portion of the dummy gate 32s are removed. Figure 8 ) may be exposed to the outside. An etching process may be used to selectively remove the sacrificial layer 28 exposed to the outside.

[0150] A gate insulating layer 32b and a gate electrode 32a may be formed in the space where the sacrificial layer 28 has been removed. The gate insulating layer 32b may be conformally formed on the surface exposed in the space where the sacrificial layer 28 has been removed. The gate electrode 32a may be formed to fill the space on the gate insulating layer 32b. The gate insulating layer 32b or the gate electrode 32a may be formed by using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, etc. A gate capping layer 32d may be formed on the gate insulating layer 32b and / or the gate electrode 32a on the active patterns 16 and 26.

[0151] like Fig.10 As shown, a third insulating portion 46a may be formed to cover the gate structure 32 and the source and drain patterns 34 on the semiconductor substrate 10p. Fig. 9 and Fig.10, it is shown that the third insulating portion 46a is formed after the source and drain patterns 34 are formed. In some example embodiments, a portion of the third insulating portion 46a may be formed before the source and drain patterns 34 are formed. In this case, the source and drain patterns 34 may be grown and formed in the space between the third insulating portions 46a. However, example embodiments are not limited thereto, and the process sequence of the source and drain patterns 34 and the third insulating portion 46a may be modified in various ways. Many other variations are possible.

[0152] In some example embodiments, a third through connector 50c (see FIG. 5A ) may be formed in the second area A2. Fig.14 ) and the fourth insulating portion 46b of the portion between the source and drain patterns 34 (see Figure 3 ). The fourth insulating portion 46b may be formed before forming the third through connector 50c. Thus, the second insulating layer 46 may be formed.

[0153] Then, if Figures 11 to 13 As shown, the stacked structure 20 in the first region A1 may be removed, and the diode pattern 14 (see Figure 1 ) or a second insulating portion 44b is formed on the pattern portion 14p. Figures 11 to 13 Shown with Figure 4 The corresponding part.

[0154] like Fig.11 As shown, a first opening 42 a exposing the stack structure 20 may be formed in the first area A1 .

[0155] For example, a mask layer 48 may be disposed on the first insulating portion 44a to expose a portion of the first region A1 where the stacked structure 20 is located. For example, the mask layer 48 may be formed by a photolithography process, but example embodiments are not limited thereto. The first opening 42a may be formed by removing a portion of the first insulating portion 44a located at the top of the stacked structure 20 through an etching process performed from the front surface using the mask layer 48. As the etching process, dry etching or wet etching may be applied.

[0156] In example embodiments, in the second direction (the Y-axis direction of the drawing), the width of the first opening 42a may be greater than the width of the stacked structure 20 in the first area A1. Therefore, the stacked structure 20 may be stably removed in a removal process of the stacked structure 20 to be performed later through the first opening 42a. However, example embodiments are not limited thereto. In the second direction, the width of the first opening 42a may be equal to or less than the width of the stacked structure 20 in the first area A1.

[0157] like Fig.12 As shown, the stack structure 20 can be removed by using the first opening 42a (see Fig.11 ) to form the second opening 42b. Therefore, an opening 42c including the first opening 42a and the second opening 42b can be formed.

[0158] The process of removing the stacked structure 20 may be performed using an etching process capable of selectively etching the stacked structure 20. For example, the process of removing the stacked structure 20 may be performed by a dry etching process or a wet etching process. The etching process may not be smoothly performed in the region where the first insulating portion 44a is located, and the first insulating portion 44a may serve as a kind of etching stop surface. Therefore, the stacked structure 20 may be selectively removed. However, example embodiments are not limited thereto.

[0159] The mask layer 48 may be removed after the opening 42c is formed. Fig.12 and Fig.13 In the figure, it is shown that the second insulating portion 44b is formed (see Fig.13 ), but example embodiments are not limited thereto. In some example embodiments, the mask layer 48 may be removed in a chemical mechanical polishing process performed in a process of forming the second insulating portion 44b or in a subsequent process.

[0160] like Fig.13 As shown, the second insulating portion 44b may be formed to fill the opening 42c. The second insulating portion 44b may be formed by forming an insulating material to fill the opening 42c, and then performing a chemical mechanical polishing process to be flush with the front surface (eg, top surface) of the first insulating portion 44a. Thus, the first insulating layer 44 may be formed.

[0161] Then, if Fig.14 As shown, the through connector 50 may be formed in the first area A1. In this case, the through connector 50 may also be formed in the second area A2. For example, the first through connector 50a and the second through connector 50b may be formed in the first area A1, and the third through connector 50c may be formed in the second area A2.

[0162] In example embodiments, the first through portion, the second through portion, and the third through portion may be formed to correspond to the first through connector 50a, the second through connector 50b, and the third through connector 50c, respectively. The first through portion to the third through portion may be formed by various etching processes (eg, dry etching processes).

[0163] In example embodiments, after forming the first through portion to the third through portion, a metal-semiconductor compound layer 14s may be formed on the first side surface of the first conductive region 14a exposed by the first through portion, and on the second side surface of the second conductive region 14b exposed by the second through portion. For example, a metal layer may be formed on the first side surface of the first conductive region 14a and the second side surface of the second conductive region 14b, and heat treatment may be performed to form the metal-semiconductor compound layer 14s. However, example embodiments are not limited thereto. In some example embodiments, the metal-semiconductor compound layer 14s may be formed by heat treatment in a subsequent process, rather than performing heat treatment after forming the metal layer. In some example embodiments, the process of forming the metal-semiconductor compound layer 14s may not be performed separately. In this case, by the heat treatment process performed in the subsequent process, the semiconductor material of the first conductive region 14a or the second conductive region 14b and the metal of the first through connector 50a or the second through connector 50b may be chemically bonded to each other, thereby forming the metal-semiconductor compound layer 14s.

[0164] The first through connector 50a, the second through connector 50b, and the third through connector 50c may be formed by filling the conductive material in the first through portion, the second through portion, and the third through portion, respectively. After the conductive material is filled, a planarization process may be performed so that the front surface (e.g., the top surface) of the conductive material is flush with the front surface of the insulating layer 40. For example, the planarization process may be performed by chemical mechanical polishing.

[0165] Then, if Fig.15 As shown, a first contact portion 52 and a second contact portion 54 (see Figure 3 ) and wiring portion 60.

[0166] For example, a first contact portion 52 electrically connected to the source and drain pattern 34 may be formed in the second area A2. The first contact portion 52 electrically connected to the source and drain pattern 34 may be formed by forming a contact hole through the second insulating layer 46 in the second area A2 to expose the source and drain pattern 34, and then filling the contact hole with a conductive material.

[0167] Furthermore, a first upper insulating layer 68 a may be formed on the insulating layer 40 and the first contact portion 52 .

[0168] A contact hole extending through the first upper insulating layer 68a and exposing the through connector 50 may be formed. For example, a first contact hole and a second contact hole may be formed through the first upper insulating layer 68a in the first region A1 to expose the first through connector 50a and the second through connector 50b, and a third contact hole may be formed through the first upper insulating layer 68a in the second region A2 to expose the third through connector 50c. The first to third contact holes may be filled with a conductive material to form contact vias 62 connected to the through connectors 50, respectively.

[0169] A contact hole may be formed through the first upper insulating layer 68 a , the second insulating layer 46 , and the gate capping layer 32 d to expose the gate electrode 32 a , and a second contact portion 54 connected to the gate electrode 32 a may be formed by filling the contact hole with a conductive material.

[0170] The process sequence of the contact via 62 and the second contact portion 54 may be modified in various ways. That is, the second contact portion 54 may be formed after or after the contact via 62 is formed, or the contact via 62 and the second contact portion 54 may be formed together.

[0171] Furthermore, the first wiring layer 64, the second wiring layer 66, and the second upper insulating layer 68b may be formed on the first upper insulating layer 68a. Thus, the wiring portion 60 may be formed.

[0172] Then, if Fig.16 As shown, in a state where the rear surface of the semiconductor substrate 10p (see FIG. 5 ) is located at the upper part, the main body portion 12 (see FIG. 5 ) of the semiconductor substrate 10p can be removed. Fig.15 ), and a base insulating layer 10 can be formed.

[0173] The process of removing the main body portion 12 of the semiconductor substrate 10p may be performed by an etching process using an etching material capable of selectively etching the semiconductor substrate 10p. In this case, the etching process may not be performed smoothly in the area where the first insulating layer 44 or the second insulating layer 46 is provided, and therefore, the rear surface of the first insulating layer 44 or the second insulating layer 46 may act as a kind of etching stop surface. Therefore, the main body portion 12 of the semiconductor substrate 10p can be stably removed until the rear surface of the first insulating layer 44 or the second insulating layer 46. However, the example embodiments are not limited thereto. The process of removing the main body portion 12 of the semiconductor substrate 10p may be performed by at least one of a wet etching process or a polishing process (e.g., a chemical mechanical polishing (CMP) process). Many other variations are possible.

[0174] Then, if Fig.17As shown, a rear wiring portion 70 including a rear contact via hole 72 extending through the base insulating layer 10 may be formed in the second area A2.

[0175] For example, a contact opening may be formed in the base insulating layer 10 to expose the through connector 50 (e.g., the third through connector 50c) in the second area A2, and the rear contact via 72 may be formed by filling the contact opening with a conductive material. For example, a planarization process may be performed after filling the contact opening with a conductive material. For example, the planarization process may be performed by a chemical mechanical etching process.

[0176] A rear wiring layer 76 and a rear insulating layer 78 may be formed. Various processes may be applied to form the rear wiring layer 76 and the rear insulating layer 78. Thus, the rear wiring portion 70 may be formed.

[0177] In the drawings and the above description, the through connector 50 is formed after the gate structure 32 and the source and drain pattern 34 included in the second semiconductor device 200 are formed in the second area A2, but example embodiments are not limited thereto. In some example embodiments, after the through connector 50 is formed, the gate structure 32 and the source and drain pattern 34 included in the second semiconductor device 200 may be formed. In some example embodiments, the through connector 50 may be formed during a process of forming a portion included in the second semiconductor device 200.

[0178] Reference Figure 8 and Fig. 9 The manufacturing process of the second semiconductor device 200 may be an example. Therefore, any one of various manufacturing processes may be applied as a manufacturing method of the second semiconductor device 200.

[0179] In the following, reference will be made to Fig.18 and Fig.19 A first semiconductor device and an integrated circuit including the first semiconductor device according to example embodiments different from the above example embodiments are described in more detail. To the extent that an element is not described in detail below, it is understood that the element is at least similar to a corresponding element that has been described elsewhere within the present disclosure.

[0180] Fig.18 is a plan view showing a first semiconductor device according to example embodiments, and Fig.19 is along Fig.18 A cross-sectional view taken along line AA′. Fig. 20 is shown along Fig.18 BB′ is a cross-sectional view of the first semiconductor device and the second semiconductor device. Fig. 20 Shows Figure 4 The corresponding part in . Fig. 20(b) shows a cross section (YZ plane in the figure) of the source and drain pattern perpendicular to the first direction (X-axis direction in the figure), and conceptually shows the second wiring layer 66 and the third through connector 50c connected to the source and drain pattern 34.

[0181] Reference Fig.18 and Fig. 20 , the first semiconductor device 100 according to example embodiments may include a diode pattern 14 on a base insulating layer 10, an insulating layer 40 (e.g., a first insulating layer 44), a through connector 50, a wiring portion 60, and a rear contact portion 74. Herein, the through connector 50 and the rear contact portion 74 may form a connector connecting the diode pattern 14 and the wiring portion 60.

[0182] In example embodiments, the first insulating layer 44 covering the diode pattern 14 on the base insulating layer 10 may include a first insulating portion 44a. The stack structure 20 including the channel layer 26 and the sacrificial layer 28 may be on the diode pattern 14. For example, a semiconductor layer may be on the diode pattern 14. Therefore, the first insulating portion 44a may cover the stack structure 20 on the diode pattern 14.

[0183] That is, the stack structure 20 formed in the process of manufacturing the second semiconductor device including the BSPDN structure may be retained without being removed. Therefore, since there is no need to add a process for removing the stack structure 20, the manufacturing process may be simplified.

[0184] However, example embodiments are not limited thereto. In some example embodiments, by executing Figures 11 to 13 In the process shown in FIG. 1 , the first insulating layer 44 may include a first insulating portion 44 a and a second insulating portion 44 b (see FIG. 1 ). Figure 2 ), the second insulating portion 44b is an upper insulating portion on the diode pattern 14.

[0185] The through connector 50 may be at the periphery of the diode pattern 14. The through connector 50 may extend through the insulating layer 40 (e.g., the first insulating layer 44) to electrically connect the diode pattern 14 and the first wiring layer 64. For example, the through connector 50 may contact the rear contact portion 74 connected to the diode pattern 14 and the contact via 62. In this case, the through connector 50 may include a first through connector 50a connected to the first conductive region 14a, and a second through connector 50b connected to the second conductive region 14b.

[0186] In example embodiments, the through connector 50 extending through the first insulating layer 44 may be spaced apart from the diode pattern 14. The first through connector 50a may be at a portion where the first conductive region 14a is located in the first direction (the X-axis direction in the figure). The first through connector may be spaced apart from the first side surface 141 of the diode pattern 14 in the second direction (the Y-axis direction in the figure) at a certain distance on the first side of the diode pattern 14. The second through connector 50b may be at a portion where the second conductive region 14b is located in the first direction. The second through connector 50b may be spaced apart from the second side 142 of the diode pattern 14 at a certain distance on a second side of the diode pattern 14 opposite to the first side in the second direction.

[0187] For example, the first through connector 50a may be positioned to correspond to the center portion of the first conductive region 14a in the first direction, and the second through connector 50b may be positioned to correspond to the center portion of the second conductive region 14b in the first direction. Therefore, the distance between the first through connector 50a and the first conductive region 14a and the distance between the second through connector 50b and the second conductive region 14b may be reduced, and the first through connector 50a and the second through connector 50b may be stably formed.

[0188] The rear contact portion 74 may extend through at least a portion of the base insulating layer 10, and may electrically connect the rear surface of the diode pattern 14 and the rear surface of the through connector 50. For example, the first rear contact portion 74a may contact the first through connector 50a, and the second rear contact portion 74b may contact the second through connector 50b.

[0189] In this case, the width of the rear contact portion 74 in the first direction (the X-axis direction in the figure) may be greater than the width of the through connector 50 in the first direction, and the length of the rear contact portion 74 in the second direction (the Y-axis direction in the figure) may be greater than the width of the through connector 50 in the second direction. Therefore, the through connector 50 can be stably connected to the rear contact portion 74.

[0190] In an embodiment, the rear contact portion 74 may include a first rear contact portion 74a and a second rear contact portion 74b. The first rear contact portion 74a may extend along the second direction (the Y-axis direction in the figure) to connect the first conductive region 14a and the first through connector 50a. The second rear contact portion 74b may extend along the second direction to connect the second conductive region 14b and the second through connector 50b. Therefore, the rear surface of the diode pattern 14 and the rear surface of the through connector 50 may be connected by using the rear contact portion 74, so that the rear surface of the diode pattern 14 and the rear surface of the through connector 50 are stably electrically connected to each other.

[0191] For example, the diode pattern 14, the first wiring portion 64a and the second wiring portion 64b may each have a straight or linear shape extending in the first direction, and the first and second rear contact portions 74a and 74b may each have a straight or linear shape extending in the second direction.

[0192] Based on the diode pattern 14, the first rear contact portion 74a and the second rear contact portion 74b may extend in opposite directions along the second direction (the Y-axis direction in the figure). Fig.18 The first rear contact portion 74a extending to the lower side of the Fig.18 The second rear contact portion 74b (on the upper side) can be formed from the first end ( Fig.18 ) to the second end ( Fig.18 For example, the first rear contact portion 74a and the second rear contact portion 74b may be arranged in a zigzag shape.

[0193] In an example embodiment, the rear contact portion 74 may include at least one of titanium, tungsten, nickel, cobalt, tantalum, molybdenum, copper, aluminum, gold, tin, manganese, ruthenium, beryllium or an alloy thereof. The rear contact portion 74 may include one or more layers. The rear contact portion 74 may be a part of the rear wiring portion 70, and may include the same material as the rear contact via 72 or the rear wiring layer 76. However, example embodiments are not limited thereto, and the rear contact portion 74 may include a material different from the rear contact via 72 or the rear wiring layer 76.

[0194] In this case, the metal-semiconductor compound layer 14s may be at a boundary between the rear surface (e.g., bottom surface) of the first conductive region 14a and the front surface (e.g., top surface) of the first rear contact portion 74a. That is, the first rear contact portion 74a may be electrically connected to the first conductive region 14a through the metal-semiconductor compound layer 14s. Similarly, the metal-semiconductor compound layer 14s may be at a boundary between the rear surface (e.g., bottom surface) of the second conductive region 14b and the front surface (e.g., top surface) of the second rear contact portion 74b. That is, the second rear contact portion 74b may be electrically connected to the second conductive region 14b through the metal-semiconductor compound layer 14s.

[0195] The metal-semiconductor compound layer 14s may include a compound of a metal and a semiconductor material included in the diode pattern 14. For example, the metal-semiconductor compound layer 14s may include a metal silicide, for example, at least one of titanium silicide, tungsten silicide, nickel silicide, cobalt silicide, tantalum silicide, or molybdenum silicide. The metal included in the metal-semiconductor compound layer 14s may be the same as or different from the metal included in the rear contact portion 74. However, example embodiments are not limited to the material of the metal-semiconductor compound layer 14s.

[0196] Reference Figure 3 and Figure 4 The description of the second semiconductor device 200 may be applied to the second semiconductor device 200 .

[0197] According to example embodiments, stability of a connection structure may be improved by connecting the diode pattern 14 and the through connector 50 using the rear contact portion 74 .

[0198] Will refer to Figure 21 to Figure 24 A method for manufacturing the first semiconductor device 100 having a bodyless structure is described in detail. As described above, the first semiconductor device 100 forms an integrated circuit together with the second semiconductor device 200 having a BSPDN structure. Hereinafter, a method for manufacturing the integrated circuit including the first semiconductor device 100 and the second semiconductor device 200 will be described while describing a method for manufacturing the first semiconductor device 100.

[0199] Figure 21 to Figure 24 is a cross-sectional view illustrating a method of manufacturing an integrated circuit including a first semiconductor device according to example embodiments. Figure 21 to Figure 24 Shown with Fig. 20 The corresponding part.

[0200] like Fig.21 As shown, a semiconductor substrate 10p and a stacked structure 20 may be formed, a first insulating layer 44 including a first insulating portion 44a may be formed in the first region A1, and a gate structure 32 included in the second semiconductor device 200 may be formed in the second region A2 (see Figure 3 ) and the source and drain patterns 34, and a second insulating layer 46 including a third insulating portion and / or a fourth insulating portion may be formed. In this regard, the reference Figures 5 to 10 Description.

[0201] Then, if Fig. 22 As shown, a through connector 50 may be formed in the first area A1, and a first contact portion 52 and a second contact portion 54 may be formed (see Figure 3 ) and wiring portion 60.

[0202] In the process of forming the through connector 50, the first through connector 50a and the second through connector 50b may be formed in the first area A1, and the third through connector 50c may be formed in the second area A2. In this regard, except that the through connector 50 is spaced apart from the diode pattern 14 and the process of forming the metal-semiconductor compound layer 14s is not performed, the reference 14 may be applied as is. Figure 1 4 Descriptions.

[0203] Reference Figure 1 The description of FIG. 5 can be applied as it is to the process of forming the first contact portion 52, the second contact portion 54, and the wiring portion 60.

[0204] Then, if Fig.23 As shown, on the rear surface of the semiconductor substrate 10p (see Fig. 22 ) is located at the upper part, the main body portion 12 of the semiconductor substrate 10p can be removed (see Fig. 22 ), and a base insulating layer 10 can be formed.

[0205] Then, if Fig.24 As shown, a rear contact portion 74 extending through the base insulating layer 10 in the first area A1 may be formed, and a rear wiring portion 70 including a rear contact via 72 extending through the base insulating layer 10 may be formed in the second area A2.

[0206] For example, contact openings may be formed in the first area A1 and the second area A2. In the first area A1, a first contact opening exposing the first through connector 50a and the first conductive area 14a, and a second contact opening exposing the second through connector 50b and the second conductive area 14b may be formed. In addition, in the second area A2, a third contact opening may be formed through the base insulating layer 10 to expose the third through connector 50c.

[0207] In example embodiments, after forming the first to third contact openings, a metal-semiconductor compound layer 14s may be formed on the rear surface of the first conductive region 14a exposed by the first contact opening, and on the rear surface of the second conductive region 14b exposed by the second contact opening. For example, a metal layer may be formed on the rear surface of the first conductive region 14a and the rear surface of the second conductive region 14b, and heat treatment may be performed to form the metal-semiconductor compound layer 14s. However, example embodiments are not limited thereto. In some example embodiments, the metal-semiconductor compound layer 14s may be formed by heat treatment in a subsequent process, rather than performing heat treatment after forming the metal layer. In some example embodiments, the process of forming the metal-semiconductor compound layer 14s may not be performed separately. In this case, by a heat treatment process performed in a subsequent process, the semiconductor material of the first conductive region 14a or the second conductive region 14b and the metal of the first rear contact portion 74a or the second rear contact portion 74b may be chemically bonded to each other, thereby forming the metal-semiconductor compound layer 14s.

[0208] The rear contact portion 74 and the rear contact via 72 may be formed by filling the first contact opening, the second contact opening, and the third contact opening with a conductive material. For example, a planarization process may be performed after the first contact opening, the second contact opening, and the third contact opening are filled with a conductive material. For example, the planarization process may be performed by a chemical mechanical etching process.

[0209] A rear wiring layer 76 and a rear insulating layer 78 may be formed. Various processes may be applied to form the rear wiring layer 76 and the rear insulating layer 78. Thus, the rear wiring portion 70 may be formed.

[0210] In the drawings and the above description, the through connector 50 is formed after the gate structure 32 and the source and drain pattern 34 included in the second semiconductor device 200 are formed in the second area A2, but example embodiments are not limited thereto. After the through connector 50 is formed, the gate structure 32 and the source and drain pattern 34 included in the second semiconductor device 200 may be formed. The through connector 50 may be formed during a process of forming a portion included in the second semiconductor device 200.

[0211] Although some exemplary embodiments have been described in detail above, the scope of the present disclosure is not limited thereto. Various modifications and improvements made by those skilled in the art using the basic concepts of the present disclosure as defined in the appended claims also fall within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a diode pattern on the base insulating layer, the diode pattern including a first conductive region and a second conductive region having opposite conductive types to each other; an insulating layer, covering the diode pattern on the base insulating layer; A wiring portion, on the insulating layer; as well as A through connector extends through the insulating layer at a periphery of the diode pattern to electrically connect the diode pattern and the wiring portion.

2. The semiconductor device according to claim 1, wherein The through connector includes a first through connector connected to the first conductive region at a first side of the diode pattern and a second through connector connected to the second conductive region at a second side of the diode pattern opposite to the first side.

3. The semiconductor device according to claim 2, wherein: The first conductive region and the second conductive region are adjacent to each other in a first direction, The first through connector is located at the first side of the diode pattern in a second direction, the second direction intersecting the first direction, and The second through-connector is located at the second side of the diode pattern in the second direction.

4. The semiconductor device according to claim 1, wherein: The first conductive region includes a plurality of first conductive regions, and the second conductive region includes a plurality of second conductive regions, The plurality of first conductive regions and the plurality of second conductive regions are alternately arranged in a first direction, and The through connector comprises: a plurality of first through connectors located on a first side of the diode pattern in a second direction crossing the first direction and connected to the plurality of first conductive regions, respectively; and A plurality of second through connectors are located at a second side of the diode pattern opposite to the first side in the second direction and are respectively connected to the plurality of second conductive regions.

5. The semiconductor device according to claim 4, wherein: The wiring part includes: a first wiring portion extending in the first direction at the first side of the diode pattern and electrically connected to the plurality of first through connectors, and A second wiring portion extends along the first direction at the second side of the diode pattern and is electrically connected to the plurality of second through connectors.

6. The semiconductor device according to claim 5, wherein: The diode pattern, the first wiring portion, and the second wiring portion each have a straight shape extending along the first direction.

7. The semiconductor device according to claim 1, wherein A side surface of the diode pattern and a side surface of the through connector are connected to each other.

8. The semiconductor device according to claim 7, wherein: A metal-semiconductor compound layer is at a boundary between the side surface of the diode pattern and the side surface of the through connector.

9. The semiconductor device according to claim 7, wherein: The insulating layer includes an upper insulating portion on the diode pattern.

10. The semiconductor device according to claim 1, wherein The diode pattern and the through connector are spaced apart from each other, and The semiconductor device further includes a rear contact portion extending through at least a portion of the base insulating layer and electrically connecting a rear surface of the diode pattern and a rear surface of the through connector.

11. The semiconductor device according to claim 10, wherein: The first conductive region and the second conductive region are adjacent to each other in a first direction, The through connector comprises: a first through connector located at a first side of the diode pattern in a second direction intersecting the first direction, and a second through connector located at a second side of the diode pattern opposite to the first side in the second direction, and The rear contact portion comprises: a first rear contact portion extending along the second direction and electrically connecting the first conductive region to the first through connector, and The second rear contact portion extends along the second direction and electrically connects the second conductive region to the second through connector.

12. The semiconductor device according to claim 11, wherein The first back contact portion and the second back contact portion extend in the second direction and are opposite to each other based on the diode pattern.

13. The semiconductor device according to claim 10, wherein: A metal-semiconductor compound layer is at a boundary between the rear surface of the diode pattern and the rear contact portion.

14. The semiconductor device according to claim 10, further comprising: A semiconductor layer, on the diode pattern, or The insulating layer includes an upper insulating portion on the diode pattern.

15. A semiconductor device comprising: a diode pattern on the base insulating layer, the diode pattern including a first conductive region and a second conductive region having opposite conductive types to each other; an insulating layer, covering the diode pattern on the base insulating layer; A wiring portion, on the insulating layer; as well as A connector electrically connects a side surface or a rear surface of the diode pattern and the wiring portion.

16. The semiconductor device according to claim 15, wherein: The connector includes a through connector extending through the insulating layer and connected to a side surface of the diode pattern.

17. The semiconductor device according to claim 15, wherein: The connector includes a through connector and a rear contact portion, wherein the through connector is spaced apart from the diode pattern and extends through the insulating layer, and the rear contact portion extends through at least a portion of the base insulating layer and electrically connects the rear surface of the diode pattern to the rear surface of the through connector.

18. An integrated circuit comprising: A base insulating layer having a first region and a second region; a first semiconductor device in the first region; as well as a second semiconductor device, in the second region, the second semiconductor device comprising a back side power distribution network (BSPDN) structure, the BSPDN structure comprising a rear wiring portion, the rear wiring portion comprising a rear contact via extending through the base insulating layer, Wherein, the first semiconductor device comprises: a diode pattern, on the base insulating layer, the diode pattern including a first conductive region and a second conductive region, the first conductive region and the second conductive region having conductivity types opposite to each other, an insulating layer covering the diode pattern on the base insulating layer, a wiring portion on the insulating layer, and A through connector extends through the insulating layer at a periphery of the diode pattern and electrically connects the diode pattern to the wiring portion.

19. The integrated circuit of claim 18, wherein: The second semiconductor device comprises: an active pattern on the base insulating layer; a gate structure on the active pattern; a pair of source and drain patterns, respectively on both sides of the active pattern; and Another through connector extends through the insulating layer at a periphery of a corresponding one of the pair of source and drain patterns and electrically connects the corresponding one of the pair of source and drain patterns with the rear wiring portion via the wiring portion.

20. The integrated circuit of claim 19, wherein: The active pattern includes a plurality of channel patterns having nanosheet shapes spaced apart from each other in a thickness direction.

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