Wide bandgap semiconductor composite chip structure and preparation method thereof

Abstract

The invention provides a wide bandgap semiconductor composite chip structure and a preparation method thereof, and belongs to the technical field of semiconductor devices. According to the composite chip structure, a wide bandgap semiconductor voltage withstanding unit with a wide bandgap semiconductor material as a main body and a switch control unit manufactured on a traditional semiconductor material are vertically integrated through a conductive plug, so that the composite chip structure has the voltage withstanding performance of the wide bandgap semiconductor material; and various problems during the manufacturing of the wide bandgap semiconductor material switch control device are avoided, and the problems of heterogeneous material interface defects and interface potential barriers in the existing integration technology are also avoided. The composite chip structure has a smaller chip area and better electrical properties.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a wide bandgap semiconductor composite chip structure and a preparation method thereof. Background Art

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), and aluminum nitride (AlN) have advantages over silicon (Si) materials in terms of physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity. Power devices such as diodes, transistors, and power modules made of wide bandgap semiconductor materials have better electrical properties, which can overcome the defects of silicon-based devices that cannot meet the application requirements of high power, high voltage, high frequency, and high temperature. It is also one of the breakthrough paths that can surpass Moore's Law. Therefore, it is widely used in the field of new energy (such as photovoltaics, energy storage, charging piles, electric vehicles, etc.). However, there are various problems in the actual design, production, and application of power devices. For example, the structure of silicon carbide MOSFET devices has many defects in the gate oxide layer, the threshold voltage is prone to drift, the preparation process is complex, and special process equipment (including high-temperature annealing equipment) is required. It is difficult to achieve P-type doping through ion implantation for materials such as gallium nitride, gallium oxide, diamond, and aluminum nitride. At the same time, silicon power devices and processes are very mature, and the design, production and equipment of devices have mature industrial equipment and experience. Therefore, integrating the switch control unit in traditional silicon power devices with the wide bandgap semiconductor drift region as a voltage-resistant unit to obtain a composite chip has become the research direction of researchers.

[0003] The prior art CN118039634A discloses a silicon control unit and a wide bandgap semiconductor unit composite device structure and a manufacturing method thereof. The device structure is to directly epitaxially or bond a silicon single crystal thin film layer on the surface of the wide bandgap semiconductor material layer, to manufacture the channel switch control area of ​​the MOSFET in the silicon single crystal thin film layer, and to use the wide bandgap semiconductor material layer as a withstand voltage unit. Although the device structure successfully integrates the silicon control unit and the wide bandgap semiconductor withstand voltage unit to obtain a composite device, solving the problems of wide bandgap semiconductor device design, process manufacturing and the need for special equipment; however, the composite device structure still has the following problems: the heterostructure interface between the wide bandgap semiconductor material and the silicon material has interface defects such as an oxide layer and an amorphous layer; the heterojunction structure constitutes an interface barrier, resulting in the inability of the current to be effectively conducted at the interface, thereby forming a large interface capacitance and affecting the switching characteristics of the device. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a wide bandgap semiconductor composite chip structure and a preparation method thereof. The wide bandgap semiconductor withstand voltage unit and the switch control unit are vertically integrated through a conductive plug, so that the composite chip structure has a smaller area and better electrical performance.

[0005] Specifically, in order to achieve the above purpose, the present invention adopts the following technical solutions: A wide bandgap semiconductor composite chip structure, wherein the cell structure of the composite chip structure comprises, from bottom to top, a substrate, a drift layer, a first buried layer and a switch control unit; a second buried layer distributed in an island shape is provided in the drift layer; the second buried layer is connected to the first buried layer through a connecting column; a first doped region penetrating the first buried layer and located above the second buried layer is provided in the first buried layer; a first ohmic contact metal layer and a second ohmic contact metal layer are deposited in an area on the upper surface of the first buried layer that needs to be electrically connected to the switch control unit; the second ohmic contact metal layer is located on the upper surface of the first doped region; the switch The control unit includes a semiconductor material layer, a third ohmic contact metal layer and a fourth ohmic contact metal layer located on the upper surface of the semiconductor material layer; a plurality of conductive plugs are arranged in the semiconductor material layer and at least penetrate the semiconductor material layer; the first ohmic contact metal layer is electrically connected to the third ohmic contact metal layer through the conductive plug; the second ohmic contact metal layer is electrically connected to the fourth ohmic contact metal layer through the conductive plug; the doping type of the substrate, the drift layer, the first doping region and the semiconductor material layer is the first type, and the doping type of the first buried layer, the second buried layer and the connecting column is the second type.

[0006] In a preferred solution, a bonding interface layer is provided on the upper surface of the first buried layer, and the semiconductor material layer is located on the upper surface of the bonding interface layer.

[0007] In a preferred embodiment, the material of the substrate is at least one of single crystal SiC, polycrystalline SiC, and Si.

[0008] In a preferred embodiment, the material of the drift layer is at least one of SiC, GaN, Ga2O3, and AlN.

[0009] In a preferred solution, a dimension of the drift layer from the substrate to the first buried layer is 1000 nm to 150 μm.

[0010] In a preferred embodiment, a dimension of the first buried layer from the substrate to the first buried layer is 10 nm to 500 nm.

[0011] In a preferred embodiment, the material of the bonding interface layer is silicon dioxide or BCB.

[0012] In a preferred embodiment, the semiconductor material layer is made of at least one of silicon, GaN, and 3C-SiC.

[0013] In a preferred embodiment, a size of the bonding interface layer along a direction from the substrate to the bonding interface layer is 1 nm to 10 μm.

[0014] In a preferred solution, a size of the semiconductor material layer along a direction from the substrate to the semiconductor material layer is 100 nm to 10 μm.

[0015] In a preferred solution, the switch control unit is any one of a MOSFET device, a HEMT device, an NPN-type transistor, a PNP-type transistor, a JFET switch control unit or a diode.

[0016] In a preferred embodiment, the material of the conductive plug is at least one of titanium, titanium nitride, tungsten, aluminum and copper.

[0017] The present invention also provides a method for preparing the composite chip structure in any of the above-mentioned solutions, comprising the following steps: S1, forming the drift layer on the surface of one side of the substrate; forming a first buried layer on the top layer or upper surface of the drift layer; S2, forming the second buried layer and the connecting pillar distributed in an island shape in the drift layer, forming the first doped region in the first buried layer, and annealing; S3, depositing an ohmic contact metal on the upper surface of the first buried layer, and etching to retain an area that needs to be electrically connected to other devices, to obtain the first ohmic contact metal layer and the second ohmic contact metal layer, and annealing to obtain a wide bandgap semiconductor withstand voltage unit; S4, combining the semiconductor material layer with the upper surface of the wide bandgap semiconductor voltage-resistant unit; S5, manufacturing the switch control unit in the semiconductor material layer; S6. Etch a through hole that at least penetrates the semiconductor material layer in the corresponding area where the switch control unit and the wide bandgap semiconductor withstand voltage unit need to be electrically connected; deposit a first dielectric layer on the side wall of the through hole, and then deposit a conductive material on the upper surface of the semiconductor material layer and inside the through hole, and etch to obtain the conductive plug.

[0018] In a preferred embodiment, the preparation method further comprises the following steps: forming an isolation layer, a gate and a source on the upper surface of the device structure obtained in step S6, wherein the isolation layer isolates the gate and the source; and forming a drain on the surface of the substrate away from the drift layer.

[0019] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: (1) The wide bandgap semiconductor composite chip structure provided by the present invention combines the high withstand voltage and high power characteristics of wide bandgap semiconductor materials with the mature process platform of traditional semiconductor material switch control units, and realizes the vertical integration of the wide bandgap semiconductor withstand voltage unit using wide bandgap semiconductor materials as drift layers and the traditional semiconductor material switch control units, so that the composite chip structure has both high withstand voltage characteristics and a smaller chip area.

[0020] (2) The present invention avoids the problems of interface defects and interface barriers caused by direct integration of silicon-based switch control units and wide bandgap semiconductor material withstand voltage units through heterogeneous materials in the prior art. In the present invention, a conductive plug is used to realize the electrical connection between the traditional semiconductor material switch control unit and the wide bandgap semiconductor withstand voltage unit, which effectively overcomes the problem of the current being unable to flow effectively due to the interface barrier and the formation of a large interface capacitance that affects the switching characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic structural diagram of a wide bandgap semiconductor composite chip structure provided by the present invention; Figure 2 A schematic structural diagram of another wide bandgap semiconductor composite chip structure provided by the present invention; Figure 3 A schematic structural diagram of another wide bandgap semiconductor composite chip structure provided by the present invention; Figure 4 for Figure 1 The top view of the structure on the upper surface of the first buried layer, the area within the red dotted line in the figure is the second buried layer; Figure 5 for Figure 1 A top view of the structure at section AA'; Figure 6~Figure 8 A schematic diagram of the structure obtained in steps S1 to S3 of preparing a wide bandgap semiconductor composite chip structure in the present invention; Fig. 9 , Fig.10 Schematic diagram of the structure obtained by using different combination methods of the semiconductor material layer and the wide bandgap semiconductor withstand voltage unit in step S4 of preparing the wide bandgap semiconductor composite chip structure in the present invention; Figure 11~Figure 13 Schematic diagram of different device structures obtained in step S5 of preparing a wide bandgap semiconductor composite chip structure in the present invention; Figure 14~Figure 16 Schematic diagram of different device structures obtained in step S6 of preparing a wide bandgap semiconductor composite chip structure in the present invention.

[0022] In the figure: 1. wide bandgap semiconductor withstand voltage unit; 101. substrate; 102. drift layer; 103. first buried layer; 104. second buried layer; 105. connecting column; 106. first doped region; 107. first ohmic contact metal layer; 108. second ohmic contact metal layer; 2. bonding interface layer; 3. switch control unit; 301. semiconductor material layer; 302. through hole; 303. first dielectric layer; 304. well region; 305. second doped region; 306. third ohmic contact metal layer; 307. fourth ohmic contact metal layer; 308. isolation layer; 309. AlGaN layer; 310. p-GaN layer; 4. conductive plug; 5. gate; 6. source; 7. drain. DETAILED DESCRIPTION

[0023] The following content is combined with the embodiments to clearly and completely describe the technical solution of the present application so that those skilled in the art can fully understand the present application. Obviously, the described embodiments are only some preferred embodiments of the present application, rather than all embodiments. Any equivalent transformation or substitution made to the following implementation modes by those of ordinary skill in the art without creative work belongs to the protection scope of the present application.

[0024] Directional terms described in this application, such as "upper", "lower", "inner", "outer", "bottom", "upper surface", etc., indicate directions or positional relationships based on directions or positional relationships in the drawings of the specification, or directions or positional relationships in which the products of this application are usually placed when in use, and are only for the convenience of describing and understanding the product structure of this application. Therefore, directional terms cannot be understood as limiting this application. In this application, unless otherwise clearly defined, expressions such as "upper", "above", "above", and "upper surface" of a first feature on a second feature indicate that the first feature and the second feature may be in direct contact or indirect contact through an intermediate medium; the first feature may be directly above or obliquely above the second feature, or simply indicate that the first feature is higher in level than the second feature. Expressions such as "lower", "below", "below", and "lower surface" of a first feature on a second feature indicate that the first feature and the second feature may be in direct contact or indirect contact through an intermediate medium; the first feature may be directly below or obliquely below the second feature, or simply indicate that the first feature is lower in level than the second feature. Ordinal numbers used in this application, such as "first", "second", etc., are only used for descriptive purposes to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. The methods not described in detail in the following embodiments are all conventional methods well known to those skilled in the art.

[0025] The full names of the abbreviations in the following embodiments are as follows: MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor, metal oxide semiconductor field effect transistor; HEMT: High Electron Mobility Transistors, high electron mobility transistor; MOCVD: Metal-organic Chemical Vapor Deposition, organic metal chemical vapor deposition; JFET: Junction Field-Effect Transistor, junction field effect transistor; MBE: Molecular beam epitaxy; CVD: Chemical Vapor Deposition, chemical vapor deposition; ALD: Atomic layer deposition, atomic layer deposition; BCB: Benzocyclobutene.

[0026] Example 1 A wide bandgap semiconductor composite chip structure, composed of a number of cellular structures. Figures 1 to 5Each cell structure includes a substrate 101, a drift layer 102, a first buried layer 103 and a switch control unit 3 from bottom to top. An island-shaped second buried layer 104 is distributed in the drift layer 102 below the first buried layer 103. The second buried layer 104 is connected to the first buried layer 103 through a connecting column 105 to prevent the second buried layer 104 from floating. A first doped region 106 is provided in the first buried layer 103, penetrating the first buried layer 103 and located above the second buried layer 104. A first ohmic contact metal layer 107 and a second ohmic contact metal layer 108 are deposited on the upper surface of the first buried layer 103 in an area that needs to be electrically connected to the switch control unit 3. The second ohmic contact metal layer 108 is located on the upper surface of the first doped region 106. The switch control unit 3 includes a semiconductor material layer 301, a third ohmic contact metal layer 306 and a fourth ohmic contact metal layer 307 located on the upper surface of the semiconductor material layer 301 (i.e., the surface of the semiconductor material layer 301 away from the first buried layer 103). The semiconductor material layer 301 is provided with a plurality of conductive plugs 4 that at least penetrate the semiconductor material layer 301. The first ohmic contact metal layer 107 is electrically connected to the third ohmic contact metal layer 306 through the conductive plugs 4. The second ohmic contact metal layer 108 is electrically connected to the fourth ohmic contact metal layer 307 through the conductive plugs 4. The doping type of the substrate 101, the drift layer 102, the first doping region 106, and the semiconductor material layer 301 is the first type, and the doping type of the first buried layer 103, the second buried layer 104, and the connecting column 105 is the second type.

[0027] In the above scheme, the drift layer 102, the first buried layer 103, the second buried layer 104, the connecting column 105, the first ohmic contact metal layer 107 and the second ohmic contact metal layer 108 constitute a wide bandgap semiconductor withstand voltage unit 1. The first ohmic contact metal layer 107 of the wide bandgap semiconductor withstand voltage unit 1 is electrically connected to the third ohmic contact metal layer 306 of the switch control unit 3 through the conductive plug 4. The second ohmic contact metal layer 108 of the wide bandgap semiconductor withstand voltage unit 1 is electrically connected to the fourth ohmic contact metal layer 307 of the switch control unit 3 through the conductive plug 4. The composite chip structure obtained by vertically integrating the wide bandgap semiconductor withstand voltage unit 1 and the switch control unit 3, the wide bandgap semiconductor withstand voltage unit 1 enables the composite chip structure to have excellent lateral withstand voltage turn-off performance and good forward conduction characteristics under reverse bias voltage. Since the first buried layer 103 is provided with the first doped region 106 as a current path, when a reverse bias voltage is applied to the composite chip structure, the island-shaped second buried layer 104 can completely block the first doped region 106 and shield the high electric field in the reverse direction. Figure 4 and Figure 5) is connected to the first buried layer 103 through the connection pillars 105 periodically arranged in the drift layer 102, so that the second buried layer 104 is not in a floating state, so that the reverse depletion of the PN junction of the device can be restored in time during the dynamic switching process, reducing the switching capacitance and achieving a good reverse electric field shielding effect during the continuous switching process. The second ohmic contact metal layer 108 located on the upper surface of the first doped region 106 is electrically connected to the fourth ohmic contact metal layer 307 in the switch control unit 3 through the conductive plug 4, so that the current can flow between the wide bandgap semiconductor withstand voltage unit 1 and the switch control unit 3.

[0028] In some specific embodiments, the doping types of the substrate 101, the drift layer 102, the first doping region 106, and the semiconductor material layer 301 are all N-type, and the doping types of the first buried layer 103, the second buried layer 104, and the connecting pillar 105 are all P-type. In other specific embodiments, the doping types of the substrate 101, the drift layer 102, the first doping region 106, and the semiconductor material layer 301 are all P-type, and the doping types of the first buried layer 103, the second buried layer 104, and the connecting pillar 105 are all N-type.

[0029] As an example, the material of the substrate 101 is at least one of single crystal SiC, polycrystalline SiC, and Si.

[0030] As an example, the material of the drift layer 102 is at least one of SiC, GaN, Ga 2 O 3 , and AlN.

[0031] As an example, the thickness of the drift layer 102 (the dimension along the direction from the substrate 101 to the first buried layer 103 or along the direction from the first buried layer 103 to the substrate 101) is 1000nm~150μm; for example, the thickness of the substrate 101 is 1000nm, 1001nm, 1002nm, 1005nm, 1010nm, 1015nm, 1020nm, 1025nm, 1030nm, 1040nm, 1050nm...2000nm, 2100nm, 2200nm, 2300nm, 2400nm, 2500nm, 2600nm, 2800nm...10μm, 11μm, 12μm, 13μm, 14μm...150μm, preferably 10μm.

[0032] As an example, the thickness of the first buried layer 103 (the dimension along the direction from the substrate 101 to the first buried layer 103 or along the direction from the first buried layer 103 to the substrate 101) is 10nm~500nm; for example, the thickness of the first buried layer 103 is 10nm, 11nm, 12nm, 15nm, 20nm, 22nm, 25nm, 30nm, 35nm, 40nm, 50nm...500nm, preferably 100nm.

[0033] As an example, the material of the first ohmic contact metal layer 107 is nickel or titanium-nickel-aluminum alloy.

[0034] As an example, the material of the second ohmic contact metal layer 108 is nickel or titanium-nickel-aluminum alloy.

[0035] In some specific embodiments, the wide bandgap semiconductor withstand voltage unit 1 and the switch control unit 3 are combined through the interface layer 2 to form a complete composite chip cell structure (such as Figure 1 and Figure 2 as shown).

[0036] As an example, the material of the bonding interface layer 2 is silicon dioxide or / and BCB; preferably silicon dioxide. For example, when the material of the semiconductor material layer 301 is silicon, a layer of silicon dioxide is deposited on the upper surface of the first buried layer 103 by CVD or ALD or spin coating process as the bonding interface layer 2. The semiconductor material layer 301 is deposited on the upper surface of the silicon dioxide dielectric layer. The switch control unit 3 and the wide bandgap semiconductor withstand voltage unit 1 are combined into a whole through the silicon dioxide dielectric layer.

[0037] As an example, the thickness of the bonding interface layer 2 (the dimension in the direction along the substrate 101 pointing to the bonding interface layer 2) is 1nm~10μm; for example, the thickness of the bonding interface layer 2 is 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 10nm, 12nm, 15nm...300nm, 310nm, 320nm, 330nm, 340nm, 350nm, 360nm, 380nm...1μm, 1.5μm, 2μm, 3μm, 4μm...10μm, preferably 300nm.

[0038] In some other specific embodiments, the wide bandgap semiconductor withstand voltage unit 1 and the switch control unit 3 form a complete composite chip cell structure by epitaxially growing (for example, using MOCVD, MBE, etc.) a semiconductor material layer 301 on the surface of the first buried layer 103. Figure 3 As shown, when the material of the drift layer 102 is silicon carbide, a GaN layer is heteroepitaxially grown directly on the upper surface of the first buried layer 103 to obtain a semiconductor material layer 301, and an AlGaN layer 309 is grown on the upper surface of the GaN layer.

[0039] As an example, the switch control unit 3 is any one of a MOSFET device, a HEMT device, an NPN transistor, a PNP transistor, a JFET switch control unit or a diode.

[0040] like Figure 1As shown, when the switch control unit 3 is a MOSFET device, it includes a semiconductor material layer 301, a well region 304 arranged in the semiconductor material layer 301, a second doping region 305 arranged in the semiconductor material layer 301, a third ohmic contact metal layer 306 and a fourth ohmic contact metal layer 307 located on the upper surface of the semiconductor material layer 301, a gate 5, a source 6 and a drain 7; the gate 5 and the source 6 are separated by an isolation layer 308; and the second doping region 305 is used as a source doping region. Among them, the doping type of the well region 304 is opposite to the doping type of the semiconductor material layer 301, and the doping type of the second doping region 305 is the same as the doping type of the semiconductor material layer 301. The first buried layer 103 is connected to the source 6 through the first ohmic contact metal layer 107 and the conductive plug 4 located on its upper surface, and a lateral equipotential field plate is constructed. When the reverse withstand voltage is applied, it can realize the reverse depletion pinch-off of the PN junction in the passage area in the drift layer 102 together with the island-shaped second buried layer 104, so as to achieve a more reliable reverse withstand voltage capability. When the switch control unit 3 is a MOSFET device, when the device is turned on (i.e., a positive voltage is applied to the gate 5 relative to the source 6, and a positive voltage is also applied to the drain 7 relative to the source 6), the current conduction path of the composite chip structure is as follows: Figure 1 When the device is turned off (i.e., a negative voltage or 0V is applied to the gate 5 relative to the source 6, and the drain 7 is at a positive high voltage relative to the source 6), the PN junction formed by the first buried layer 103 and the second buried layer 104 connected to the first buried layer 103 through the connecting column 105 and the drift layer 102 is reversely depleted, and the depletion region expands to pinch off the channel of the drift layer 102 (as shown in FIG. Figure 1 At the same time, the island-shaped second buried layers 104 will also be depleted due to the reverse bias of the PN junction formed with the drift layer 102, and the depletion region will expand and pinch off the channel of the drift layer 102 (as shown by the red dotted line above). Figure 1 The red dotted line above helps improve the pressure resistance.

[0041] like Figure 2 and Figure 3As shown, the material of the drift layer 102 is silicon carbide, and the switch control unit 3 is a p-GaN HEMT device. The switch control unit 3 includes a semiconductor material layer 301 (the material of the semiconductor material layer 301 is GaN), an AlGaN layer 309 deposited on the upper surface of the semiconductor material layer 301, a p-GaN layer 310 located on the upper surface of the AlGaN layer 309, and a gate 5, a source 6 and a drain 7 located on the upper surface of the p-GaN layer 310; the gate 5 and the source 6 are separated by an isolation layer 308. When the switch control unit 3 is a p-GaN HEMT switch control unit, the advantages of different wide bandgap semiconductor materials can be combined and complemented. When the upper switch control unit is a p-GaN HEMT unit structure constructed of a GaN material layer, the high mobility of the two-dimensional electron gas between AlGaN and GaN, and the relatively stable threshold turn-on characteristics of the p-GaN gate can be used to construct a faster switching characteristic, while retaining the high withstand voltage and high heat dissipation performance of silicon carbide.

[0042] As an example, the thickness of the semiconductor material layer 301 (the dimension in the direction along the substrate 101 pointing to the semiconductor material layer 301 or in the direction along the semiconductor material layer 301 pointing to the substrate 101) is 100nm~10μm; for example, the thickness of the semiconductor material layer 301 is 100nm, 101nm, 102nm, 103nm, 105nm, 110nm, 115nm, 125nm, 130nm, 140nm, 150nm...200nm, 210nm, 220nm, 230nm, 240nm, 250nm, 260nm, 280nm...1μm, 1.5μm, 2μm, 3μm, 4μm...10μm, preferably 600nm.

[0043] As an example, the material of the semiconductor material layer 301 is at least one of silicon, GaN, and 3C-SiC.

[0044] As an example, the third ohmic contact metal layer 306 is nickel or titanium nickel aluminum alloy.

[0045] As an example, the fourth ohmic contact metal layer 307 is nickel or titanium-nickel-aluminum alloy.

[0046] As an example, the material of the isolation layer 308 is SiO 2 .

[0047] As an example, the material of the conductive plug 4 is at least one of titanium, titanium nitride, tungsten, aluminum, and copper.

[0048] As an example, the material of the gate 5 is aluminum and / or copper.

[0049] As an example, the material of the source electrode 6 is aluminum and / or copper.

[0050] As an example, the material of the drain electrode 7 is aluminum and / or copper.

[0051] Example 2 Reference Figures 6 to 16 , a method for preparing a wide bandgap semiconductor composite chip structure, comprising the following steps: S1. A wide bandgap semiconductor material layer is epitaxially grown or bonded on the surface of one side of the substrate 101 to obtain a drift layer 102. A first buried layer 103 is formed on the top layer of the drift layer 102 by ion implantation or epitaxial growth.

[0052] S2, forming an island-shaped second buried layer 104 in the drift layer 102 by ion implantation, forming a connecting column 105 in the drift layer 102 by ion implantation, forming a first doped region 106 in the first buried layer 103 by ion implantation, and annealing. The first doped region 106 penetrates the first buried layer 103 and is located above the second buried layer 104.

[0053] S3. Deposit ohmic contact metal on the upper surface of the first buried layer 103, and etch to retain the area that needs to be electrically connected to other devices, to obtain the first ohmic contact metal layer 107 and the second ohmic contact metal layer 108, and anneal to form ohmic contact between the drift layer 102 and the first ohmic contact metal layer 107 and the second ohmic contact metal layer 108; obtain a wide bandgap semiconductor withstand voltage unit 1.

[0054] S4, combining the semiconductor material layer 301 with the upper surface of the wide bandgap semiconductor withstand voltage unit 1 (such as Fig. 9 and Fig.10 as shown).

[0055] S5, manufacturing a switch control unit 3 (such as Figures 11 to 13 as shown).

[0056] S6. In the corresponding area where the switch control unit 3 and the wide bandgap semiconductor withstand voltage unit 1 need to be electrically connected, a through hole 302 is etched that at least penetrates the semiconductor material layer 301. A first dielectric layer 303 is deposited on the sidewall of the through hole 302. Then, a conductive material is deposited on the upper surface of the semiconductor material layer 301 and inside the through hole 302, and etched to obtain a conductive plug 4. At this point, the vertical integration of the wide bandgap semiconductor withstand voltage unit 1 and the switch control unit 3 is completed.

[0057] In some specific embodiments, the annealing conditions in step S2 are: annealing at a temperature of 400°C to 1100°C for 5 to 300 seconds. For example, the annealing temperature is 400°C, 405°C, 410°C, 420°C, 430°C, 450°C, 500°C, 550°C, 600°C, ... 1100°C; the annealing time is 5s, 6s, 7s, 8s, 9s, 10s, 12s, 15s, 20s, 30s, 40s, 60s, 100s ... 300s.

[0058] In some specific embodiments, the annealing conditions in step S3 are: XXX is annealed at 400°C-1100°C for 5-300s. For example, the annealing temperature is 400°C, 402°C, 408°C, 410°C, 415°C, 425°C, 480°C, 520°C, 580°C, 600°C...1100°C; the annealing time is 5s, 8s, 10s, 15s, 20s, 30s, 35s, 50s, 70s, 75s, 90s...300s.

[0059] In some specific embodiments, the semiconductor material layer 301 is bonded to the upper surface of the wide bandgap semiconductor withstand voltage unit 1 in step S4 by the following method: a bonding interface layer 2 is deposited on the upper surface of the wide bandgap semiconductor withstand voltage unit 1 by CVD, ALD or spin coating process. A semiconductor material layer 301 is bonded to the upper surface of the bonding interface layer 2 by a wafer-level bonding process. The through hole 302 in step S6 penetrates the semiconductor material layer 301 and the bonding interface layer 2.

[0060] In some other specific embodiments, in step S4 , the semiconductor material layer 301 is epitaxially grown directly on the upper surface of the wide bandgap semiconductor voltage-withstanding unit 1 by MOCVD or MBE method, thereby bonding the semiconductor material layer 301 to the upper surface of the wide bandgap semiconductor voltage-withstanding unit 1 .

[0061] Reference Fig.10 , Fig.13 and Figure 1Taking the MOSFET switch control unit as an example, in step S5, a well region 304 is first formed in the source region of the semiconductor material layer 301 by ion implantation, and then a second doping region 305 with interval distribution is formed in the top layer of the semiconductor material layer 301 by ion implantation. A portion of the second doping region 305 is located in the well region 304 as a source doping region. Ohmic contact metal is deposited on the upper surface of the semiconductor material layer 301 and etched, and the ohmic contact metal of the area that needs to be electrically connected to the wide bandgap semiconductor withstand voltage unit 1 is retained to obtain a third ohmic contact metal layer 306 and a fourth ohmic contact metal layer 307. Annealing (annealing conditions are the same as in step S3) is performed to form ohmic contacts between the semiconductor material layer 301 and the third ohmic contact metal layer 306 and the fourth ohmic contact metal layer 307. Insulating material is deposited on the upper surface of the semiconductor material layer 301 and etched to obtain a gate dielectric layer, and a gate 5 is made on the upper surface of the gate dielectric layer. Then, insulating material is deposited and etched on the surface of the obtained device to obtain an interlayer dielectric layer. The gate dielectric layer and the interlayer dielectric layer are collectively referred to as the isolation layer 308. Metal is continuously deposited on the upper surface of the obtained device structure and etched to obtain the source 6; metal is deposited on the surface of the substrate 101 away from the drift layer 102 to obtain the drain 7.

[0062] Reference Fig.12 , Fig.13 , Fig.15 , Fig.16 , Figure 2 and Figure 3 Taking the p-GaN HEMT switch control unit as an example, the semiconductor material layer 301 in step S5 is a GaN layer, an AlGaN layer 309 is deposited on the upper surface of the GaN layer, a p-type GaN is deposited on the upper surface of the AlGaN layer 309 and etched to obtain a p-GaN layer 310, and a conductive material is deposited on the upper surface of the p-GaN layer 310 and etched to obtain a gate 5. An insulating material is deposited on the surface of the obtained device structure and etched to obtain an interlayer dielectric layer. The interlayer dielectric layer is used as an isolation layer 308 to isolate the gate 5 from the source 6 that is subsequently manufactured. Metal is continuously deposited and etched on the upper surface of the obtained device structure to obtain a source 6. Metal is deposited on the surface of the substrate 101 away from the drift layer 102 to obtain a drain 7.

[0063] The above-described embodiments are only preferred embodiments of the present application and are not intended to limit the scope of protection of the present application. For any person skilled in the art, the present application may have various changes and modifications. Any simple equivalent changes and modifications made based on the scope of protection of the present application and the contents of the specification should be included in the scope of protection of the present application.

Claims

1. A wide bandgap semiconductor composite chip structure, characterized in that: The cell structure of the composite chip structure includes, from bottom to top, a substrate, a drift layer, a first buried layer and a switch control unit; a second buried layer with island-shaped distribution is provided in the drift layer; the second buried layer is connected to the first buried layer through a connecting column; a first doped region penetrating the first buried layer and located above the second buried layer is provided in the first buried layer; a first ohmic contact metal layer and a second ohmic contact metal layer are deposited on the upper surface of the first buried layer and in an area that needs to be electrically connected to the switch control unit; the second ohmic contact metal layer is located on the upper surface of the first doped region; The switch control unit comprises a semiconductor material layer, a third ohmic contact metal layer and a fourth ohmic contact metal layer located on the upper surface of the semiconductor material layer; a plurality of conductive plugs at least penetrating the semiconductor material layer are arranged in the semiconductor material layer; the first ohmic contact metal layer is electrically connected to the third ohmic contact metal layer through the conductive plugs; The second ohmic contact metal layer is electrically connected to the fourth ohmic contact metal layer through the conductive plug; The doping types of the substrate, the drift layer, the first doping region, and the semiconductor material layer are of the first type, and the doping types of the first buried layer, the second buried layer, and the connecting column are of the second type.

2. The composite chip structure according to claim 1, characterized in that: A bonding interface layer is disposed on the upper surface of the first buried layer, and the semiconductor material layer is located on the upper surface of the bonding interface layer.

3. The composite chip structure according to claim 2, characterized in that: The material of the bonding interface layer is silicon dioxide or BCB.

4. The composite chip structure according to claim 2, characterized in that: The size of the bonding interface layer along the direction from the substrate to the bonding interface layer is 1 nm to 10 μm.

5. The composite chip structure according to claim 1, characterized in that: The material of the substrate is at least one of single crystal SiC, polycrystalline SiC, and Si; or / and, the material of the drift layer is at least one of SiC, GaN, Ga2O3, and AlN; or / and, the material of the semiconductor material layer is at least one of silicon, GaN, and 3C-SiC.

6. The composite chip structure according to claim 1, characterized in that: The size of the drift layer along the direction from the substrate to the first buried layer is 1000nm~150μm; or / and, the size of the first buried layer along the direction from the substrate to the first buried layer is 10nm~500nm; or / and, the size of the semiconductor material layer along the direction from the substrate to the semiconductor material layer is 100nm~10μm.

7. The composite chip structure according to claim 1, characterized in that: The switch control unit is any one of a MOSFET device, a HEMT device, an NPN transistor, a PNP transistor, a JFET switch control unit or a diode.

8. The composite chip structure according to claim 1, characterized in that: The conductive plug is made of at least one of titanium, titanium nitride, tungsten, aluminum and copper.

9. The method for preparing the composite chip structure according to any one of claims 1 to 8, characterized in that: The following steps are involved: S1, forming the drift layer on the surface of one side of the substrate; forming a first buried layer on the top layer or upper surface of the drift layer; S2, forming the second buried layer and the connecting pillar distributed in an island shape in the drift layer, forming the first doped region in the first buried layer, and annealing; S3, depositing an ohmic contact metal on the upper surface of the first buried layer, and etching to reserve an area that needs to be electrically connected to other devices to obtain the first ohmic contact metal layer and the second ohmic contact metal layer, and annealing; A wide bandgap semiconductor withstand voltage unit is obtained; S4, combining the semiconductor material layer with the upper surface of the wide bandgap semiconductor voltage-resistant unit; S5, manufacturing the switch control unit in the semiconductor material layer; S6. Etch a through hole that at least penetrates the semiconductor material layer in the corresponding area where the switch control unit and the wide bandgap semiconductor withstand voltage unit need to be electrically connected; deposit a first dielectric layer on the side wall of the through hole, and then deposit a conductive material on the upper surface of the semiconductor material layer and inside the through hole, and etch to obtain the conductive plug.

10. The preparation method according to claim 9, characterized in that: The following steps are involved: An isolation layer, a gate electrode and a source electrode are formed on the upper surface of the device structure obtained in step S6, wherein the isolation layer isolates the gate electrode and the source electrode; A drain is formed on a surface of the substrate facing away from the drift layer.

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