Array substrate and display panel

Abstract

This application discloses an array substrate and a display panel. The array substrate includes a substrate, a first metal layer, a common electrode layer, and a capacitance compensation block. The first metal layer is disposed on one side of the substrate and includes a first scan line and a second scan line. The common electrode layer is disposed on the side of the first metal layer away from the substrate and includes multiple spaced-apart region blocks. Each region block is multiplexed as a touch electrode and includes multiple rows of common electrodes arranged along a column direction and a connection portion connecting two adjacent rows of common electrodes. The capacitance compensation block is electrically connected to a region block. In a plan view of the array substrate, the first scan line is located between two adjacent rows of common electrodes in the same region block and partially overlaps with the connection portion. The second scan line is located between two adjacent region blocks, and the capacitance compensation block at least partially overlaps with the second scan line. This application can improve the display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate and a display panel. Background Technology

[0002] In-cell flat panel display technology with high resolution and excellent image quality is one of the key technologies in the industry. Touch screen reporting is achieved by graphically dividing the common electrode layer into multiple area blocks. The pen / hand causes changes in the capacitance of local area blocks. Adjacent area blocks are disconnected. Each area block corresponds to multiple scan lines. The overlap area between the area block and the corresponding scan line will affect the load of the corresponding scan line.

[0003] In a given area, the scan lines located at the center of the area have a larger overlap with the area, while those located at the edges have a smaller overlap. Therefore, the load on the scan lines at the center is greater than that on the edges, resulting in horizontal lines appearing on the display and affecting the display quality.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0005] The purpose of this application is to provide an array substrate and a display panel to improve the display effect.

[0006] To solve the above problems, the technical solution of this application is as follows:

[0007] In a first aspect, this application proposes an array substrate, comprising:

[0008] Substrate;

[0009] A first metal layer is disposed on one side of the substrate and includes a first scan line and a second scan line;

[0010] A common electrode layer is disposed on the side of the first metal layer away from the substrate. The common electrode layer includes a plurality of spaced-apart region blocks, each region block being multiplexed as a touch electrode. Each region block includes a plurality of rows of common electrodes arranged along a column direction and a connecting portion connecting two adjacent rows of common electrodes.

[0011] A capacitor compensation block is electrically connected to one of the aforementioned region blocks;

[0012] In a plan view of the array substrate, the first scan line is located between two adjacent common electrode rows in the same region block and partially overlaps with the connection portion;

[0013] The second scan line is located between two adjacent region blocks, and the capacitance compensation block at least partially overlaps with the second scan line.

[0014] In one embodiment of this application, the capacitor compensation block is disposed on the same layer as the region block and is connected to the edge of one region block near the edge of another region block.

[0015] In one embodiment of this application, the capacitor compensation block is integrally formed with the common electrode row located at the edge of the region block.

[0016] In one embodiment of this application, the plurality of region blocks include a first region block and a second region block spaced apart along the column direction;

[0017] The first region block includes a first common electrode row, a second common electrode row, and a first connecting portion. The second common electrode row is located on the side of the first common electrode row closer to the second region block, and the first connecting portion connects the first common electrode row and the second common electrode row.

[0018] The second region block includes a third common electrode row, a fourth common electrode row, and a second connecting portion. The fourth common electrode row is located on the side of the third common electrode row that is close to the first region block. The second connecting portion connects the third common electrode row and the third common electrode row.

[0019] In a plan view of the array substrate, a first scan line is located between the first common electrode row and the second common electrode row, and overlaps with the first connection portion;

[0020] A first scan line is located between the third common electrode row and the fourth common electrode row, and partially overlaps with the second connection portion;

[0021] A second scan line is located between the second common electrode row and the fourth common electrode row, and at least partially overlaps with the capacitance compensation block;

[0022] Among them, between two adjacent first region blocks and second region blocks, the capacitance compensation block includes a first compensation block;

[0023] In the first region block, the side of the second common electrode row closest to the fourth common electrode row is the first side;

[0024] In the second region block, the side of the fourth common electrode row closest to the second common electrode row is the second side, and the first compensation block is connected to one of the first side and the second side;

[0025] In a plan view of the array substrate, the first compensation block at least partially overlaps with the second scan line.

[0026] In one embodiment of this application, between two adjacent first region blocks and second region blocks, the capacitor compensation block further includes a second compensation block, which is connected to the other side of the first side and the second side, and the second compensation block is spaced apart from the first compensation block;

[0027] In a plan view of the array substrate, the second compensation block at least partially overlaps with the second scan line.

[0028] In one embodiment of this application, the second common electrode row includes a plurality of first sub-electrodes arranged along the row direction, and each first sub-electrode is connected to the first compensation block on the side near the fourth common electrode row.

[0029] The fourth common electrode row includes a plurality of second sub-electrodes arranged along the row direction, and each second sub-electrode is connected to the second compensation block on the side of the second common electrode row.

[0030] In one embodiment of this application, in a plan view of the array substrate, the overlapping area of ​​the first compensation block and the second scan line is the first overlapping area, and the overlapping area of ​​the second compensation block and the second scan line is the second overlapping area, wherein the first overlapping area is equal to the second overlapping area.

[0031] In one embodiment of this application, in a plan view of the array substrate, the second scan line is located on one side of the second common electrode row, the second scan line is spaced apart from the fourth common electrode row, and the area of ​​the first compensation block is smaller than the area of ​​the second compensation block.

[0032] In one embodiment of this application, the common electrode row includes a plurality of sub-electrodes arranged along the row direction;

[0033] The array substrate further includes:

[0034] Multiple pixel electrodes, wherein one pixel electrode is configured to correspond to one sub-electrode;

[0035] A second metal layer is disposed between the first metal layer and the common electrode layer. The second metal layer includes multiple data lines that extend along the column direction and are arranged along the row direction.

[0036] In a plan view of the array substrate, a column of pixel electrodes is provided between two adjacent data lines; in the column of pixel electrodes, the pixel electrodes in odd-numbered rows are electrically connected to one of the two adjacent data lines, and the pixel electrodes in even-numbered rows are electrically connected to the other of the two adjacent data lines.

[0037] In one embodiment of this application, the first metal layer further includes:

[0038] A first gate is connected to the first scan line, and a pixel electrode is correspondingly disposed on the first gate;

[0039] The third compensation block is connected to the first scan line and located on one side of the first gate;

[0040] A second gate is connected to the second scan line, and a pixel electrode is correspondingly disposed on the second gate; and

[0041] The fourth compensation block is connected to the second scan line and is located on one side of the second gate;

[0042] Within the same region block, the connecting portion forms a first capacitor with the adjacent third compensation block, and the capacitor compensation block forms a second capacitor with the adjacent fourth compensation block.

[0043] In one embodiment of this application, the second metal layer further includes:

[0044] A first drain is disposed corresponding to the first gate, and the first drain is electrically connected to the pixel electrode corresponding to the first gate;

[0045] The second drain is disposed corresponding to the second gate, and the second drain is electrically connected to the pixel electrode corresponding to the second gate;

[0046] In a plan view of the array substrate, the third compensation block, the first drain, and the pixel electrode corresponding to the first drain overlap, and the fourth compensation block, the second drain, and the pixel electrode corresponding to the second drain overlap.

[0047] In one embodiment of this application, the common electrode row includes a plurality of sub-electrodes arranged along the row direction;

[0048] The array substrate further includes:

[0049] Multiple pixel electrodes, wherein one pixel electrode is configured to correspond to one sub-electrode;

[0050] A second metal layer is disposed between the first metal layer and the common electrode layer. The second metal layer includes multiple data lines that extend along the column direction and are arranged along the row direction.

[0051] In a plan view of the array substrate, a data line is disposed on one side of a plurality of pixel electrodes in the same column, and the plurality of pixel electrodes in the same column are electrically connected to the corresponding data line.

[0052] Secondly, this application proposes a display panel including an array substrate. The array substrate includes a substrate, a first metal layer, a common electrode layer, and a capacitance compensation block. The first metal layer is disposed on one side of the substrate and includes a first scan line and a second scan line. The common electrode layer is disposed on the side of the first metal layer away from the substrate. The common electrode layer includes a plurality of spaced-apart region blocks. The region blocks are multiplexed as touch electrodes. Each region block includes a plurality of common electrode rows arranged along a column direction and a connection portion connecting two adjacent common electrode rows. The capacitance compensation block is electrically connected to one of the region blocks. In a plan view of the array substrate, the first scan line is located between two adjacent common electrode rows in the same region block and partially overlaps with the connection portion. The second scan line is located between two adjacent region blocks, and the capacitance compensation block at least partially overlaps with the second scan line.

[0053] In this application, a capacitance compensation block is provided between two adjacent area blocks, and the capacitance compensation block overlaps at least partially with the second scan line. Because the load of the second scan line increases after the second scan line overlaps with the capacitance compensation block, the difference in load between the first scan line located at the center of the same area block and the second scan line located at the edge of the area block is reduced, weakening the impact of horizontal lines on the display effect and thus improving the display effect. Attached Figure Description

[0054] Figure 1 This is a plan view of the array substrate of this application;

[0055] Figure 2 yes Figure 1 Enlarged view of point A in the middle;

[0056] Figure 3 yes Figure 2 Enlarged view of point B in the middle;

[0057] Figure 4 This is a schematic diagram of the array substrate of the column inversion architecture of this application;

[0058] Figure 5 This is a schematic diagram of the array substrate of the dot inversion architecture of this application;

[0059] Figure 6 This is a schematic diagram of an embodiment of the first scan line and common electrode row of the dot inversion architecture of this application;

[0060] Figure 7 This is a schematic diagram of an embodiment of the second scan line and common electrode row of the dot inversion architecture of this application;

[0061] Figure 8 yes Figure 2 An enlarged view of an embodiment at point C;

[0062] Figure 9 yes Figure 2 An enlarged view of another embodiment at point C;

[0063] Figure 10 yes Figure 2 An enlarged view of another embodiment at point C. Detailed Implementation

[0064] The terms used in this specification and claims have the meanings that are commonly understood by one of ordinary skill in the art to which this application pertains. The terms used in this specification and claims are for the purpose of facilitating the description and understanding of this application only, and are not intended to limit this application to the narrow interpretation of the specific terms used in the specification and claims.

[0065] This application proposes a display panel that can be applied to tablet computers, e-readers, electronic display screens, laptops, mobile phones, augmented reality (AR) / virtual reality (VR) devices, media players, wearable devices, digital cameras, car navigation systems, etc.

[0066] Optionally, the display panel is a liquid crystal display (LCD). The embodiments of this application are described using a liquid crystal display panel as an example, and the display panel includes an array substrate 100.

[0067] Please see Figure 1This application discloses an array substrate 100, including a substrate 10, a first metal layer 20, a common electrode layer 30, and a capacitor compensation block 40. The first metal layer 20 is disposed on one side of the substrate 10 and includes a first scan line 21 and a second scan line 22. The common electrode layer 30 is disposed on the side of the first metal layer 20 away from the substrate 10. The common electrode layer 30 includes a plurality of spaced-apart region blocks 31. The region blocks 31 are multiplexed as touch electrodes. The region block 31 includes a plurality of common electrode rows 32 arranged along the column direction and a connection portion 33 connecting two adjacent common electrode rows 32. The capacitor compensation block 40 is electrically connected to a region block 31.

[0068] Please see Figure 2 In a plan view of the array substrate 100, the first scan line 21 is located between two adjacent common electrode rows 32 of the same region block 31 and partially overlaps with the connection portion 33. The second scan line 22 is located between two adjacent region blocks 31. The capacitor compensation block 40 at least partially overlaps with the second scan line 22.

[0069] In this application, a capacitance compensation block 40 is provided between two adjacent region blocks 31, and the capacitance compensation block 40 overlaps at least partially with the second scan line 22. Because the second scan line 22 overlaps with the capacitance compensation block 40, the load on the second scan line 22 increases, thereby reducing the difference in load between the first scan line 21 located at the center of the same region block 31 and the second scan line 22 located at the edge of the same region block 31. This weakens the impact of horizontal lines on the display effect, thereby improving the display effect.

[0070] Optionally, the substrate 10 is a flexible substrate 10, and the material of the substrate 10 is polyimide.

[0071] Optionally, the substrate 10 is a rigid substrate 10, and the material of the substrate 10 is glass.

[0072] Optionally, the array substrate 100 also includes multiple touch traces 62. Each touch trace 62 is electrically connected to a region block 31, and the touch trace 62 is also electrically connected to a chip disposed in a non-display area. The touch traces 62 can be disposed between the substrate 10 and the first metal layer 20, or they can be disposed on the same layer as the second metal layer 60. The placement of the touch traces 62 is not limited here.

[0073] Optionally, the capacitor compensation block 40 and the area block 31 are disposed in different layers. Optionally, the capacitor compensation block 40 is disposed between the common electrode layer 30 and the first metal layer 20, which can further increase the capacitance formed by the capacitor compensation block 40 and the second scan line 22, thereby increasing the load of the second scan line 22 and further reducing the load difference between the first scan line 21 and the second scan line 22, further weakening the impact of horizontal lines on the display effect, thereby improving the display effect.

[0074] Please see Figure 3 Optionally, the capacitor compensation block 40 is disposed on the same layer as the region block 31 and connected to the edge of one region block 31 near the edge of another region block 31. Compared with the embodiment where the capacitor compensation block 40 and the region block 31 are disposed on different layers, this embodiment can reduce the process of forming the film layer where the capacitor compensation block 40 is located by one step, and form the capacitor compensation block 40 and the region block 31 in one step, thereby improving production efficiency and reducing production costs.

[0075] Please see Figure 3 Optionally, the capacitor compensation block 40 is integrally formed with the common electrode row 32 located at the edge of the region block 31. In this embodiment, the material of the capacitor compensation block 40 is the same as that of the region block 31. During the patterning process of forming the region block 31, the capacitor compensation block 40 can be formed simultaneously, thereby further improving production efficiency and reducing production costs.

[0076] Optionally, the common electrode row 32 includes a plurality of sub-electrodes 34 arranged along the row direction.

[0077] Please see Figure 4 Optionally, the array substrate 100 is a stripe-structured array substrate 100. The stripe-structured array substrate 100 further includes multiple pixel electrodes 50 and a second metal layer 60. Each pixel electrode 50 is correspondingly disposed with a sub-electrode 34. The second metal layer 60 is disposed between the first metal layer 20 and the common electrode layer 30. The second metal layer 60 includes multiple data lines 61. The data lines 61 extend along the column direction. The multiple data lines 61 are arranged along the row direction.

[0078] In a plan view of the array substrate 100 with column inversion architecture, a data line 61 is disposed on one side of multiple pixel electrodes 50 in the same column, and the multiple pixel electrodes 50 in the same column are electrically connected to the corresponding data line 61.

[0079] In the column-inverted architecture array substrate 100, multiple sub-pixels are included. Each sub-pixel includes a sub-electrode 34 and a pixel electrode 50 corresponding to the sub-electrode 34. In the column-inverted architecture, the pixels are arranged in a column-flipped manner, meaning that sub-pixels in adjacent columns alternately display different colors during display to reduce visual ghosting and improve display quality. In the column-inverted architecture, the pixels are arranged column-wise, which means that pixels in the same column share the same data line 61. This arrangement helps reduce the number of data lines 61, thereby reducing cost and complexity. Since the data lines 61 are shared column-wise, pixels in the same column are driven simultaneously. This driving method can improve the refresh rate because only the data of one column of pixels needs to be processed at a time. By setting a capacitor compensation block 40 in the column-inverted architecture, the load difference between the first scan line 21 and the second scan line 22 corresponding to a single area block 31 can be reduced, weakening the impact of horizontal stripes on the display effect, thereby improving the display effect.

[0080] Please see Figure 5 Optionally, the array substrate 100 is a flip-flop array substrate 100. The flip-flop array substrate 100 further includes multiple pixel electrodes 50 and a second metal layer 60. Each pixel electrode 50 is correspondingly disposed with a sub-electrode 34. The second metal layer 60 is disposed between the first metal layer 20 and the common electrode layer 30. The second metal layer 60 includes multiple data lines 61. The data lines 61 extend along the column direction. The multiple data lines 61 are arranged along the row direction.

[0081] In a plan view of the dot-inverted array substrate 100, a column of pixel electrodes 50 is provided between two adjacent data lines 61. In a column of pixel electrodes 50, the pixel electrodes 50 in odd-numbered rows are electrically connected to one of the two adjacent data lines 61, and the pixel electrodes 50 in even-numbered rows are electrically connected to the other of the two adjacent data lines 61.

[0082] The dot-inverted array substrate 100 includes multiple sub-pixels. Each sub-pixel includes a sub-electrode 34 and a pixel electrode 50 corresponding to the sub-electrode 34. In the dot-inverted array substrate 100, the pixels are arranged in a dot-inverted manner, meaning that each pixel is a different color from its neighboring pixels, thereby reducing visual ghosting and improving display quality. In the dot-inverted array substrate 100, a single data line 61 can simultaneously drive pixels of two different colors in two adjacent columns, a design that simplifies the driving circuitry.

[0083] Optionally, in the dot-inversion array substrate 100, the first metal layer 20 further includes a first gate 23, a third compensation block 24, a second gate 25, and a fourth compensation block 26. The first gate 23 is connected to the first scan line 21. A pixel electrode 50 is correspondingly disposed on the first gate 23. The third compensation block 24 is connected to the first scan line 21 and is located on one side of the first gate 23. The second gate 25 is connected to the second scan line 22. A pixel electrode 50 is correspondingly disposed on the second gate 25. The fourth compensation block 26 is connected to the second scan line 22 and is located on one side of the second gate 25. In the same region block 31, the connection portion 33 and the adjacent third compensation block 24 form a first capacitor, and the capacitor compensation block 40 and the adjacent fourth compensation block 26 form a second capacitor.

[0084] In traditional dot-inversion array substrates, due to the non-repetitive design of adjacent odd-numbered and even-numbered sub-pixels, a shift in the second metal layer 60 relative to the first metal layer 20 during the fabrication process can cause differences in the compensation capacitance between even-numbered and odd-numbered sub-pixels. To address this issue, please refer to [link to relevant documentation]. Figure 6 The first scan line 21 connects to the third compensation block 24, and the second scan line 22 connects to the fourth compensation block 26. When the second metal layer 60 is offset relative to the first metal layer 20, the difference in compensation capacitance between even-numbered and odd-numbered sub-pixels can be reduced. However, since the first scan line 21 is equipped with the third compensation block 24, the third compensation block 24 forms a first capacitance with the connection part 33. The second scan line 22 is equipped with the fourth compensation block 26, and therefore cannot form a capacitance with the connection part 33. This further increases the load difference between the first scan line 21 in the center of the region block 31 and the second scan line 22 at the edge of the region block 31.

[0085] Please see Figure 7 In this embodiment, a capacitor compensation block 40 is provided at the edge of the region block 31, and the capacitor compensation block 40 and the fourth compensation block 26 form a second capacitor. Due to the formation of the second capacitor, the load difference between the first scan line 21 and the second scan line 22 can be reduced, the impact of horizontal lines on the display effect can be weakened, and thus the display effect can be improved.

[0086] Optionally, the capacitance value of the second capacitor is greater than that of the first capacitor, thereby further reducing the load difference between the first scan line 21 and the second scan line 22, weakening the impact of horizontal lines on the display effect, and thus improving the display effect.

[0087] Optionally, in the dot-inversion array substrate 100, the second metal layer 60 further includes a first drain 63 and a second drain 64. The first drain 63 is disposed corresponding to the first gate 23. The first drain 63 is electrically connected to the pixel electrode 50 corresponding to the first gate 23. The second drain 64 is disposed corresponding to the second gate 25. The second drain 64 is electrically connected to the pixel electrode 50 corresponding to the second gate 25.

[0088] In a plan view of the array substrate 100 with the dot-inversion architecture, the third compensation block 24, the first drain 63, and the pixel electrode 50 corresponding to the first drain 63 overlap. The fourth compensation block 26, the second drain 64, and the pixel electrode 50 corresponding to the second drain 64 overlap.

[0089] In a traditional dot-inversion array substrate, when the second metal layer 60 is offset relative to the first metal layer 20, the compensation capacitance of even-numbered sub-pixels differs from that of odd-numbered sub-pixels. This embodiment addresses this by setting a third compensation block 24 and a fourth compensation block 26, with the third compensation block 24 overlapping with the first drain 63 and the pixel electrode 50, and the fourth compensation block 26 overlapping with the second drain 64 and the pixel electrode 50. This reduces the difference in compensation capacitance between even-numbered and odd-numbered sub-pixels, improving the display performance of the dot-inversion array substrate 100.

[0090] Optionally, in the dot-inversion architecture array substrate 100, the array substrate 100 further includes a semiconductor layer located between the second metal layer 60 and the first metal layer 20. The semiconductor layer includes a first active layer 71 and a second active layer 72. The first active layer 71 overlaps with the first gate 23, a portion of the first drain 63 overlaps with the first active layer 71, and a portion of the data line 61 corresponding to the first drain 63 overlaps with the first active layer 71; this portion of the data line 61 is multiplexed as a source. The second active layer 72 overlaps with the second gate 25, a portion of the second drain 64 overlaps with the second active layer 72, and a portion of the data line 61 corresponding to the second drain 64 overlaps with the second active layer 72; this portion of the data line 61 is multiplexed as a source.

[0091] Please see Figure 8 In the first embodiment of this application:

[0092] Optionally, the plurality of region blocks 31 include a first region block 31a and a second region block 31b that are spaced apart along the column direction.

[0093] The first region block 31a includes a first common electrode row, a second common electrode row 32a, and a first connecting portion 33. The second common electrode row 32a is located on the side of the first common electrode row closer to the second region block 31b. The first connecting portion 33 connects the first common electrode row and the second common electrode row 32a.

[0094] The second region block 31b includes a third common electrode row, a fourth common electrode row 32b, and a second connecting portion 33. The fourth common electrode row 32b is located on the side of the third common electrode row closest to the first region block 31a. The second connecting portion 33 connects the third common electrode row and the third common electrode row.

[0095] In a plan view of the array substrate 100, a first scan line 21 is located between the first common electrode row and the second common electrode row 32a, and overlaps with the first connection portion 33.

[0096] A first scan line 21 is located between the third common electrode row and the fourth common electrode row 32b, and partially overlaps with the second connection portion 33.

[0097] A second scan line 22 is located between the second common electrode row 32a and the fourth common electrode row 32b, and at least partially overlaps with the capacitor compensation block 40.

[0098] Among them, between two adjacent first region blocks 31a and second region blocks 31b, the capacitor compensation block 40 includes a first compensation block 41.

[0099] In the first region block 31a, the side of the second common electrode row 32a closest to the fourth common electrode row 32b is the first side.

[0100] In the second region block 31b, the side of the fourth common electrode row 32b closest to the second common electrode row 32a is the second side. The first compensation block 41 is connected to the first side.

[0101] In a plan view of the array substrate 100, the first compensation block 41 at least partially overlaps with the second scan line 22.

[0102] In the first embodiment of this application, between two adjacent first region blocks 31a and second region blocks 31b, a first compensation block 41 is connected to the side of the second common electrode row 32a near the fourth common electrode row 32b, and the first compensation block 41 overlaps at least partially with the second scan line 22. This can increase the load of the second scan line 22, thereby reducing the load difference between the first scan line 21 and the second scan line 22 caused by the overlap of the first scan line 21 with the connecting portion 33, weakening the impact of horizontal lines on the display effect, and thus improving the display effect.

[0103] Please see Figure 9 In the second embodiment of this application:

[0104] To avoid redundancy, the second embodiment of this application will describe the parts that differ from the first embodiment of this application.

[0105] The second embodiment of this application differs from the first embodiment of this application in that:

[0106] Optionally, the first compensation block 41 is connected to the second side.

[0107] In the second embodiment of this application, between two adjacent first region blocks 31a and second region blocks 31b, a first compensation block 41 is connected to the side of the fourth common electrode row 32b near the second common electrode row 32a, and the first compensation block 41 at least partially overlaps with the second scan line 22. This can increase the load of the second scan line 22, thereby reducing the load difference between the first scan line 21 and the second scan line 22 caused by the overlap of the first scan line 21 with the connecting portion 33, weakening the impact of horizontal lines on the display effect, and thus improving the display effect.

[0108] Please see Figure 10 In the third embodiment of this application:

[0109] To avoid redundancy, the third embodiment of this application will describe the parts that differ from the first embodiment of this application.

[0110] The third embodiment of this application differs from the first embodiment in that:

[0111] Optionally, between two adjacent first region blocks 31a and second region blocks 31b, the capacitor compensation block 40 further includes a second compensation block 42. The second compensation block 42 is connected to the other side of the first side and the second side, and the second compensation block 42 is spaced apart from the first compensation block 41.

[0112] In a plan view of the array substrate 100, the second compensation block 42 at least partially overlaps with the second scan line 22.

[0113] In the third embodiment of this application, between two adjacent first region blocks 31a and second region blocks 31b, a second compensation block 42 is connected to the side of the fourth common electrode row 32b near the second common electrode row 32a, and the second compensation block 42 at least partially overlaps with the second scan line 22. Based on the first embodiment, the load of the second scan line 22 can be further increased, thereby further reducing the load difference between the first scan line 21 and the second scan line 22 caused by the overlap of the first scan line 21 with the connecting part 33, further weakening the influence of horizontal lines on the display effect, and thus further improving the display effect.

[0114] Optionally, between two adjacent first region blocks 31a and second region blocks 31b, the first compensation block 41 connected to the first region block 31a is insulated from the second compensation block 42 connected to the second region block 31b.

[0115] Optionally, the second common electrode row 32a includes a plurality of first sub-electrodes 34a arranged along the row direction. Each first sub-electrode 34a is connected to a first compensation block 41 on the side near the fourth common electrode row 32b.

[0116] The fourth common electrode row 32b includes a plurality of second sub-electrodes 34b arranged along the row direction. Each second sub-electrode 34b is connected to a second compensation block 42 on the side closest to the second common electrode row 32a.

[0117] In this embodiment, in the first region block 31a, the first common electrode row includes a plurality of sub-electrodes 34 arranged along the row direction. The sub-electrodes 34 of the first common electrode row are connected to the first sub-electrodes 34a of the adjacent second common electrode row 32a along the column direction via a connecting portion 33. Therefore, a first scan line 21 located between the first and second common electrode rows 32a overlaps with the plurality of connecting portions 33, resulting in a capacitance formed between the first scan line 21 and the plurality of connecting portions 33, thus causing a large load on the first scan line 21. In this embodiment, a first compensation block 41 is connected to the side of each first sub-electrode 34a near the fourth common electrode row 32b, and multiple first compensation blocks 41 are connected to the side of the second common electrode row 32a near the fourth common electrode row 32b. This causes a second scan line 22 located between the second common electrode row 32a and the fourth common electrode row 32b to overlap with multiple first compensation blocks 41. The multiple first compensation blocks 41 and the second scan line 22 form a capacitor, thereby increasing the load of the second scan line 22 and reducing the load difference between the first scan line 21 and the second scan line 22, weakening the impact of horizontal lines on the display effect, and thus improving the display effect.

[0118] Similarly, in the second region block 31b, the third common electrode row includes multiple sub-electrodes 34 arranged along the row direction. The sub-electrodes 34 of the third common electrode row are connected to the second sub-electrodes 34b of the adjacent fourth common electrode row 32b along the column direction via a connection portion 33. Therefore, a first scan line 21 located between the third and fourth common electrode rows 32b overlaps with the multiple connection portions 33, resulting in a capacitance formed between the first scan line 21 and the multiple connection portions 33, thus causing a large load on the first scan line 21. In this embodiment, a second compensation block 42 is connected to the side of each second sub-electrode 34b near the second common electrode row 32a, so that multiple second compensation blocks 42 are connected to the side of the fourth common electrode row 32b near the second common electrode row 32a. This causes a second scan line 22 located between the second common electrode row 32a and the fourth common electrode row 32b to overlap with multiple second compensation blocks 42. The multiple second compensation blocks 42 and the second scan line 22 form a capacitor, thereby further increasing the load of the second scan line 22 and further reducing the load difference between the first scan line 21 and the second scan line 22, further weakening the impact of horizontal lines on the display effect, and thus further improving the display effect.

[0119] Optionally, in a plan view of the array substrate 100, the overlapping area of ​​the first compensation block 41 and the second scan line 22 is the first overlapping area, and the overlapping area of ​​the second compensation block 42 and the second scan line 22 is the second overlapping area, and the first overlapping area is equal to the second overlapping area.

[0120] In this embodiment, since the first overlapping area is equal to the second overlapping area, the capacitance formed by the first compensation block 41 and the second scan line 22 is the same as the capacitance formed by the second compensation block 42 and the second scan line 22. This avoids capacitance differences between adjacent area blocks 31, which could cause differences in the recovery time of area blocks 31 after touch, leading to display abnormalities and improving the display effect.

[0121] Optionally, in a plan view of the array substrate 100, the second scan line 22 is located on one side of the second common electrode row 32a. The second scan line 22 is spaced apart from the fourth common electrode row 32b. The area of ​​the first compensation block 41 is smaller than the area of ​​the second compensation block 42.

[0122] In this embodiment, in the plan view of the array substrate 100, since the second scan line 22 is located on one side of the second common electrode row 32a, the first compensation block 41 connected to the side of the second common electrode row 32a near the fourth common electrode row 32b can directly overlap with the second scan line 22 and have a first overlapping area. However, since the second scan line 22 and the fourth common electrode row 32b are spaced apart, the second compensation block 42 needs to extend a certain distance along the column direction and cross the distance between the second scan line 22 and the fourth common electrode row 32b before it can overlap with the second scan line 22 and form a second overlapping area. Because the second compensation block 42 needs to cross the distance between the second scan line 22 and the fourth common electrode row 32b, the effective area of ​​the second compensation block 42 must be larger than the effective area of ​​the first compensation block 41.

[0123] The specific embodiments of this application have been described in detail above. The embodiments disclosed above are merely preferred embodiments of this application. Those skilled in the art can make many modifications and improvements without departing from the concept of this application. All such modifications and improvements fall within the scope of protection defined by the claims of this application.

Claims

1. An array substrate, characterized in that, include: Substrate; A first metal layer is disposed on one side of the substrate and includes a first scan line and a second scan line; A common electrode layer is disposed on the side of the first metal layer away from the substrate. The common electrode layer includes a plurality of spaced-apart region blocks. The region blocks are multiplexed as touch electrodes. Each region block includes a plurality of common electrode rows arranged along the column direction and a connection portion connecting two adjacent common electrode rows. Each common electrode row includes a plurality of sub-electrodes arranged along the row direction. Multiple pixel electrodes, wherein one pixel electrode is configured to correspond to one sub-electrode; A second metal layer is disposed between the first metal layer and the common electrode layer. The second metal layer includes multiple data lines that extend along the column direction and are arranged along the row direction. as well as A capacitor compensation block is electrically connected to one of the aforementioned region blocks; In a plan view of the array substrate, the first scan line is located between two adjacent common electrode rows in the same region block and partially overlaps with the connection portion; The second scan line is located between two adjacent region blocks, and the capacitance compensation block at least partially overlaps with the second scan line.

2. The array substrate as described in claim 1, characterized in that, The capacitor compensation block is disposed on the same layer as the area block and is connected to the edge of one area block near the edge of another area block.

3. The array substrate as described in claim 2, characterized in that, The capacitor compensation block is integrally formed with the common electrode row located at the edge of the region block.

4. The array substrate as described in claim 2, characterized in that, The plurality of said region blocks include a first region block and a second region block that are spaced apart along the column direction; The first region block includes a first common electrode row, a second common electrode row, and a first connecting portion. The second common electrode row is located on the side of the first common electrode row closer to the second region block, and the first connecting portion connects the first common electrode row and the second common electrode row. The second region block includes a third common electrode row, a fourth common electrode row, and a second connecting portion. The fourth common electrode row is located on the side of the third common electrode row that is close to the first region block. The second connecting portion connects the third common electrode row and the third common electrode row. In a plan view of the array substrate, a first scan line is located between the first common electrode row and the second common electrode row, and overlaps with the first connection portion; A first scan line is located between the third common electrode row and the fourth common electrode row, and partially overlaps with the second connection portion; A second scan line is located between the second common electrode row and the fourth common electrode row, and at least partially overlaps with the capacitance compensation block; Among them, between two adjacent first region blocks and second region blocks, the capacitance compensation block includes a first compensation block; In the first region block, the side of the second common electrode row closest to the fourth common electrode row is the first side; In the second region block, the side of the fourth common electrode row closest to the second common electrode row is the second side, and the first compensation block is connected to one of the first side and the second side; In a plan view of the array substrate, the first compensation block at least partially overlaps with the second scan line.

5. The array substrate as described in claim 4, characterized in that, Between two adjacent first region blocks and second region blocks, the capacitor compensation block further includes a second compensation block, which is connected to the other side of the first side and the second side, and the second compensation block is spaced apart from the first compensation block. In a plan view of the array substrate, the second compensation block at least partially overlaps with the second scan line.

6. The array substrate as described in claim 5, characterized in that, The second common electrode row includes a plurality of first sub-electrodes arranged along the row direction, and each first sub-electrode is connected to the first compensation block on the side near the fourth common electrode row; The fourth common electrode row includes a plurality of second sub-electrodes arranged along the row direction, and each second sub-electrode is connected to the second compensation block on the side of the second common electrode row.

7. The array substrate as described in claim 6, characterized in that, In the plan view of the array substrate, the overlapping area of ​​the first compensation block and the second scan line is the first overlapping area, and the overlapping area of ​​the second compensation block and the second scan line is the second overlapping area. The first overlapping area is equal to the second overlapping area.

8. The array substrate as claimed in claim 7, characterized in that, In a plan view of the array substrate, the second scan line is located on one side of the second common electrode row, the second scan line is spaced apart from the fourth common electrode row, and the area of ​​the first compensation block is smaller than the area of ​​the second compensation block.

9. The array substrate as claimed in claim 1, characterized in that, In a plan view of the array substrate, a column of pixel electrodes is provided between two adjacent data lines; in the column of pixel electrodes, the pixel electrodes in odd-numbered rows are electrically connected to one of the two adjacent data lines, and the pixel electrodes in even-numbered rows are electrically connected to the other of the two adjacent data lines.

10. The array substrate as claimed in claim 9, characterized in that, The first metal layer further includes: A first gate is connected to the first scan line, and a pixel electrode is correspondingly disposed on the first gate; The third compensation block is connected to the first scan line and located on one side of the first gate; A second gate is connected to the second scan line, and a pixel electrode is correspondingly disposed on the second gate; and The fourth compensation block is connected to the second scan line and is located on one side of the second gate; Within the same region block, the connecting portion forms a first capacitor with the adjacent third compensation block, and the capacitor compensation block forms a second capacitor with the adjacent fourth compensation block.

11. The array substrate as claimed in claim 10, characterized in that, The second metal layer further includes: A first drain is disposed corresponding to the first gate, and the first drain is electrically connected to the pixel electrode corresponding to the first gate; The second drain is disposed corresponding to the second gate, and the second drain is electrically connected to the pixel electrode corresponding to the second gate; In a plan view of the array substrate, the third compensation block, the first drain, and the pixel electrode corresponding to the first drain overlap, and the fourth compensation block, the second drain, and the pixel electrode corresponding to the second drain overlap.

12. The array substrate as claimed in claim 1, characterized in that, In a plan view of the array substrate, a data line is disposed on one side of a plurality of pixel electrodes in the same column, and the plurality of pixel electrodes in the same column are electrically connected to the corresponding data line.

13. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-12.

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