Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, the semiconductor device comprises a substrate, a first grid electrode and a second grid electrode, the substrate comprises an active region, a plurality of grooves are formed in the active region, and the plurality of grooves are arranged along a first direction; the first gate and the second gate extend in the first direction, a first part of the first gate is located on the active region, a second part of the first gate covers the side wall and the bottom of the groove, the first part is connected with the second part, and the second gate is located on the active region. The area of the semiconductor device is reduced, and the integration level of the semiconductor device in integrated circuit design is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] In integrated circuit design, semiconductor IP cores refer to reusable pre-designed modules that can be used to build more complex chip systems. Power Performance Area evaluation is a key step in determining the efficiency and applicability of IP cores in specific applications. Higher performance, lower power consumption and smaller area are the directions for continuous optimization of IP cores. The occupied area refers to the physical space occupied by the IP core on the chip. A smaller IP core area can provide higher integration, thereby accommodating more functional modules on the same chip. Therefore, area optimization is very competitive for IP cores.

[0003] Figure 1 It is a three-dimensional schematic diagram of an OTP device in the prior art. Please refer to Figure 1 , Figure 1 The figure shows a partial structure of an OTP (One Time Programmable) device. The OTP device generally includes an NMOS tube and a MOS capacitor. The OTP device reads "0" by default. The gate oxide portion is broken down by applying a voltage to the gate of the MOS capacitor, and reads "1" after programming. The substrate 10 includes an active region 12 and a trench isolation structure 14. The first gate 21 and the second gate 22 serve as the gate of the NMOS tube and the gate of the MOS capacitor, respectively. The first gate 21 and the second gate 22 extend along a first direction D1 and are arranged at intervals along a second direction D2. The first gate 21 and the second gate 22 are both located on the active region 12. Since the size of the first gate 21 along the first direction D1 is related to the size of the active area 12, that is, the contact area between the first gate 21 and the active area 12 needs to be guaranteed to ensure the electrical performance of the OTP device (the contact area between the gate (the second gate 22) of the MOS capacitor and the active area 12 does not need to be guaranteed), and since the first gate 21 is located on the active area 12, in order to obtain a larger contact area between the first gate 21 and the active area 12, the size of the first gate 21 along the first direction D1 and the size S1 of the active area 12 are generally larger, which makes it difficult to reduce the area of ​​the OTP device and to obtain a higher degree of integration in the integrated circuit design. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for preparing the same, so as to reduce the area of ​​the semiconductor device and improve the integration of the semiconductor device in the design of integrated circuits.

[0005] In order to achieve the above object, the present invention provides a semiconductor device, comprising: A substrate, wherein the substrate comprises an active region, wherein a plurality of grooves are formed in the active region, and the plurality of grooves are arranged along a first direction; The first gate and the second gate both extend along the first direction, the first portion of the first gate is located on the active area, the second portion of the first gate covers the sidewall and bottom of the groove, the first portion and the second portion are connected, and the second gate is located on the active area.

[0006] Optionally, the depth of the groove is smaller than the depth of the active area.

[0007] Optionally, the thickness of the first gate is smaller than the depth of the groove.

[0008] Optionally, a size of the groove along the second direction is smaller than or equal to a size of the first gate along the second direction, and the first direction and the second direction intersect perpendicularly.

[0009] Optionally, a size of the groove along the first direction is smaller than a size of the active area along the first direction.

[0010] Optionally, the plurality of grooves are arranged in a strip shape, and the first gate and the second gate are both in a strip shape.

[0011] Optionally, it also includes a first doped region, a second doped region and a third doped region, the first doped region and the second doped region are respectively located in the active regions on both sides of the first gate, the second doped region is located in the active region between the first gate and the second gate, and the second doped region and the third doped region are respectively located in the active regions on both sides of the second gate.

[0012] Optionally, a trench isolation structure is further included, which is located in the substrate and extends along the first direction, and the groove, the first doping region, the second doping region and the third doping region are all located between adjacent trench isolation structures.

[0013] Optionally, the semiconductor device is an OTP device.

[0014] The present invention also provides a method for preparing a semiconductor device, comprising: Providing a substrate, wherein the substrate includes an active area, a plurality of grooves are formed in the active area, and the plurality of grooves are arranged along a first direction; A first gate and a second gate are formed, both extending along the first direction, a first portion of the first gate is located on the active area, a second portion of the first gate covers the sidewall and bottom of the groove, the first portion and the second portion are connected, and the second gate is located on the active area.

[0015] In the semiconductor device and the preparation method thereof provided by the present invention, the substrate includes an active area, a plurality of grooves are formed in the active area, and the plurality of grooves are arranged along a first direction; the first gate and the second gate both extend along the first direction, the first part of the first gate is located on the active area, the second part of the first gate covers the sidewall and bottom of the groove, the first part and the second part are connected, and the second gate is located on the active area. The present invention provides a plurality of grooves in the active area, the plurality of grooves are arranged along the first direction, the first gate extends along the first direction, the arrangement direction of the grooves is the same as the extension direction of the first gate, so that part of the first gate covers the sidewall and bottom of the groove, so as to increase the contact area between the first gate and the active area, thereby reducing the size of the active area along the first direction, reducing the area of ​​the semiconductor device, and improving the integration of the semiconductor device in the integrated circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a three-dimensional schematic diagram of an OTP device in the prior art.

[0017] Figure 2 A three-dimensional schematic diagram of a semiconductor device provided by an embodiment of the present invention.

[0018] Figure 3 for Figure 2 3D schematic diagram along section line C1C2.

[0019] Figure 4 for Figure 2 Schematic cross-sectional view along section line A1A2.

[0020] Figure 5 for Figure 2 Schematic cross-sectional view along section line B1B2.

[0021] Figure 6 for Figure 2 Schematic cross-sectional view along section line C1C2.

[0022] Figure 7 A three-dimensional schematic diagram of a method for preparing a semiconductor device provided in an embodiment of the present invention after providing a substrate.

[0023] Figure 8 A three-dimensional schematic diagram of a method for preparing a semiconductor device provided in an embodiment of the present invention after a groove is formed.

[0024] Fig. 9 for Figure 8 Schematic cross-sectional view along section line C1C2.

[0025] Fig.10 A three-dimensional schematic diagram of a semiconductor device manufacturing method provided in an embodiment of the present invention after a polysilicon layer is formed.

[0026] Wherein, the accompanying drawings are marked as follows: 10, 100 - substrate; 12, 120 - active region; 14, 140 - trench isolation structure; 160 - recess; 21, 210 - first gate; 22, 220 - second gate; 200 - polysilicon layer. DETAILED DESCRIPTION

[0027] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0028] As used in the present invention, the singular forms "a", "an", and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0029] Figure 2 A three-dimensional schematic diagram of a semiconductor device provided in this embodiment, Figure 3 for Figure 2 The three-dimensional schematic diagram along the section line C1C2, Figure 4 for Figure 2 The schematic cross-sectional view along the section line A1A2 is shown in FIG. Figure 5 for Figure 2 The schematic cross-sectional view along the section line B1B2 is shown in FIG. Figure 6 for Figure 2 The cross-sectional diagram along the section line C1C2 is shown in FIG. Figure 2 FIG. 1 shows a partial structure of a semiconductor device, wherein the section line C1C2 is a section along the edge of the first gate 210, so as to show the specific structure of the first gate 210 and the groove 160. Please refer to FIG. Figure 2The present embodiment provides a semiconductor device, which is an OTP device, including a substrate 100, a first gate 210 and a second gate 220, wherein the substrate 100 may be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, or a fully depleted silicon-on-insulator substrate. The substrate 100 includes an active region 120, the active region 120 having a first dimension extending along a first direction D1 and a second dimension extending along a second direction D2, the first direction D1 and the second direction D2 intersect vertically, the first dimension of the active region 120 is related to the dimension of the first gate 210 extending along the first direction D1, specifically, the first dimension of the active region 120 is related to the contact area between the first gate 210 and the active region 120, generally, the larger the contact area between the first gate 210 and the active region 120, the larger the dimension of the first gate 210 extending along the first direction D1, and the larger the first dimension of the active region 120. A trench isolation structure 140 is formed in the substrate 100 . The trench isolation structure 140 extends along a first direction D1 and is arranged along a second direction D2 . The first gate 210 and the second gate 220 are located on the active region 120 between adjacent trench isolation structures 140 .

[0030] Please refer to Figure 3 and Figure 6 , a plurality of grooves 160 are formed in the active area 120, and the plurality of grooves 160 are arranged along the first direction D1, and the plurality of grooves 160 are arranged in a strip shape, and the number of the grooves 160 is at least one. In this embodiment, the depth of the groove 160 is less than the depth of the active area 120, so as to prevent the groove 160 from penetrating the active area 120; the depths of the plurality of grooves 160 are preferably the same, so as to facilitate the preparation and formation of the plurality of grooves 160 in the same preparation process; the size of the groove 160 along the first direction D1 is less than the size of the active area 120 along the first direction D1, so as to realize that part of the first gate 210 is located on the active area 120.

[0031] Please refer to Figure 2 , the first gate 210 and the second gate 220 both extend along the first direction D1, the first gate 210 and the second gate 220 are both strip-shaped, and the second gate 220 is located on the active area 120; please refer to Figure 4 , the first portion of the first gate 210 is located on the active region 120; please refer to Figure 5 and Figure 6 , the second portion of the first gate 210 covers the sidewall and bottom of the groove 160, and the first portion and the second portion are connected to form a complete first gate 210. In this embodiment, the thickness of the first gate 210 is less than the depth of the groove 160 (see Figure 5), so that the first gate 210 does not completely fill the groove 160, but covers the sidewall and bottom of the groove 160; the thickness of the first gate 210 and the second gate 220 are preferably the same, which is conducive to forming the first gate 210 and the second gate 220 in the same preparation process. In this embodiment, the size of the groove 160 along the second direction D2 is less than or equal to the size of the first gate 210 along the second direction D2. Figure 5 The dimension of the groove 160 along the second direction D2 is equal to the dimension of the first gate 210 along the second direction D2, so that in a cross section (see Figure 5 ) In the second direction D2, the first gate 210 covers the bottom of the groove 160 and does not extend to cover a portion of the surface of the active region 120. When the size of the groove 160 along the second direction D2 is smaller than the size of the first gate 210 along the second direction D2, the first gate 210 covers the bottom of the groove 160 and extends to cover a portion of the surface of the active region 120 in a cross section (not shown in the figure) in the second direction D2.

[0032] Furthermore, the semiconductor device also includes a first doping region, a second doping region and a third doping region (not shown in the figure), the first doping region and the second doping region are respectively located in the active region 120 on both sides of the first gate 210, the second doping region is located in the active region 120 between the first gate 210 and the second gate 220, the second doping region and the third doping region are respectively located in the active region 120 on both sides of the second gate 220, the groove 160, the first doping region, the second doping region and the third doping region are all located between adjacent trench isolation structures 140; the first doping region, the second doping region and the third doping region serve as source regions or drain regions, the first doping region, the second doping region and the third doping region have the same doping type, a lightly doped region (not shown in the figure) is also formed in the active region 160, and the first doping region, the second doping region and the third doping region are located in the lightly doped region.

[0033] In this embodiment, the OTP device includes an NMOS tube and a MOS capacitor. In order to ensure the electrical performance of the OTP device, it is necessary to ensure that the gate of the NMOS tube has a large contact area with the active area, and it is not necessary to ensure the contact area between the gate of the MOS capacitor and the active area. The first gate 210 is the gate of the NMOS tube, and the second gate 220 is the gate of the MOS capacitor. Therefore, it is necessary to ensure that the first gate 210 has a large contact area with the active area 120, and it is not necessary to change the morphology of the second gate 220. In this embodiment, by providing a plurality of grooves 160 in the active area 120, the plurality of grooves 160 are arranged along the first direction D1, the first gate 210 extends along the first direction D1, and the arrangement direction of the grooves 160 is the same as the extension direction of the first gate 210, so that part of the first gate 210 (the second part of the first gate 210) covers the sidewall and bottom of the groove 160, so as to increase the contact area between the first gate 210 and the active area 120, thereby reducing the size of the active area 120 along the first direction D1, reducing the area of ​​the semiconductor device, and improving the integration of the semiconductor device in the integrated circuit design. For example, see Figure 1 and Figure 2 , Figure 2 The size of the first gate 210 and the size S2 of the active area 120 along the first direction D1 are smaller than Figure 1 The size of the first gate 21 along the first direction D1 and the size S1 of the active region 120 are equal, thereby reducing the size of the active region 120 along the first direction D1, thereby reducing the area of ​​the semiconductor device.

[0034] This embodiment further provides a method for preparing a semiconductor device, which is used to prepare the above-mentioned semiconductor device, wherein the semiconductor device is an OTP device, comprising: Step S1: providing a substrate, wherein the substrate includes an active region, a plurality of grooves are formed in the active region, and the plurality of grooves are arranged along a first direction; Step S2: forming a first gate and a second gate, both extending along the first direction, wherein the first portion of the first gate is located on the active area, the second portion of the first gate covers the sidewall and bottom of the groove, the first portion and the second portion are connected, and the second gate is located on the active area.

[0035] Figure 7 A three-dimensional schematic diagram of a semiconductor device manufacturing method according to the present embodiment after providing a substrate, Figure 8 A three-dimensional schematic diagram of a semiconductor device after a groove is formed in the method for preparing the semiconductor device provided in this embodiment. Fig. 9 for Figure 8 The cross-sectional diagram along the section line C1C2 is shown in FIG. Fig.10 The following is a three-dimensional schematic diagram of the semiconductor device manufacturing method provided in this embodiment after the polysilicon layer is formed. Figure 7~Figure 10The method for preparing the semiconductor device provided in this embodiment is described in detail.

[0036] Execute step S1: Please refer to Figure 7 , providing a substrate 100, the substrate 100 includes an active area 120, the active area 120 has a first size extending along a first direction D1 and a second size extending along a second direction D2, the first direction D1 and the second direction D2 intersect vertically. A trench isolation structure 140 is formed in the substrate 100, the trench isolation structure 140 extends along the first direction D1 and is arranged along the second direction D2. Please refer to Figure 8 and Fig. 9 , Fig. 9 for Figure 8 The cross-sectional schematic diagram along the section line C1C2, wherein the section line C1C2 is a section along the edge of the groove 160, the substrate 100 is etched to form a plurality of grooves 160 in the active area 120, and the plurality of grooves 160 are arranged in a strip shape along the first direction D1, and the structure and size of the grooves 160 are as described above.

[0037] Execute step S2: Please refer to Fig.10 , forming a polysilicon layer 200 to cover the active area 120 and the sidewalls and bottom of the groove 160; please refer to Figure 2 ,right Fig.10 The polysilicon layer 200 in the embodiment of the present invention is patterned to form a first gate 210 and a second gate 220. The first gate 210 and the second gate 220 both extend along the first direction D1. The first gate 210 and the second gate 220 are both strip-shaped. The second gate 220 is located on the active area 120. The first portion of the first gate 210 is located on the active area 120. The second portion of the first gate 210 covers the sidewall and the bottom of the groove 160. The first portion and the second portion are connected to form a complete first gate 210.

[0038] Furthermore, a lightly doped region is formed in the active region 160, and a first doped region, a second doped region and a third doped region are formed in the lightly doped region, the first doped region and the second doped region are respectively located in the active region 120 on both sides of the first gate 210, the second doped region is located in the active region 120 between the first gate 210 and the second gate 220, the second doped region and the third doped region are respectively located in the active region 120 on both sides of the second gate 220, the groove 160, the first doped region, the second doped region and the third doped region are all located between adjacent trench isolation structures 140; the first doped region, the second doped region and the third doped region serve as source regions or drain regions.

[0039] In summary, in the semiconductor device and preparation method provided by the present invention, the substrate includes an active area, a plurality of grooves are formed in the active area, and the plurality of grooves are arranged along a first direction; the first gate and the second gate both extend along the first direction, the first part of the first gate is located on the active area, the second part of the first gate covers the sidewall and bottom of the groove, the first part and the second part are connected, and the second gate is located on the active area. The present invention sets a plurality of grooves in the active area, the plurality of grooves are arranged along the first direction, the first gate extends along the first direction, the arrangement direction of the grooves is the same as the extension direction of the first gate, so that part of the first gate covers the sidewall and bottom of the groove, so as to increase the contact area between the first gate and the active area, thereby reducing the size of the active area along the first direction, reducing the area of ​​the semiconductor device, and improving the integration of the semiconductor device in the integrated circuit design.

[0040] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A substrate, wherein the substrate comprises an active region, wherein a plurality of grooves are formed in the active region, and the plurality of grooves are arranged along a first direction; The first gate and the second gate both extend along the first direction, the first portion of the first gate is located on the active area, the second portion of the first gate covers the sidewall and bottom of the groove, the first portion and the second portion are connected, and the second gate is located on the active area.

2. The semiconductor device according to claim 1, wherein The depth of the groove is smaller than the depth of the active area.

3. The semiconductor device according to claim 2, wherein: The thickness of the first gate is smaller than the depth of the groove.

4. The semiconductor device according to claim 1, wherein A size of the groove along a second direction is smaller than or equal to a size of the first gate along the second direction, and the first direction and the second direction intersect perpendicularly.

5. The semiconductor device according to claim 4, wherein: A size of the groove along the first direction is smaller than a size of the active area along the first direction.

6. The semiconductor device according to claim 1, wherein: A plurality of the grooves are arranged in a strip shape, and the first grid and the second grid are both in a strip shape.

7. The semiconductor device according to claim 1, wherein: It also includes a first doped region, a second doped region and a third doped region, the first doped region and the second doped region are respectively located in the active regions on both sides of the first gate, the second doped region is located in the active region between the first gate and the second gate, and the second doped region and the third doped region are respectively located in the active regions on both sides of the second gate.

8. The semiconductor device according to claim 7, wherein: It also includes a trench isolation structure, which is located in the substrate and extends along the first direction. The groove, the first doping region, the second doping region and the third doping region are all located between adjacent trench isolation structures.

9. The semiconductor device according to claim 1, wherein: The semiconductor device is an OTP device.

10. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, wherein the substrate includes an active area, a plurality of grooves are formed in the active area, and the plurality of grooves are arranged along a first direction; A first gate and a second gate are formed, both extending along the first direction, a first portion of the first gate is located on the active area, a second portion of the first gate covers the sidewall and bottom of the groove, the first portion and the second portion are connected, and the second gate is located on the active area.

Images