Multi-finger GGNMOS protection device inserted into floating P region and implementation method thereof

Abstract

The invention discloses a multi-finger GGNMOS protection device inserted into a floating P region and an implementation method of the multi-finger GGNMOS protection device. The protection device aims at electrostatic discharge protection of an integrated circuit under the CMOS technology. N + and P + on the surface are highly doped active regions. And the inserted floating space P is a middle doped region. And a P-sub substrate is adopted on the lowermost side. And carrying out P-sub low doping. The protection device is sequentially introduced from the outer side to the middle, firstly, P + active regions on the two sides of the device serve as substrates to be in contact, and the P + active regions are connected to a cathode through metal wires; the N + active regions on the two sides serve as source electrodes of the finger NMOS on the outer side and are connected to the Cathode through metal wires; the floating P region penetrates through the grid electrode, is inserted and has no external potential; the N + active region is symmetrically arranged on the left side and the right side, and the N + active region serves as a drain electrode in the multi-finger GGNMOS structure and is connected to an anode; n +, which passes through the grid electrode and finally is in the middle region, is used as a source electrode of the middle finger, and is connected to the Cathode. And all the grids are connected to the Cathode, so that the design requirement of the GGNMOS is met.

Description

Technical Field

[0001] The invention relates to a multi-finger GGNMOS protection device inserted into a floating P region and a realization method thereof, belonging to the technical field of electricity. Background Art

[0002] With the continuous improvement of semiconductor chip manufacturing process and the reduction of feature size, integrated circuits are increasingly developing towards miniaturization and high density, and are easily affected by electrostatic discharge (ESD). The so-called ESD discharge refers to the breakdown of the medium between two objects with different charges when they are close to or in contact with each other, resulting in transient charge transfer. A minor ESD event in life may not cause any harm to the human body, but for most electronic products, especially integrated circuit (IC) chips, those imperceptible ESD may cause serious damage and even cause permanent failure of the device.

[0003] Gate-grounded NMOS (GGNMOS) is widely used in on-chip ESD protection due to its inherent inactive discharge mechanism and compatibility with complementary metal oxide semiconductor (CMOS) processes. Compared with single-finger structures, multi-finger GGNMOS has better robustness and wider effective width. However, due to the different substrate resistances in the trigger mechanism and traditional structures, multi-finger GGNMOS has the problem of uneven turn-on. Specifically, the substrate resistance of the middle finger of the multi-finger GGNMOS has a larger substrate resistance than that of the other fingers. Therefore, when the parasitic GGNMOS drain and P-body undergo avalanche breakdown to generate ionization current, the middle finger can reach the emitter level of 0.7V through a smaller substrate current, thereby completing the turn-on of the parasitic NPN. As the current increases, the fingers on both sides will gradually meet the conditions to complete the turn-on. The overall structure will present a turn-on mechanism in which the middle finger turns on first and the fingers on both sides turn on later.

[0004] In order to solve the problem of uneven opening of multi-finger GGNMOS structures, the existing mainstream solutions are dynamic substrate technology and substrate triggering technology. That is, the error of the substrate resistance of the middle and two side fingers can be reduced by increasing the substrate resistance. However, this method will reduce the area efficiency of the device on the one hand, and the increase in the actual on-resistance will reduce the robustness of the device on the other hand. Or an additional substrate current is injected into the substrate through an auxiliary trigger method to help the fingers on both sides turn on quickly. This method generally introduces a new structure to complete the first turn-on, inject a large amount of current into the substrate, and speed up the turn-on speed of the overall GGNMOS.

[0005] In summary, the starting point for optimizing the turn-on uniformity of the multi-finger GGNMOS structure is to modulate the parasitic NPN emitter junction of each finger to meet the 0.7V forward bias condition. More specifically, according to Ohm's law, the substrate resistance and substrate injection current are processed to meet the conditions that the turn-on speed of the middle finger is reduced and wait for the turn-on of the two side fingers; or the turn-on speed of the two side fingers is increased to reduce the time difference with the turn-on of the middle finger. Summary of the invention

[0006] The purpose of the invention is to address the defects and shortcomings of the above-mentioned prior art and propose a multi-finger GGNMOS protection device inserted into a floating P region and its implementation method, which can improve the turn-on uniformity of the multi-finger structure GGNMOS ESD protection device and improve the ability to discharge current. The present invention optimizes the generation of multiple hysteresis in the multi-finger device by adding an additional P well, and has a significant optimization of the uniform turn-on of the device in the simulation results, while effectively reducing the ESD window.

[0007] The technical solution adopted by the present invention to solve its technical problems is: a multi-finger GGNMOS protection device inserted into a floating P region and its implementation method. The protection device is for electrostatic discharge protection of integrated circuits under CMOS process. The N+ and P+ on the surface of the protection device are highly doped active regions. The inserted floating P is a medium doping region. The bottom uses a P-sub substrate. The P-sub is low doped. (N-type refers to phosphorus doping and P-type refers to boron doping). The connection of electrodes in the device structure is as follows, introduced from the outside to the middle, first the P+ active regions on both sides of the device, which are used as substrate contacts and connected to the cathode through metal wires; then the N+ active regions on both sides, which are used as the source of the outer finger NMOS and are connected to the cathode through metal wires; through the gate, there is an inserted floating P region without external potential; followed by the symmetrical N+ active regions on the left and right sides, which are used as the drain in the multi-finger GGNMOS structure and are connected to the anode; through the gate, finally the N+ in the middle region, which is used as the source of the middle finger and is connected to the cathode. All gates are connected to the Cathode to meet the design requirements of GGNMOS.

[0008] The present invention verifies the multi-finger GGNMOS with a four-finger structure, so the subsequent results will be presented with a four-finger structure.

[0009] The present invention also provides a method for implementing a multi-finger GGNMOS protection device inserted into a floating P region, which can be placed at the chip IO port and automatically perform ESD (electrostatic discharge) protection as a protection device. The protection device has two working modes, one of which is that the Anode anode is under normal working voltage and the protection device is in a closed state to reduce unnecessary power consumption. Under normal pressure, the N+ connected to the Anode will not avalanche breakdown with the P-sub, and the ESD current discharge path is in a closed state. At the same time, the parasitic NPN is in reverse bias, and the anode voltage is not enough to open the discharge channel of the entire device.

[0010] Another is that electrostatic discharge occurs at the anode end, and a large current flows through the anode and flows to the cathode. The protection device is turned on. The entire conduction process is divided into the following steps:

[0011] Step 1: When an ESD event occurs at Anode, the voltage at Anode rises rapidly. The voltage increase increases the local electric field of the N+ active region and the floating P+ reverse-biased junction. The high electric field increases the carrier collision ionization rate in this area until avalanche breakdown occurs, generating a large number of hole-electron pairs in PW.

[0012] Step 2: The generation of a large number of hole-electron pairs causes the GGNMOS to produce a negative resistance effect due to conductivity modulation, and the TLP curve shows hysteresis. As the hole current flows to the cathode, a potential difference is generated between the GGNMOS source and the substrate contact. As the current continues to increase, when the potential difference reaches 0.7V, the TLP curve reaches the holding voltage (Vt2) point. Since the substrate resistance of the middle finger GGNOMS is larger, the parasitic GGNMOS of the middle finger will be turned on first. The first hysteresis is completed.

[0013] Step 3: Since the inserted floating P+ region increases the substrate resistance of the fingers on both sides, the substrate resistance error with the middle finger is reduced; at the same time, the higher concentration on the side close to the floating P+ region brings a higher ionization current, and the parasitic NPN of the fingers on both sides can reach the maintenance voltage point as quickly as possible to complete the second hysteresis.

[0014] Step 4: Avalanche ionization occurs on the surfaces of both sides of the Anode, but because the concentration is higher on the side close to the floating P+ region, more hole-electron pairs are generated than on the other side. In terms of substrate current size, the substrate current on the side with higher concentration will be larger. As the ESD signal continues to increase, the current density of the middle finger with smaller resistance will continue to increase, becoming the main channel for current discharge. At this time, the middle and edge fingers are fully opened to discharge the ESD signal until the device fails due to local thermal breakdown.

[0015] Beneficial effects:

[0016] 1. The present invention inserts a floating P+ region, which can reduce the error in the substrate resistance of the middle finger and the fingers on both sides. At the same time, in the actual opening process, because the floating P+ has a higher concentration than the substrate, a substrate current much larger than the anode N+ and the substrate generated by avalanche ionization is injected, which assists the parasitic NPN on both sides to turn on faster, effectively improving the opening uniformity of the multi-finger GGNMOS.

[0017] 2. The present invention can improve the ability of discharging current, and optimize the generation of multiple hysteresis in multi-finger devices by adding additional P wells. In the simulation results, the uniform opening of the device is significantly optimized, and the ESD window can be effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is the structure diagram of the traditional multi-finger GGNMOS.

[0019] Figure 2 This is a cross-sectional schematic diagram of a multi-finger GGNMOS with a floating P+ inserted in the present invention.

[0020] Figure 3 It is the TLP IV characteristic curve diagram of the present invention.

[0021] Figure 4 This is the impact ionization density distribution diagram of the present invention.

[0022] Figure 5a This is the first hysteresis hole distribution diagram of the present invention, Figure 5b Corresponding discharge path diagram.

[0023] Figure 6 This is the second hysteresis carrier distribution diagram of the present invention.

[0024] Figure 7 This is a diagram of carrier distribution when the present invention is just started.

[0025] Figure 8 This is a carrier distribution diagram when the present invention is fully turned on.

[0026] Fig. 9 FIG. 4 is a TLP IV characteristic curve diagram of the present invention at different drain floating P+ distances (Ldp).

[0027] Fig.10 FIG. 1 is a TLP IV characteristic curve diagram of the present invention at different gate floating P+ distances (Lgp). DETAILED DESCRIPTION

[0028] The present invention will be further described in detail below in conjunction with the accompanying drawings.

[0029] Traditional multi-finger GGNMOS such as Figure 1As shown. Since the distance from the base region of each parasitic side NPN to the substrate protection ring is different, the base resistance of the parasitic side NPN in the center area of ​​the multi-finger GGNMOS is higher than that in the side area. Therefore, in the multi-finger GGNMOS structure, under ESD stress, the trigger speed of the center NMOS finger is always faster than other fingers. As long as the center NMOS finger is triggered, the ESD overstress voltage will be clamped to the hysteresis holding voltage of the NMOS. As the substrate current rises, the NMOS fingers on both sides will turn on and complete the second hysteresis. In actual results, due to the existence of errors, the multi-finger GGNMOS may produce multiple hysteresis. If the other non-conducting NMOS fingers in the two side areas cannot be triggered before the first NMOS finger that is turned on is burned, the robustness of the ESD protection device will not be guaranteed.

[0030] The present invention proposes a multi-finger GGNMOS device inserted into a floating P region, the cross-sectional view of which is shown in FIG. Figure 2 Compared with the traditional GGNMOS, this structure inserts a floating P+ region into the drain of the edge NMOS finger, which has no effect on the original size, but changes the position where avalanche ionization occurs first, and increases the error of substrate resistance between different fingers, so that the multi-finger GGNMOS obtains good turn-on uniformity.

[0031] Under normal operation, since the operating voltage of the protected circuit is outside the ESD protection window, the proposed structure will not be triggered and turned on.

[0032] When the ESD signal is applied to the Anode end, the N+ potential connected to the Anode rises rapidly. As the local electric field of the N+ active region and the float-P reverse-biased junction continues to increase, the reverse-biased junction undergoes avalanche ionization, generating a large number of hole-electron pairs. The generation of a large number of hole-electron pairs causes the GGNMOS to produce a negative resistance effect due to conductivity modulation. As the hole current flows to the Cathode, a potential difference is generated between the GGNMOS source and the substrate contact. The current continues to increase. Since the substrate resistance of the middle finger GGNOMS is larger, when the potential difference reaches 0.7V, the parasitic GGNMOS of the middle finger will be turned on first. The first hysteresis is completed.

[0033] The inserted floating P+ region increases the substrate resistance of the fingers on both sides and reduces the substrate resistance error with the middle finger; at the same time, the higher concentration near the floating P+ region brings a higher ionization current, and the parasitic NPN of the fingers on both sides can reach the maintenance voltage point as quickly as possible. As the discharge current increases, the GGNMOS of the fingers on both sides meet the turn-on conditions and complete the second hysteresis. At this time, the device is fully turned on and starts to discharge the ESD signal.

[0034] On the other hand, due to the higher concentration on the float-P+ side, there will be more hole-electron pairs generated by avalanche ionization, so the substrate current will be more distributed on the edge fingers than on the center fingers, and the current density will be greater. However, as the ESD signal increases, the center finger with a smaller on-resistance will become the main path for current discharge.

[0035] The insertion of floating P+ can change the local concentration of P-sub, causing the avalanche breakdown point to change, effectively reducing the trigger voltage. At the same time, since the floating P+ region widens the distance from the drain to the substrate, the substrate resistance is increased, the parasitic NPN gain is reduced, resulting in a significant increase in the holding voltage.

[0036] The present invention uses TCAD simulation to analyze the design. In the simulation process, physical models such as Mobility, Thermodynamic, SRH, and Hydromodynamic are used. Some parameters of the device are shown in Table 1.

[0037]

[0038]

[0039] The simulation experiment curves and partial structure distribution of the present invention include the following:

[0040] For ESD protection devices in a multi-finger environment, the most important thing to pay attention to is the device's turn-on uniformity and failure current (It2). The ESD protection window of the present invention is designed to be 5-10V. In order to simulate the electrostatic stress generated by the human body model (HBM), a pulse current source with a 10ns rising edge and a 100ns width is selected as the simulation excitation and applied to the Anode end, while keeping the Cathode end grounded. The final single pulse TLP simulation curve is as follows: Figure 3 As shown. It can be seen that the new structure reduces the time interval for opening different fingers by inserting a floating P+ auxiliary edge finger to trigger the discharge. At the same time, due to the change in the location of avalanche breakdown, the trigger voltage is reduced to 8.2V. Although the actual curve still has multiple unobvious hysteresis due to parameter modulation, it can basically ensure that the opening speed of GGNMOS of different fingers is as close as possible. The finger that is turned on later no longer needs to wait for the potential rise brought by the ionization current to meet the opening condition of 0.7V, but can be turned on with the assistance of the larger substrate current from float-P+ / N+.

[0041] In order to verify the conduction principle of the proposed device, TCAD software was used to analyze the changes before and after the device was turned on. Figure 4This is a schematic diagram of the impact ionization distribution before the device is turned on. Since the concentration on the float-P+ side is higher, the impact ionization rate will be higher than that on the P-sub side. When the electric field peak reaches the silicon avalanche critical value, avalanche breakdown will occur here first.

[0042] Figure 5a This is the hole current distribution diagram of the device when the first snapback occurs. It is not difficult to see that as the avalanche ionization intensifies, a large amount of hole current will flow to the cathode connected to the substrate, and the substrate current will lead to the increase of the substrate potential, which first satisfies the opening of the middle finger GGNMOS. Figure 5b The discharge path formed by the center finger can be seen.

[0043] Figure 6 This is the current distribution diagram during the second hysteresis. The avalanche current generated at float-P+ / N+ is consistent with the discharge current direction of the edge finger GGNMOS. In addition, float-P+ extends the parasitic NPN base resistance of the edge finger. The edge finger does not need to wait for the occurrence of edge finger avalanche breakdown like the traditional structure, and the substrate potential is raised through the hole current. This undoubtedly greatly strengthens the turn-on correlation between the fingers and optimizes the uniformity of the multi-finger structure.

[0044] Figure 7 This is the current distribution diagram when the device is just turned on. However, due to the higher concentration on the side close to the floating P+ region, more hole-electron pairs are generated than on the other side. In terms of the substrate current size, the substrate current on the side with higher concentration will be larger. From the current distribution diagram, we can also see that the outer fingers will bear a larger current.

[0045] Figure 8 This is the current distribution diagram after it is fully turned on. After it is fully turned on, as the ESD stress increases, the current that needs to be discharged will also increase. The current will choose the channel with smaller resistance to flow. The substrate resistance of the center finger is smaller than that of the outer fingers, so the current density it bears will be greater. The corresponding current distribution can also be seen from the figure.

[0046] Fig. 9It can be seen that as the distance between the drain and floating P+ changes, the design window of the device's ESD changes. First, as the distance increases, the substrate resistance of the fingers on both sides increases. Under the same substrate current conditions, the fingers on both sides are more likely to meet the 0.7V turn-on condition, so the TLP curve shows better uniformity, and there is almost no trend of multiple hysteresis. Secondly, due to the increase in the base resistance of the fingers on both sides, the holding voltage of the curve increases, and the design window will become smaller. However, also because of the increase in base resistance, the TLP curve will bend earlier, which means that the overall on-resistance of the device becomes larger. In addition to the decrease in current gain, the on-resistance increase caused by the thermal electron effect will also arrive faster. A compromise is taken in the design, and Ldp is selected as 0.15um. At this time, the device can obtain good turn-on uniformity, and the area efficiency is a better choice compared to a larger distance.

[0047] By changing the floating P+ gate distance, the TLP IV characteristic curves under different conditions are obtained, such as Fig.10 As shown in Figure 2. As the spacing between the floating P+ diffusion and the gate edge gets longer, the holding voltage increases slightly, simply because the edge-finger conduction path grows and the overall on-resistance increases. For the TLP curve, the overall trend remains the same.

[0048] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A multi-finger GGNMOS protection device inserted into a floating P region, characterized in that: The N+ and P+ on the surface of the protection device are highly doped active areas, the inserted floating P is a medium doped area, the bottom uses a P-sub substrate, the P-sub is low doped, the N type refers to doping with phosphorus elements and the P type refers to doping with boron elements; The connection of electrodes in the protection device structure is as follows: from the outside to the middle, first are the P+ active regions on both sides of the device, which serve as substrate contacts and are connected to the Cathode (cathode) through metal wires; then the N+ active regions on both sides, which serve as the source of the outer finger NMOS and are connected to the Cathode through metal wires; through the gate, there is an inserted floating P region with no external potential; then there are the symmetrical N+ active regions on the left and right sides, which serve as the drain in the multi-finger GGNMOS structure and are connected to the Anode (anode); through the gate, finally the N+ in the middle region, which serves as the source of the middle finger and is connected to the Cathode, and all gates will be connected to the Cathode to meet the design requirements of GGNMOS.

2. A multi-finger GGNMOS protection device inserted into a floating P region according to claim 1, characterized in that: The protection device is a four-finger structure.

3. A method for implementing a multi-finger GGNMOS protection device inserted into a floating P region, characterized in that: The protection device is placed at the chip IO port and automatically performs ESD (electrostatic discharge) protection as a protection device. The protection device has two working modes. One is that the Anode is under normal working voltage and the protection device is in a closed state to reduce unnecessary power consumption. Under normal pressure, the N+ connected to the Anode will not avalanche breakdown with the P-sub, and the ESD current discharge path is in a closed state. At the same time, the parasitic NPN is in reverse bias. At this time, the anode voltage is not enough to open the discharge channel of the entire device. The other is that electrostatic discharge occurs at the anode end, and a large current passes through the anode and flows to the cathode. The protection device is turned on. The entire conduction process includes the following steps: Step 1: When an ESD event occurs at Anode, the voltage at Anode rises rapidly. The voltage rise increases the local electric field of the N+ active region and the floating P+ reverse-biased junction. The high electric field increases the carrier collision ionization rate in this region until avalanche breakdown occurs, generating a large number of hole-electron pairs in PW. Step 2: The generation of a large number of hole-electron pairs causes the GGNMOS to produce a negative resistance effect due to conductivity modulation, and the TLP curve shows hysteresis. As the hole current flows to the cathode, a potential difference is generated between the GGNMOS source and the substrate contact, and the current continues to increase. When the potential difference reaches 0.7V, the TLP curve reaches the holding voltage (Vt2) point. Since the substrate resistance of the middle finger GGNOMS is larger, the parasitic GGNMOS of the middle finger will be turned on first, completing the first hysteresis; Step 3: Since the inserted floating P+ region increases the substrate resistance of the fingers on both sides, the substrate resistance error with the middle finger is reduced; at the same time, the higher concentration near the floating P+ region brings a higher ionization current, and the parasitic NPN of the fingers on both sides can reach the maintenance voltage point as quickly as possible, completing the second hysteresis; Step 4: Avalanche ionization occurs on the surfaces of both sides of the Anode. However, due to the higher concentration on the side close to the floating P+ region, more hole-electron pairs are generated than on the other side. In terms of substrate current size, the substrate current on the side with higher concentration will be larger. As the ESD signal continues to increase, the current density of the middle finger with smaller resistance will continue to increase and become the main channel for current discharge. At this time, the middle and edge fingers are fully opened to discharge the ESD signal until the device fails due to local thermal breakdown.

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