Image sensor and forming method thereof

Abstract

Various embodiments of the present disclosure relate to stacked complementary metal oxide semiconductor (CMOS) image sensors. A first integrated circuit (IC) chip and a second IC chip are vertically stacked. A pixel sensor spans the first and second IC chips. The pixel sensor comprises a first transmission transistor and a photoelectric detector which are located on a first IC chip, and further comprises a source follower transistor, a transistor capacitor and a second transmission transistor which are located on a second IC chip. The transistor capacitor and the second pass transistor are electrically coupled in series from the source / drain region of the first pass transistor to the gate electrode of the source follower transistor.

Description

Technical Field

[0001] Embodiments of the present application relate to image sensors and methods of forming the same. Background Art

[0002] Integrated circuits (ICs) with image sensors are used in a variety of modern electronic devices, such as cameras, mobile phones, etc. Types of image sensors include, for example, complementary metal oxide semiconductor (CMOS) image sensors and charge coupled device (CCD) image sensors. Compared with CCD image sensors, CMOS image sensors are becoming more and more popular due to their advantages such as low power consumption, small size, fast data processing speed, direct data output, and low manufacturing cost. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, an image sensor is provided, comprising: a first integrated circuit chip; a second integrated circuit chip stacked with the first integrated circuit chip; and a pixel sensor spanning the first integrated circuit chip and the second integrated circuit chip, wherein the pixel sensor comprises a first transfer transistor and a photodetector located at the first integrated circuit chip, and further comprises a source follower transistor, a transistor capacitor, and a second transfer transistor located at the second integrated circuit chip; wherein the transistor capacitor and the second transfer transistor are electrically coupled in series from the source / drain region of the first transfer transistor to the gate electrode of the source follower transistor.

[0004] According to another aspect of an embodiment of the present application, an image sensor is provided, comprising: a first substrate; a first pixel portion, located on the first substrate and comprising a photodetector; a second substrate, located below the first substrate; and a second pixel portion, located on the second substrate and comprising a source follower transistor and a transistor capacitor, wherein the transistor capacitor electrically isolates a gate electrode of the source follower transistor from the first pixel portion, and wherein the transistor capacitor has a gate dielectric layer having a step profile; wherein the first pixel portion and the second pixel portion form a common pixel sensor.

[0005] According to another aspect of an embodiment of the present application, a method for forming an image sensor is provided, the method comprising: forming a first integrated circuit chip including a first pixel portion, wherein the first pixel portion includes a photodetector and a first transfer transistor electrically coupled from the photodetector to a first node; forming a second integrated circuit chip including a second pixel portion, wherein the second pixel portion includes a source follower transistor, a transistor capacitor and a second transfer transistor, and wherein a gate electrode of the source follower transistor is electrically coupled to the second node; and bonding the first integrated circuit chip and the second integrated circuit chip together to electrically couple the first pixel portion and the second pixel portion into a pixel sensor; wherein, after bonding, the second transfer transistor and the transistor capacitor are electrically coupled in series from the first node to the second node. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A circuit diagram of some embodiments of a stacked complementary metal oxide semiconductor (CMOS) image sensor including pixel sensors for high conversion gain (HCG) arranged across a first integrated circuit (IC) chip and a second IC chip is shown.

[0008] Figure 2 Shows Figure 1 Signal timing diagrams of some embodiments of a pixel sensor.

[0009] Figure 3A-3C Shows Figure 1 Potential diagrams of some embodiments of pixel sensors at different times.

[0010] Figure 4A and Figure 4B Shows Figure 1 Circuit diagrams of some alternative embodiments of stacked CMOS image sensors in which the pixel sensors are different.

[0011] Figure 5 Shows Figure 1 Circuit diagram of some embodiments of a stacked CMOS image sensor, wherein the stacked CMOS sensor further includes a third IC chip having an application specific integrated circuit (ASIC).

[0012] Figure 6 Shows Figure 5 Schematic cross-sectional views of some embodiments of stacked CMOS image sensors.

[0013] Figure 7 Shows Figure 5 Schematic cross-sectional views of some alternative embodiments of stacked CMOS image sensors, wherein the stacked CMOS image sensor includes a plurality of pixel sensors.

[0014] Figure 8 Shows Figure 7 A top view layout diagram of some embodiments of a stacked CMOS image sensor.

[0015] Fig. 9 Shows Figure 1 A top view layout diagram of some first embodiments of a stacked CMOS image sensor at a second IC chip.

[0016] Figure 10A-10C Shows Fig. 9 Cross-sectional views of some first embodiments of stacked CMOS image sensors.

[0017] Figures 11A-11C Shows Fig. 9 Cross-sectional views of some second embodiments of stacked CMOS image sensors.

[0018] Fig.12 Shows Fig. 9 Cross-sectional views of some embodiments of a stacked CMOS image sensor at a first IC chip and a second IC chip.

[0019] Fig.13 Shows Figure 1 A top view layout diagram of some second embodiments of a stacked CMOS image sensor at a second IC chip.

[0020] Figure 14A-Figure 14C Shows Fig.13 Cross-sectional views of some first embodiments of stacked CMOS image sensors.

[0021] Figure 15A-Figure 15C Shows Fig.13 Cross-sectional views of some second embodiments of stacked CMOS image sensors.

[0022] Fig.16 Shows Fig.13 Cross-sectional views of some embodiments of a stacked CMOS image sensor at a first IC chip and a second IC chip.

[0023] Fig.17 A cross-sectional view of some embodiments of a stacked CMOS image sensor is shown, the sensor including a plurality of pixel sensors, each pixel sensor such as Fig.12 As shown, a third IC chip including ASIC is also included.

[0024] Fig.18 Shows Fig.17 Cross-sectional views of some alternative embodiments of stacked CMOS image sensors.

[0025] FIG. 19A to FIG. 35B A series of views illustrating some embodiments of a method for forming a stacked CMOS image sensor including pixel sensors for HCG.

[0026] Fig.36 Shows FIG. 19A to FIG. 35B A block diagram of some embodiments of the method.

[0027] Figures 37 to 42B Shows FIG. 19A to FIG. 35B A series of views of some first alternative embodiments of the method.

[0028] FIG. 43A to FIG. 46B Shows FIG. 19A to FIG. 35B A series of views of some second alternative embodiments of the method. DETAILED DESCRIPTION

[0029] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0030] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0031] A stacked complementary metal oxide semiconductor (CMOS) image sensor may include a first integrated circuit (IC) chip, a second IC chip, and a pixel sensor. The pixel sensor is repeated to form a pixel array and includes a pinned photodiode (PPD) and a plurality of readout devices. The readout device includes a transfer transistor and a source follower transistor. The PPD is configured to accumulate photogenerated charge, and the transfer transistor is configured to selectively transfer the photogenerated charge to a floating diffusion node. The source follower transistor has a gate electrode electrically coupled to the floating diffusion node and is configured to convert the charge at the gate electrode into an output voltage.

[0032] The first and second IC chips are stacked vertically and house the pixel sensor. The PPD, transfer transistor, and floating diffusion node are located in the first IC chip, and the remaining readout devices are located in the second IC chip. In contrast to arranging all the readout devices in the first IC chip, arranging some of the readout devices in the second IC chip frees up space in the first IC chip. This allows the size of the pixel sensor to be reduced without reducing the size of the PPD and without affecting the full well capacity (FWC). Therefore, arranging some of the readout devices in the second IC chip allows the pixel density of the stacked CMOS image sensor to be increased without compromising the FWC.

[0033] Although arranging some readout devices in the second IC chip can increase pixel density without compromising FWC, it also results in a long conduction path from the floating diffusion node to the gate electrode of the source follower transistor. Due to its length, the long conduction path has a large amount of parasitic capacitance, which increases the capacitance at the gate electrode. In addition, the long conduction path electrically couples the parasitic capacitance at the floating diffusion node to the gate electrode. Because the conversion gain is inversely proportional to the capacitance at the gate electrode, the increase in capacitance at the gate electrode reduces the conversion gain of the source follower transistor. The reduction in conversion gain, in turn, reduces low-light performance.

[0034] Various embodiments of the present disclosure relate to a stacked CMOS image sensor, including a pixel sensor for high conversion gain (HCG) and a method of forming a stacked CMOS image sensor. The pixel sensor includes a PPD and a plurality of readout devices. In addition, the readout device includes a PPD transfer transistor, a transistor capacitor, a capacitor transfer transistor, and a source follower transistor.

[0035] The PPD and the PPD transfer transistor are located on the first IC chip, and the PPD transfer transistor is configured to selectively transfer photogenerated charge from the PPD to the first floating diffusion node. The remaining readout devices are located at the second IC chip, and the gate electrode of the source follower transistor is electrically coupled to the second floating diffusion node. In addition, the capacitor transfer transistor and the transistor capacitor are electrically coupled in series from the second floating diffusion node to the first floating diffusion node, so that the transistor capacitor separates the capacitor transfer transistor from the first floating diffusion node. The transistor capacitor is configured to selectively store charge from the first floating diffusion node, and the capacitor transfer transistor is configured to selectively transfer charge from the transistor capacitor to the second floating diffusion node.

[0036] By electrically separating the second floating diffusion node from the first floating diffusion node, the transistor capacitor and the capacitor transfer transistor isolate the second floating diffusion node from the parasitic capacitance at the first floating diffusion node and along the long conductive path extending from the first floating diffusion node to the transistor capacitor. As a result, the parasitic capacitance at the second floating diffusion node and at the gate electrode of the source follower transistor is reduced. This in turn results in HCG at the source follower transistor and improves low light performance. In addition, as opposed to arranging all readout devices in the first IC chip, arranging some readout devices in the second IC chip allows the size of the pixel sensor to be reduced without reducing the size of the PPD. This in turn allows the pixel density to be increased without compromising the FWC.

[0037] refer to Figure 1 , a circuit diagram 100 of some embodiments of a stacked CMOS image sensor including a pixel sensor 102 for HCG is provided. The pixel sensor 102 spans a first IC chip 104a and a second IC chip 104b of the stack. The first and second IC chips 104a, 104b are shown as being stacked laterally, but may alternatively be stacked vertically. The pixel sensor 102 may, for example, be an active pixel sensor (APS) having a lateral overflow integrating capacitor (LOFIC) architecture or some other suitable architecture. In addition, the pixel sensor 102 may also be referred to as a pixel, etc.

[0038] The pixel sensor 102 includes a PPD 106 and a plurality of readout devices 108 configured to facilitate readout of the PPD 106. In alternative embodiments, the PPD 106 may be other suitable types of photodetectors. The readout devices 108 include, among others, a PPD transfer transistor 110, a transistor capacitor 112, a capacitor transfer transistor 114, a source follower transistor 116, and a row select transistor 118. The PPD 106 and the PPD transfer transistor 110 are located at a first IC chip 104a, and the remaining readout devices 108 are located at a second IC chip 104b. Placing some of the readout devices 108 at the second IC chip 104b, rather than arranging all of the readout devices 108 at the first IC chip 104a, allows the size of the pixel sensor 102 to be reduced without reducing the size of the PPD 106. This in turn allows the pixel density to be increased without compromising the FWC.

[0039] The PPD transfer transistor 110 is configured to selectively transfer photogenerated charge from the PPD 106 to the first floating diffusion node FD1. The source follower transistor 116 is gated by the charge at the second floating diffusion node FD2. The transistor capacitor 112 and the capacitor transfer transistor 114 are electrically coupled in series from the second floating diffusion node FD2 to the first floating diffusion node FD1, such that the transistor capacitor 112 isolates the capacitor transfer transistor 114 from the first floating diffusion node FD1. The transistor capacitor 112 is configured to selectively store charge from the first floating diffusion node FD1, and the capacitor transfer transistor 114 is configured to selectively transfer charge from the transistor capacitor 122 to the second floating diffusion node FD2.

[0040] By electrically separating the second floating diffusion node FD2 from the first floating diffusion node FD1, the transistor capacitor 112 and the capacitor transfer transistor 114 isolate the parasitic capacitance in the second floating diffusion node FD2 from the parasitic capacitance at the first floating diffusion node FD1 and the parasitic capacitance at the long conductive path 120 extending from the first floating diffusion node FD1 to the transistor capacitor 112. As a result, the parasitic capacitance at the second floating diffusion node FD2 and the gate electrode of the source follower transistor 116 is reduced. The reduced parasitic capacitance increases the conversion gain of the source follower transistor 116, which in turn increases the low light performance of the pixel sensor 102.

[0041] As described above, the source follower transistor 116 is gated by the charge at the second floating diffusion node FD2 and is powered from the power supply V ddThe source follower transistor 116 is electrically coupled to the row select transistor 118. In addition, the source follower transistor 116 is configured to convert the charge into an output signal having a voltage that follows or is proportional to the charge. The row select transistor 118 is selected by the row select signal RS and is configured to selectively pass the output signal to the output OUT of the pixel sensor 102.

[0042] The conversion gain of the source follower transistor 116 is inversely proportional to the capacitance at the gate electrode of the source follower transistor 116. Where V is the voltage of the output signal, Q is the charge, V / Q is the conversion gain, and C is the capacitance. Therefore, by reducing the parasitic capacitance at the gate electrode, the transistor capacitor 112 and the capacitor transfer transistor 114 increase the conversion gain of the source follower transistor 116, so that the source follower transistor 116 can have HCG. This in turn can improve the low light performance of the pixel sensor 102.

[0043] The transistor capacitor 112 is gated by the capacitor signal CAP and the capacitor transfer transistor 114 is gated by the capacitor transfer signal CAP TX. In addition, the transistor capacitor 112 has a gate dielectric layer with a stepped thickness, and as schematically shown, the gate electrode of the transistor capacitor 122 has a stepped profile.

[0044] The stepped thickness of the transistor capacitor 112 gradually decreases from a first side electrically coupled to the first floating diffusion node FD1 to a second side opposite to the first side electrically coupled to the capacitor transfer transistor 114. As described below, the stepped thickness results in a stepped potential that creates a potential barrier to prevent the charge at the transistor capacitor 112 from returning to the first floating diffusion node FD1.

[0045] The PPD 106 and the PPD transfer transistor 110 are electrically coupled in series from the first floating diffusion node FD1 to the ground GND. The cathode of the PPD 106 is electrically coupled to the PPD transfer transistor 110, and the anode of the PPD 106 is electrically coupled to the ground GND. The PPD 106 is configured to accumulate charges (e.g., electrons) generated in response to incident light. The PPD transfer transistor 110 is electrically coupled to the first floating diffusion node FD1 and is gated by the PPD transfer signal PPD TX. In addition, as described above, the PPD transfer transistor 110 is configured to selectively transfer the photogenerated charges from the PPD 106 to the first floating diffusion node FD1.

[0046] The readout device 108 also includes a LOFIC transistor 122, a LOFIC 124, and a reset transistor 126 electrically coupled to a common node. The LOFIC transistor 122 is selected by a LOFIC signal LFG and is electrically coupled from the common node to the second floating diffusion node FD2. The LOFIC 124 is electrically coupled from the common node to the ground GND. The reset transistor 126 is selected by a reset signal RST and is electrically coupled from the common node to the power supply V dd .

[0047] Prior to charge accumulation in PPD 106, reset transistor 126 and LOFIC transistor 122 cooperate with PPD pass transistor 110, transistor capacitor 112, and capacitor pass transistor 114 to electrically couple PPD 106 to power supply V dd , to reset PPD 106 to the pinning voltage. During use of pixel sensor 102 in a high light environment, LOFIC transistor 122 cooperates with PPD transfer transistor 110, transistor capacitor 112, and capacitor transfer transistor 114 and is configured to electrically couple PPD 106 to LOFIC 124 to transfer excess charge from PPD 106 to LOFIC 124. This excess charge corresponds to charge that exceeds the saturation level of PPD 106, so that transferring the excess charge can prevent high light blooming.

[0048] In some embodiments, the transistor of the readout device 108 is a metal oxide semiconductor field effect transistor (MOSFET), a fin field effect transistor, a full-all-around gate field effect transistor, a nanosheet field effect transistor, or any combination of the above transistors. In some embodiments, the transistor capacitor 112 has a structure of a MOSFET, etc. and / or is a MOSFET, etc. In addition, in some embodiments, the transistor capacitor 112 has a structure of a capacitor in a charge coupled device (CCD) pixel sensor and / or is a metal oxide semiconductor (MOS) capacitor, etc. In some embodiments, the transistor capacitor 112 has a capacitance of about 0.1 picofarads (pF) to 10 femtofarads (fF) or some other suitable capacitance.

[0049] In some embodiments, the readout device 108 at the second IC chip 104b may be considered as an intra-pixel circuit, etc. In some embodiments, the transistor capacitor 112 may be considered as a MOS capacitor, etc. In some embodiments, the capacitor transfer transistor 114 may be considered as a HCG transistor, etc.

[0050] refer to Figure 2 , provides Figure 1 The signal timing diagram 200 of some embodiments of the pixel sensor 102 is shown. The horizontal axis corresponds to time, which is divided into 12 time periods, respectively marked as T0, T1, etc. to T11 The time periods T1-T9 correspond to the readout cycles. The time period T0 corresponds to the previous readout cycle (partially shown). 10 and T 11 Corresponding to a subsequent readout cycle (partially shown).

[0051] The vertical axis corresponds to Figure 1 The signals at the respective gate electrodes of the readout devices 108 in the circuit are shown in FIG. These signals include a reset signal RST, a PPD transfer signal PPD TX, a LOFIC signal LFG, a row selection signal RS, a capacitor transfer signal CAP TX, and a capacitor signal CAP. In addition, each signal has a high state corresponding to the ON (e.g., conductive) state of the corresponding readout device, and also has a low state corresponding to the OFF (e.g., non-conductive) state of the corresponding readout device.

[0052] During time period T1, pixel sensor 102 is reset. This includes, among other things, setting PPD 106 to its pinning voltage. Reset signal RST, PPD transfer signal PPD TX, and capacitor signal CAP are pulsed to a high state. In addition, LOFIC signal LFG and capacitor transfer signal CAP TX are continuously in a high state. As a result, PPD transfer transistor 110, transistor capacitor 112, capacitor transfer transistor 114, LOFIC transistor 122, and reset transistor 126 are in an on state and together form a circuit that electrically couples PPD 106 to power supply V dd conductive path.

[0053] During the time period T2-T4, the PPD 106 accumulates charge in response to incident light. The PPD transmission signal PPD TX is in a low state during the entire time period T2-T4, and thus the PPD transmission transistor 110 is in an off state during the entire time period T2-T4. This provides a barrier to prevent charge from being removed from the PPD 106.

[0054] During the entire time period T2-T4, while the capacitor signal CAP and the PPD transmission signal PPD TX are in a low state, the capacitor signal CAP and PPD TX may be optionally pulsed to a high state. In this alternative embodiment, the transistor capacitor 112, the PPD transmission transistor 110, the capacitor transmission transistor 114, and the LOFIC transistor 122 will be in an ON state. This will cause a conductive path to transfer excess charge from the PPD 106 to the LOFIC 124 to prevent saturation and blooming of the PPD 106 during use of the pixel sensor 102 in a high light environment.

[0055] In the period T5, the accumulation of charge has ended, and there is a delay before the charge is transferred. Except for the row selection signal RS, the signals are in a low state.

[0056] During time period T6, the charge accumulated at PPD 106 is transferred from PPD 106 to transistor capacitor 112. PPD transfer signal PPD TX and capacitor signal CAP are pulsed to a high state, while capacitor transfer signal CAP TX remains in a low state. Therefore, PPD transfer transistor 110 and transistor capacitor 112 are in an ON state, while capacitor transfer transistor 114 is in an OFF state.

[0057] As follows Figure 3B As shown, the ON state of PPD transfer transistor 110 and the ON state of transistor capacitor 112 create a potential difference from PPD 106 to transistor capacitor 112, which causes charge to move from PPD 106 to transistor capacitor 112. In addition, the OFF state of capacitor transfer transistor 114 creates a barrier that prevents charge from moving to the second floating diffusion node FD2.

[0058] In time period T7, the charge at transistor capacitor 112 is transferred to second floating diffusion node FD2. Capacitor transfer signal CAP TX is pulsed to a high state, while transistor capacitor 112 is in a low state. Therefore, capacitor transfer transistor 114 is in an ON state, while transistor capacitor 112 is in an OFF state.

[0059] As follows Figure 3C As shown, the OFF state of the transistor capacitor 112 and the ON state of the capacitor transfer transistor 114 generate a potential difference from the transistor capacitor 122 to the second floating diffusion node FD2, which causes the charge to move from the transistor capacitor 112 to the second floating diffusion node FD2. In addition, the transistor capacitor 112 has a stepped gate dielectric thickness that generates a step potential. The step potential generates a potential barrier that prevents the charge from moving from the transistor capacitor 112 to the first floating diffusion node FD1.

[0060] In time period T8, the charge at the second floating diffusion node FD2 is converted into an output signal having a voltage that follows or is proportional to the charge. In addition, the row select transistor 118 passes the output signal to the output OUT of the pixel sensor 102. The row select signal RS is continuously in a high state, so that the row select transistor 118 is in an ON state. In addition, the capacitor transfer signal CAP TX is in a low state, so that the capacitor transfer transistor 114 is in an OFF state. The ON state of the row select transistor 118 passes the output signal from the source follower transistor 116 to the output OUT. The OFF state of the capacitor transfer transistor 114 creates a potential barrier to prevent the charge from moving out of the second floating diffusion node FD2.

[0061] By electrically separating the second floating diffusion node FD2 from the first floating diffusion node FD1, the transistor capacitor 112 and the capacitor transfer transistor 114 isolate the second floating diffusion node FD2 from the parasitic capacitance at the first floating diffusion node FD1 and the long conductive path 120 extending from the first floating diffusion node FD1 to the transistor capacitor 112. As a result, the parasitic capacitance at the second floating diffusion node FD2 and the gate electrode of the source follower transistor 116 is reduced. The reduced parasitic capacitance increases the conversion gain of the source follower transistor 116, which in turn increases the low light performance of the pixel sensor 102.

[0062] In time period T9, the readout of the charge has ended and there is a delay before the next readout cycle. The reset signal RST, PPD transfer signal PPD TX and capacitor signal CAP are in a low state, while the LOFIC signal LFG, row selection signal RS and capacitor transfer signal CAP TX are in a high state.

[0063] refer to Figure 3A-3C , respectively Figure 2 The time periods T5, T6 and T7 provide Figure 1 300A-300C of some embodiments of pixel sensor 102. The horizontal axis corresponds to locations within pixel sensor 102. The vertical axis corresponds to potentials increasing vertically downward from ground GND.

[0064] See also Figure 3A , charge 302 has accumulated at PPD 106, and the potential of PPD 106 is a first voltage V1. For example, this accumulation may occur at Figure 2 106. In addition, PPD transfer transistor 110, transistor capacitor 112, and capacitor transfer transistor 114 are in the OFF state. Because PPD transfer transistor 110 is in the OFF state, the potential at PPD transfer transistor 110 rises relative to the potential at PPD 106. This creates a potential barrier that prevents charge 302 from moving from PPD 106 to first floating diffusion node FD1.

[0065] focus on Figure 3B , charge 302 moves from PPD 106 to transistor capacitor 112. PPD pass transistor 110 and transistor capacitor 112 are in the ON state, and capacitor pass transistor 114 is in the OFF state.

[0066] Because the PPD transfer transistor 110 is in the ON state, the potential at the PPD transfer transistor 110 is between the potential at the PPD 106 (e.g., the first voltage V1) and the potential at the first floating diffusion node FD1 (e.g., the second voltage V2). In addition, because the transistor capacitor 112 is in the ON state, the potential at the transistor capacitor 122 (e.g., the third voltage V3) is less than the potential at the first floating diffusion node FD1. Overall, this creates a potential difference that helps transfer the charge 302 to the transistor capacitor 112.

[0067] Because capacitor transfer transistor 114 is in the OFF state, the potential at capacitor transfer transistor 114 (eg, first voltage V1) rises relative to the potential at transistor capacitor 112. This creates a potential barrier, preventing charge 302 from moving from transistor capacitor 112 to second floating diffusion node FD2.

[0068] focus on Figure 3C , the charge 302 moves from the transistor capacitor 112 to the second floating diffusion node FD2. The PPD transfer transistor 110 and the transistor capacitor 112 are in the OFF state, and the capacitor transfer transistor 114 is in the ON state.

[0069] Because the transistor capacitor 112 is in the OFF state, the potential at the transistor capacitor 122 (e.g., the first voltage V1) is increased relative to the potential at the second floating diffusion node (e.g., the third voltage V3). In addition, since the capacitor transfer transistor 114 is in the ON state, the potential at the capacitor transfer transistor 114 is between the potential at the transistor capacitor 112 and the potential at the second floating diffusion node FD2. Overall, this creates a potential difference that helps transfer the charge 302 to the second floating diffusion node FD2.

[0070] Since the gate dielectric thickness of the transistor capacitor 112 is stepped, its potential is also stepped. The stepped potential is highest near the first floating diffusion node FD1, thus it forms a potential barrier to prevent the charge 302 from moving to the first floating diffusion node FD1.

[0071] like Figure 3A-3C As shown, a first voltage V1, a second voltage V2, and a third voltage V3 are indicated. In some embodiments, the first voltage V1 is or is approximately 1.9 volts, the second voltage V2 is or is approximately 2.2 volts, and the third voltage V3 is or is approximately 2.8 volts. However, in alternative embodiments, other suitable voltages are also feasible.

[0072] refer to Figure 4A and Figure 4B , provides Figure 1Circuit diagrams 400A, 400B of some alternative embodiments of stacked CMOS image sensors, wherein the pixel sensor 102 is varied. Figure 4A , LOFIC transistors 122 and LOFIC 124 are omitted. Therefore, reset transistor 126 is powered from power supply V dd is electrically coupled to the second floating diffusion node FD2. Figure 4B , pixel sensor 102 includes a plurality of PPDs 106. For example, pixel sensor 102 may have two PPDs, four PPDs (as shown), eight PPDs, or some other suitable number of PPDs. In addition, pixel sensor 102 includes a plurality of PPD transfer transistors 110 that correspond one-to-one with PPDs 106.

[0073] Each PPD 106 is electrically coupled in series with a corresponding one of the PPD pass transistors 110 from the first floating diffusion node FD1 to the ground GND. Figure 1 The PPD transfer transistors 110 are selected by corresponding PPD transfer signals (e.g., PPD TX1, PPD TX2, PPD TX3, and PPD TX4). In addition, the PPD transfer transistors 110 are configured to selectively transfer the photogenerated charges from the PPD 106 to the first floating diffusion node FD1, respectively. For example, the PPD transfer transistors 110 can each be configured as Figure 1 The counterpart shown.

[0074] Although Figure 4B LOFIC transistors 122 and LOFIC 124 are shown, but in Figure 4B In an alternative embodiment of the stacked CMOS image sensor, the LOFIC transistor 122 and the LOFC 124 may be omitted. Figure 2 The signal timing diagram 200 is described for a pixel sensor having a single PPD, but it is still applicable to Figure 4B For example, Figure 4B The PPD transmission signal (such as PPD TX1, etc.) in can be expressed separately as Figure 2 The PPD signal in .

[0075] refer to Figure 5 , provides Figure 1 The circuit diagram 500 of some embodiments of the stacked CMOS image sensor of FIG. 500 further includes a third IC chip 104c. The third IC chip 104c is bonded to the second IC chip 104b and separated from the first IC chip 104a by the second IC chip 104b. In addition, the third IC chip 104c contains an application specific integrated circuit (ASIC) 502.

[0076] ASIC 502 is electrically coupled to the output OUT of pixel sensor 102 and any other pixel sensors (not shown) of the stacked CMOS image sensor. In addition, ASIC 502 may be configured to perform analog-to-digital conversion (ADC), buffering, image processing, etc., or any combination of the above operations, for example. In some embodiments, ASIC 502 buffers the output OUT of pixel sensor 102 and the output of any other pixel sensors of the stacked CMOS image sensor and performs ADC to generate digital data representing an image, and then performs image processing on the image.

[0077] ASIC 502 is formed in part from a plurality of transistors, including a plurality of n-type transistors 504n (only one is shown) and a plurality of p-type transistors 504p (only one is shown). Note that ellipses at ASIC 502 are used to represent zero or more additional n-type transistors and / or p-type transistors. N-type transistors 504n and p-type transistors 504p may be, for example, MOSFETs, FinFETs, GAA-FETs, nanosheet field effect transistors, some other suitable type of transistors, or any combination of the above transistors.

[0078] refer to Figure 6 , provides Figure 5 Schematic cross-sectional view 600 of some embodiments of a stacked CMOS image sensor, wherein first, second, and third IC chips 104a-104c are vertically stacked. The first IC chip 104a is located at the top of the stacked CMOS image sensor and is configured to receive radiation 602 from the top of the stacked CMOS image sensor. The second IC chip 104b is located below and bonded to the first IC chip 104a, and the third IC chip 104c is located below and bonded to the second IC chip 104b.

[0079] refer to Figure 7 , provides Figure 5 Schematic cross-sectional view 700 of some alternative embodiments of a stacked CMOS image sensor, wherein the stacked CMOS image sensor includes a plurality of pixel sensors 102. The pixel sensors 102 share an ASIC 502, such as Figure 5 Alternatively, the pixel sensor 102 may be Figure 4A or Figure 4B In addition, Figure 6 As shown, the first, second, and third IC chips 104a-104c are vertically stacked.

[0080] refer to Figure 8 , provides Figure 7 A top view layout diagram 800 of some embodiments of a stacked CMOS image sensor, wherein a plurality of pixel sensors 102 are arranged in a plurality of rows and a plurality of columns. For example, Figure 7 The schematic cross-sectional view 700 may be taken along Figure 8 The line A-A' in is intercepted.

[0081] Multiple lines include from R1, R2, etc. to R M The rows and columns include C1, C2, etc. N The subscripts of the row labels correspond to the row numbers, where M is an integer greater than 3. Similarly, the subscripts of the column labels correspond to the column numbers, where N is an integer greater than 3. In addition, the plurality of rows and columns form a two-dimensional array, wherein the pixel sensors 102 are arranged in a periodic grid pattern. Other suitable patterns are also possible.

[0082] refer to Fig. 9 , provided at the second IC chip 104b Figure 1 A top view layout diagram 900 of some first embodiments of a stacked CMOS image sensor is shown. The transistor capacitor 112, the capacitor transfer transistor 114, the LOFIC transistor 122, and the reset transistor 126 are located on the first active semiconductor region 902, and the row selection transistor 118 and the source follower transistor 116 are located on the second active semiconductor region 904. In addition, the second floating diffusion node FD2 is located in the first active semiconductor region 902, and is laterally located between the capacitor transfer transistor 114 and the LOFIC transistor 122.

[0083] Capacitor transfer transistor 114 is electrically coupled to transistor capacitor 112 and is also electrically coupled to second floating diffusion node FD2 through first active semiconductor region 902. Similarly, LOFIC transistor 122 is electrically coupled to second floating diffusion node FD2 and is also electrically coupled to reset transistor 126 through first active semiconductor region 902. Row select transistor 118 is electrically coupled to source follower transistor 116 through second active semiconductor region 904.

[0084] The first active semiconductor region 902 and the second active semiconductor region 904 are separated from each other by an isolation structure 906 and are respectively surrounded by the isolation structure 906. In addition, the first active semiconductor region 902 has an L-shaped top-view geometry around the corner of the second active semiconductor region 904. In alternative embodiments, the first active semiconductor region 902 may, for example, have some other suitable top-view geometry. The isolation structure 906 may, for example, be or include a shallow trench isolation (STI) structure and / or some other suitable type of isolation structure.

[0085] The transistor capacitor 112, the capacitor transfer transistor 114, the LOFIC transistor 122, the reset transistor and the row selection transistor 118, and the source follower transistor 116 include corresponding gate electrodes 908. The gate electrodes 908 overlap with the first active semiconductor region 902 and the second active semiconductor region 904, respectively, and are separated from each other. In addition, the gate electrode of the source follower transistor 116 is electrically coupled to the second floating diffusion node FD2 through a conductive path 910. For example, the conductive path 910 can be formed by a wire and a through hole.

[0086] In some embodiments, the length L of the gate electrode 908 of the transistor capacitor 112 is cg In some embodiments, the gate electrode 908 of the capacitor transfer transistor 114 has a length L of about 50-500 nanometers, about 50-275 nanometers, about 275-500 nanometers, or some other suitable value. ctg In some embodiments, gate electrode 908 of transistor capacitor 112 is separated from gate electrode 908 of capacitor pass transistor 114 by a spacing S of about 10-200 nanometers, about 10-105 nanometers, about 105-200 nanometers, or some other suitable value.

[0087] In some embodiments, the first active semiconductor region 902 has a first width W1 of about 20-500 nanometers, about 20-260 nanometers, about 260-500 nanometers, or some other suitable value at the gate electrode 908 of the transistor capacitor 112. In some embodiments, the first active semiconductor region 902 has a second width W2 of about 20-500 nanometers, about 20-260 nanometers, about 260-500 nanometers, or some other suitable value at the gate electrode 908 of the capacitor transfer transistor 114.

[0088] refer to Figure 10A-10C , provides Fig. 9 The cross-sectional views 1000A-1000C of some first embodiments of stacked CMOS image sensors are shown. The cross-sectional views 1000A-1000C may be respectively taken along Fig. 9 The B-B', C-C' and D-D' lines are intercepted.

[0089] The first active semiconductor region 902 and the second active semiconductor region 904 correspond to regions of the semiconductor substrate 1002 and are surrounded and bounded by the isolation structure 906. In addition, the transistor capacitor 112, the capacitor transfer transistor 114, the LOFIC transistor 122, the reset transistor 126, and the row select transistor 118, and the source follower transistor 116 (collectively referred to as devices) are located on the semiconductor substrate 1002, at the first and second active semiconductor regions 902, 904, respectively.

[0090] The device includes a separate gate electrode 908, a separate gate dielectric layer 1004, a separate well 1006, a separate channel 1008, a corresponding sidewall spacer structure 1010, and a corresponding source / drain region 1012. It should be noted that as used below, a source / drain region can be a source region or a drain region. In addition, the device is located below and electrically coupled to an interconnect structure 1014, which includes a plurality of contact vias 1016a embedded in an interconnect dielectric layer 1018.

[0091] The gate electrodes 908 cover the gate dielectric layer 1004, respectively, and border corresponding regions in the source / drain region 1012. In addition, a sidewall spacer structure 1010 is located on the sidewalls of the gate electrode 908. The sidewall spacer structure 1010 includes a separate first spacer layer 1020 and a separate second spacer layer 1022. In an alternative embodiment, the first spacer layer 1020 or the second spacer layer 1022 is omitted. The second spacer layer 1022 wraps around the bottom corners of the first spacer layer 1020 to separate the first spacer layer 1010 from the gate electrode 908 and the semiconductor substrate 1002. The first spacer layer 1020 and the second spacer layer 1022 are dielectrics.

[0092] The wells 1006 are respectively located under the gate dielectric layer 1004 and extend from the source / drain regions 1012 under the gate dielectric layer 1004. The wells 1006 and the source / drain regions 1012 are located in the semiconductor substrate 1002 along the top of the semiconductor substrate 1002. In addition, the wells 1006 and the source / drain regions 1012 share a first doping type, but the source / drain regions 1012 have a higher doping concentration than the wells 1006. At the body 1002b of the semiconductor substrate 1002, the first doping type is opposite to the second doping type. For example, the first doping type may be n-type, and the second doping type may be, for example, p-type, and vice versa.

[0093] Well 1006 of PPD transfer transistor 110, transistor capacitor 112, and capacitor transfer transistor 114 corresponds to Figure 3A-3C For example, Figure 3A-3CThe potential at transistor capacitor 112 in is the potential at well 1006 of transistor capacitor 112. In addition, well 1006 can have different doping concentrations to control the potential. Assuming that the gate voltage, gate dielectric thickness, etc. remain constant, Figure 3A-3C In the embodiment, a higher doping concentration may result in a higher potential (eg, closer to ground GND).

[0094] The channel 1008 is buried in the well 1006 and selectively conducts electricity according to the bias of the corresponding gate electrode 908. Burying the channel 1008 in the well 1006 can prevent the channel 1008 from picking up noise on the top surface of the semiconductor substrate 1002, thereby improving imaging performance.

[0095] See also Fig. 10A , the capacitor transfer transistor 114 and the LOFIC transistor 122 share one of the source / drain regions 1012, which is also the second floating diffusion node FD2. In addition, the transistor capacitor 112 and the capacitor transfer transistor 114 are bordered without an intermediate source / drain region and share a sidewall spacer structure 1010. In addition, the gate dielectric layer 1004 of the transistor capacitor 112 has a dielectric thickness T d1 Gradually reduce to the second dielectric thickness T d2 The stepped outline.

[0096] Having a first dielectric thickness T d1 A portion of the gate dielectric layer 1004 of the transistor capacitor 112 has a first dielectric length L d1 , and having a second dielectric thickness T d2 Another portion of the gate dielectric layer 1004 of the transistor capacitor 112 has a second dielectric length L d2 In some embodiments, the first dielectric length L d1 With the second dielectric length L d2 The ratio (e.g., L d1 / L d2 ) is greater than or equal to 0.1 and less than or equal to 0.5. However, in other embodiments, other suitable values ​​are also feasible.

[0097] The first dielectric thickness T d1 is located at a first side of transistor capacitor 112, which is electrically coupled to a first floating diffusion node FD1. Note that the first floating diffusion node FD1 is located at Fig. 10A The second dielectric thickness T d2 The first dielectric thickness T is located at a second side of the transistor capacitor 112, the second side being opposite to the first side and being electrically coupled to the capacitor transfer transistor 114. In some embodiments, the first dielectric thickness T d1is about 30-100 angstroms, 30-65 angstroms, 65-100 angstroms, or other suitable values. In some embodiments, the second dielectric thickness T d2 The second dielectric thickness T is about 20-100 angstroms, 20-60 angstroms, 60-100 angstroms, or other suitable values. In some embodiments, the gate dielectric layer 1004 of the capacitor transfer transistor 114 has a second dielectric thickness T d2 .

[0098] As mentioned above, Figure 3A-3C The potential at transistor capacitor 112 in is the potential at well 1006 of transistor capacitor 122. Further, changing the thickness of gate dielectric layer 1004 of transistor capacitor 112 will change the potential at its well 1006. Assuming that gate voltage, well doping concentration, etc. remain constant, Figure 3A-3C In the embodiment of the present invention, a thicker gate dielectric layer may result in a higher potential (eg, closer to ground GND).

[0099] In view of the above, the stepped profile at the gate dielectric layer 1004 of the transistor capacitor 112 results in a stepped potential at the well 1006 of the transistor capacitor 112. Figure 3A-3C and Fig. 10A , the stepped potential is at its highest level on the first side of the transistor capacitor 112 electrically coupled to the first floating diffusion node FD1. This creates a potential barrier that prevents the charge 302 from Figure 3C moves back to the first floating diffusion node FD1 during the transmission process.

[0100] Focus on Fig. 10B , the boundary between the row select transistor 118 and the source follower transistor 116 has no intermediate source / drain region. In addition, the row select transistor 118 and the source follower transistor 116 share one of the sidewall spacer structures 1010.

[0101] Focus on Fig. 10C , the LOFIC transistor 122 and the reset transistor 126 are bordered without an intermediate source / drain region. In addition, the LOFIC transistor 122 and the reset transistor 126 share one of the sidewall spacer structures 1010 .

[0102] refer to Figures 11A-11C , provides Fig. 9 The cross-sectional views 1100A-1100C of some second embodiments of stacked CMOS image sensors are shown. The cross-sectional views 1100A-1100C may be respectively along Fig. 9 The B-B', C-C' and D-D' lines in the Figure 10A-10C In contrast, some adjacent devices share source / drain regions and have separate sidewall spacer structures.

[0103] See also Fig.11A , the transistor capacitor 112 and the capacitor transfer transistor 114 are separated by one of the source / drain regions 1012. In addition, the transistor capacitor 112 and the capacitor transfer transistor 114 have separate sidewall spacer structures 1010 spaced apart from each other.

[0104] See also Fig. 11B , the row select transistor 118 and the source follower transistor 116 are separated by one of the source / drain regions 1012. In addition, the row select transistor 118 and the source follower transistor 116 have separate sidewall spacer structures 1010 spaced apart from each other.

[0105] Focus on Fig. 11C , the LOC transistor 122 and the reset transistor 126 are defined and separated by one of the source / drain regions 1012. In addition, the LOC transistor 122 and the reset transistor 126 have separate sidewall spacer structures 1010 spaced apart from each other.

[0106] refer to Fig.12 , provides Fig. 9 A cross-sectional view 1200 of some embodiments of a stacked CMOS image sensor at a first IC chip 104a and a second IC chip 104b. For example, the cross-sectional view 1200 may be taken along Fig. 9 The line BB' in is intercepted.

[0107] The first IC chip 104a covers the second IC chip 104b and includes a first semiconductor substrate 1202. The first semiconductor substrate 1202 accommodates the PPD 106 and the PPD pass transistor 110. The PPD 106 and the PPD pass transistor 110 are at least partially formed by the first semiconductor substrate 1202 and are surrounded by an isolation structure 1204. The first semiconductor substrate 1202 can be, for example, a bulk substrate of single crystal silicon, silicon germanium, etc. The isolation structure 1204 can be, for example, an STI structure and / or some other suitable isolation structure.

[0108] PPD 106 includes a collector region 1206 and a pinning region 1208 located below collector region 1206 on the front side of first semiconductor substrate 1202. In addition, PPD 106 includes a portion of body 1202b of first semiconductor substrate 1202 that abuts and surrounds pinning region 1208 and collector region 1206. During operation, PPD 106 receives radiation from above first semiconductor substrate 1202, which causes charge to accumulate in collector region 1206. The potential at collector region 1206 corresponds to Figure 3A-3C The potential at PPD 106 in FIG.

[0109] The body 1202b and the pinning region 1208 of the first semiconductor substrate 1202 correspond to the doping region of the first semiconductor substrate 1201 and share a first doping type. In addition, the pinning region 1208 has a higher doping concentration than the body 1202b of the first semiconductor substrate 1202. The collector region 1206 corresponds to the doping region of the first semiconductor substrate 1202 and has a second doping type opposite to the first doping type. For example, the first doping type may be p-type and the second doping type may be n-type, or vice versa. In addition, the collector region 1206 is adjacent to the pinning region 1208 and the body 1202b of the first semiconductor substrate 1202 to form a PN junction.

[0110] The PPD pass transistor 110 interfaces with the PPD 106 at the front side of the first semiconductor substrate 1202. In addition, the PPD pass transistor 110 includes a gate electrode 1210, a gate dielectric layer 1212, a sidewall spacer structure 1214, a pair of source / drain regions 1216, and a channel 1218. The gate electrode 1210 and the gate dielectric layer 1212 are stacked, and the gate dielectric layer 1212 separates the gate electrode 1210 from the first semiconductor substrate 1202. The sidewall spacer structure 1214 is located on the sidewalls of the gate electrode 1210 and the gate dielectric layer 1212.

[0111] The source / drain regions 1216 are located in the first semiconductor substrate 1202 and are separated from each other by a channel 1218 in the first semiconductor substrate 1202. In addition, the source / drain regions 1216 correspond to doped regions of the first semiconductor substrate 1202, which share a common doping type, which is opposite to the doping type of the body 1202b of the first semiconductor substrate 1202. For example, the source / drain regions 1216 may be n-type and the body 1202b of the first semiconductor substrate 1202 may be p-type, or vice versa. One of the source / drain regions 1216 is formed by the collector region 1206, and the other of the source / source regions 1216 forms the first floating diffusion node FD1.

[0112] The first interconnect structure 1220 is located below the PPD transfer transistor 110 and is electrically coupled to the PPD transfer transistor 110. The first interconnect structure 1220 includes a plurality of conductive lines 1222 and a plurality of vias 1224 stacked in an interconnect dielectric layer 1226. The conductive lines 1222 and the vias 1224 are respectively grouped into a plurality of conductive line layers and a plurality of via layers that are alternately stacked to form a conductive path.

[0113] The second IC chip 104b is located below the first IC chip 104a and includes a second semiconductor substrate 1002 containing a plurality of devices. These devices include a transistor capacitor 112, a capacitor transfer transistor 114, and a LOFIC transistor 122. Fig.12In addition to the cross-sectional view 1200 of FIG. 1 , these devices may include a source follower transistor 116, a row select transistor 118, and a reset transistor 126. These devices are at least partially formed by the second semiconductor substrate 1002 and are surrounded by the isolation structure 906. In addition, these devices may be as shown in FIG. Fig. 9 and Figure 10A-10C or Fig. 9 and Figures 11A-11C The second semiconductor substrate 1002 may be, for example, a bulk substrate of single crystal silicon, silicon germanium, or the like.

[0114] The second interconnect structure 1014 overlies the device and is electrically coupled to the device. The second interconnect structure 1014 includes a plurality of conductive lines 1228 and a plurality of vias 1016 stacked in an interconnect dielectric layer 1018. The conductive lines 1228 and the vias 1016 are respectively grouped into a plurality of conductive line layers and a plurality of via layers that are alternately stacked to form a conductive path. For example, the second interconnect structure 1014 may be formed Fig. 9 In addition, the vias at the via level closest to the second semiconductor substrate 1002 can also be regarded as contact vias. Fig.12 Outside of the cross-sectional view 1200 , the LOFIC 124 is located in the second interconnect structure 1014 and is electrically coupled thereto.

[0115] The bonding structure 1230 is located between the first IC chip 104a and the second IC chip 104b and helps to bond the first and second IC chips 104a, 104b together at the bonding interface 1232. For example, such bonding may include a combination of metal-to-metal bonding and dielectric-to-dielectric bonding at the bonding interface 1232.

[0116] The bonding structure 1230 includes a bonding dielectric layer 1234 that is independent of the first and second IC chips 104a, 104b, and is in direct contact and bonded together at a bonding interface 1232. In addition, the bonding structure 1230 includes bonding pads 1236 that are independent of the first and second IC chips 104a, 104b, and are in direct contact and bonded together at a bonding interface 1232. The bonding pads 1236 are respectively inserted into the bonding dielectric layer 1234, and are respectively electrically coupled to the first and second interconnect structures 1220, 1014 through bonding through holes 1238 in the bonding dielectric layer 1234.

[0117] As described above, the transistor capacitor 112 and the capacitor transfer transistor 114 isolate the second floating diffusion FD2 from the parasitic capacitance at the first floating diffusion node FD1 and the long conductive path 120 extending from the first floating diffusion node FD1 to the transistor capacitor 114. The long conductive path 120 is formed by the bonding structure 1230, the first interconnect structure 1220 and the second interconnect structure 1014.

[0118] refer to Fig.13 , provided at the second IC chip 104b Figure 1 A top view layout diagram 1300 of some second embodiments of stacked CMOS image sensors. Fig. 9 In contrast, the reset transistor 126 and the LOFIC transistor 122 are located on a third active semiconductor region 1302 that is separated from the first and second active semiconductor regions 902, 904. In addition, the second active semiconductor region 904 has been moved to Fig. 9 The location where the reset transistor 126 and the LOFIC transistor 122 are located.

[0119] Conductive path 1304 extends from gate electrode 908 of source follower transistor 116 to electrically couple gate electrode 908 to second floating diffusion node FD2 and further to source / drain region 1012a of LOFIC transistor 122. Conductive path 1304 may be formed of a conductive line and a via, for example.

[0120] refer to Figure 14A-Figure 14C , provides Fig.13 The cross-sectional views 1400A-1400C of some first embodiments of stacked CMOS image sensors are shown. The cross-sectional views 1400A-1400C may be respectively taken along Fig.13 In addition, for example, the cross-sectional views 1400A-1400C may be respectively Figure 10A-10C The cross-sectional views 1000A-1000C are the same, but by comparison Fig.13 and Fig. 9 You can see the changes in the layout.

[0121] refer to Figure 15A-Figure 15C , provides Fig.13 The cross-sectional views 1500A-1500C of some second embodiments of stacked CMOS image sensors are shown. The cross-sectional views 1500A-1500C may be respectively along Fig.13 The E-E', F-F' and G-G' lines in Figure 14A-Figure 14C In contrast, some adjacent devices share source / drain regions and have separate sidewall spacer structures.

[0122] refer to Fig.16 , provides Fig.13 A cross-sectional view 1600 of some embodiments of a stacked CMOS image sensor at a first IC chip 104a and a second IC chip 104b. For example, the cross-sectional view 1600 may be taken along Fig.13 The E-E' line in FIG. 1 may be intercepted by Fig.12 As shown in the cross-sectional view 1200, in addition to comparing Fig.13 and Fig. 9 See the layout changes.

[0123] refer to Fig.17 , a cross-sectional view 1700 of some embodiments of a stacked CMOS image sensor is provided, wherein the stacked CMOS image sensor includes a plurality of pixel sensors 102, each pixel sensor such as Fig.12 As shown, a third IC chip 104c having ASIC 502 is also included. The third IC chip 104c is located below the second IC chip 104b and includes a plurality of transistors 504 formed at least partially by a third semiconductor substrate 1704 of the third IC chip 104c. The third semiconductor substrate 1704 can be, for example, a bulk substrate of single crystal silicon, silicon germanium, or the like.

[0124] The transistors 504 are located on the front side of the third semiconductor substrate 1704 and are further laterally separated from each other by isolation structures 1706. The isolation structures 1706 may be or include, for example, an STI structure or some other suitable isolation structure. In addition, the transistors 504 include a separate gate electrode 1708, a separate gate dielectric layer 1710, a separate sidewall spacer structure 1712, a separate pair of source / drain regions 1714, and a separate channel 1716.

[0125] The gate electrodes 1708 are stacked with gate dielectric layers 1710, respectively, which separate the gate electrodes 1708 from the third semiconductor substrate 1704. Sidewall spacer structures 1712 are dielectrics and are respectively located on the sidewalls of the gate electrodes 1708. Pairs of source / drain regions 1714 are located in the third semiconductor substrate 1704. In addition, the source / drain regions of each pair of source / drain regions 1714 are separated by a corresponding one of the channels 1716.

[0126] A third interconnect structure 1718 overlies the transistor 504 and is electrically coupled to the transistor 504. The third interconnect structure 1718 includes a plurality of conductive lines 1720 and a plurality of vias 1722 stacked in an interconnect dielectric layer 1724. The conductive lines 1720 and the vias 1722 are grouped into a plurality of conductive line levels and a plurality of via levels stacked alternately, respectively, to form a conductive path leading out of the transistor 504.

[0127] There is an additional bonding structure 1726 between the third interconnect structure 1718 and the second semiconductor substrate 1002. In addition, the additional bonding structure 1726 facilitates bonding the second and third IC chips 104b, 104c together at the additional bonding interface 1728. For example, such bonding may include a combination of metal-to-metal bonding and dielectric-to-dielectric bonding at the additional bonding interface 1728.

[0128] The additional bonding structure 1726 includes an additional bonding dielectric layer 1730 that is independent of the second and third IC chips 104b, 104c, and is in direct contact and bonded together at an additional bonding interface 1728. In addition, the additional bonding structure 1726 includes additional bonding pads 1732 that are independent of the second and third IC chips 104b, 104c, and are in direct contact and bonded together at the additional bonding interface 1728. The additional bonding pads 1732 are respectively inserted into the additional bonding dielectric layer 1730, and are respectively electrically coupled to the third interconnect structure 1718 and the plurality of TSVs 1734 through additional bonding vias 1736 in the additional bonding dielectric layer 1730.

[0129] The TSV 1734 is independent of the pixel sensor 102 and extends through the second semiconductor substrate 1002 from the second interconnect structure 1014 to the additional bonding structure 1726. In addition, the TSV 1734 is separated from the second semiconductor substrate 1002 by a separate TSV dielectric layer 1738.

[0130] Transistor 504 and third interconnect structure 1718 form ASIC 502, which is electrically coupled to pixel sensor 102 via additional bonding structure 1726 and TSV 1734. For example, ASIC 502 may be configured as Figure 5 , Figure 6 and Figure 7 As shown, transistor 504 may correspond to Figure 5 In addition, ASIC 502 may be configured to perform ADC, buffering, image processing, etc., or any combination thereof, for example.

[0131] refer to Fig.18 , provides Fig.17 A cross-sectional view 1800 of some alternative embodiments of a stacked CMOS image sensor, wherein pixel sensors 102 are each as Fig.16 shown.

[0132] Although Fig.12 and Fig.17 It shows that Fig. 10A The pixel sensor embodiment shown, however, Fig.11A And / or any other pixel sensor embodiments shown in the figures herein are also feasible. Fig.16 and Fig.18 It shows that Fig.14A The pixel sensor embodiment shown, however Fig.15A and / or any other embodiments of the pixel sensor in this document are possible.

[0133] refer to FIG. 19A to FIG. 35B, provides a series of views of some embodiments of a method for forming a stacked CMOS image sensor including a pixel sensor for HCG. For example, the method can be performed to form a Fig.17 The stacked CMOS image sensor shown or some other suitable stacked CCD image sensor.

[0134] like Fig.19A , Fig.19B and Fig. 20 As shown, a first IC chip 104a including a first pixel portion 102a of a pixel sensor is formed.

[0135] Focus on Fig.19A The cross-sectional view 1900A and Fig.19B In the circuit diagram 1900B, an isolation structure 1204 is formed in the first semiconductor substrate 1202 to surround and define the first pixel portion 102a. The isolation structure 1204 may be or include, for example, an STI structure, etc. In addition, the PPD 106, the first floating diffusion node FD1, and the PPD transfer transistor 110 are formed.

[0136] The PPD 106 and the first floating diffusion node FD1 are formed in the first semiconductor substrate 1202. In addition, the PPD 106 and the first floating diffusion node FD1 are formed to be laterally separated from each other. The PPD 106 includes a collector region 1206 and a pinning region 1208 covering the collector region 1206, and also includes a portion of a body 1202b of the first semiconductor substrate 1202. The body 1202b of the first semiconductor substrate 1202 forms an anode of the PPD 106 or is otherwise electrically coupled to the anode of the PPD 106, and the collector region 1206 forms a cathode of the PPD 106.

[0137] The collector region 1206, the pinning region 1208, and the first floating diffusion node FD1 correspond to the doped regions of the first semiconductor substrate 1202. The collector region 1206 and the first floating diffusion node FD1 share a first doping type, and the pinning region 1208 and the body 1202b of the first semiconductor substrate 1202 share a second doping type opposite to the first doping type. For example, the first doping type may be n-type, and the second doping type may be p-type, or vice versa. In addition, the pinning region 1208 and the body 1202b of the first semiconductor substrate 1202 surround the collector region 1206 and the first floating diffusion node FD, so that the boundary between the collector region 1206 and the first floating diffusion node FD is defined by a PN junction.

[0138] The PPD pass transistor 110 includes a gate electrode 1210, a gate dielectric layer 1212, a sidewall spacer structure 1214, a pair of source / drain regions 1216, and a channel 1218. The gate electrode 1210 and the gate dielectric layer 1212 are vertically stacked on the first semiconductor substrate 1202, and the sidewall spacer structure 1214 is located on the sidewall of the gate electrode 1210. The source / drain regions 1216 are located in the first semiconductor substrate 1202 and are separated from each other by the channel 1218 in the first semiconductor substrate 1202. In addition, the source / drain regions 1216 correspond to the collector region 1206 and the first floating diffusion node FD1.

[0139] Focus on Fig. 20 2000 , a first interconnect structure 1220 and a first bonding substructure 1230 a are formed.

[0140] The first interconnect structure 1220 is formed above the PPD transfer transistor 110 and the first floating diffusion node FD1 and is electrically coupled thereto. The first interconnect structure 1220 includes a plurality of conductive lines 1222 and a plurality of vias 1224 in an interconnect dielectric layer 1226. The conductive lines 1222 and the vias 1224 are conductive and are grouped into a plurality of conductive line layers and a plurality of via layers, respectively, which are alternately stacked.

[0141] The first bonding substructure 1230a is formed over and electrically coupled to the first interconnect structure 1220. The first bonding substructure 1230a includes a bonding pad 1236 and a bonding via 1238 in a bonding dielectric layer 1234. The bonding pad 1236 and the bonding dielectric layer 1234 form a common bonding surface facing away from the first interconnect structure 1220, and the bonding via 1238 extends from the bonding pad 1232 to the first interconnect structure 1220.

[0142] like Fig.21A , Fig.21B , Figure 22-Figure 26 , Fig.27A , Fig.27B , Fig.28 , Fig.29A and Fig.29B As shown in FIG. 1 , a second IC chip 104b including a second pixel portion 102b of a pixel sensor is formed. For example, the second pixel portion 102b may be as shown in FIG. Fig. 9 and Figure 10A-10C , Fig. 9 and Figures 11A-11C , Fig.13 and Figure 14A-Figure 14C or Fig.13 and Figure 15A-Figure 15C shown.

[0143] Focus on Fig.21A A cross-sectional view of 2100A and Fig.21B210B, forming an isolation structure 906. For example, the cross-sectional view 2100A can be taken along the line BB' in the top view layout view 2100B. The isolation structure 906 surrounds and defines the first active semiconductor region 902 and the second active semiconductor region 904. The first active semiconductor region 902 has an L-shaped top view geometry and surrounds the corner of the second active semiconductor region 904. The isolation structure 906 can be or include, for example, an STI structure, etc.

[0144] Focus on Fig. 22 2200, a plurality of wells 1006 and a plurality of source / drain regions 1012 are formed in the second semiconductor substrate 1002 by selectively doping the second semiconductor substrate 1002. The plurality of wells 1006 may be formed by a first selective doping process, and then the plurality of source / drain regions 1012 may be formed by a second selective doping process, or vice versa. For example, the selective doping process may include ion implantation with a mask (e.g., photoresist, etc.), or some other suitable type of selective doping process.

[0145] The well 1006 and the source / drain region 1012 correspond to the readout device being formed, which includes a transistor capacitor, a capacitor transfer transistor, and a LOFIC transistor 122. The well 1006 and the source / drain region 1012 are arranged along the top surface of the second semiconductor substrate 1002 and share a doping type that is opposite to the doping type at the body 1002b of the second semiconductor substrate 1002. For example, the doping type may be n-type, while the opposite doping type may be p-type, or vice versa. In addition, the source / drain region 1012 has a higher doping concentration than the well 1006, and the source / drain region corresponding to the capacitor transfer transistor may be regarded as a second floating diffusion node FD2.

[0146] Focus on Fig.23 2300, a first dielectric layer 2302 is deposited on the second semiconductor substrate 1002. The first dielectric layer 2302 has a first dielectric thickness T d1 , and for example may be or include silicon oxide or the like.

[0147] Focus on Fig.24 2400, the first dielectric layer 2302 is patterned to form a dielectric structure 2402p that is independent and covers one of the wells 1006. As described below, the well corresponds to the transistor capacitor being formed. The patterning further exposes the portion of the second semiconductor substrate 1002 that is not covered by the dielectric structure 2402p. The patterning can be performed, for example, by a lithography / etching process or by some other suitable patterning process.

[0148] Focus on Fig.252500, a second dielectric layer 2502 is deposited on the second semiconductor substrate 1002. The second dielectric layer 2502 has a thickness T less than the first dielectric layer 1002. d1 The second dielectric thickness T d2 The second dielectric layer 2502 may be or include, for example, silicon oxide, etc. In some embodiments, the second dielectric layer 2502 is the same material as the dielectric structure 2402p. In addition, the second dielectric layer 2502 is deposited by thermal oxidation, etc., so that the second dielectric layer 2502 is minimally deposited on the dielectric structure 2402p.

[0149] Focus on Fig.26 In the cross-sectional view 2600 of FIG. 2600 , a conductive layer 2602 is deposited over the second dielectric layer 2502 and the dielectric structure 2402p. In some embodiments, planarization is further performed to planarize the top surface of the conductive layer 2602. For example, planarization may be performed by chemical mechanical polishing (CMP) and / or by some other suitable planarization process.

[0150] Focus on Fig.27A A cross-sectional view of 2700A and Fig.27B In the top view layout diagram 2700B, the conductive layer 2602, the second dielectric layer 2502 and the dielectric structure 2402p are patterned together. For example, the cross-sectional view 2700A can be taken along the line BB' in the top view layout diagram 2700B.

[0151] Patterning forms a plurality of readout devices, including transistor capacitor 112, capacitor transfer transistor 114, source follower transistor 116, row select transistor 118, LOFIC transistor 122, and reset transistor 126. In addition, patterning forms a plurality of gate electrodes 908 and a plurality of gate dielectric layers 1004, which are independent of the readout devices and form gate stacks of the readout devices. For example, patterning may be performed by a lithography / etching process or by some other suitable patterning process.

[0152] The gate electrode 908 is formed by the conductive layer 2602 and covers the gate dielectric layer 1004. The gate dielectric layer 1004 is formed by the second dielectric layer 2502, and the gate dielectric layer 1004 of the transistor capacitor 112 is also formed by the dielectric structure 2402p. In addition, the gate dielectric layer 1004 covers the well 1006, which is independent for the readout device.

[0153] Since the gate dielectric layer 1004 of the transistor capacitor 112 is formed by the dielectric structure 2402p and the second dielectric layer 2502, the gate dielectric layer 1004 of the transistor capacitor 112 has a stepped profile. In addition, the gate electrode 908 of the transistor capacitor 112 has a stepped bottom profile. The stepped profile at the gate dielectric layer 1004 of the transistor capacitor 112 generates a potential with a stepped profile at the well 1006 of the transistor capacitor. As described above, this creates a potential barrier that prevents charge from flowing from the transistor capacitor 112 to the first floating diffusion node FD1.

[0154] Focus on Fig.28 28, a plurality of sidewall spacer structures 1010 are respectively formed on the sidewalls of the gate electrode 908. The sidewall spacer structures 1010 include a separate first spacer layer 1020 and a separate second spacer layer 1022. In an alternative embodiment, the first spacer layer 1020 or the second spacer layer 1022 is omitted. The second spacer layer 1022 surrounds the bottom corner of the first spacer layer 1020 to separate the first spacer layer 1010 from the gate electrode 908 and the semiconductor substrate 1002. The first spacer layer 1020 and the second spacer layer 1022 are dielectrics.

[0155] Focus on Fig.29A A cross-sectional view of 2900A and Fig.29B 2900B, a second interconnect structure 1014 and a LOFIC 124 are formed. The second interconnect structure 1014 is formed over a readout device (e.g., transistor capacitor 112, capacitor transfer transistor 114, etc.) on the second semiconductor substrate 1002 and is electrically coupled to the readout device. In addition, while forming the second interconnect structure 1014, the LOFIC 124 is formed in the second interconnect structure 1014 and is electrically coupled to the second interconnect structure 1014. Note that the LOFIC 124 is located outside the cross-sectional view 2900A.

[0156] The second interconnect structure 1014 includes a plurality of conductive lines 1228 and a plurality of vias 1016 in an interconnect dielectric layer 1018. The conductive lines 1228 and the vias 1016 are conductive and are respectively divided into a plurality of conductive line levels and a plurality of via levels, which are alternately stacked to form a conductive path interconnecting the readout device and the LOFIC 124, such as Fig.29B For example, such a conductive path includes electrically coupling the second floating diffusion node FD2 to the source follower transistor 116 (see FIG. Fig.27B ) conductive path.

[0157] In addition to the second interconnect structure 1014 and the LOFIC 124, a second bonding substructure 1230b is formed over and electrically coupled to the second interconnect structure 1014. The second bonding substructure 1230b includes a bonding pad 1236 and a bonding via 1238 in a bonding dielectric layer 1234. The bonding pad 1236 and the bonding dielectric layer 1234 form a common bonding surface facing away from the second interconnect structure 1014, and the bonding via 1238 extends from the bonding pad 1232 to the second interconnect structure 1014.

[0158] like Fig. 30A The cross-sectional view 3000A and Fig. 30B As shown in the circuit diagram 3000B, Fig.29A and Fig.29B The second IC chip 104b is flipped vertically and bonded to the first bonding interface 1232. Fig. 20 The first IC chip 104a. The bonding includes metal-to-metal bonding and dielectric-to-dielectric bonding. Fig. 20 The first pixel portion 102a and Fig.29A and Fig.29B The second pixel portion 102b in the form the pixel sensor 102. In addition, the junction electrically couples the first floating diffusion node FD1 to the transistor capacitor 112 via the long conductive path 120.

[0159] During use of the pixel sensor 102, charge accumulates at the PPD 106. Thereafter, the charge is transferred from the PPD 106 to the transistor capacitor 112 through the first floating diffusion node FD1. Furthermore, the charge is transferred from the transistor capacitor 112 to the second floating diffusion node FD2 through the capacitor transfer transistor 114. Thus, the transistor capacitor 112 and the capacitor transfer transistor 114 electrically isolate the second floating diffusion node FD2 from the first floating diffusion node FD1.

[0160] By electrically separating the second floating diffusion node FD2 from the first floating diffusion node FD1, the transistor capacitor 112 and the capacitor transfer transistor 114 isolate the second floating diffusion node FD2 from the parasitic capacitance at the first floating diffusion node FD1 and along the long conductive path 120 extending from the first floating diffusion node FD1 to the transistor capacitor 114. As a result, the parasitic capacitance at the second floating diffusion node FD2 and at the gate electrode of the source follower transistor 116 is reduced. This in turn increases the conversion gain of the source follower transistor 116, thereby improving low light performance.

[0161] like Fig.31As shown in the cross-sectional view 3100 of FIG. 3 , the second semiconductor substrate 1002 is thinned from the side opposite to the second interconnect structure 1014. For example, the thinning may be performed by CMP and / or some other suitable planarization process.

[0162] like Fig.31 As shown in the cross-sectional view 3100 of FIG. 31 , a TSV 1734 is formed, which extends through the second semiconductor substrate 1002 to the second interconnect structure 1014. In addition, the TSV 1734 is formed by a TSV dielectric layer 1738, which is separated from the second semiconductor substrate 1002 and the interconnect dielectric layer 1018 of the second interconnect structure 1014. The TSV 1734 is conductive to provide electrical coupling from the back side of the second semiconductor substrate 1002 to the second interconnect structure 1014.

[0163] like Fig.32 As shown in the cross-sectional view 3200 of FIG. 3200 , the third bonding substructure 1726 a is formed on the back side of the second semiconductor substrate 1002. The third bonding substructure 1726 a includes a bonding pad 1732 and a bonding through hole 1736 in the bonding dielectric layer 1730. The bonding pad 1732 and the bonding dielectric layer 1730 form a common bonding surface, and the bonding through hole 1736 extends from the bonding pad 1732 to the TSV 1734.

[0164] like Fig.33 , Fig.34A and Fig.34B As shown, a third IC chip 104c including an ASIC 502 is formed.

[0165] Focus on Fig.33 3300, a plurality of transistors 504 are formed on a third semiconductor substrate 1704. The transistors 504 are located on the front side of the third semiconductor substrate 1704 and are laterally separated from each other by isolation structures 1706. The isolation structures 1706 can be or include, for example, an STI structure or some other suitable isolation structure. In addition, the transistors 504 include a separate gate electrode 1708, a separate gate dielectric layer 1710, a separate sidewall spacer structure 1712, a separate source / drain region 1714 pair, and a separate channel 1716.

[0166] The gate electrodes 1708 are stacked with gate dielectric layers 1710, respectively, which separate the gate electrodes 1708 from the third semiconductor substrate 1704. Sidewall spacer structures 1712 are dielectric and are respectively located on the sidewalls of the gate electrodes 1708. Pairs of source / drain regions 1714 are located in the third semiconductor substrate 1704. In addition, the source / drain regions of each pair of source / drain regions 1714 are separated by a corresponding one of the channels 1716.

[0167] Focus on Fig.34A Cross-sectional view 3400A and Fig.34B 3400B, forming a third interconnect structure 1718 and a fourth bonding substructure 1726b. The third interconnect structure 1718 covers the transistor 504 and is electrically coupled to the transistor 504. The third interconnect structure 1718 includes a plurality of wires 1720 and a plurality of vias 1722 in an interconnect dielectric layer 1724. The wires 1720 and the vias 1722 are conductive and are grouped into a plurality of wire layers and a plurality of via layers that are alternately stacked to form a conductive path, respectively. The conductive path interconnects the transistors 504 to form an ASIC 502 and / or additional circuits.

[0168] The fourth bonding substructure 1726b is formed over and electrically coupled to the third interconnect structure 1718, and further includes a bonding pad 1732 and a bonding via 1736 in the bonding dielectric layer 1730. The bonding pad 1732 and the bonding dielectric layer 1730 form a common bonding surface facing away from the third interconnect structure 1718, and the bonding via 1736 extends from the bonding pad 1732 to the third interconnect structure 1718.

[0169] like Fig.35A Cross-sectional view of 3500A and Fig.35B As shown in the circuit diagram 3500B, Fig.32 The structure is flipped vertically and joined to the second joint interface 1728. Fig.34A and Fig.34B The third IC chip 104c is connected to the pixel sensor 102. The bonding electrically couples the pixel sensor 102 to the ASIC 502 and includes a metal-to-metal bonding and a dielectric-to-dielectric bonding. In addition, the first semiconductor substrate 1202 is thinned from the side opposite to the first interconnect structure 1220. For example, the thinning can be performed by CMP or the like.

[0170] Although FIG. 19A to FIG. 35B The invention is described with reference to a method, but it is to be understood that the structures shown in these figures are not limited to this method but can be independent of this method. FIG. 19A to FIG. 35B Although described as a series of actions, it should be understood that in other embodiments, the order of the actions may be changed. FIG. 19A to FIG. 35B A particular set of actions is shown and described, but some of the actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0171] refer to Fig.36 , provides FIG. 19A to FIG. 35B Block diagram 3600 of some embodiments of the method.

[0172] At block 3602, a first IC chip is provided that includes a first pixel portion of a pixel sensor, wherein the first pixel portion includes a PPD and a PPD transfer transistor. Fig.19A , Fig.19B and Fig. 20 At block 3602a, a PPD and a first floating diffusion node are formed in a first semiconductor substrate. For example, see Fig.19A and Fig.19B At block 3602b, a PPD pass transistor is formed on the first semiconductor substrate between the boundary of the PPD and the first floating diffusion node. For example, see Fig.19A and Fig.19B At block 3602c, a first interconnect structure is formed covering and electrically coupling the PPD transfer transistor and the first floating diffusion node. For example, see Fig. 20 .

[0173] At block 3604, a second IC chip is formed that includes a second pixel portion of the pixel sensor, wherein the second pixel portion includes a plurality of readout devices including a transistor capacitor, a capacitor transfer transistor, and a source follower transistor. Fig.21A , Fig.21B , Figure 22-Figure 26 , Fig.27A , Fig.27B , Fig.28 , Fig.29A and Fig.29B At block 3604a, a readout device is formed on a second semiconductor substrate. For example, see Fig.21A , Fig.21B , Figure 22-Figure 26 , Fig.27A , Fig.27B and Fig.28 At block 3604b, a second interconnect structure is formed overlying and electrically coupled to the readout device, wherein the gate of the source follower transistor is electrically coupled to the second floating diffusion node, and upon completion of the formation of the second interconnect structure, the transistor capacitor and the capacitor transfer transistor are electrically coupled in series from the second floating diffusion node. For example, see Fig.29A and Fig.29B .

[0174] At block 3606, the first and second IC chips are bonded together at a first bonding interface to electrically couple the transistor capacitor from the capacitor transfer transistor to the first floating diffusion node. Fig. 30A and Fig. 30B As described above, the transistor capacitor and capacitor transfer transistor isolate the second floating diffusion node from the parasitic capacitance at the first floating diffusion node and the long conductive path extending from the first floating diffusion node to the transistor capacitor. This improves the conversion gain of the source follower transistor, thereby improving pixel performance.

[0175] At block 3608, a TSV is formed that extends through the second semiconductor substrate to the second interconnect structure. Fig.31 .

[0176] At block 3610, a bonding substructure covering the TSV and electrically coupled to the TSV is formed on a side of the second semiconductor substrate opposite the second interconnect structure. Fig.32 .

[0177] At block 3612, a third IC chip is formed that includes an ASIC, wherein the ASIC includes a plurality of transistors on a third semiconductor substrate. Fig.33 , Fig.34A and Fig.34B .

[0178] At block 3614, the second and third IC chips are bonded together at a second bonding interface. Fig.35A and Fig.35B .

[0179] Although Fig.36 The block diagram 3600 is shown and described herein as a series of actions or events, but it should be understood that the order of these actions or events shown should not be interpreted as limiting. For example, some actions may occur in different orders and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, all of the actions shown may not be required to implement one or more aspects or embodiments described herein, and one or more actions described herein may be performed in one or more separate actions and / or stages.

[0180] refer to Figures 37 to 42B , provides FIG. 19A to FIG. 35B A series of views of some first alternative embodiments of the method of wherein the thicknesses of the first and second dielectric layers 2302, 2502 are swapped (changing Fig.23 and Fig.25 and Fig.37 and Fig.39 For example, the method can be performed to form Fig.17 The stacked CMOS image sensor shown or some other suitable stacked CCD image sensor.

[0181] The method comprises executing Fig.19A , Fig.19B and Fig. 20 The described actions are performed to form the first IC chip 104a. Fig.37 As shown in the cross-sectional view 3700, the execution of Fig.21A , Fig.21B , Fig. 22 and Fig.23 The described actions are performed to partially form the second IC chip 104b, except that the first dielectric layer 2302 is formed with a second dielectric thickness T d2 (See, for example, Fig.25 ) deposition.

[0182] like Fig.38 As shown in the cross-sectional view 3800 of FIG. 3800 , the first dielectric layer 2302 is patterned. The patterning is similar to Fig.24 However, the patterning does not form a single dielectric structure, but rather forms a plurality of dielectric structures 2402p that are independent of the well 1006 and respectively cover the well 1006. In addition, the patterning exposes portions of the second semiconductor substrate 1002 that are not covered by the dielectric structure 2402p. The patterning can be performed, for example, by a photolithography / etching process or by some other suitable patterning process.

[0183] like Fig.39 As shown in the cross-sectional view 3900 of FIG. 39, the second dielectric layer 2502 is deposited on the second semiconductor substrate 1002. Fig.25 In addition to the second dielectric layer 2502 having a first dielectric thickness T d1 (See, for example, Fig.23 In addition, the second dielectric layer 2502 is deposited by thermal oxidation or the like, so that its deposition on the dielectric structure 2402p is minimal.

[0184] like Fig.40 As shown in the cross-sectional view 4000 of , the conductive layer 2602 is deposited on the second dielectric layer 2502 and the dielectric structure 2402p. In some embodiments, planarization is further performed to planarize the top surface of the conductive layer 2602. For example, the planarization can be performed by CMP and / or by some other suitable planarization process.

[0185] like Fig.41A Cross-sectional view of 4100A and Fig.41B As shown in the top view layout diagram 4100B, the conductive layer 2602, the second dielectric layer 2502 and the dielectric structure 2402p are patterned. For example, Fig.41A The cross-sectional view 4100A can be taken along the line BB' in the top view layout view 4100B. In addition to the gate dielectric layer 1004 being formed by the dielectric structure 2402p, the gate dielectric layer 1004 of the transistor capacitor 112 is also formed by the second dielectric layer 2502. The patterning process is as follows Fig.27A and Fig.27B described.

[0186] like Fig.42A Cross-sectional view of 4200A and Fig.42B As shown in the circuit diagram 4200B, the execution of Fig.28 , Fig.29A , Fig.29B , Fig. 30A , Fig. 30B , Figure 31-Figure 33 , Fig.34A , Fig.34B , Fig.35A and Fig.35B Describes the actions to complete a stacked CMOS image sensor.

[0187] Although Figures 37 to 42B The invention is described with reference to a method, but it is to be understood that the structures shown in these figures are not limited to this method but can be independent of this method. Figures 37 to 42B Although described as a series of actions, it should be understood that in other embodiments, the order of the actions may be changed. Figures 37 to 42B A particular set of actions is shown and described, but some of the actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0188] refer to FIG. 43A to FIG. 46B , provides FIG. 19A to FIG. 35B A series of views of some second alternative embodiments of the method of wherein the layout of the second pixel portion 102b is different (the Fig.21A and Fig.21B and Fig.43A and Fig.43B For example, the method can be performed to form Fig.18 The stacked CMOS image sensor shown or some other suitable stacked CCD image sensor.

[0189] The method comprises executing Fig.19A , Fig.19B and Fig. 20 The described actions are performed to form the first IC chip 104a. Fig.43A Cross-sectional view of 4300A and Fig.43B As shown in the top view layout diagram 4300B, the execution of Fig.21A and Fig.21B The described actions are to form the isolation structure 906. However, Fig.21A and Fig.21B In contrast, the isolation structure 906 has a different layout. For example, the cross-sectional view 4300A may be taken along the line EE' in the top view layout view 4300B.

[0190] The isolation structure 906 surrounds and defines the first active semiconductor region 902, the second active semiconductor region 904, and the third active semiconductor region 1302. The first active semiconductor region 902 and the third active semiconductor region 1302 are laterally elongated in a first dimension. The second active semiconductor region 904 is located on a common side of the first and third active semiconductor regions 902, 1302 and is laterally elongated in a second dimension orthogonal to the first dimension.

[0191] like Fig.44A Cross-sectional view of 4400A and Fig.44B As shown in the top view layout diagram 4400B, the execution of Figure 22-Figure 26 , Fig.27A and Fig.27B The described actions are performed to form multiple readout devices. However, the readout devices are formed in a different layout. The capacitor transfer transistor 114 and the LOFIC transistor 122 no longer share one of the source / drain regions 1012 corresponding to the second floating diffusion node FD2.

[0192] like Fig.45A Cross-sectional view of 4500A and Fig.45B As shown in the circuit diagram 4500B, the implementation of Fig.28 , Fig.29A and Fig.29B The actions described above are performed to form the sidewall spacer structure 1010, the second interconnect structure 1014 and the second bonding substructure 1230b. The second interconnect structure 1014 is similar to Fig.29A , except that it has a different wiring and via arrangement to electrically couple the second floating diffusion node FD2 to the gate electrode 908 of the source follower transistor 116 and the source / drain region 1012 of the LOFIC transistor 122 .

[0193] like Fig.46A Cross-sectional view of 4600A and Fig.46B As shown in the circuit diagram 4600B, the implementation of Fig. 30A , Fig. 30B , Figure 31-Figure 33 , Fig.34A , Fig.34B , Fig.35A and Fig.35B Describes the actions to complete a stacked CMOS image sensor.

[0194] Although FIG. 43A to FIG. 46B The invention is described with reference to a method, but it is to be understood that the structures shown in these figures are not limited to this method but can be independent of this method. FIG. 43A to FIG. 46B Although described as a series of actions, it should be understood that in other embodiments, the order of the actions may be changed. FIG. 43A to FIG. 46B A particular set of actions is shown and described, but some of the actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0195] In view of the foregoing, various embodiments of the present disclosure are directed to a stacked CMOS image sensor, including a pixel sensor for HCG and a method of forming the same.

[0196] In some embodiments, the present invention provides an image sensor, comprising: a first IC chip; a second IC chip stacked with the first IC chip; and a pixel sensor spanning the first IC chip and the second IC chip, wherein the pixel sensor comprises a first transfer transistor and a photodetector located at the first IC chip, and further comprises a source follower transistor, a transistor capacitor, and a second transfer transistor located at the second IC chip; wherein the transistor capacitor and the second transfer transistor are electrically coupled in series from the source / drain region of the first transfer transistor to the gate electrode of the source follower transistor. In some embodiments, the transistor capacitor is electrically connected between the source / drain region and the second transfer transistor. In some embodiments, the transistor capacitor comprises a gate electrode, a first side, and a second side opposite to the first side, and is electrically coupled to the source / drain region on the first side, and is electrically coupled to the second transfer transistor on the second side, and wherein the gate electrode of the transistor capacitor has a first thickness on the first side and a second thickness greater than the first thickness on the second side. In some embodiments, the second side of the transistor capacitor faces the second transfer transistor. In some embodiments, the pixel sensor further comprises an additional transistor, wherein the second IC chip comprises a semiconductor substrate and a trench isolation structure, the trench isolation structure defining a first active semiconductor region in the semiconductor substrate, the transistor capacitor, the second transfer transistor, and the additional transistor being arranged on the first active semiconductor region, and wherein the additional transistor and the second transfer transistor share a common source / drain region. In some embodiments, the trench isolation structure defines a second semiconductor active region in the semiconductor substrate, and the source follower transistor is arranged on the second active region, and wherein the second active semiconductor region is separated from the first active semiconductor region. In some embodiments, the transistor capacitor and the second transfer transistor share a sidewall spacer structure, the sidewall spacer structure being located between the transistor capacitor and the second transfer transistor, and being located on corresponding gate electrode sidewalls of the transistor capacitor and the second transfer transistor.

[0197] In some embodiments, the present invention provides an image sensor, comprising: a first substrate; a first pixel portion, located on the first substrate, and comprising a photodetector; a second substrate, located below the first substrate; and a second pixel portion, located on the second substrate, and comprising a source follower transistor and a transistor capacitor, wherein the transistor capacitor electrically isolates the gate electrode of the source follower transistor from the first pixel portion, and wherein the transistor capacitor has a gate dielectric layer having a stepped profile; wherein the first pixel portion and the second pixel portion form a common pixel sensor. In some embodiments. The gate dielectric layer has a first thickness on a first side of the transistor capacitor electrically coupled to the first pixel portion, and has a second thickness less than the first thickness on a second side of the transistor capacitor opposite to the first side. In some embodiments, the second pixel portion also includes a transfer transistor electrically coupled from the gate electrode of the source follower transistor to the second side of the transistor capacitor. In some embodiments, the image sensor also includes: a trench isolation structure, located in the second substrate, and defining a first active semiconductor region and a second active semiconductor region separated from the first active semiconductor region, wherein the transistor capacitor is located on the first active semiconductor region, and wherein the source follower transistor is located on the second active semiconductor region. In some embodiments, the first active semiconductor region has a top-view geometry that is substantially L-shaped. In some embodiments, the trench isolation structure defines a third active semiconductor region spaced apart from the first active semiconductor region and the second active semiconductor region, and wherein the second pixel portion includes a reset transistor located on the third active semiconductor region. In some embodiments, the first pixel portion further includes a transfer transistor configured to selectively transfer photogenerated charge from the photodetector to a first floating diffusion node, the first floating diffusion node being electrically coupled to a source / drain region of the transistor capacitor.

[0198] In some embodiments, the present disclosure provides a method of forming an image sensor, the method comprising: forming a first integrated circuit (IC) chip including a first pixel portion, wherein the first pixel portion includes a photodetector and a first transfer transistor electrically coupled from the photodetector to a first node; forming a second IC chip including a second pixel portion, wherein the second pixel portion includes a source follower transistor, a transistor capacitor, and a second transfer transistor, and wherein a gate electrode of the source follower transistor is electrically coupled to the second node; and bonding the first IC chip and the second IC chip together to electrically couple the first pixel portion and the second pixel portion into a pixel sensor; wherein after bonding, the second transfer transistor and the transistor capacitor are electrically coupled in series from the first node to the second node. In some embodiments, bonding comprises metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the formation of the second IC chip includes: depositing a first dielectric layer over the substrate; patterning the first dielectric layer to form a dielectric structure and laterally exposing the substrate outside the dielectric structure; depositing a second dielectric layer on the exposed portion of the substrate; depositing a conductive layer covering the second dielectric layer; and patterning the second dielectric layer and the conductive layer to form a gate dielectric layer and a gate electrode, respectively, the gate electrode corresponding to the transistor capacitor and covering a portion of the dielectric structure and the second dielectric layer that together form the gate dielectric layer. In some embodiments, the thickness of the second dielectric layer is less than the thickness of the first dielectric layer. In some embodiments, the second dielectric layer is deposited on the exposed portion of the substrate before being deposited on the dielectric structure. In some embodiments, the method also includes: forming a third IC chip including an ASIC; and bonding the second chip and the third IC chip together so that the second IC chip is located between the first IC chip and the third IC chip, and so that the ASIC is electrically coupled to the pixel sensor.

[0199] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensor, comprising: a first integrated circuit chip; a second integrated circuit chip, stacked with the first integrated circuit chip; as well as a pixel sensor spanning the first integrated circuit chip and the second integrated circuit chip, wherein the pixel sensor includes a first transfer transistor and a photodetector located at the first integrated circuit chip, and further includes a source follower transistor, a transistor capacitor, and a second transfer transistor located at the second integrated circuit chip; Wherein the transistor capacitor and the second transfer transistor are electrically coupled in series from a source / drain region of the first transfer transistor to a gate electrode of the source follower transistor.

2. The image sensor according to claim 1, wherein: The transistor capacitor is electrically connected between the source / drain region and the second pass transistor.

3. The image sensor according to claim 1, wherein: The transistor capacitor comprises a gate electrode, a first side and a second side opposite to the first side, and is electrically coupled to the source / drain region on the first side and is electrically coupled to the second pass transistor on the second side, and wherein the gate electrode of the transistor capacitor has a first thickness on the first side and a second thickness on the second side that is greater than the first thickness.

4. The image sensor according to claim 3, wherein: The second side of the transistor capacitor faces the second pass transistor.

5. The image sensor according to claim 1, wherein: The pixel sensor also includes an additional transistor, wherein the second integrated circuit chip includes a semiconductor substrate and a trench isolation structure, the trench isolation structure defines a first active semiconductor region in the semiconductor substrate, the transistor capacitor, the second transfer transistor and the additional transistor are arranged on the first active semiconductor region, and wherein the additional transistor and the second transfer transistor share a common source / drain region.

6. The image sensor according to claim 5, wherein: The trench isolation structure defines a second active semiconductor region in the semiconductor substrate, and the source follower transistor is arranged on the second active region, and wherein the second active semiconductor region is separated from the first active semiconductor region.

7. An image sensor, comprising: a first substrate; A first pixel portion, located on the first substrate and comprising a photodetector; a second substrate, located below the first substrate; as well as a second pixel portion disposed on the second substrate and comprising a source follower transistor and a transistor capacitor, wherein the transistor capacitor electrically isolates a gate electrode of the source follower transistor from the first pixel portion, and wherein the transistor capacitor has a gate dielectric layer having a stepped profile; Wherein, the first pixel portion and the second pixel portion form a common pixel sensor.

8. The image sensor according to claim 7, wherein: The gate dielectric layer has a first thickness on a first side of the transistor capacitor electrically coupled to the first pixel portion and has a second thickness less than the first thickness on a second side of the transistor capacitor opposite the first side.

9. The image sensor according to claim 8, wherein: The second pixel portion also includes a transfer transistor electrically coupled from a gate electrode of the source follower transistor to a second side of the transistor capacitor.

10. A method of forming an image sensor, the method comprising: forming a first integrated circuit chip including a first pixel portion, wherein the first pixel portion includes a photodetector and a first transfer transistor electrically coupled from the photodetector to a first node; forming a second integrated circuit chip including a second pixel portion, wherein the second pixel portion includes a source follower transistor, a transistor capacitor, and a second transfer transistor, and wherein a gate electrode of the source follower transistor is electrically coupled to a second node; and bonding the first integrated circuit chip and the second integrated circuit chip together to electrically couple the first pixel portion and the second pixel portion into a pixel sensor; wherein, after joining, the second pass transistor and the transistor capacitor are electrically coupled in series from the first node to the second node.

Images