Display panel and display device

Abstract

The embodiment of the invention discloses a display panel and a display device, a first pole plate and a second pole plate of a first capacitor are respectively located on a first conductive layer and a second conductive layer, and an active layer is located on one side, far away from a substrate, of the second conductive layer, so that the first capacitor is located below a first driving transistor or a second driving transistor; the first pole plate or the second pole plate of the first capacitor can perform bottom shading on the first driving transistor or the second driving transistor, the influence of illumination on the electrical performance of the driving transistor is improved, and the display effect is improved. A second pole plate of the first capacitor is connected with a driving grid of a first driving transistor and a driving grid of a second driving transistor in the pixel circuit, the first driving transistor and the second driving transistor are connected in parallel, and the driving grid of the first driving transistor and the driving grid of the second driving transistor are located on different sides of the active layer; the display uniformity of the low-gray-scale picture of the display panel is good, and the maximum brightness of the display panel is high.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, users' requirements for picture display effects are getting higher and higher.

[0003] Existing display panels have the problem of poor display effects, which affects user experience. Summary of the invention

[0004] The present invention provides a display panel and a display device to improve the display effect of the display panel and enhance the user experience.

[0005] According to one aspect of the present invention, there is provided a display panel, comprising:

[0006] substrate;

[0007] An active layer and a plurality of conductive layers are stacked on one side of the substrate, wherein a plurality of pixel circuits are formed in the active layer and the conductive layer; the pixel circuit comprises a first driving transistor, a second driving transistor and a first capacitor; the first driving transistor and the second driving transistor are connected in parallel;

[0008] The multi-layer conductive layer comprises a first conductive layer and a second conductive layer, the second conductive layer is located on a side of the first conductive layer away from the substrate; the first electrode plate of the first capacitor is located in the first conductive layer, the second electrode plate of the first capacitor is located in the second conductive layer, and the second electrode plate of the first capacitor is connected to the driving gate of the first driving transistor and the driving gate of the second driving transistor; along the thickness direction of the display panel, the driving gate of the first driving transistor and the driving gate of the second driving transistor are located on different sides of the active layer;

[0009] The active layer is located on a side of the second conductive layer away from the substrate.

[0010] According to another aspect of the present invention, a display device is provided, comprising the display panel according to any embodiment of the present invention.

[0011] The display panel and display device of the embodiment of the present invention include a first conductive layer and a second conductive layer through a stacked multilayer conductive layer, the first electrode plate and the second electrode plate of the first capacitor are respectively located in the first conductive layer and the second conductive layer, and the active layer is located on the side of the second conductive layer away from the substrate, so that the first capacitor is located below the first drive transistor or the second drive transistor, so that the first electrode plate or the second electrode plate of the first capacitor can perform bottom light shielding on the first drive transistor or the second drive transistor, which is conducive to improving the influence of light on the electrical performance of the drive transistor and improving the display effect. The second electrode plate of the first capacitor is connected to the drive gate of the first drive transistor and the drive gate of the second drive transistor in the pixel circuit, and the first drive transistor and the second drive transistor are connected in parallel. Along the thickness direction of the display panel, the drive gate of the first drive transistor and the drive gate of the second drive transistor are located on different sides of the active layer, so that the display uniformity of the low grayscale picture of the display panel is good and the maximum brightness of the display panel is high. In this way, the display effect of the display panel is further improved through the structure of the first drive transistor and the second drive transistor in parallel.

[0012] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 is a top view of a display panel provided by an embodiment of the present invention;

[0015] Figure 2 is a cross-sectional view of a display panel provided by an embodiment of the present invention;

[0016] Figure 3 is a cross-sectional view of another display panel provided by an embodiment of the present invention;

[0017] Figure 4 is a top view of another display panel provided by an embodiment of the present invention;

[0018] Figure 5 is a cross-sectional view of another display panel provided by an embodiment of the present invention;

[0019] Figure 6 is a cross-sectional view of another display panel provided by an embodiment of the present invention;

[0020] Figure 7 is a cross-sectional view of another display panel provided by an embodiment of the present invention;

[0021] Figure 8 is a cross-sectional view of another display panel provided by an embodiment of the present invention;

[0022] Fig. 9 is a top view of another display panel provided by an embodiment of the present invention;

[0023] Fig.10 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0024] Fig.11 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0025] Fig.12 yes Fig.11 A schematic structural diagram of the first conductive layer;

[0026] Fig.13 yes Fig.11 A schematic structural diagram of a first conductive layer and a second conductive layer;

[0027] Fig.14 yes Fig.11 A schematic structural diagram of the first conductive layer, the second conductive layer, the active layer and the third conductive layer;

[0028] Fig.15 yes Fig.11 A schematic diagram of the structure of the first conductive layer, the second conductive layer, the active layer, the third conductive layer and the first type of via hole;

[0029] Fig.16 yes Fig.11 A schematic structural diagram of a first conductive layer, a second conductive layer, an active layer, a third conductive layer, a first type of via hole, and a second type of via hole;

[0030] Fig.17 yes Fig.11 A schematic structural diagram of a first conductive layer, a second conductive layer, an active layer, a third conductive layer, a first type of via, a second type of via and a fourth conductive layer;

[0031] Fig.18 yes Fig.11 A schematic structural diagram of the first conductive layer, the second conductive layer, the active layer, the third conductive layer and the fifth conductive layer;

[0032] Fig.19 yes Fig.11 A schematic structural diagram of the second conductive layer, the active layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer;

[0033] Fig. 20 is a cross-sectional view of another display panel provided by an embodiment of the present invention;

[0034] Fig.21 is a cross-sectional view of another display panel provided by an embodiment of the present invention;

[0035] Fig. 22 is a cross-sectional view of another display panel provided by an embodiment of the present invention;

[0036] Fig.23 is a cross-sectional view of another display panel provided by an embodiment of the present invention;

[0037] Fig.24 is a cross-sectional view of another display panel provided by an embodiment of the present invention;

[0038] Fig.25 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0039] Fig.26 is a working timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0040] Fig. 27 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] Figure 1is a top view of a display panel provided by an embodiment of the present invention, Figure 2 is a cross-sectional view of a display panel provided by an embodiment of the present invention, Figure 3 is a cross-sectional view of another display panel provided by an embodiment of the present invention, wherein Figure 2 Can correspond Figure 1 Cut along AA' to get: Figure 3 Can correspond Figure 1 Cut along BB', refer to Figure 1-Figure 3 The display panel includes a substrate 10; an active layer and a multi-layer conductive layer stacked on one side of the substrate 10, wherein a plurality of pixel circuits are formed in the active layer and the conductive layer; the pixel circuit includes a first driving transistor DT1, a second driving transistor DT2 and a first capacitor C1; the first driving transistor DT1 and the second driving transistor DT2 are connected in parallel; the multi-layer conductive layer includes a first conductive layer 31 and a second conductive layer 32, wherein the second conductive layer 32 is located on a side of the first conductive layer 31 away from the substrate 10; a first electrode plate 01 of the first capacitor C1 is located on the first conductive layer 31, a second electrode plate 02 of the first capacitor C1 is located on the second conductive layer 32, and the second electrode plate 02 of the first capacitor C1 is connected to a driving gate (referred to as the first driving gate G1) of the first driving transistor DT1 and a driving gate (referred to as the second driving gate G2) of the second driving transistor DT2; along the thickness direction z of the display panel, the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2 are located on different sides of the active layer; the active layer is located on a side of the second conductive layer 32 away from the substrate 10.

[0044] Specifically, the substrate 10 is used to provide protection and support for the display panel, wherein the substrate 10 may be a flexible substrate formed of materials such as polyimide (PI), polyethylene naphthalate (PEN) or polyethylene terephthalate (PET), or a hard substrate formed of materials such as glass. An active layer and a plurality of conductive layers are arranged on one side of the substrate 10, an insulating layer is arranged between the active layer and the adjacent conductive layer, and the plurality of conductive layers are isolated from each other by the insulating layer. A plurality of pixel circuits are formed in the active layer and the plurality of conductive layers, and the pixel circuits are used to drive the light-emitting elements in the display panel to emit light.

[0045] The pixel circuit includes a first driving transistor DT1 and a second driving transistor DT2 connected in parallel, wherein the first driving transistor DT1 and the second driving transistor DT2 are connected in parallel, that is, the first electrode of the first driving transistor DT1 is connected to the first electrode of the second driving transistor DT2, and the second electrode of the first driving transistor DT1 is connected to the second electrode of the second driving transistor DT2, wherein the first electrode is a source electrode and the second electrode is a drain electrode or the first electrode is a drain electrode and the second electrode is a source electrode. The first driving transistor DT1 and the second driving transistor DT2 respectively include driving gate electrodes, wherein the driving gate electrodes are gate electrodes to which data voltages are written, and the first driving transistor DT1 and the second driving transistor DT2 can respectively generate driving currents according to the data voltages of the driving gate electrodes, and the sum of the driving currents generated by the first driving transistor DT1 and the driving currents generated by the second driving transistor DT2 is used as the total driving current for driving the light-emitting device to emit light.

[0046] In this embodiment, along the thickness direction z of the display panel, the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2 are located on different sides of the active layer. In an optional embodiment, the first driving transistor DT1 is bottom gate driven (that is, the first driving transistor DT1 includes a bottom gate located on the side of the active layer close to the substrate 10, and the bottom gate of the first driving transistor DT1 serves as the driving gate of the first driving transistor DT1), and the second driving transistor DT2 is top gate driven (that is, the second driving transistor DT2 includes a top gate located on the side of the active layer away from the substrate 10, and the top gate of the second driving transistor DT2 serves as the driving gate of the second driving transistor DT2); or the first driving transistor DT1 is top gate driven (that is, the first driving transistor DT1 includes a top gate located on the side of the active layer away from the substrate 10, and the top gate of the first driving transistor DT1 serves as the driving gate of the first driving transistor DT1), and the second driving transistor DT2 is bottom gate driven (that is, the second driving transistor DT2 includes a bottom gate located on the side of the active layer close to the substrate 10, and the bottom gate of the second driving transistor DT2 serves as the driving gate of the second driving transistor DT2). The subthreshold swing of the bottom-gate driven transistor is large, which is beneficial to improving the display uniformity of low grayscale images; the subthreshold swing of the top-gate driven transistor is small, which is beneficial to increasing the driving current and improving the maximum brightness of the display. In this way, the structure of the first driving transistor DT1 and the second driving transistor DT2 in parallel is beneficial to improving the display effect of the display panel. In some embodiments, the first driving transistor DT1 and the second driving transistor DT2 can be single-gate devices; in other embodiments, the first driving transistor DT1 and the second driving transistor DT2 are dual-gate devices; in other optional embodiments of the present invention, one of the first driving transistor DT1 and the second driving transistor DT2 is a single-gate device, and the other is a dual-gate device.

[0047] In this embodiment, the pixel circuit further includes a first capacitor C1, and the first plate 01 and the second plate 02 of the first capacitor C1 in the pixel circuit are respectively located in the first conductive layer 31 and the second conductive layer 32, and the second plate 02 of the first capacitor C1 is connected to the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2, and the first capacitor C1 can store the voltage of the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2. In some optional embodiments, the second plate 02 of the first capacitor C1 can be used as the driving gate of the first driving transistor DT1 or the driving gate of the second driving transistor DT2; in other optional embodiments, the second plate 02 of the first capacitor C1 can be separately set with the driving gate of the first driving transistor DT1, and the second plate 02 of the first capacitor C1 is connected to the driving gate of the first driving transistor DT1 by means of vias and / or jumpers. Similarly, the second plate 02 of the first capacitor C1 can be separately set with the driving gate of the second driving transistor DT2, and the second plate 02 of the first capacitor C1 is connected to the driving gate of the second driving transistor DT2 by means of vias and / or jumpers.

[0048] The pixel circuit includes transistor elements including the first driving transistor DT1 and the second driving transistor DT2. Since the channel region of the transistor element located in the active layer is sensitive to light, light irradiating the channel region of the transistor element will affect the electrical performance of the transistor element. In this embodiment, the active layer is located on the side of the second conductive layer 32 away from the substrate 10, so that the first plate 01 or the second plate of the first capacitor C1 is located below the first driving transistor DT1 or the second driving transistor DT2, so that the first plate 01 or the second plate 02 of the first capacitor C1 can shield the first driving transistor DT1 or the second driving transistor DT2 from the bottom, which is conducive to improving the influence of light on the electrical performance of the driving transistor and further improving the display effect.

[0049] Optionally, the material of the active layer includes metal oxide, which is beneficial to reducing leakage current of the pixel circuit.

[0050] The display panel of this embodiment includes a first conductive layer and a second conductive layer through a stacked multilayer conductive layer, the first electrode plate and the second electrode plate of the first capacitor are respectively located in the first conductive layer and the second conductive layer, and the active layer is located on the side of the second conductive layer away from the substrate, so that the first capacitor is located below the first drive transistor or the second drive transistor, so that the first electrode plate or the second electrode plate of the first capacitor can perform bottom light shielding on the first drive transistor or the second drive transistor, which is conducive to improving the influence of light on the electrical performance of the drive transistor and improving the display effect. The second electrode plate of the first capacitor is connected to the drive gate of the first drive transistor and the drive gate of the second drive transistor in the pixel circuit, and the first drive transistor and the second drive transistor are connected in parallel. Along the thickness direction of the display panel, the drive gate of the first drive transistor and the drive gate of the second drive transistor are located on different sides of the active layer, so that the display uniformity of the low grayscale picture of the display panel is good and the maximum brightness of the display panel is high. In this way, the display effect of the display panel is further improved through the structure of the first drive transistor and the second drive transistor in parallel.

[0051] Figure 4 is a top view of another display panel provided by an embodiment of the present invention, Figure 5 is a cross-sectional view of another display panel provided by an embodiment of the present invention, Figure 6 is a cross-sectional view of another display panel provided by an embodiment of the present invention, Figure 7 is a cross-sectional view of another display panel provided by an embodiment of the present invention, Figure 8 is a cross-sectional view of another display panel provided by an embodiment of the present invention, wherein: Figure 5 Can correspond Figure 4 Cut along CC' to get, Figure 6 Can correspond Figure 4 Cut along DD' to get, Figure 7 Can correspond Figure 4 Cut along EE' to get, Figure 8 Can correspond Figure 4 Cut along FF', reference Figure 1-Figure 8 Optionally, the active layer includes a first active layer 21 , and the channel region of the first driving transistor DT1 and the channel region of the second driving transistor DT2 are located in the first active layer 21 .

[0052] The orthographic projection of the driving gate (first driving gate G1) of the first driving transistor DT1 on the substrate 10 at least partially overlaps with the orthographic projection of the channel region of the first driving transistor DT1 on the substrate 10, and the orthographic projection of the driving gate (second driving gate G2) of the second driving transistor DT2 on the substrate 10 at least partially overlaps with the orthographic projection of the channel region of the second driving transistor DT2 on the substrate 10. The channel region of the first driving transistor DT1 is located in the first active layer 21, and the source region and the drain region of the first driving transistor DT1 are respectively located on both sides of the channel region of the first driving transistor DT1, that is, the first electrode and the second electrode of the first driving transistor DT1 are respectively located on both sides of the channel region of the first driving transistor DT1; the channel region of the second driving transistor DT2 is located in the first active layer 21, and the source region and the drain region of the second driving transistor DT2 are respectively located on both sides of the channel region of the second driving transistor DT2, that is, the first electrode and the second electrode of the second driving transistor DT2 are located on both sides of the channel region of the second driving transistor DT2. The channel region of the first driving transistor DT1 and the channel region of the second driving transistor DT2 are located in the same layer, so that the source of the first driving transistor DT1 and the source of the second driving transistor DT2 can be connected in the first active layer 21, and the drain of the first driving transistor DT1 and the drain of the second driving transistor DT2 can also be connected in the first active layer 21, so that the parallel connection of the first driving transistor DT1 and the second driving transistor DT2 is realized in the first active layer 21, and the parallel connection of the first driving transistor DT1 and the second driving transistor DT2 can be realized without vias and / or jumpers, which simplifies the preparation process of the display panel, simplifies the layout structure of the display panel, and is conducive to improving the pixel density.

[0053] Continue to refer Figure 4-Figure 8 Optionally, the first driving transistor DT1 includes a first gate and a second gate G3, the first gate is located on the side of the active layer close to the substrate 10, and the second gate G3 is located on the side of the active layer away from the substrate 10; the orthographic projections of the first gate and the second gate G3 on the substrate 10 at least partially cover the orthographic projections of the channel region of the first driving transistor DT1 on the substrate 10; the first gate serves as the driving gate of the first driving transistor DT1, that is, the first gate serves as the first driving gate G1. Optionally, the display panel further includes a third conductive layer 33, the third conductive layer 33 is located on the side of the active layer away from the substrate 10, and the second gate G3 is located on the third conductive layer 33.

[0054] The first gate serves as the bottom gate of the first driving transistor DT1, and the second gate G3 serves as the top gate of the first driving transistor DT1. The bottom gate serves as the driving gate of the first driving transistor DT1. The orthographic projections of the first gate and the second gate G3 on the substrate 10 at least partially cover the orthographic projections of the channel region of the first driving transistor DT1 on the substrate 10, so that the first gate and the second gate G3 can respectively shield the bottom and top of the channel region of the first driving transistor DT1, thereby improving the influence of light on the electrical performance of the first driving transistor DT1. By setting the first driving transistor DT1 as a dual-gate structure, the control ability of the gate over the channel region can be enhanced, and the bottom gate driving method is conducive to improving the subthreshold swing of the first driving transistor DT1, which is conducive to grayscale development and improving the uniformity of display brightness. On the first active layer 21, the area covered by the second gate G3 of the first driving transistor DT1 serves as the channel region of the first driving transistor DT1.

[0055] Optionally, the second gate G3 of the first driving transistor DT1 is connected to the first electrode of the first driving transistor DT1 , so as to ensure that the threshold voltage of the first driving transistor DT1 will not be affected by the voltage of the second gate G3 .

[0056] Continue to refer Figure 4-Figure 8 The second driving transistor DT2 includes a third gate G4 and a fourth gate, the third gate G4 is located on a side of the active layer close to the substrate 10, and the fourth gate is located on a side of the active layer away from the substrate 10; the orthographic projections of the third gate G4 and the fourth gate on the substrate 10 at least partially cover the orthographic projection of the channel region of the second driving transistor DT2 on the substrate 10; the fourth gate serves as the driving gate of the second driving transistor DT2, that is, the fourth gate serves as the second driving gate G2.

[0057] The third gate G4 serves as the bottom gate of the second driving transistor DT2, and the fourth gate serves as the top gate of the second driving transistor DT2. The top gate serves as the driving gate of the second driving transistor DT2. The positive projection of the third gate G4 on the substrate 10 at least partially covers the positive projection of the channel region of the second driving transistor DT2 on the substrate 10, so that the third gate G4 and the fourth gate can respectively shield the bottom and top of the channel region of the second driving transistor DT2, improve the influence of light on the electrical performance of the second driving transistor DT2, and enhance the display effect. By setting the second driving transistor DT2 as a dual-gate structure, the control ability of the gate over the channel region can be enhanced, and the top gate driving method makes the subthreshold swing of the second driving transistor DT2 smaller, which is conducive to increasing the driving current, thereby increasing the maximum brightness of the light-emitting device. On the first active layer 21, the area covered by the fourth gate of the second driving transistor DT2 serves as the channel region of the second driving transistor DT2.

[0058] Optionally, the length of the channel region of the second driving transistor DT2 is smaller than the length of the channel region of the first driving transistor DT1; in this way, the threshold voltage of the second driving transistor DT2 can be close to the threshold voltage of the first driving transistor DT1, so that when the pixel circuit includes a threshold voltage compensation module, the threshold voltage compensation effect of the first driving transistor DT1 and the second driving transistor DT2 is good, thereby improving the display effect of the display panel.

[0059] Optionally, the third gate G4 of the second driving transistor DT2 is connected to the first electrode of the second driving transistor DT2; in this way, it can be ensured that the threshold voltage of the second driving transistor DT2 will not be affected by the voltage of the third gate G4.

[0060] In some embodiments, the third gate G4 is located in the second conductive layer 32. In some embodiments, the fourth gate is located in the third conductive layer 33.

[0061] Continue to refer Figure 1-Figure 8 Optionally, the first active layer 21 includes a first active portion 211 , the first active portion 211 extends along the first direction x, and the channel region of the first driving transistor DT1 is located in the first active portion 211 .

[0062] On the first active portion 211, the area covered by the second gate G3 of the first driving transistor DT1 serves as the channel region of the first driving transistor DT1, the first end of the first active portion 211 serves as the source of the first driving transistor DT1, and the second end of the first active portion 211 serves as the drain of the first driving transistor DT1. Along the first direction x, the first end and the second end of the first active portion 211 are located on both sides of the channel region of the first driving transistor DT1.

[0063] Optionally, the first active layer 21 includes a second active portion 212 , and the second active portion 212 extends along the first direction x; the channel region of the second driving transistor DT2 is located in the second active portion 212 .

[0064] On the second active portion 212, the area covered by the fourth gate of the second driving transistor DT2 serves as the channel region of the second driving transistor DT2, the first end of the second active portion 212 serves as the source of the second driving transistor DT2, and the second end of the second active portion 212 serves as the drain of the second driving transistor DT2. Along the first direction x, the first end and the second end of the second active portion 212 are located on both sides of the channel region of the second driving transistor DT2.

[0065] The first active layer 21 further includes a third active portion 213 and a fourth active portion 214, the third active portion 213 and the fourth active portion 214 extend along the second direction y, respectively, and the second direction y intersects the first direction x; the third active portion 213 connects the first end of the first active portion 211 and the first end of the second active portion 212, respectively; the fourth active portion 214 connects the second end of the first active portion 211 and the second end of the second active portion 212, respectively. In this way, in the first active layer 21, the source of the first driving transistor DT1 and the second driving transistor DT2 are connected through the third active portion 213, and the drain of the first driving transistor DT1 and the second driving transistor DT2 are connected through the fourth active portion 214, thereby realizing the parallel connection of the first driving transistor DT1 and the second driving transistor DT2 in the first active layer 21.

[0066] Continue to refer Figure 1-Figure 8 Optionally, the second plate 02 of the first capacitor C1 serves as the driving gate of the first driving transistor DT1. In this way, the second plate 02 of the first capacitor C1 and the driving gate of the first driving transistor DT1 do not need to be connected through a via or a jumper, which simplifies the structure of the display panel and helps to improve the pixel density. Optionally, the orthographic projection of the first plate 01 of the first capacitor C1 on the substrate 10 overlaps at least partially with the orthographic projection of the second plate 02 of the first capacitor C1 on the substrate 10, and the overlapping area of ​​the two constitutes the effective capacitance of the first capacitor C1. In some embodiments, the orthographic projection of the first plate 01 of the first capacitor C1 on the substrate 10 covers the orthographic projection of the second plate 02 of the first capacitor C1 on the substrate 10.

[0067] Optionally, the orthographic projection of the second electrode 02 of the first capacitor C1 on the substrate 10 at least partially covers the orthographic projection of the channel region of the first driving transistor DT1 on the substrate 10, that is, the driving gate of the first driving transistor DT1 is overlapped with the channel region of the first driving transistor DT1, so that the second electrode 02 of the first capacitor C1 can serve as the upper electrode of the first capacitor C1, and can also shield the bottom of the first driving transistor DT1, thereby improving the influence of light on the electrical performance of the first driving transistor DT1.

[0068] Optionally, the orthographic projection of the first electrode 01 of the first capacitor C1 on the substrate 10 at least partially covers the orthographic projection of the channel region of the first driving transistor DT1 on the substrate 10; in this way, the first electrode located on the first conductive layer 31 can serve as both the lower electrode of the first capacitor C1 and the light-shielding layer of the driving transistor, which can save layout space and improve layout space utilization. At the same time, it can also avoid changes in the electrical performance of the driving transistor caused by light, which is beneficial to improving the reliability of the pixel circuit and thus improving the reliability of the screen.

[0069] Continue to refer Figure 1-Figure 8Optionally, the display panel further includes a first connection line L1, a first end of the first connection line L1 is electrically connected to the driving gate of the first driving transistor DT1 through a first type via K1, and a second end of the first connection line L1 is electrically connected to the driving gate of the second driving transistor DT2 through a second type via K2.

[0070] The orthographic projection of the first connection line L1 on the substrate 10 at least partially overlaps with the orthographic projection of the driving gate of the first driving transistor DT1 on the substrate 10, and the orthographic projection of the first connection line L1 on the substrate 10 at least partially overlaps with the orthographic projection of the driving gate of the second driving transistor DT2 on the substrate 10, so that the first connection line L1 can be connected to the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2 through vias, respectively, to achieve electrical connection between the two. By connecting the gate of the first driving transistor DT1 and the gate of the second driving transistor DT2 through the first connection line L1, the layout space occupied by the first driving transistor DT1 and the second driving transistor DT2 can be reduced, and the pixel density can be improved.

[0071] Optionally, the display panel further includes a fourth conductive layer 34, which is located on a side of the third conductive layer 33 away from the substrate 10, and the first connecting line L1 is located in the fourth conductive layer 34. An interlayer insulating layer 140 is provided between the third conductive layer 33 and the fourth conductive layer 34, a second gate insulating layer 130 is provided between the third conductive layer 33 and the active layer, a first gate insulating layer 120 is provided between the active layer and the second conductive layer 32, and a first type via K1 connecting the first end of the first connecting line L1 and the driving gate of the first driving transistor DT1 penetrates the interlayer insulating layer 140, the second gate insulating layer 130 and the first gate insulating layer 120. A second type via K2 connecting the second end of the first connecting line L1 and the driving gate of the second driving transistor DT2 penetrates the interlayer insulating layer 140. Optionally, the resistivity of the fourth conductive layer 40 is less than the resistivity of the third conductive layer 33.

[0072] Fig. 9 is a top view of another display panel provided by an embodiment of the present invention, referring to Fig. 9, Optionally, the display panel further includes a power line VDD, and the orthographic projection of the power line VDD on the substrate 10 does not overlap or partially overlaps with the orthographic projection of the first connection line L1 on the substrate 10. Specifically, when the orthographic projection of the power line VDD on the substrate 10 overlaps with the orthographic projection of the first connection line L1 on the substrate 10, there is a facing area between the power line VDD and the first connection line L1, and a parasitic capacitor is formed between the two. Since the first connection line L1 is respectively connected to the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2, the larger the parasitic capacitance formed between the first connection line L1 and the power line VDD, the greater the influence of the parasitic capacitance on the voltage of the driving gate of the first driving transistor DT1 and the second driving transistor DT2, which is not conducive to the improvement of the display effect. In some embodiments, it is set that the orthographic projection of the power line VDD on the substrate 10 does not overlap with the orthographic projection of the first connection line L1 on the substrate 10, that is, the facing area of ​​the power line VDD and the first connection line L1 is 0, so that there is no parasitic capacitance between the two, thereby improving the display effect. In other embodiments, the orthographic projection of the power line VDD on the substrate 10 is partially overlapped with the orthographic projection of the first connection line L1 on the substrate 10 instead of completely overlapped, which can also reduce the parasitic capacitance between the two and help improve the display effect.

[0073] Optionally, the power line VDD includes a first sub-power line VDD1 extending along the second direction y, and the orthographic projection of the first sub-power line VDD1 on the substrate 10 does not overlap or partially overlaps with the first connection line L1. The extension of the first sub-power line VDD1 along the first direction x includes the first sub-power line VDD1 extending in a straight line, a folded line, or a curve, or a combination of at least two of them.

[0074] Continue to refer Figure 4-Figure 9 Optionally, the display panel further includes a second connection line L2, a first end of the second connection line L2 is electrically connected to the second gate G3 of the first driving transistor DT1 through the second type via K2, a second end of the second connection line L2 is electrically connected to the third gate G4 of the second driving transistor DT2 through the first type via K1, a third end of the second connection line L2 is connected to the first electrode of the first driving transistor DT1 and the first electrode of the second driving transistor DT2 through the second type via K2; the second electrode of the first driving transistor DT1 is connected to the second electrode of the second driving transistor DT2 through the fourth active portion 214. Optionally, the second connection line L2 is located in the fourth conductive layer 34.

[0075] The second type via K2 connecting the first end of the second connection line L2 and the second gate G3 of the first driving transistor DT1 penetrates the interlayer insulating layer 140; the first type via K1 connecting the second end of the second connection line L2 and the third gate G4 of the second driving transistor DT2 penetrates the interlayer insulating layer 140, the second gate insulating layer 130 and the first gate insulating layer 120; the second type via K2 connecting the third end of the second connection line L2 and the first electrode of the first driving transistor DT1 and the first electrode of the second driving transistor DT2 penetrates the interlayer insulating layer 140 and the second gate insulating layer 130. Optionally, the third end of the second connection line L2 can be connected to the first end of the first active portion 211, the first end of the second active portion 212 or the third active portion 213 through the second type via K2. In this embodiment, the second gate G3 of the first driving transistor DT1 is connected to the first electrode, the third gate G4 of the second driving transistor DT2 is connected to the first electrode, and the second gate G3 of the first driving transistor DT1 is connected to the third gate G4 of the second driving transistor DT2 is connected. This can reduce the layout space occupied by the first driving transistor DT1 and the second driving transistor DT2, thereby improving the pixel density.

[0076] Fig.10 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention, Fig.11 is a structural schematic diagram of another display panel provided by an embodiment of the present invention, Fig.12 yes Fig.11 Schematic diagram of the structure of the first conductive layer, Fig.13 yes Fig.11 A schematic diagram of the structure of the first conductive layer and the second conductive layer, Fig.14 yes Fig.11 A schematic diagram of the structure of the first conductive layer, the second conductive layer, the active layer and the third conductive layer, Fig.15 yes Fig.11 A schematic diagram of the structure of the first conductive layer, the second conductive layer, the active layer, the third conductive layer and the first type of via hole, Fig.16 yes Fig.11 A schematic diagram of the structure of the first conductive layer, the second conductive layer, the active layer, the third conductive layer, the first type of vias and the second type of vias, Fig.17 yes Fig.11 A schematic diagram of the structure of the first conductive layer, the second conductive layer, the active layer, the third conductive layer, the first type via hole, the second type via hole and the fourth conductive layer, Fig.18 yes Fig.11 A schematic diagram of the structure of the first conductive layer, the second conductive layer, the active layer, the third conductive layer and the fifth conductive layer, Fig.19 yes Fig.11The schematic diagram of the structure of the second conductive layer, the active layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer in FIG. Figure 10-Figure 19 Optionally, the pixel circuit also includes a first transistor T1, and the gate of the first transistor T1 is located in the third conductive layer 33; the display panel also includes a second active layer 22, the second active layer 22 is in the same layer as the first active layer 21 and is not connected, and the channel region of the first transistor T1 is in the second active layer 22.

[0077] Among them, the channel region of the first transistor T1 is located at the positive projection position of the gate of the first transistor T1 on the second active layer 22, and the gate of the first transistor T1 is located in the third conductive layer 33. For example, the first metal wire J1 located in the third conductive layer 33 includes the gate of the first transistor T1. On the second active layer 22, the position where the second active layer 22 and the first metal wire J1 intersect is the channel region of the first transistor T1.

[0078] Optionally, the display panel further includes a first initialization signal line Vref1, a first electrode of the first transistor T1 is connected to the first initialization signal line Vref1 through a second type via K2, and a second electrode of the first transistor T1 is connected to the first electrode plate 01 of the first capacitor C1 through a third connection line L3.

[0079] Optionally, the first initialization signal line Vref1 includes a first sub-initialization signal line Vref11 extending along the first direction x, and the first electrode of the first transistor T1 is connected to the first sub-initialization signal line Vref11 through the second type via K2. In some embodiments, the first sub-initialization signal line Vref11 is located in the fourth conductive layer 34. The second type via K2 connecting the first electrode of the first transistor T1 and the first sub-initialization signal line Vref11 penetrates the interlayer insulating layer 140 and the second gate insulating layer 130.

[0080] Fig. 20 is a cross-sectional view of another display panel provided by an embodiment of the present invention, Fig. 20 Can correspond Fig.11 Cut along MM', reference Fig.11 and Fig. 20 Optionally, the third connection line L3 is located in the fourth conductive layer 34. The first end of the third connection line L3 is connected to the second electrode of the first transistor T1 through the second type via K2, and the second end of the third connection line L3 is connected to the first electrode plate 01 of the first capacitor C1 through the first type via K1.

[0081] The second end of the third connection line L3 can be connected to the second active layer 22 through the second type via K2, thereby realizing the connection with the second electrode of the first transistor T1. Accordingly, the second type via K2 needs to penetrate the interlayer insulating layer 140 and the second gate insulating layer 130. The first type via K1 connecting the second end of the third connection line L3 and the first electrode plate 01 of the first capacitor C1 needs to penetrate the interlayer insulating layer 140, the second gate insulating layer 130, the first gate insulating layer 120 and the capacitor insulating layer 110, and the capacitor insulating layer 110 is arranged between the first conductive layer 31 and the second conductive layer 32.

[0082] When the first transistor T1 is turned on, the first initialization voltage on the first sub-initialization signal line Vref11 can be transmitted to the first electrode 01 of the first capacitor C1 through the first transistor T1. The second electrode 02 of the first capacitor C1 is connected to the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2. Through the coupling effect of the first capacitor C1, the initialization of the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2 can be achieved.

[0083] Optionally, the display panel further includes a first scan signal line Sn1, and the orthographic projection of the first scan signal line Sn1 on the substrate 10 overlaps with the orthographic projection of the gate of the first transistor T1 on the substrate 10, and at the overlapping position, the gate of the first transistor T1 is connected to the first scan signal line Sn1 through the second type via K2. In some embodiments, the first scan signal lines Sn1 extend along the first direction x respectively. In some embodiments, the first scan signal lines Sn1 are located in the fourth conductive layer 34. The first sub-initialization signal line Vref11 is located on a side of the first scan signal line Sn1 away from the second active portion 212.

[0084] As described above, the first metal line J1 located in the third conductive layer 33 includes the gate of the first transistor T1, and the orthographic projection of the first scan signal line Sn1 on the substrate 10 overlaps with the orthographic projection of the first metal line J1 on the substrate 10. At the overlapping position, the first scan signal line Sn1 is connected to the first metal line J1 through the second type via K2 to provide a first scan signal to the gate of the first transistor T1.

[0085] Optionally, the display panel further includes a second transistor T2, the gate of the second transistor T2 is located in the third conductive layer 33, the channel region of the second transistor T2 is located in the first active layer 21, and the channel region of the second transistor T2 is located at the positive projection position of the gate of the second transistor T2 on the first active layer 21. Optionally, the second transistor T2 is used to compensate for the threshold voltage of the driving transistor.

[0086] On the first active layer 21, the intersection of the first active layer 21 and the first metal wire J1 is the channel region of the second transistor T2. The first metal wire J1 located in the third conductive layer 33 also includes the gate of the second transistor T2. The gate of the second transistor T2 and the gate of the first transistor T1 are an integrated structure. The gate of the second transistor T2 is connected to the first scanning signal line Sn1 through the second type via K2. Optionally, the first scanning signal line Sn1 can be connected to the first metal wire J1 through a second type via K2 to achieve connection with the gates of the first transistor T1 and the second transistor T2 in the same pixel circuit, thereby reducing the number of openings and improving the signal transmission quality. In other embodiments, the first scanning signal line Sn1 may also be respectively connected to the gate of the first transistor T1 and the gate of the second transistor T2 through different second-type vias K2. For example, at the intersection of the first metal line J1 and the second active layer 22, the first scanning signal line Sn1 is connected to the first metal line J1 through a second-type via K2, and at the intersection of the first metal line J1 and the first active layer 21, the first scanning signal line Sn1 is connected to the first metal line J1 through another second-type via K2.

[0087] Optionally, the first electrode of the second transistor T2 is connected to the second electrodes of the first driving transistor DT1 and the second electrode of the second driving transistor DT2 through the fourth active portion 214 , and the second electrode of the second transistor T2 is connected to the driving gate of the second driving transistor DT2 through the fourth connection line L4 .

[0088] Optionally, the first active layer 21 also includes a fifth active portion 215, and the channel region of the second transistor T2 is in the fifth active portion 215; the fifth active portion 215 connects the first active portion 211 and the second active portion 212 through the fourth active portion 214, thereby realizing the connection between the first electrode of the second driving transistor DT2 and the second electrode of the first driving transistor DT1 and the second electrode of the second driving transistor DT2.

[0089] Optionally, the first electrode of the second transistor T2 is connected to the first end of the fourth connection line L4 via the second type via K2, and the driving gate of the second driving transistor DT2 is connected to the second end of the fourth connection line L4 via the second type via K2.

[0090] In some embodiments, along the second direction y, the second active portion 212 is located between the first active portion 211 and the first scanning signal line Sn1. Accordingly, along the second direction y, the second driving transistor DT2 is located between the first driving transistor DT1 and the first scanning signal line Sn1. In this way, the distance between the driving gate of the second driving transistor DT2 and the first scanning signal line Sn1 can be made closer, and accordingly, the distance between the second transistor T2 and the driving gate of the second driving transistor DT2 is made closer, so that the length of the fourth connecting line L4 is shorter, so that the fourth connecting line L4 and other signal lines in the display panel will not form a large parasitic capacitance, which is beneficial to improve the display effect of the display panel.

[0091] Optionally, the second transistor T2 and the first transistor T1 are arranged along the first direction x, that is, the two transistors connected to the first scanning signal line Sn1 are arranged along the first direction x, and optimizing the layout structure is beneficial to improving the pixel density.

[0092] Optionally, the display panel further includes a third transistor T3, the gate of the third transistor T3 is located in the third conductive layer 33, and the channel region of the third transistor T3 is located in the first active layer 21. The channel region of the third transistor T3 is located at the positive projection position of the gate of the third transistor T3 on the first active layer 21, and the gate of the third transistor T3 is located in the third conductive layer 33. For example, the second metal line J2 located in the third conductive layer 33 includes the gate of the third transistor T3, and the position where the first active layer 21 and the second metal line J2 intersect on the first active layer 21 is the channel region of the third transistor T3.

[0093] Optionally, the first active layer 21 further includes a sixth active portion 216 , which is located on a side of the first active portion 211 away from the fifth active portion 215 along the second direction y, and is connected to the first active portion 211 through the third active portion 213 , and a channel region of the third transistor T3 is in the sixth active portion 216 .

[0094] Optionally, the display panel further includes a second initialization signal line Vref2, a first electrode of the third transistor T3 is electrically connected to the second initialization signal line Vref2 through a second type via K2, and a second electrode of the third transistor T3 is connected to a first electrode of the first driving transistor DT1 and a first electrode of the second driving transistor DT2 through a third active portion 213. In some embodiments, the second initialization signal line Vref2 extends along the first direction x. Optionally, the second initialization signal line Vref2 is located in the fourth conductive layer 34.

[0095] Among them, the positive projection of the second initialization signal line Vref2 on the substrate 10 overlaps with the positive projection of the sixth active part 216 on the substrate 10. For example, the second initialization signal line Vref2 and the sixth active part 216 are arranged to cross each other. At the intersection of the two, the second initialization signal line Vref2 is connected to the sixth active part 216 through the second type via K2, thereby connecting the second initialization signal line Vref2 to the first electrode of the third transistor T3. The sixth active part 216 is connected to the first end of the first active part 211 and the first end of the second active part 212 through the third active part 213, thereby connecting the second electrode of the third transistor T3 to the first electrode of the first driving transistor DT1 and the first electrode of the second driving transistor DT2. When the third transistor T3 is turned on, the first electrode of the first driving transistor DT1, the second gate G3, and the first electrode and the third gate G4 of the second driving transistor DT2 are initialized to the second initialization voltage on the second initialization signal line Vref2. When the third transistor T3 and the second transistor T2 are turned on at the same time, the driving gate of the first driving transistor DT1 is discharged to the second initialization signal line Vref2 through the second transistor T2, the first driving transistor DT1 and the third transistor T3, and the driving gate of the second driving transistor DT2 is discharged to the second initialization signal line Vref2 through the second transistor T2, the second driving transistor DT2 and the third transistor T3, thereby compensating the threshold voltages of the first driving transistor DT1 and the second driving transistor DT2.

[0096] Optionally, the display panel further includes a second scan signal line Sn2, and the orthographic projection of the second scan signal line Sn2 on the substrate 10 overlaps with the orthographic projection of the gate of the third transistor T3 on the substrate 10, and at the overlapping position, the second scan signal line Sn2 is connected to the gate of the third transistor T3 through the second type via K2. In some embodiments, the second scan signal line Sn2 extends along the first direction x; in some embodiments, the second scan signal line Sn2 is located in the fourth conductive layer 34.

[0097] The orthographic projection of the second scanning signal line Sn2 on the substrate 10 overlaps with the orthographic projection of the second metal line J2 on the substrate 10. At the overlapping position, the second scanning signal line Sn2 is connected to the second metal line J2 through the second type via K2, that is, the second scanning signal line Sn2 is connected to the gate of the third transistor T3 through the second type via K2 to provide a second scanning signal to the gate of the third transistor T3.

[0098] Optionally, the second scan signal line Sn2 is located between the second initialization signal line Vref2 and the first scan signal line Sn1.

[0099] Optionally, the display panel also includes a fourth transistor T4, a fifth transistor T5 and a second capacitor C2; the display panel also includes a third initialization signal line Vref3 and a data line Data, the second electrode of the fourth transistor T4 is connected to the third initialization signal line Vref3, the second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5, and is connected to the first electrode plate 03 of the second capacitor C2, the second electrode plate 04 of the second capacitor C2 is connected to the second electrodes of the first driving transistor DT1 and the second driving transistor DT2, and the first electrode of the fifth transistor T5 is connected to the data line Data. Among them, the fourth transistor T4 is used to transmit a fixed voltage to the first plate 03 of the second capacitor C2, the fifth transistor T5 is used to transmit a data voltage to the first plate 03 of the second capacitor C2, and the second capacitor C2 is used to couple the voltage change of its first plate to the second plate, that is, the second capacitor C2 can couple the voltage change of its first plate to the second pole of the first driving transistor DT1 and the second pole of the second driving transistor DT2, and transmit it to the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2 through the second transistor T2, so that the voltage of the driving gate of the first driving transistor DT1 is associated with the data voltage, and the voltage of the driving gate of the second driving transistor DT2 is associated with the data voltage. Optionally, the first plate 03 of the second capacitor C2 is located in the first conductive layer 31, and the second plate 04 of the second capacitor C2 is located in the second conductive layer 32.

[0100] Optionally, the active layer also includes a third active layer 23, which is in the same layer as the first active layer 21 and is not connected; the channel region of the fourth transistor T4 and the channel region of the fifth transistor T5 are located in the third active layer 23, the channel region of the fourth transistor T4 is located at the positive projection position of the gate of the fourth transistor T4 on the third active layer 23, the channel region of the fifth transistor T5 is located at the positive projection position of the gate of the fifth transistor T5 on the third active layer 23, and the gate of the fourth transistor T4 and the gate of the fifth transistor T5 are located in the third conductive layer 33.

[0101] Optionally, the second metal line J2 includes the gate of the fourth transistor T4, and on the third active layer 23, the position where the third active layer 23 and the second metal line J2 intersect is the channel region of the fourth transistor T4. Optionally, the positive projection of the second scan signal line Sn2 on the substrate 10 overlaps at least partially with the positive projection of the gate of the fourth transistor T4 on the substrate 10, and at the overlapping position, the second scan signal line Sn2 is connected to the gate of the fourth transistor T4 through the second type via K2. The gate of the fourth transistor T4 is an integral structure with the gate of the third transistor T3. Optionally, the second scan signal line Sn2 can be connected to the second metal line J2 through a second type via K2 to achieve connection with the gates of the third transistor T3 and the fourth transistor T4 in the same pixel circuit, thereby reducing the number of openings and improving the signal transmission quality. In other embodiments, the second scan signal line Sn2 may also be connected to the gate of the third transistor T3 and the gate of the fourth transistor T4 respectively through different second type vias K2. For example, at the intersection of the second metal line J2 and the first active layer 21, the second scan signal line Sn2 is connected to the second metal line J2 through a second type via K2, and at the intersection of the second metal line J2 and the third active layer 23, the second scan signal line Sn2 is connected to the second metal line J2 through another second type via K2.

[0102] Optionally, the third active layer 23 is located on a side of the first active portion 211 away from the second active portion 212. In some embodiments, the third active layer 23 extends along the second direction y.

[0103] Specifically, the second electrode of the fourth transistor T4 is connected to the third initialization signal line Vref3 through the second type via K2, the first electrode of the fourth transistor T4 is connected to the first electrode plate 03 of the second capacitor C2 through the fifth connection line L5, and the second electrode plate 04 of the second capacitor C2 is connected to the second electrode of the first driving transistor DT1 and the second electrode of the first driving transistor DT1 through the sixth connection line L6. Fig.21 is a cross-sectional view of another display panel provided by an embodiment of the present invention, Fig.21 Can correspond Fig.11 Cut along NN' to obtain reference Fig.11 and Fig.21 Specifically, the first end of the fifth connection line L5 is connected to the second electrode of the fourth transistor T4 through the second type via K2, and the second end of the fifth connection line L5 is connected to the first electrode plate 03 of the second capacitor C2 through the first type via K1. Fig. 22 is a cross-sectional view of another display panel provided by an embodiment of the present invention, Fig. 22 Can correspond Fig.11 Cut along PP', refer to Fig.11 and Fig. 22The first end of the sixth connection line L6 is connected to the second electrode plate 04 of the second capacitor C2 through the first type via K1, and the second end of the sixth connection line L6 is connected to the second electrode of the first driving transistor DT1 and the second electrode of the second driving transistor DT2 through the second type via K2.

[0104] The orthographic projection of the third active layer 23 on the substrate 10 overlaps with the orthographic projection of the third initialization signal line Vref3 on the substrate 10 . At the overlapping position, the third active layer 23 is connected to the third initialization signal line Vref3 through the second type via K2 .

[0105] Optionally, the third initialization signal line Vref3 extends along the first direction x. In some embodiments, the third initialization signal line Vref3 is located in the fourth conductive layer 34 .

[0106] Optionally, the third initialization signal line Vref3 is located between the first scan signal line Sn1 and the second scan signal line Sn2. The purpose of this arrangement is to optimize the position of each transistor in the layout to reduce the layout space occupied, thereby improving the layout space utilization and pixel density.

[0107] In some embodiments, a first electrode of the fifth transistor T5 is connected to the first electrode plate 03 of the second capacitor C2 through a fifth connection line L5, and a second electrode of the fifth transistor T5 is connected to the data line Data through a seventh connection line L7. Fig.23 is a cross-sectional view of another display panel provided by an embodiment of the present invention, Fig.23 Can correspond Fig.11 Cut along QQ' to obtain reference Fig.11 and Fig.23 Specifically, the first end of the seventh connection line L7 is connected to the second electrode of the fifth transistor T5 through the second type via K2, and the second end of the seventh connection line L7 is connected to the data line Data through the third type via K3.

[0108] Optionally, the fifth connection line L5 is located in the fourth conductive layer 34 ; the sixth connection line L6 is located in the fourth conductive layer 34 ; and the seventh connection line L7 is located in the fourth conductive layer 34 .

[0109] Optionally, the display panel further includes a fifth conductive layer 35 , which is located on a side of the fourth conductive layer 34 away from the substrate 10 , and the data line Data is located on the fifth conductive layer 35 ; the data line Data extends along the second direction y.

[0110] The first planarization layer 150 is disposed between the fifth conductive layer 35 and the fourth conductive layer 34 , and the third type via K3 is a via that penetrates the first planarization layer.

[0111] Optionally, the third transistor T3 and the fourth transistor T4 are arranged along the first direction x; that is, the two transistors connected to the second scanning signal line Sn2 are arranged along the first direction x, which optimizes the layout structure and is conducive to improving the pixel density.

[0112] Optionally, the display panel also includes a third scanning signal line Sn3. In some embodiments, the third scanning signal line Sn3 is located in the third conductive layer 33. The third scanning signal line Sn3 includes a gate of the fifth transistor T5. In this way, there is no need to additionally set a metal wire in other conductive layers as the gate of the fifth transistor T5, which can reduce the wiring in the display panel and thereby improve the pixel density.

[0113] In some other embodiments, the third scanning signal line Sn3 is located in the fourth conductive layer 34, and its orthographic projection on the substrate 10 at least partially covers the gate of the fifth transistor T5. The third scanning signal line Sn3 is connected to the gate of the fifth transistor T5 through the second type via K2. This setting can reduce the resistance of the third scanning signal line Sn3, reduce the signal transmission voltage drop of the third scanning signal line Sn3, and improve the display effect.

[0114] Optionally, along the second direction y, the third scan signal line Sn3 is located on a side of the second scan signal line Sn2 away from the first scan signal line Sn1 .

[0115] Optionally, the pixel circuit further includes a sixth transistor T6, the channel region of the sixth transistor T6 is located in the first active layer 21, and the gate of the sixth transistor T6 is in the third conductive layer 33; the channel region of the sixth transistor T6 is at the positive projection position of the gate of the sixth transistor T6 on the first active layer 21, the first electrode of the sixth transistor T6 is connected to the first electrode plate 01 of the first capacitor C1 through the eighth connection line L8, and the second electrode of the sixth transistor T6 is connected to the second sub-initialization signal line Vref12 through the ninth connection line L9. When the sixth transistor T6 is turned on, the first initialization voltage on the second sub-initialization signal line Vref12 can be transmitted to the first electrode plate 01 of the first capacitor C1 to initialize the first electrode plate 01 of the first capacitor C1.

[0116] Specifically, the first end of the eighth connection line L8 is connected to the first electrode of the sixth transistor T6 through the second type via K2, and the second end of the eighth connection line L8 is connected to the first electrode plate 01 of the first capacitor C1 through the first type via K1; the first end of the ninth connection line L9 is connected to the second electrode of the sixth transistor T6 through the second type via K2, and the first end of the ninth connection line L9 is connected to the second sub-initialization signal line Vref12.

[0117] Optionally, the first initialization signal line Vref1 includes a second sub-initialization signal line Vref12, the second sub-initialization signal line Vref12 extends along the second direction y, and the second sub-initialization signal line Vref12 is connected to the first sub-initialization signal line Vref11 through a third type via K3; in this way, the first sub-initialization signal line Vref11 and the second sub-initialization signal line Vref12 form a mesh structure, which reduces the resistance of the first initialization signal line Vref1, reduces the transmission voltage drop of the first initialization signal line Vref1, and improves display uniformity.

[0118] Fig.24 is a cross-sectional view of another display panel provided by an embodiment of the present invention, Fig.24 Can correspond Fig.11 Cutting along WW', optionally, the fifth conductive layer 35 further includes a tenth connection line L10, the orthographic projection of the tenth connection line L10 on the substrate 10 overlaps with the orthographic projection of the eighth connection line L8 on the substrate 10, and the tenth connection line L10 is connected to the eighth connection line L8 through the third type via K3. Optionally, the display panel further includes a light-emitting device D1, the light-emitting device D1 includes a first electrode Y1, a light-emitting layer, and a second electrode (the second electrode is connected to a fixed voltage line VSS) stacked on a side of the conductive layer away from the substrate 10, the orthographic projection of the first electrode Y1 on the substrate 10 at least partially covers the orthographic projection of the tenth connection line L10 on the substrate 10, and the first electrode Y1 is connected to the tenth connection line L10 through a fourth type via. In this way, through the fourth type of via hole between the first electrode Y1 of the light-emitting device D1 and the tenth connection line L10, the third type of via hole K3 between the tenth connection line L10 and the eighth connection line L8, and the second type of via hole K2 between the eighth connection line L8 and the first electrode of the sixth transistor T6, a total of three via holes in the thickness direction z of the display panel are used to realize the connection between the first electrode Y1 of the light-emitting device D1 and the first electrode of the sixth transistor T6, compared with the use of a deep hole connection between the first electrode Y1 of the light-emitting device D1 and the first electrode of the sixth transistor T6, so that the connection between the first electrode Y1 of the light-emitting device D1 and the sixth transistor T6 is easy to realize. When the sixth transistor T6 is turned on, the first initialization voltage on the second sub-initialization signal line Vref12 can be transmitted to the first electrode Y1 of the light-emitting device D1 to initialize the first electrode Y1 of the light-emitting device D1.

[0119] Optionally, the orthographic projection of the tenth connecting line L10 on the substrate 10 covers the orthographic projection of the channel region of the sixth transistor T6 on the substrate 10; in this way, the tenth connecting line L10 can perform top light shielding on the channel region of the sixth transistor T6, thereby improving the influence of light on the electrical properties of the sixth transistor T6 and improving the display effect.

[0120] In some embodiments, the third scanning signal line Sn3 is located in the third conductive layer 33, and the third scanning signal line Sn3 includes the gate of the sixth transistor T6. In this way, there is no need to set an additional metal line in other conductive layers as the gate of the sixth transistor T6, which can reduce the wiring in the display panel and thus improve the pixel density.

[0121] In some other embodiments, the third scanning signal line Sn3 is located in the fourth conductive layer 34, and its orthographic projection on the substrate 10 at least partially covers the gate of the sixth transistor T6. The third scanning signal line Sn3 is connected to the gate of the sixth transistor T6 through the second type via K2. This setting can reduce the resistance of the third scanning signal line Sn3, reduce the signal transmission voltage drop of the third scanning signal line Sn3, and improve the display effect.

[0122] Optionally, the sixth transistor T6 and the fifth transistor T5 are arranged along the first direction x; that is, the two transistors connected to the third scanning signal line Sn3 are arranged along the first direction x, which optimizes the layout structure and is conducive to improving the pixel density.

[0123] Optionally, the display panel further includes a first light-emitting control signal line EM1 and a second light-emitting control signal line EM2, and the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 extend along the first direction x. The pixel circuit further includes a seventh transistor T7 and an eighth transistor T8, the gate of the seventh transistor T7 and the gate of the eighth transistor T8 are located in the third conductive layer 33, and the channel region of the seventh transistor T7 and the channel region of the eighth transistor T8 are located in the first active layer 21; the channel region of the seventh transistor T7 is located at the positive projection position of the gate of the seventh transistor T7 on the first active layer 21, and the channel region of the eighth transistor T8 is located at the positive projection position of the gate of the eighth transistor T8 on the first active layer 21.

[0124] Optionally, the channel region of the seventh transistor T7 is located in the fifth active portion 215 .

[0125] Optionally, the channel region of the eighth transistor T8 is located in the third active portion 213 .

[0126] Specifically, the first electrode of the seventh transistor T7 is connected to the power line VDD through the second type via K2, and the second electrode of the seventh transistor T7 is connected to the second electrode of the first driving transistor DT1 and the second electrode of the second driving transistor DT2 through the fourth active part 214. The first electrode of the eighth transistor T8 is connected to the first electrode of the first driving transistor DT1 and the first electrode of the second driving transistor DT2 in the third active part 213, and the second electrode of the eighth transistor T8 is connected to the first electrode plate 01 of the first capacitor C1 through the eighth connection line L8. When the seventh transistor T7 and the eighth transistor T8 are turned on, the driving current generated by the first driving transistor DT1 and the second driving transistor DT2 is transmitted to the light emitting device D1, thereby driving the light emitting device D1 to emit light for display.

[0127] Optionally, the power line VDD includes a second sub-power line VDD2 extending along the first direction x and a first sub-power line VDD1 extending along the first direction x, the second sub-power line VDD2 and the first sub-power line VDD1 are arranged in different layers and are connected through a third type via K3; the first electrode of the seventh transistor T7 is connected to the first sub-power line VDD1 through the second type via K2; in this way, the first sub-power line VDD1 and the second sub-power line VDD2 form a power line VDD with a mesh structure, reducing the resistance of the first power line VDD, thereby reducing the signal transmission voltage drop of the power line VDD, and improving display uniformity.

[0128] Optionally, the second sub-power line VDD2 is located in the fourth conductive layer 34, and the first sub-power line VDD1 is located in the fifth conductive layer 35. In some embodiments, the orthographic projection of the first sub-power line VDD1 on the substrate 10 covers the orthographic projections of the channel region of the first driving transistor DT1, the channel region of the second driving transistor DT2, the channel region of the first transistor T1, the channel region of the second transistor T2, the channel region of the third transistor T3, the channel region of the fourth transistor T4, the channel region of the fifth transistor T5, and the channel region of the seventh transistor T7 on the substrate 10. In this way, the first power line VDD of the fifth conductive layer 35 can perform top light shielding on the channel regions of multiple transistors in the pixel circuit, further improve the influence of light on the electrical performance of the transistors, and enhance the display effect.

[0129] Fig.25 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, referring to Fig.25Optionally, the orthographic projection of the first electrode Y1 of the light-emitting device on the substrate at least partially covers the orthographic projection of the channel region of the eighth transistor T8 on the substrate. In this way, the channel region of the eighth transistor T8 whose channel region is not covered by the fifth conductive layer is covered from the top by the first electrode, which can improve the influence of electrical performance on the electrical performance of the eighth transistor T8, and then the channel region of each transistor in the pixel circuit is covered by the fifth conductive layer and the first electrode of the light-emitting device D1, further improving the display effect.

[0130] Optionally, the first light-emitting control signal line EM1 includes the gate of the seventh transistor T7. In this case, on the first active layer 21, the position where the first active layer 21 and the first light-emitting control signal line EM1 intersect is the channel region of the seventh transistor T7; or the first light-emitting control signal line EM1 is located in the fourth conductive layer 34, and the orthographic projection of the first light-emitting control signal line EM1 on the substrate 10 at least partially covers the orthographic projection of the gate of the seventh transistor T7 on the substrate 10, and the first light-emitting control signal line EM1 is connected to the gate of the seventh transistor T7 through the second type via K2. Wherein, Fig.11 FIG. 4 exemplarily shows a case where the first light emission control signal line EM1 includes the gate of the seventh transistor T7 .

[0131] Optionally, the second light-emitting control signal line EM2 includes the gate of the eighth transistor T8. In this case, on the first active layer 21, the position where the first active layer 21 and the second light-emitting control signal line EM2 intersect is the channel region of the eighth transistor T8; or the second light-emitting control signal line EM2 is located in the fourth conductive layer 34, and the orthographic projection of the second light-emitting control signal line EM2 on the substrate 10 at least partially covers the orthographic projection of the gate of the eighth transistor T8 on the substrate 10, and the second light-emitting control signal line EM2 is connected to the gate of the eighth transistor T8 through the second type via K2. Wherein, Fig.11 The figure exemplifies the case where the second light-emitting control signal line EM2 is located in the fourth conductive layer 34. In this case, the display panel also includes a third metal wire J3 located in the third conductive layer 33. The third metal wire J3 serves as the gate of the eighth transistor T8. On the first active layer 21, the position where the first active layer 21 intersects with the third metal wire J3 is the channel region of the eighth transistor T8.

[0132] Optionally, the first light-emitting control signal line EM1 is located on a side of the first sub-initialization signal line Vref11 of the first initialization signal line Vref1 away from the first scanning signal line Sn1; the second light-emitting control signal line EM2 is located on a side of the second initialization signal line Vref2 away from the first scanning signal line Sn1; the purpose of this setting is to optimize the position of each transistor in the layout to reduce the space occupied by the layout, thereby improving the layout space utilization and improving the pixel density.

[0133] In some embodiments, the second sub power line VDD2 is located at a side of the first light emitting control signal line EM1 away from the first scan signal line Sn1.

[0134] Continue to refer Fig.11 and Fig.12 Optionally, the first conductive layer 31 further includes a first light shielding layer 311 and a second light shielding layer 312; along the first direction x, the first light shielding layer 311 is located between the first electrode plate 01 of the first capacitor C1 and the first electrode plate 03 of the second capacitor C2; along the second direction y, the second light shielding layer 312 and the first light shielding layer 311 are arranged along the second direction y. The first light shielding layer 311 and the second light shielding layer 312 can be used to shield the bottom of the channel region of the transistor in the pixel circuit to further improve the influence of light on the electrical performance of the transistor.

[0135] Combination Figure 11-Figure 14 In some embodiments, the orthographic projection of the first light-shielding layer 311 on the substrate 10 covers at least a portion of the orthographic projection of the channel region of the third transistor T3 on the substrate 10, at least a portion of the orthographic projection of the channel region of the fourth transistor T4 on the substrate 10, and at least a portion of the orthographic projection of the channel region of the fifth transistor T5 on the substrate 10, thereby bottom-shielding the channel region of the third transistor T3, the channel region of the fourth transistor T4, and the channel region of the fifth transistor T5, respectively.

[0136] In some embodiments, the orthographic projection of the second light-shielding layer 312 on the substrate 10 covers at least a portion of the orthographic projection of the channel region of the first transistor T1 on the substrate 10, at least a portion of the orthographic projection of the channel region of the second transistor T2 on the substrate 10, and at least a portion of the orthographic projection of the channel region of the seventh transistor T7 on the substrate 10, thereby bottom-shielding the channel region of the first transistor T1, the channel region of the second transistor T2, and the channel region of the seventh transistor T7, respectively.

[0137] In some embodiments, the orthographic projection of the first electrode plate 01 of the first capacitor C1 on the substrate 10 covers the orthographic projection of at least part of the channel region of the sixth transistor T6 on the substrate 10 and the orthographic projection of at least part of the channel region of the eighth transistor T8 on the substrate 10. In this way, the first electrode plate 01 of the first capacitor C1 serves as both the lower electrode plate of the first capacitor C1 and the bottom light shielding layer of the channel region of the sixth transistor T6 and the channel region of the eighth transistor T8, which can save layout space, improve the influence of light on the electrical performance of the sixth transistor T6 and the eighth transistor T8, and enhance the display effect and screen reliability.

[0138] Optionally, the first electrode plate 01 of the first capacitor C1 includes a main body 101 and a branch portion 102. Along the first direction x, the branch portion 102 is located on one side of the main body 101, and the branch portion 102 extends along the second direction y. The orthographic projection of the branch portion 102 on the substrate 10 covers at least a portion of the orthographic projection of the channel region of the sixth transistor T6 on the substrate 10 and at least a portion of the orthographic projection of the channel region of the eighth transistor T8 on the substrate 10. The orthographic projection of the main body 101 on the substrate 10 at least partially overlaps with the orthographic projection of the second electrode plate 02 of the first capacitor C1 on the substrate 10. In this way, on the one hand, an effective capacitor is formed by overlapping the main body 101 with the second electrode plate 02 of the first capacitor C1, and on the other hand, the setting of the branch portion 102 facilitates the connection between the first electrode plate 01 of the first capacitor C1 and the transistor in the pixel circuit.

[0139] Optionally, the first light shielding layer 311 is connected to the third initialization signal line Vref3 through the first type via K1; thus, the potential of the first light shielding layer 311 is kept fixed, so that the first light shielding layer 311 can also play a shielding role, further improving the display effect of the display panel.

[0140] Optionally, the second light-shielding layer 312 is connected to at least one of the power line VDD, the first initialization signal line Vref1, the second initialization signal line Vref2 and the third initialization signal line Vref3; in this way, the potential of the second light-shielding layer 312 is ensured to be fixed, so that the second light-shielding layer 312 can also play a shielding role, further improving the display effect of the display panel.

[0141] On the basis of the above embodiments, optionally, the display panel further includes: a capacitor insulating layer 110, the capacitor insulating layer 110 is located between the first conductive layer 31 and the second conductive layer 32, and the orthographic projection of the capacitor insulating layer 110 on the substrate 10 covers the orthographic projection of the first conductive layer 31 on the substrate 10; a first gate insulating layer 120, the first gate insulating layer 120 is located between the second conductive layer 32 and the active layer, and the orthographic projection of the first gate insulating layer 120 on the substrate 10 covers the orthographic projection of the second conductive layer 32 on the substrate 10; a second gate insulating layer 130, the second gate insulating layer 130 is located between the active layer and the third conductive layer 33, and the orthographic projection of the second gate insulating layer 130 on the substrate 10 covers the orthographic projection of the active layer on the substrate 10. an orthographic projection on the substrate 10; an interlayer insulating layer 140, the interlayer insulating layer 140 is located between the third conductive layer 33 and the fourth conductive layer 34, and the orthographic projection of the interlayer insulating layer 140 on the substrate 10 covers the orthographic projection of the third conductive layer 33 on the substrate 10; a first planarizing layer 150, the first planarizing layer 150 is located between the fourth conductive layer 34 and the fifth conductive layer 35, and the orthographic projection of the first planarizing layer 150 on the substrate 10 covers the orthographic projection of the fourth conductive layer 34 on the substrate 10; a second planarizing layer 160, the second planarizing layer 160 is located on the side of the fifth conductive layer 35 away from the substrate 10, and the orthographic projection of the second planarizing layer 160 on the substrate 10 covers the orthographic projection of the fifth conductive layer 35 on the substrate 10;

[0142] Optionally, the first type via K1 penetrates the interlayer insulating layer 140, the second gate insulating layer 130, the first gate insulating layer 120, or the first type via K1 penetrates the interlayer insulating layer 140, the second gate insulating layer 130, the first gate insulating layer 120 and the capacitor insulating layer; the second type via K2 penetrates the interlayer insulating layer 140, or the second type via K2 penetrates the interlayer insulating layer 140 and the second gate insulating layer 130; the third type via K3 penetrates the first planarizing layer 150; and the fourth type via penetrates the second planarizing layer 160.

[0143] Fig.26 is a working timing diagram of a pixel circuit provided by an embodiment of the present invention, and the working timing is applicable to Fig.11 The pixel circuit shown, reference Fig.11 and Fig.26 The working process of the pixel circuit includes: an initialization phase t1, a threshold voltage compensation phase t2, a data writing phase t3 and a light emitting phase t4. Optionally, each transistor in the pixel circuit is an N-type transistor, which can be an oxide transistor, such as an indium gallium zinc oxide transistor.

[0144] In the initialization stage t1, the signals on the second scanning signal line Sn2 and the first scanning signal line Sn1 are sequentially changed to high level, and the signal on the first light-emitting control signal line EM1 is high level. The first transistor T1 is turned on, and the signal on the first initialization signal line Vref1 is transmitted to the first electrode of the light-emitting device D1 and the first plate of the first capacitor C1 through the first transistor T1. The seventh transistor T7 is turned on, and the power supply voltage on the power line VDD is transmitted to the second electrode of the first driving transistor DT1 and the second driving transistor DT2 through the seventh transistor T7. The second transistor T2 and the third transistor T3 are turned on.

[0145] In the threshold voltage compensation stage t2, the signals on the second scanning signal line Sn2 and the first scanning signal line Sn1 remain at a high level, and the signal on the first light-emitting control signal line EM1 is at a low level. The second transistor T2 and the third transistor T3 remain turned on. The driving gate G1 of the first driving transistor DT1 discharges to the second initialization signal line Vref2 through the second transistor T2, the first driving transistor DT1 and the third transistor T3, thereby performing threshold voltage compensation on the first driving transistor DT1. The driving gate G2 of the second driving transistor DT2 discharges to the second initialization signal line Vref2 through the second transistor T2, the second driving transistor DT2 and the third transistor T3, thereby performing threshold voltage compensation on the second driving transistor DT2. The fourth transistor T4 is turned on to transmit the third initialization voltage on the third initialization signal line Vref3 to the first plate of the second capacitor C2.

[0146] In the data writing phase t3, the signal on the third scanning signal line Sn3 is a high level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, the data voltage on the data line Data is transmitted to the first electrode plate of the second capacitor C2 through the fifth transistor T5, and the second capacitor C2 couples the change of the data voltage relative to the third initialization voltage to the driving gate G1 of the first driving transistor DT1 and the driving gate G2 of the second driving transistor DT2 through the second transistor T2. The sixth transistor T6 is turned on, and the first initialization voltage of the first initialization signal line Vref1 is transmitted to the first electrode of the light emitting device D1.

[0147] In the light emitting stage t4, the signals on the first light emitting control signal line EM1 and the second light emitting control signal line EM2 are at high level, the seventh transistor T7 and the eighth transistor T8 are turned on, and the first driving transistor DT1 and the second driving transistor DT2 drive the light emitting device D1 to emit light.

[0148] Among them, the voltage change on the fixed voltage line VSS connected to the light-emitting device D1 will cause the voltage change of the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2, and due to the existence of parasitic capacitance at the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2, the voltage change of the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2 is different from the voltage change amplitude on the fixed voltage line VSS connected to the light-emitting device D1. In the above embodiment of the present invention, the positive projection of the power line VDD on the substrate 10 and the positive projection of the first connecting line L1 on the substrate 10 do not overlap or partially overlap, reducing the parasitic capacitance at the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2, thereby reducing the influence of the voltage change on the fixed voltage line VSS on the display effect, and improving the display uniformity.

[0149] An embodiment of the present invention further provides a display device, which includes the display panel provided by any embodiment of the present invention. Therefore, the display device also has the beneficial effects described in any of the above embodiments. Fig. 27 A structural schematic diagram of a display device provided in an embodiment of the present invention. In this embodiment, the display device can be a mobile phone or any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals and other products. The embodiment of the present invention does not make any special limitations on this.

[0150] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0151] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: substrate; An active layer and a plurality of conductive layers stacked on one side of the substrate, wherein a plurality of pixel circuits are formed in the active layer and the conductive layer; The pixel circuit includes a first driving transistor, a second driving transistor and a first capacitor; the first driving transistor and the second driving transistor are connected in parallel; The multi-layer conductive layer comprises a first conductive layer and a second conductive layer, the second conductive layer is located on a side of the first conductive layer away from the substrate; the first electrode plate of the first capacitor is located in the first conductive layer, the second electrode plate of the first capacitor is located in the second conductive layer, and the second electrode plate of the first capacitor is connected to the driving gate of the first driving transistor and the driving gate of the second driving transistor; along the thickness direction of the display panel, the driving gate of the first driving transistor and the driving gate of the second driving transistor are located on different sides of the active layer; The active layer is located on a side of the second conductive layer away from the substrate.

2. The display panel according to claim 1, characterized in that: The active layer includes a first active layer, and the channel region of the first driving transistor and the channel region of the second driving transistor are located in the first active layer; Preferably, the first driving transistor comprises a first gate and a second gate, the first gate is located on a side of the active layer close to the substrate, and the second gate is located on a side of the active layer away from the substrate; the orthographic projections of the first gate and the second gate on the substrate at least partially cover the orthographic projection of the channel region of the first driving transistor on the substrate; The first gate serves as a driving gate of the first driving transistor; Preferably, the second gate of the first driving transistor is connected to the first electrode of the first driving transistor; Preferably, the display panel further comprises a third conductive layer, the third conductive layer is located on a side of the active layer away from the substrate, and the second gate is located on the third conductive layer; Preferably, the second driving transistor comprises a third gate and a fourth gate, the third gate is located on a side of the active layer close to the substrate, and the fourth gate is located on a side of the active layer away from the substrate; the orthographic projections of the third gate and the fourth gate on the substrate at least partially cover the orthographic projection of the channel region of the second driving transistor on the substrate; The fourth gate serves as a driving gate of the second driving transistor; Preferably, the length of the channel region of the second driving transistor is smaller than the length of the channel region of the first driving transistor; Preferably, the third gate of the second driving transistor is connected to the first electrode of the second driving transistor; Preferably, the third gate is located in the second conductive layer; Preferably, the fourth gate is located in the third conductive layer; Preferably, the first active layer includes a first active portion, the first active portion extends along a first direction, and the channel region of the first driving transistor is located in the first active portion; Preferably, the first active layer includes a second active portion, the second active portion extends along the first direction; the channel region of the second driving transistor is located in the second active portion; Preferably, the first active layer also includes a third active portion and a fourth active portion, the third active portion and the fourth active portion respectively extend along a second direction, the second direction intersects with the first direction; the third active portion respectively connects the first end of the first active portion and the first end of the second active portion; the fourth active portion respectively connects the second end of the first active portion and the second end of the second active portion.

3. The display panel according to claim 1 or 2, characterized in that: The second plate of the first capacitor serves as a driving gate of the first driving transistor; Preferably, the active layer comprises a first active layer, the channel region of the first driving transistor is located in the first active layer, and the orthographic projection of the second electrode plate of the first capacitor on the substrate at least partially covers the orthographic projection of the channel region of the first driving transistor on the substrate; Preferably, the orthographic projection of the first electrode plate of the first capacitor on the substrate at least partially covers the orthographic projection of the channel region of the first driving transistor on the substrate; Preferably, the orthographic projection of the first electrode plate of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the second electrode plate of the first capacitor on the substrate; Preferably, the orthographic projection of the first electrode plate of the first capacitor on the substrate covers the orthographic projection of the second electrode plate of the first capacitor on the substrate.

4. The display panel according to claim 2, characterized in that: The display panel further includes a first connection line, a first end of the first connection line is electrically connected to the driving gate of the first driving transistor through a first type via hole, and a second end of the first connection line is electrically connected to the driving gate of the second driving transistor through a second type via hole; Preferably, the display panel further comprises a power line, and an orthographic projection of the power line on the substrate does not overlap or partially overlaps with the first connecting line; Preferably, the power line comprises a first sub-power line extending along the second direction, and an orthographic projection of the first sub-power line on the substrate does not overlap or partially overlaps with an orthographic projection of the first connecting line on the substrate; Preferably, the display panel further comprises a fourth conductive layer, the fourth conductive layer is located on a side of the third conductive layer away from the substrate, and the first connecting line is located on the fourth conductive layer; Preferably, the display panel further comprises a second connecting line, a first end of the second connecting line is electrically connected to the second gate of the first driving transistor through the second type via hole, a second end of the second connecting line is electrically connected to the third gate of the second driving transistor through the first type via hole, a third end of the second connecting line is connected to the first electrode of the first driving transistor and the first electrode of the second driving transistor through the second type via hole; the second electrode of the first driving transistor is connected to the second electrode of the second driving transistor through the fourth active portion; Preferably, the second connecting line is located in the fourth conductive layer.

5. The display panel according to claim 2, characterized in that: The pixel circuit further includes a first transistor, the gate of which is located in the third conductive layer; the display panel further includes a second active layer, which is in the same layer as the first active layer and is not connected to the first active layer, and the channel region of the first transistor is in the second active layer; Preferably, the channel region of the first transistor is located at the positive projection position of the gate of the first transistor on the second active layer; the display panel further comprises a first initialization signal line, the first electrode of the first transistor is connected to the first initialization signal line through a second type via hole, and the second electrode of the first transistor is connected to the first electrode plate of the first capacitor through a third connection line; Preferably, the first end of the third connection line is connected to the second electrode of the first transistor through the second type via, and the second end of the third connection line is connected to the first electrode plate of the first capacitor through the first type via; Preferably, the display panel further comprises a first scanning signal line, an orthographic projection of the first scanning signal line on the substrate overlaps with an orthographic projection of the gate of the first transistor on the substrate, and at the overlapping position, the gate of the first transistor is connected to the first scanning signal line through a second type via hole; Preferably, the first scanning signal lines extend along the first direction respectively; Preferably, the first initialization signal line includes a first sub-initialization signal line extending along the first direction, and the first electrode of the first transistor is connected to the first sub-initialization signal line through the second type via hole; Preferably, the display panel further comprises a fourth conductive layer, the fourth conductive layer is located on a side of the third conductive layer away from the substrate, and the first scanning signal line is located on the fourth conductive layer; Preferably, the first sub-initialization signal line is located in the fourth conductive layer; Preferably, the third connecting line is located in the fourth conductive layer; Preferably, the first scanning signal line extends along a first direction, an orthographic projection of the first scanning signal line on the substrate overlaps with an orthographic projection of the gate of the first transistor on the substrate, and at the overlapping position, the first scanning signal line is connected to the gate of the first transistor through a second type via hole; Preferably, the first sub-initialization signal line is located at a side of the first scanning signal line away from the second active portion; Preferably, the display panel further comprises a second transistor, a gate of the second transistor is located in the third conductive layer, a channel region of the second transistor is located in the first active layer, and the channel region of the second transistor is located at a positive projection position of the gate of the second transistor on the first active layer; Preferably, the first electrode of the second transistor is connected to the second electrode of the first driving transistor and the second electrode of the second driving transistor through the fourth active portion, the second electrode of the second transistor is connected to the driving gate of the second driving transistor through a fourth connecting line; the gate of the second transistor is connected to the first scanning signal line through the second type via hole; Preferably, the first electrode of the second transistor is connected to the first end of the fourth connection line through the second type via hole, and the driving gate of the second driving transistor is connected to the second end of the fourth connection line through the second type via hole; Preferably, the second transistor is used to compensate for the threshold voltage of the driving transistor; Preferably, the first active layer further includes a fifth active portion, and the channel region of the second transistor is in the fifth active portion; the fifth active portion connects the first active portion and the second active portion through the fourth active portion; Preferably, along the second direction, the second active portion is located between the first active portion and the first scanning signal line; Preferably, along the second direction, the second driving transistor is located between the first driving transistor and the first scanning signal line; Preferably, the second transistor and the first transistor are arranged along the first direction.

6. The display panel according to claim 5, characterized in that: Also comprising a third transistor, the gate of the third transistor is located in the third conductive layer, the channel region of the third transistor is located in the first active layer, and the channel region of the third transistor is located at a positive projection position of the gate of the second transistor on the first active layer; Preferably, the first active layer further includes a sixth active portion, and along the second direction, the sixth active portion is located on a side of the first active portion away from the fifth active portion, the sixth active portion is connected to the first active portion through the third active portion, and the channel region of the third transistor is in the sixth active portion; Preferably, the display panel further includes a second initialization signal line, the first electrode of the third transistor is electrically connected to the second initialization signal line through a second type via hole, and the second electrode of the third transistor is connected to the first electrode of the first driving transistor and the first electrode of the second driving transistor through a third active portion; Preferably, the second initialization signal line extends along the first direction; Preferably, the display panel further comprises a second scanning signal line, an orthographic projection of the second scanning signal line on the substrate overlaps with an orthographic projection of the gate of the third transistor on the substrate, and at the overlapping position, the second scanning signal line is connected to the gate of the third transistor through a second type via hole; Preferably, the second scanning signal line is located between the second initialization signal line and the first scanning signal line; Preferably, the second scanning signal line extends along the first direction; Preferably, the second scanning signal line is located in the fourth conductive layer; Preferably, the second initialization signal line is located in the fourth conductive layer; Preferably, the display panel further includes a fourth transistor, a fifth transistor and a second capacitor; The active layer further includes a third active layer, which is in the same layer as the first active layer and is not connected; the channel region of the fourth transistor and the channel region of the fifth transistor are located in the third active layer, the channel region of the fourth transistor is located at the positive projection position of the gate of the fourth transistor on the third active layer, the channel region of the fifth transistor is located at the positive projection position of the gate of the fifth transistor on the third active layer, and the gate of the fourth transistor and the gate of the fifth transistor are located in the third conductive layer; Preferably, the third active layer is located on a side of the first active portion away from the second active portion; Preferably, the third active layer extends along the second direction; Preferably, the display panel further includes a third initialization signal line, the second electrode of the fourth transistor is connected to the third initialization signal line through a second type via, the first electrode of the fourth transistor is connected to the first electrode plate of the second capacitor through a fifth connection line, and the second electrode plate of the second capacitor is connected to the second electrode of the first drive transistor and the second electrode of the first drive transistor through a sixth connection line; Preferably, the third initialization signal line extends along the first direction; Preferably, the third initialization signal line is located in the fourth conductive layer; Preferably, the third initialization signal line is located between the first scanning signal line and the second scanning signal line; Preferably, the first electrode plate of the second capacitor is located on the first conductive layer, and the second electrode plate of the second capacitor is located on the second conductive layer; Preferably, the first end of the fifth connection line is connected to the second electrode of the fourth transistor through a second type via, and the second end of the fifth connection line is connected to the first electrode plate of the second capacitor through a first type via; Preferably, the first end of the sixth connection line is connected to the second electrode plate of the second capacitor through a first type via, and the second end of the sixth connection line is connected to the second electrode of the first driving transistor and the second electrode of the second driving transistor through a second type via; Preferably, the display panel further comprises a data line, the first electrode of the fifth transistor is connected to the first electrode plate of the second capacitor through the fifth connecting line, and the second electrode of the fifth transistor is connected to the data line through a seventh connecting line; Preferably, the first end of the seventh connection line is connected to the second electrode of the fifth transistor through a second type via, and the second end of the seventh connection line is connected to the data line through a third type via; Preferably, the fifth connecting line is located in the fourth conductive layer; Preferably, the sixth connecting line is located in the fourth conductive layer; Preferably, the seventh connecting line is located in the fourth conductive layer; Preferably, the display panel further comprises a fifth conductive layer, the fifth conductive layer is located on a side of the fourth conductive layer away from the substrate, and the data line is located on the fifth conductive layer; The data line extends along the second direction; Preferably, an orthographic projection of the second scan signal line on the substrate at least partially overlaps with an orthographic projection of the gate of the fourth transistor on the substrate, and at the overlapping position, the second scan signal line is connected to the gate of the fourth transistor through a second type via hole; Preferably, the third transistor and the fourth transistor are arranged along the first direction; Preferably, the display panel further includes a third scan signal line, the third scan signal line is located in the third conductive layer, the third scan signal line includes the gate of the fifth transistor, or the third scan signal line is located in the fourth conductive layer, the orthographic projection of the third scan signal line on the substrate at least partially covers the gate of the fifth transistor, and the third scan signal line is connected to the gate of the fifth transistor through a second type via hole; Preferably, the third scanning signal line is located on a side of the second scanning signal line away from the first scanning signal line; Preferably, the pixel circuit further includes a sixth transistor, a channel region of the sixth transistor is located in the first active layer, and a gate of the sixth transistor is located in the third conductive layer; the channel region of the sixth transistor is located at a positive projection position of the gate of the sixth transistor on the first active layer, a first electrode of the sixth transistor is connected to a first electrode plate of the first capacitor through an eighth connecting line, and a second electrode of the sixth transistor is connected to a second sub-initialization signal line through a ninth connecting line; Preferably, the first initialization signal line includes the second sub-initialization signal line, the second sub-initialization signal line extends along the second direction, and the second sub-initialization signal line is connected to the first sub-initialization signal line through a third type via; Preferably, the first end of the eighth connection line is connected to the first electrode of the sixth transistor through a second type via, and the second end of the eighth connection line is connected to the first electrode plate of the first capacitor through a first type via; Preferably, the first end of the ninth connection line is connected to the second electrode of the sixth transistor through a second type via hole, and the first end of the ninth connection line is connected to the second sub-initialization signal line; Preferably, the fifth conductive layer further includes a tenth connecting line, an orthographic projection of the tenth connecting line on the substrate overlaps with an orthographic projection of the eighth connecting line on the substrate, and the tenth connecting line is connected to the eighth connecting line through a third type via; Preferably, the display panel further includes a light-emitting device, the light-emitting device includes a first electrode, a light-emitting layer, and a second electrode stacked on a side of the conductive layer away from the substrate, an orthographic projection of the first electrode on the substrate at least partially covers an orthographic projection of the tenth connecting line on the substrate, and the first electrode is connected to the tenth connecting line through a fourth type via hole; Preferably, the orthographic projection of the tenth connecting line on the substrate covers the orthographic projection of the channel region of the sixth transistor on the substrate; The third scan signal line is located in the third conductive layer, the third scan signal line includes the gate of the sixth transistor, or the third scan signal line is located in the fourth conductive layer, the orthographic projection of the third scan signal line on the substrate at least partially covers the gate of the sixth transistor, and the third scan signal line is connected to the gate of the sixth transistor through a second type via hole; Preferably, the sixth transistor and the fifth transistor are arranged along the first direction; Preferably, the display panel further includes a first light-emitting control signal line and a second light-emitting control signal line, and the first light-emitting control signal line and the second light-emitting control signal line extend along the first direction; The pixel circuit further includes a seventh transistor and an eighth transistor, the gate of the seventh transistor and the gate of the eighth transistor are located in the third conductive layer, and the channel region of the seventh transistor and the channel region of the eighth transistor are located in the first active layer; the channel region of the seventh transistor is located at the positive projection position of the gate of the seventh transistor on the first active layer, and the channel region of the eighth transistor is located at the positive projection position of the gate of the eighth transistor on the first active layer; Preferably, the channel region of the seventh transistor is located in the fifth active portion; Preferably, the channel region of the eighth transistor is located in the third active portion; Preferably, the first electrode of the seventh transistor is connected to the power line through the second type via, and the second electrode of the seventh transistor is connected to the second electrode of the first driving transistor and the second electrode of the second driving transistor through the fourth active portion; Preferably, the power line comprises a second sub-power line extending along the first direction and a first sub-power line extending along the first direction, the second sub-power line and the first sub-power line are arranged in different layers and connected through a third type via; the first electrode of the seventh transistor is connected to the first sub-power line through a second type via; Preferably, the second sub-power line is located in the fourth conductive layer, and the first sub-power line is located in the fifth conductive layer; Preferably, the orthographic projection of the first sub-power line on the substrate covers the orthographic projections of the channel region of the first driving transistor, the channel region of the second driving transistor, the channel region of the first transistor, the channel region of the second transistor, the channel region of the third transistor, the channel region of the fourth transistor, the channel region of the fifth transistor, and the channel region of the seventh transistor on the substrate respectively; Preferably, the orthographic projection of the first electrode of the light-emitting device on the substrate at least partially covers the orthographic projection of the channel region of the eighth transistor on the substrate; Preferably, the first electrode of the eighth transistor is connected to the first electrode of the first driving transistor and the first electrode of the second driving transistor in the third active portion, and the second electrode of the eighth transistor is connected to the first electrode plate of the first capacitor through an eighth connecting line; Preferably, the first light-emitting control signal line includes the gate of the seventh transistor; or the first light-emitting control signal line is located in the fourth conductive layer, and the orthographic projection of the first light-emitting control signal line on the substrate at least partially covers the orthographic projection of the gate of the seventh transistor on the substrate, and the first light-emitting control signal line is connected to the gate of the seventh transistor through a second type via hole; Preferably, the second light-emitting control signal line includes the gate of the eighth transistor; or the second light-emitting control signal line is located in the fourth conductive layer, and the orthographic projection of the second light-emitting control signal line on the substrate at least partially covers the orthographic projection of the gate of the eighth transistor on the substrate, and the second light-emitting control signal line is connected to the gate of the eighth transistor through a second type via; Preferably, the first light-emitting control signal line is located at a side of the first sub-initialization signal line of the first initialization signal line away from the first scanning signal line; the second light-emitting control signal line is located at a side of the second initialization signal line away from the first scanning signal line; Preferably, the second sub-power line is located on a side of the first light emitting control signal line away from the first scanning signal line.

7. The display panel according to claim 6, characterized in that: The first conductive layer further includes a first light shielding layer and a second light shielding layer; Along the first direction, the first light shielding layer is located between the first electrode plate of the first capacitor and the first electrode plate of the second capacitor; along the second direction, the second light shielding layer and the first light shielding layer are arranged along the second direction; Preferably, the orthographic projection of the first light shielding layer on the substrate covers at least a portion of the orthographic projection of the channel region of the third transistor on the substrate, at least a portion of the orthographic projection of the channel region of the fourth transistor on the substrate, and at least a portion of the orthographic projection of the channel region of the fifth transistor on the substrate; Preferably, the orthographic projection of the second light shielding layer on the substrate covers at least part of the orthographic projection of the channel region of the first transistor on the substrate, at least part of the orthographic projection of the channel region of the second transistor on the substrate, and at least part of the orthographic projection of the channel region of the seventh transistor on the substrate; Preferably, the orthographic projection of the first electrode plate of the first capacitor on the substrate covers at least a portion of the orthographic projection of the channel region of the sixth transistor on the substrate and at least a portion of the orthographic projection of the channel region of the eighth transistor on the substrate; Preferably, the first electrode plate of the first capacitor includes a main body and a branch portion, the branch portion is located at one side of the main body along the first direction, the branch portion extends along the second direction, the orthographic projection of the branch portion on the substrate covers at least part of the orthographic projection of the channel region of the sixth transistor on the substrate and at least part of the orthographic projection of the channel region of the eighth transistor on the substrate, and the orthographic projection of the main body on the substrate at least partially overlaps with the orthographic projection of the second electrode plate of the first capacitor on the substrate; Preferably, the first light shielding layer is connected to the third initialization signal line through the first type via hole; Preferably, the second light shielding layer is connected to at least one of the power line, the first initialization signal line, the second initialization signal line, and the third initialization signal line.

8. The display panel according to claim 6, characterized in that: The display panel further includes: a capacitor insulating layer, the capacitor insulating layer being located between the first conductive layer and the second conductive layer, and an orthographic projection of the capacitor insulating layer on the substrate covering an orthographic projection of the first conductive layer on the substrate; a first gate insulating layer, wherein the first gate insulating layer is located between the second conductive layer and the active layer, and an orthographic projection of the first gate insulating layer on the substrate covers an orthographic projection of the second conductive layer on the substrate; a second gate insulating layer, wherein the second gate insulating layer is located between the active layer and the third conductive layer, and an orthographic projection of the second gate insulating layer on the substrate covers an orthographic projection of the active layer on the substrate; an interlayer insulating layer, wherein the interlayer insulating layer is located between the third conductive layer and the fourth conductive layer, and an orthographic projection of the interlayer insulating layer on the substrate covers an orthographic projection of the third conductive layer on the substrate; a first planarization layer, wherein the first planarization layer is located between the fourth conductive layer and the fifth conductive layer, and an orthographic projection of the first planarization layer on the substrate covers an orthographic projection of the fourth conductive layer on the substrate; a second planarization layer, wherein the second planarization layer is located on a side of the fifth conductive layer away from the substrate, and an orthographic projection of the second planarization layer on the substrate covers an orthographic projection of the fifth conductive layer on the substrate; Preferably, the first type via hole penetrates the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer, or the first type via hole penetrates the interlayer insulating layer, the second gate insulating layer, the first gate insulating layer, and the capacitor insulating layer; The second type via hole penetrates the interlayer insulating layer, or the second type via hole penetrates the interlayer insulating layer and the second gate insulating layer; The third type via hole penetrates the first planarization layer; The fourth type via hole penetrates the second planarization layer.

9. The display panel according to claim 1, characterized in that: The material of the active layer includes metal oxide.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 9.

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