Electrode, display panel including the same, and method of manufacturing the electrode

Abstract

The invention discloses an electrode, a display panel comprising the electrode and a method for manufacturing the electrode. An electrode according to an embodiment of the present disclosure includes a first layer including a transparent conductive oxide including indium. The first layer includes a first region and a second region surrounding at least a portion of the first region. An indium content of a surface of the first layer corresponding to the first region is greater than an indium content of a surface of the first layer corresponding to the second region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0148080 filed on October 31, 2023 and all rights derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure herein relates to an electrode, a display panel including the electrode, and a method of manufacturing the electrode, and more particularly, to an electrode having improved manufacturing efficiency and manufacturing reliability, a display panel including the electrode, and a method of manufacturing the electrode. Background Art

[0004] Various electronic devices that can be worn on the body are being developed, and such devices may be referred to as wearable electronic devices. Wearable electronic devices may have various forms, and may be attachable to or detachable from various parts of the human body or clothing. In an example, a wearable electronic device that may be mounted on a user's head may be referred to as, for example, a head-mounted display (HMD) device. In some cases, a device such as an HMD may need to form a fine structure with an ultra-high resolution of more than 3000 ppi (pixels per inch). Summary of the invention

[0005] An object of the present disclosure is to provide an electrode having improved manufacturing efficiency while achieving high resolution, a display panel including the electrode, and a method of manufacturing the electrode.

[0006] The electrode according to the embodiment supported by the present disclosure includes a first layer, the first layer including a transparent conductive oxide containing indium. The first layer includes a first region and a second region surrounding at least a portion of the first region. The indium content of the surface of the first layer corresponding to the first region is greater than the indium content of the surface of the first layer corresponding to the second region.

[0007] In an embodiment, the electrode according to an embodiment supported by the present disclosure may further include a metal layer disposed under the first layer and including aluminum.

[0008] In an embodiment, the electrode according to an embodiment supported by the present disclosure may further include a second layer disposed between the metal layer and the first layer and including aluminum oxide.

[0009] In an embodiment, the transparent conductive oxide may include indium tin oxide (ITO).

[0010] In an embodiment, a surface roughness of a surface of the first layer corresponding to the first region may be greater than a surface roughness of a surface of the first layer corresponding to the second region.

[0011] In an embodiment, the first region may include a plurality of first sub-regions spaced apart from each other.

[0012] In an embodiment, the second region may surround each of the plurality of first sub-regions.

[0013] In an embodiment, the first layer may be provided as a single layer consisting of a transparent conductive oxide.

[0014] In an embodiment, the thickness of the first layer may be in a range from about 2 nm to about 12 nm.

[0015] The display panel according to the embodiment supported by the present disclosure includes a pixel defining layer and a light-emitting element, and the pixel opening is defined in the pixel defining layer. The light-emitting element includes a first electrode exposed through the pixel opening, a second electrode arranged on the first electrode, and at least one functional layer arranged between the first electrode and the second electrode. The first electrode includes a first layer, which includes a transparent conductive oxide containing indium. The first layer includes a first area and a second area surrounding at least a portion of the first area. The indium content of the surface of the first layer corresponding to the first area is greater than the indium content of the surface of the first layer corresponding to the second area.

[0016] In an embodiment, the first electrode may further include: a metal layer disposed under the first layer and including aluminum; and a second layer disposed between the metal layer and the first layer and including aluminum oxide.

[0017] In an embodiment, the at least one functional layer may include: a first emission layer emitting first light; and a second emission layer disposed on the first emission layer and emitting second light different from the first light.

[0018] In an embodiment, the light emitting element may include a first light emitting element, a second light emitting element, and a third light emitting element spaced apart in a direction perpendicular to the thickness direction. The first light emitting element may emit red light, the second light emitting element may emit green light, and the third light emitting element may emit blue light.

[0019] The method of manufacturing an electrode according to an embodiment supported by the present disclosure includes: forming a preliminary first layer, the preliminary first layer including a transparent conductive oxide containing indium; forming a photoresist pattern on the preliminary first layer, wherein the photoresist pattern includes an opening portion; and forming a first layer by etching the preliminary first layer using the photoresist pattern as a mask. The formation of the first layer includes: providing a material containing hydrogen (H 2) plasma; and after the first step, a second step of providing a second plasma to the preliminary first layer. In the first step, indium in the transparent conductive oxide is aggregated by the first plasma and forms an aggregated pattern. In the second step, a second plasma is provided to etch the aggregated pattern.

[0020] In an embodiment, each of the first step and the second step may be performed multiple times, and the first step and the second step may be performed alternately.

[0021] In an embodiment, the first layer may include a first region and a second region surrounding at least a portion of the first region. An indium content of a surface of the first layer corresponding to the first region may be greater than an indium content of a surface of the first layer corresponding to the second region.

[0022] In an embodiment, the first region may correspond to a region where the aggregation pattern is formed in the first step.

[0023] In an embodiment, the first step of providing the first plasma may be performed for more than 30 seconds.

[0024] In an embodiment, the method of manufacturing an electrode according to an embodiment supported by the present disclosure may further include: forming a preliminary metal layer containing aluminum before the forming of the preliminary first layer.

[0025] A preliminary first layer may be formed on the preliminary metal layer.

[0026] In an embodiment, the method of manufacturing an electrode according to an embodiment supported by the present disclosure may further include etching the preliminary metal layer to form a metal layer, wherein the etching of the preliminary metal layer may be performed together with the etching of the preliminary first layer for forming the first layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the various aspects supported by the present disclosure, and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate embodiments supported by various aspects of the present disclosure, and together with the description, are used to explain the principles supported by the present disclosure. In the accompanying drawings:

[0028] Figure 1 is a perspective view of an electronic device according to an embodiment supported by the present disclosure;

[0029] Figure 2 is a perspective view of an electronic device according to an embodiment supported by the present disclosure;

[0030] Figure 3 is an exploded perspective view of an electronic device according to an embodiment supported by the present disclosure;

[0031] Figure 4is a cross-sectional view of a display panel according to an embodiment supported by the present disclosure;

[0032] Figure 5 is a plan view illustrating a display panel according to an embodiment;

[0033] Figure 6 is a cross-sectional view illustrating a display panel according to an embodiment;

[0034] Fig. 7A and Figure 7B is an enlarged cross-sectional view of a portion of a display panel according to an embodiment supported by the present disclosure;

[0035] Fig. 8A is a cross-sectional view of a partial configuration of a first electrode according to an embodiment supported by the present disclosure;

[0036] Figure 8B is a plan view of a partial configuration of a first electrode according to an embodiment supported by the present disclosure;

[0037] Fig. 9 is a cross-sectional view illustrating a display panel according to an embodiment supported by the present disclosure;

[0038] Fig. 10A is a flow chart illustrating a method of manufacturing an electrode according to an embodiment supported by the present disclosure;

[0039] Fig. 10B is a flow chart illustrating some steps in a method of manufacturing an electrode according to an embodiment supported by the present disclosure;

[0040] FIG. 11A to FIG. 11C are cross-sectional views sequentially illustrating a method of manufacturing an electrode according to an embodiment supported by the present disclosure;

[0041] FIG. 12A to FIG. 12C is a cross-sectional view illustrating some steps in a method of manufacturing an electrode according to an embodiment supported by the present disclosure;

[0042] Fig.13A is a graph illustrating an aggregation depth of an aggregation pattern and a strain rate of a photoresist pattern according to hydrogen ion capacity of hydrogen plasma in some steps of a method of manufacturing an electrode according to an embodiment supported by the present disclosure;

[0043] Fig. 13B is a graph illustrating a strain rate of a photoresist pattern according to ion energy of argon plasma in some steps of a method of manufacturing an electrode according to an embodiment supported by the present disclosure; and

[0044] Fig.14A and Fig. 14Bis a microscope image illustrating states of some steps in a method of manufacturing an electrode according to an embodiment supported by the present disclosure. DETAILED DESCRIPTION

[0045] In this specification, when an element (or region, layer, part, etc.) is referred to as being "on" another element, "connected to" another element, or "combined with" another element, it can be directly set on the other element, directly connected to the other element, or directly combined with the other element, or an intervening third element may also be set.

[0046] The same reference numerals always refer to the same elements. In the drawings, the thickness, proportion and scale of each element are exaggerated in order to effectively explain the technical content. "And / or" may include one or more combinations of related elements that can be defined.

[0047] It will be understood that although the terms "first" and "second" etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element may be referred to as a second element without departing from the scope of the present invention. Similarly, a second element may be referred to as a first element. Unless the context clearly indicates otherwise, the singular form is intended to also include the plural form.

[0048] In some aspects, the terms "below", "beneath", "upper" and "above" are used to explain the relationship between the elements illustrated in the drawings. These terms are relative concepts and are interpreted based on the directions illustrated in the drawings.

[0049] It will be further understood that when used in this specification, the terms "include" or "comprises" and their variations specify the presence of stated features, number symbols, steps, operations, elements, parts or combinations thereof, but do not exclude the presence or addition of one or more other features, number symbols, steps, operations, elements, parts or combinations thereof.

[0050] In this description, "directly disposed" may mean that there is no additional film, layer, region, or plate between a part (such as a film, layer, or region) and another part. For example, "directly disposed" may mean disposing two layers or two members without using an additional member (such as an adhesive member, for example) therebetween.

[0051] As used herein, the terms "about" or "approximately" include the recited value and include an appropriate range of deviations for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity. The term "about" can mean within one or more standard deviations, or within, for example, ±30%, ±20%, ±10%, ±5% of the recited value.

[0052] The term "substantially" as used herein means approximately or in fact.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which the example embodiments described herein belong. In some aspects, it will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such in this article.

[0054] Hereinafter, an electronic device according to an embodiment supported by the present disclosure and a display panel included therein will be explained with reference to the accompanying drawings.

[0055] Figure 1 is a perspective view of an electronic device EA according to an embodiment supported by the present disclosure. The electronic device EA may be a device activated by an electrical signal. Non-limiting examples of the electronic device EA may include a television, a monitor, an external billboard, a game console, a personal computer, a laptop computer, a mobile phone, a tablet computer, a navigation device, and a wearable device, but the embodiments of the present disclosure are not limited thereto.

[0056] exist Figure 1 , a head mounted display (HMD) device is illustrated as an example of the electronic device EA. The head mounted display device may be a device mounted on the user's head and providing a screen on which an image or video is displayed to the user. The head mounted display device may be a see-through type and a non-see-through type, the see-through type head mounted display device providing an augmented reality (AR) environment based on an actual external object, and the non-see-through type head mounted display device providing a virtual reality (VR) environment to the user with a screen independent of the external object.

[0057] refer to Figure 1 , the electronic device EA may include a display panel DP and a lens portion LS facing the display panel DP. In some aspects, the electronic device EA may include a main frame MF, a cover frame CF, and a fixing portion FP.

[0058] The main frame MF may be a portion worn on the user's face. The main frame MF may have a shape corresponding to the shape of the user's head (face). For example, the length of the fixing part FP may be adjusted according to the circumference of the user's head. The fixing part FP is a structure that facilitates the installation of the main frame MF, and may include a strap or a belt, etc. However, embodiments of the present disclosure are not limited thereto, and the fixing part FP may have various forms such as a helmet and glasses legs combined with the main frame MF.

[0059] The lens part LS, the display panel DP, and the cover frame CF may be mounted on the main frame MF. The main frame MF may include a space or structure in which the lens part LS and the display panel DP may be accommodated.

[0060] The lens portion LS may be disposed between the display panel DP and the user. The lens portion LS may allow light emitted from the display panel DP to pass therethrough and provide the light to the user. For example, the lens portion LS may include various types of lenses including a multi-channel lens, a convex lens, a concave lens, a spherical lens, an aspherical lens, a single lens, a composite lens, a standard lens, a narrow-angle lens, a wide-angle lens, a fixed-focus lens, and a zoom lens.

[0061] The lens portion LS may include a first lens LS1 and a second lens LS2. The first lens LS1 and the second lens LS2 may be disposed to correspond to positions of a left eye and a right eye of a user. The first lens LS1 and the second lens LS2 may be accommodated in a main frame MF.

[0062] The display panel DP may be provided to the main frame MF in a fixed state or in a detachable state. The display panel DP will be explained in more detail later.

[0063] The cover frame CF is disposed on one surface of the display panel DP and protects the display panel DP. The cover frame CF and the lens portion LS may be spaced apart with the display panel DP located therebetween.

[0064] exist Figure 1 In the following drawings, the first direction DR1 to the third direction DR3 are illustrated, and the directions indicated by the first to third directions DR1, DR2 and DR3 explained in the present disclosure are relative concepts and can be converted into other directions. In some aspects, the directions indicated by the first to third direction axes can be interpreted as the first to third directions DR1, DR2 and DR3, and the same reference numerals can be used. In the present disclosure, the first direction DR1 and the second direction DR2 are orthogonal to each other, and the third direction DR3 is the normal direction of the plane defined by the first direction DR1 and the second direction DR2.

[0065] The thickness direction of the electronic device EA may be a direction parallel to a third direction DR3, which is a normal direction of a plane defined by the first direction DR1 and the second direction DR2. In the present disclosure, the front surface (or top) and the rear surface (or bottom) of each component constituting the electronic device EA may be defined based on the third direction DR3. In the present disclosure, "on a plane" means a plane parallel to the plane defined by the first direction DR1 and the second direction DR2, and "on a cross section" means a plane parallel to the third direction DR3.

[0066] Figure 2 is a perspective view of an electronic device EA-a according to an embodiment supported by the present disclosure. Figure 2 is a perspective view illustrating another embodiment of an electronic device according to one or more embodiments of the present disclosure, and a mobile phone is illustrated as an example of the electronic device EA-a. The electronic device EA-a can display an image IM through an effective area AA-DD. The effective area AA-DD may include a plane defined by a first direction DR1 and a second direction DR2. The effective area AA-DD may include a curved surface bent from at least one side of the plane defined by the first direction DR1 and the second direction DR2. However, this is an example, and the shape of the effective area AA-DD is not limited thereto. For example, the effective area AA-DD may include the plane but not other surfaces, or the effective area AA-DD may further include at least two curved surfaces, for example, four curved surfaces bent from four sides of the plane, respectively.

[0067] The peripheral area NAA-DD is adjacent to the active area AA-DD. The peripheral area NAA-DD may surround the active area AA-DD. Accordingly, the shape of the active area AA-DD may be substantially defined by the peripheral area NAA-DD. However, this is an example illustration, and the peripheral area NAA-DD may be disposed adjacent to one side of the active area AA-DD, or may be omitted. The active area AA-DD may be provided in various shapes and is not limited to any one embodiment.

[0068] Figure 3 is an exploded perspective view of an electronic device EA-a according to an embodiment supported by the present disclosure. Figure 3 yes Figure 2 : An exploded perspective view of the electronic device EA-a shown in FIG. Figure 3 , the electronic device EA-a may include a housing HAU, a display panel DP and a window member WM.

[0069] The window member WM may cover the entire outer side of the display panel DP. The window member WM may include a transmission area TA and a frame area BZA. The front surface of the window member WM including the transmission area TA and the frame area BZA may correspond to the front surface of the electronic device EA-a. The transmission area TA may correspond to Figure 2 The active area AA-DD of the electronic device EA-a shown in FIG. 1 and the border area BZA may correspond to Figure 2 The peripheral area NAA-DD of the electronic device EA-a is shown in the figure.

[0070] The transmission area TA may be an optically transparent area. The frame area BZA may be an area having a relatively low light transmittance compared to the transmission area TA. The frame area BZA may have a specific color. The frame area BZA may be adjacent to the transmission area TA and may surround the transmission area TA. The frame area BZA may define the shape of the transmission area TA. However, the embodiments of the present disclosure are not limited thereto, and the frame area BZA may be disposed adjacent to a single side of the transmission area TA, or a portion of the frame area BZA may be omitted.

[0071] Although not shown, an input sensing portion (not shown) may be provided on the display panel DP. The input sensing portion may sense an external input applied from the outside. The external input may be an input by a user. The user's input may include various types of external inputs, such as various parts of the user's body, light, heat, a pen, and pressure, for example. More specifically, the input sensing portion may be provided on an encapsulation layer TFE (see FIG. 1 ) to be explained later of the display panel DP. Figure 6 Alternatively, the input sensing portion may be directly located on the encapsulation layer TFE (see Figure 6 ), or the input sensing portion can be directly disposed on the packaging layer TFE (see Figure 6 ) on an adhesive member (not shown). The adhesive member may include a common adhesive or adhesive.

[0072] In the present disclosure, if an element (or region, layer or part, etc.) is said to be "directly disposed" on another element, it means that a third element is not located between the element and the other element. In other words, if an element is "directly disposed" on another element, it means that the element is "in contact with" the other element.

[0073] The display panel DP may include an active area AA and a peripheral area NAA. The active area AA may correspond to Figure 2 The active area AA-DD of the electronic device EA-a illustrated in FIG. 1 and the peripheral area NAA may correspond to Figure 2 The peripheral area NAA-DD of the electronic device EA-a shown in FIG. The active area AA is where the light emitting element ED (see FIG. 1 ) to be described later is placed. Figure 6 ) area, and the peripheral area NAA may be an area surrounding the active area AA.

[0074] The housing HAU may accommodate the display panel DP, etc. The housing HAU may be combined with the window member WM.

[0075] Figure 4 is a cross-sectional view of a display panel DP according to an embodiment supported by the present disclosure. Figure 4 The diagram shows Figure 3 A cross-sectional view of the portion corresponding to line II' in FIG. Figure 4 2 is a cross-sectional view schematically illustrating the structure of the display panel DP. Figure 4 The display panel DP may include a base layer BS, a circuit layer DP-CL, a display element layer DP-ED, and an encapsulation layer TFE. In some aspects, the display panel DP may further include an optical layer PP.

[0076] The base layer BS may be a member that provides a base surface on which the circuit layer DP-CL is disposed. The base layer BS may be a rigid substrate or a flexible substrate that can be bent, folded, or curled, etc. The base layer BS may be a glass substrate, a metal substrate, or a polymer substrate. However, the embodiments of the present disclosure are not limited thereto, and the base layer BS may be an inorganic layer, an organic layer, or a composite material layer.

[0077] The circuit layer DP-CL may be disposed above the base layer BS. The circuit layer DP-CL may include an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line. After forming the insulating layer, the semiconductor layer, and the conductive layer on the base layer BS by a method including coating or deposition, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned via a plurality of photolithography processes. Subsequently, the insulating layer, the semiconductor pattern, the conductive pattern, and the signal line included in the circuit layer DP-CL may be formed.

[0078] The display element layer DP-ED may be disposed above the circuit layer DP-CL. The display element layer DP-ED may include a light emitting element ED (see Figure 6 ). For example, the display element layer DP-ED may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro-LED or a nano-LED.

[0079] The encapsulation layer TFE may be disposed above the display element layer DP-ED. The encapsulation layer TFE may protect the display element layer DP-ED from moisture, oxygen, and foreign matter such as dust particles, for example. The encapsulation layer TFE may include at least one insulating layer.

[0080] The optical layer PP may be disposed on the encapsulation layer TFE and control light reflected from a lower layer of the encapsulation layer TFE due to external light. The optical layer PP may include, for example, a polarization layer or a color filter layer.

[0081] Figure 5 1 is a plan view illustrating a display panel DP according to an embodiment. Hereinafter, the same explanation of the display panel DP may be applied to Figure 1 and Figure 3 The display panel DP included in the electronic devices EA and EA-a shown in the figure.

[0082] refer to Figure 5, the display panel DP may include a light emitting area PXA and a non-light emitting area NPXA. The non-light emitting area NPXA may surround the light emitting area PXA. A plurality of light emitting areas PXA may be provided. The light emitting area PXA may include a red light emitting area PXA-R, a green light emitting area PXA-G, and a blue light emitting area PXA-B. Each of the red light emitting area PXA-R, the green light emitting area PXA-G, and the blue light emitting area PXA-B may emit light within a different wavelength range. The red light emitting area PXA-R may emit red light, the green light emitting area PXA-G may emit green light, and the blue light emitting area PXA-B may emit blue light.

[0083] Among the plurality of light emitting regions PXA-R, PXA-G, and PXA-B, the area of ​​the blue light emitting region PXA-B may be the largest, and the area of ​​the green light emitting region PXA-G may be the smallest. However, this is an example, and the areas of the plurality of light emitting regions PXA-R, PXA-G, and PXA-B are not limited thereto. Figure 5 , the red light emitting regions PXA-R and the blue light emitting regions PXA-B are alternately arranged in one row, and the green light emitting regions PXA-G are separated from the red light emitting regions PXA-R and the blue light emitting regions PXA-B and arranged in another row. However, this is an example, and the arrangement of the plurality of light emitting regions PXA-R, PXA-G, and PXA-B is not limited thereto.

[0084] Figure 6 is a cross-sectional view illustrating a display panel DP according to an embodiment. Figure 6 The diagram shows Figure 5 The cross-sectional view of the portion corresponding to the line II-II' in FIG. The base layer BS may have a single-layer or multi-layer structure. For example, the base layer BS may include a first synthetic resin layer, an intermediate layer of a multi-layer or single-layer structure, and a second synthetic resin layer stacked in sequence. The intermediate layer may be referred to as a base barrier layer. The intermediate layer may include silicon oxide (SiO x ) layer and an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, but is not specifically limited. For example, the intermediate layer may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and an amorphous silicon layer.

[0085] Each of the first synthetic resin layer and the second synthetic resin layer may include a polyimide resin. In some aspects, each of the first synthetic resin layer and the second synthetic resin layer may include at least one of an acrylate resin, a methacrylate resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In the present disclosure, an "α" type resin means containing an "α" functional group.

[0086] The circuit layer DP-CL may be disposed on the base layer BS. The circuit layer DP-CL may include a plurality of transistors (not shown). Each of these transistors (not shown) may include a control electrode, an input electrode, and an output electrode. For example, the circuit layer DP-CL may include a switch transistor and a drive transistor for driving the light emitting element ED of the display element layer DP-ED.

[0087] The display element layer DP-ED may include a light emitting element ED and a pixel defining layer PDL. The light emitting element ED may include a first electrode EL1, a second electrode EL2 disposed on the first electrode EL1, and at least one functional layer FL disposed between the first electrode EL1 and the second electrode EL2.

[0088] The first electrode EL1 may be an anode. In an embodiment, the first electrode EL1 may include a metal layer LM (see Fig. 7A ), the second layer L2 (see Fig. 7A ) and the first layer L1 (see Fig. 7A ). Accordingly, the first electrode EL1 may be formed to have a fine structure showing excellent reliability, and the display panel DP including the first electrode EL1 may show excellent display quality. The first electrode EL1 will be explained in more detail later.

[0089] The pixel defining layer PDL may have a transparent property or a light absorbing property. For example, the light absorbing pixel defining layer PDL may include a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, a metal such as chromium or an oxide thereof. The pixel defining layer PDL may correspond to a shielding pattern having a light blocking property.

[0090] The pixel defining layer PDL may cover a portion of the first electrode EL1. For example, in the pixel defining layer PDL, a pixel opening OH that exposes a portion of the first electrode EL1 may be defined. The pixel defining layer PDL may increase the distance between the edge of the first electrode EL1 and the second electrode EL2. Accordingly, the pixel defining layer PDL may be used to prevent arc light (e.g., electric arc) from being generated at the edge of the first electrode EL1.

[0091] The second electrode EL2 may be a cathode. The second electrode EL2 may be provided as a common layer. The second electrode EL2 may be referred to as a common electrode. A common voltage may be provided to the second electrode EL2. For example, the second electrode EL2 may include at least one selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, In, Sn, and Zn, or a compound thereof (LiF), a compound selected from two or more thereof, a mixture selected from two or more thereof, or an oxide thereof.

[0092] At least one functional layer FL may include a first emission layer EML-1 and a second emission layer EML-2 disposed on the first emission layer EML-1. The first emission layer EML-1 and the second emission layer EML-2 may be disposed between the first electrode EL1 and the second electrode EL2. In some aspects, at least one functional layer FL may further include a hole transport region HTR, an electron transport region ETR, and an emission auxiliary portion OG.

[0093] The light emitting element ED may have a series structure including a plurality of emission layers EML-1 and EML-2. The first emission layer EML-1 and the second emission layer EML-2 may be provided as a common layer. However, the embodiments of the present disclosure are not limited thereto, and the light emitting element ED may include a single emission layer (the first emission layer or the second emission layer) provided as a common layer.

[0094] Each of the first emission layer EML-1 and the second emission layer EML-2 may include an organic light-emitting material and / or an inorganic light-emitting material. The first emission layer EML-1 may emit a first light, and the second emission layer EML-2 may emit a second light different from the first light. For example, the first emission layer EML-1 may emit light in a wavelength range of about 450nm to about 570nm. The second emission layer EML-2 may emit light in a wavelength range of about 590nm to about 750nm. However, this is an example, and the wavelength of light emitted from the first emission layer EML-1 and the second emission layer EML-2 is not limited thereto. In another example, the first emission layer EML-1 and the second emission layer EML-2 may emit light in the same wavelength range.

[0095] The light emitting element ED including the first emission layer EML-1 and the second emission layer EML-2 may emit white light. However, the embodiments of the present disclosure are not limited thereto, and the light emitting element ED including the first emission layer EML-1 and the second emission layer EML-2 may emit blue light.

[0096] The hole transport region HTR may be disposed between the first electrode EL1 and the first emission layer EML-1. The hole transport region HTR may include at least one of a hole injection layer, a hole transport layer, and an electron blocking layer. The hole transport region HTR may include a known hole injection material and / or a hole transport material. The hole transport region HTR may be provided as a common layer. However, the embodiments of the present disclosure are not limited thereto, and the hole transport region HTR may be patterned and provided in the pixel opening OH.

[0097] The electron transport region ETR may be disposed between the second emission layer EML-2 and the second electrode EL2. The electron transport region ETR may include at least one of an electron injection layer, an electron transport layer, and a hole blocking layer. The electron transport region ETR may include a known electron injection material and / or an electron transport material. The electron transport region ETR may be provided as a common layer. However, the embodiments of the present disclosure are not limited thereto, and the electron transport region ETR may be patterned and provided in the pixel opening OH.

[0098] The emission auxiliary part OG may be disposed between the first emission layer EML-1 and the second emission layer EML-2. The emission auxiliary part OG may include a single layer or a multilayer. The emission auxiliary part OG may include a charge generation layer. In some aspects, the emission auxiliary part OG may further include a hole transport region disposed on the charge generation layer and an electron transport region disposed below the charge generation layer. The emission auxiliary part OG may be provided as a common layer. However, embodiments of the present disclosure are not limited thereto, and the emission auxiliary part OG may be patterned and provided in the pixel opening OH.

[0099] The encapsulation layer TFE may cover the light emitting element ED. The encapsulation layer TFE may seal the display element layer DP-ED. The encapsulation layer TFE may be disposed on the second electrode EL2 and may be disposed while filling the pixel opening OH.

[0100] The encapsulation layer TFE may be a thin film encapsulation layer. The encapsulation layer TFE may be a layer or a stacked layer of multiple layers. The encapsulation layer TFE may include at least one insulating layer. The encapsulation layer TFE according to an embodiment may include at least one inorganic layer (hereinafter, encapsulation inorganic layer). In some aspects, the encapsulation layer TFE according to an embodiment may include at least one organic layer (hereinafter, encapsulation organic layer) and at least one encapsulation inorganic layer.

[0101] The encapsulated inorganic layer can protect the display element layer DP-ED from moisture and oxygen, and the encapsulated organic layer can protect the display element layer DP-ED from foreign matter such as dust particles. The encapsulated inorganic layer may include silicon nitride, silicon oxynitride, silicon oxide, titanium oxide or aluminum oxide, but is not specifically limited. The encapsulated organic layer may include acrylic compounds and epoxy compounds, etc. The encapsulated organic layer may include a photopolymerizable organic material, but is not specifically limited.

[0102] The display panel DP may include a light emitting region PXA and a non-light emitting region NPXA. The light emitting region PXA may be a region that emits light generated in the light emitting element ED. The light emitting region PXA may be a region divided by a pixel defining layer PDL. The non-light emitting region NPXA may be a region between adjacent light emitting regions PXA and may be a region corresponding to the pixel defining layer PDL. The light emitting region PXA may correspond to a pixel.

[0103] The light emitting region PXA may include a red light emitting region PXA-R, a green light emitting region PXA-G, and a blue light emitting region PXA-B. The red light emitting region PXA-R, the green light emitting region PXA-G, and the blue light emitting region PXA-B may be spaced apart from each other on a plane.

[0104] exist Figure 6 , as an illustration, the optical layer PP is illustrated as including first to third filters CF1, CF2, and CF3. The first filter CF1 may be disposed to correspond to the red light emitting region PXA-R, the second filter CF2 may be disposed to correspond to the green light emitting region PXA-G, and the third filter CF3 may be disposed to correspond to the blue light emitting region PXA-B.

[0105] For example, the first filter CF1 may be a red filter, the second filter CF2 may be a green filter, and the third filter CF3 may be a blue filter. Each of the filters CF1, CF2, and CF3 may include a polymer photosensitive resin and a pigment or dye. The first filter CF1 may include a red pigment or dye, the second filter CF2 may include a green pigment or dye, and the third filter CF3 may include a blue pigment or dye. However, the embodiments of the present disclosure are not limited thereto, and in some examples, the third filter CF3 may not include a pigment or dye. For example, the third filter CF3 may include a polymer photosensitive resin but not a pigment or dye. The third filter CF3 may be optically transparent. The third filter CF3 may be formed of a transparent photosensitive resin.

[0106] A portion of each of the first to third filters CF1, CF2, and CF3 may be disposed in the non-emission region NPXA. However, embodiments of the present disclosure are not limited thereto, and the first to third filters CF1, CF2, and CF3 may not be disposed in the non-emission region NPXA.

[0107] A light blocking portion (not shown) may be provided between two adjacent filters among the first to third filters CF1, CF2 and CF3. The light blocking portion may be a black matrix. The light blocking portion may be formed by an organic light blocking material or an inorganic light blocking material including a black pigment or a black dye. The light blocking portion may prevent light leakage and may demarcate the boundaries between adjacent filters CF1, CF2 and CF3.

[0108] Fig. 7A and Figure 7B is an enlarged cross-sectional view of a portion of a display panel according to an embodiment supported by the present disclosure. Fig. 7A and Figure 7B In each of the Figure 6 In the area of ​​XX'. Fig. 7A and Figure 7B , the configuration of the first electrodes EL1 and EL1' of the embodiment is particularly illustrated. In some embodiments, in the present disclosure, the "first electrode" may be referred to as an "electrode".

[0109] refer to Fig. 7A The first electrode EL1 may include a plurality of conductive layers. The first electrode EL1 may include at least a first layer L1. The first electrode EL1 may include, for example, a metal layer LM, a second layer L2 disposed on the metal layer LM, and a first layer L1 disposed on the second layer L2.

[0110] The total thickness of the first electrode EL1 including the first layer L1, the second layer L2 and the metal layer LM may be in the range of about 50 nm to about 150 nm. If the thickness is greater than about 150 nm, it is not easy to pattern the first electrode EL1 into a fine structure, and thus ultra-high resolution may not be achieved, and the first electrode EL1 having a thickness less than about 50 nm may be difficult to achieve. In an embodiment, the first electrode EL1 having a thickness ranging from about 50 nm to about 150 nm may be patterned into a fine structure via dry etching. Accordingly, the display panel DP including the first electrode EL1 may achieve ultra-high resolution.

[0111] Figure 1The head mounted display device (electronic device EA) shown in the figure can achieve ultra-high resolution to realize virtual reality and augmented reality, and the display panel DP including the first electrode EL1 can achieve an ultra-high resolution of about 3000 ppi or more. The electronic device EA including the display panel DP of the embodiment can show excellent display quality.

[0112] The first layer L1 includes a transparent conductive oxide (TCO). The first layer L1 includes a transparent conductive oxide containing indium. The first layer L1 may include, for example, indium tin oxide (ITO). Alternatively, the first layer L1 may include indium zinc oxide (IZO) or indium zinc tin oxide (IZTO). The first layer L1 may be a single layer composed of a transparent conductive oxide containing indium. That is, the first layer L1 may not include another material other than the transparent conductive oxide containing indium, and may have a single layer structure that does not include a plurality of layers or sections in which a recognizable interface is defined.

[0113] The thickness of the first layer L1 may be in the range of about 2 nm to about 12 nm. For example, the thickness of the first layer L1 may be about 5 nm. It is difficult to achieve a uniform thickness for a first layer having a thickness less than about 2 nm, and a first layer formed with a thickness greater than about 12 nm may have reduced stability due to self-stress. In an embodiment, the first layer L1 having a thickness range of about 2 nm to about 12 nm may be formed to a uniform thickness and may exhibit excellent processing properties.

[0114] The first electrode EL1 may further include a metal layer LM disposed below the first layer L1. The metal layer LM may include a conductive metal. The metal layer LM may include, for example, aluminum. The metal layer LM may include an aluminum alloy. The metal layer LM may include an aluminum alloy consisting of aluminum atoms and alloy atoms. In the present disclosure, alloy atoms refer to atoms other than aluminum atoms among the atoms constituting the aluminum alloy. The alloy atoms may be one or more. The aluminum alloy constituting the metal layer LM may include at least one of titanium (Ti), nickel (Ni) and lanthanum (La) as alloy atoms. For example, the metal layer LM may include an alloy consisting of aluminum and titanium. In addition, the metal layer LM may include an alloy consisting of aluminum, nickel and lanthanum.

[0115] The metal layer LM may have a ratio of alloy atoms other than aluminum atoms of about 0.01 at % to about 0.1 at % based on an atomic ratio of 100 at % (atomic percentage) of an aluminum alloy. If the ratio of alloy atoms other than aluminum atoms is about 0.01 at % or more, the generation of hillocks of the metal layer LM may be prevented. Hillocks may be protrusions on the surface of the structure. The metal layer LM having a ratio of alloy atoms other than aluminum atoms of about 0.1 at % or less may maintain resistance and exhibit excellent light reflectivity. The metal layer LM may be a first emission layer EML-1 and a second emission layer EML-2 described above (see Figure 6 ) is configured to reflect light directed downward among the light generated by the metal layer LM. Accordingly, the higher the light reflectivity of the metal layer LM, the better the display quality.

[0116] If the ratio of alloy atoms is less than about 0.01at%, the heat resistance of the aluminum alloy is reduced, and hillocks may be generated under high temperature processes. The manufacturing process of the display panel DP may include a step of forming a pixel defining layer PDL after the step of forming the first electrode EL1, and the step of forming the pixel defining layer PDL may be performed at a high temperature of about 250°C or more. If the ratio of alloy atoms is less than about 0.01at%, the aluminum alloy is not suitable as the metal layer LM of the first electrode EL1 because hillocks may be generated under high temperature processes of about 250°C or more. If the ratio of alloy atoms is greater than about 0.1at%, the resistance of the metal layer LM may increase, and the light reflectivity of the metal layer LM may decrease. If the light reflectivity of the metal layer LM decreases, the light guided upward is reduced, thereby reducing the display quality.

[0117] The thickness of the metal layer LM may be in the range of about 60 nm to about 120 nm. For example, the thickness of the metal layer LM may be about 100 nm. A metal layer LM having a thickness greater than about 120 nm results in an increase in the size of aluminum particles and an increase in surface roughness. If the surface roughness increases, diffuse reflection occurs, and diffuse reflection results in degradation of display quality. In some aspects, a metal layer LM having a thickness greater than about 120 nm is not easily formed by dry etching and may not be patterned into a fine structure.

[0118] The metal layer LM having a thickness of less than about 60 nm may transmit light, and light directed upward may be reduced, thereby reducing display quality. In an embodiment, the metal layer LM having a thickness of about 60 nm to about 120 nm exhibits low transmittance and excellent light reflectivity, thereby improving display quality.

[0119] The first electrode EL1 may include a second layer L2 disposed between the first layer L1 and the metal layer LM. The second layer L2 may be a metal oxide layer formed by oxidizing a portion of the metal included in the metal layer LM. The second layer L2 may include, for example, aluminum oxide. The second layer L2 may be directly disposed between the first layer L1 and the metal layer LM. The second layer L2 may be directly disposed on the metal layer LM, and the first layer L1 may be directly disposed on the second layer L2. In some embodiments, in the present disclosure, if an element is directly disposed on other elements, it means that no third element is disposed between the one element and the other element. In other words, if an element is directly disposed on other elements, it means that the one element is in contact with the other element.

[0120] The second layer L2 may be a layer formed by oxidizing a portion of the metal included in the metal layer LM according to the contact between the metal layer LM and the preliminary layer for forming the first layer L1 during the formation process of the metal layer LM and the first layer L1. Since the preliminary layer for forming the first layer L1 is formed of indium tin oxide or the like, the second layer L2 may be an aluminum oxide layer formed by oxidizing a portion of the aluminum included in the metal layer LM. The thickness of the second layer L2 may be in the range of, for example, about 1 nm to about 5 nm. If the thickness of the second layer L2 is greater than about 5 nm, the light absorption rate may be high, the driving voltage of the first electrode EL1 may increase, and the display quality may be deteriorated.

[0121] exist Figure 7B In the figure, it is shown that Fig. 7A The first electrode EL1 of the embodiment shown in FIG. 1 is different from the shape of the first electrode EL1 ′ of the embodiment.

[0122] refer to Figure 7B The first electrode EL1' may include a plurality of conductive layers. The first electrode EL1' includes at least a first layer L1'. The first electrode EL1' may include, for example, a metal layer LM', a second layer L2' disposed on the metal layer LM', and a first layer L1' disposed on the second layer L2'.

[0123] Fig. 7A The first electrode EL1 and Figure 7B The shape of the first electrode EL1 ′ illustrated in FIG. 5 may vary depending on the order of processes of forming the metal layers LM and LM′, the second layers L2 and L2 ′, and the first layers L1 and L1 ′.

[0124] In an embodiment, the metal layer LM and the first layer L1 may be formed by forming a preliminary layer structure for forming the metal layer LM and the first layer L1, and then patterning the preliminary layer for forming the metal layer LM and the first layer L1 together. Fig. 7A, the first electrode EL1 is shown in the figure. That is, the metal layer LM and the first layer L1 may be simultaneously formed by etching. The second layer L2 may be an oxide layer formed by oxidizing a portion of the metal element included in the preliminary layer for forming the metal layer LM during the formation of the preliminary layer for forming the first layer L1. In the first electrode EL1 of the embodiment, the first layer L1 may completely overlap with the metal layer LM, and the first layer L1 may not overlap with the remaining area except for the area in which the metal layer LM is provided.

[0125] In another embodiment, the metal layer L-M' may be formed by forming a preliminary layer for forming the metal layer LM' and patterning it, and forming a preliminary layer for forming the first layer L1' on the patterned metal layer LM' and patterning it. Figure 7B , as shown in the figure, the first electrode EL1'. That is, the metal layer L-M' and the first layer L1' may be formed by etching using separate etching steps. The second layer L2' may be an oxide layer formed by oxidizing a portion of the metal elements included in the metal layer L-M' during the formation of a preliminary layer for forming the first layer L1'. In the first electrode EL1' of the embodiment, the first layer L1' may partially overlap with the metal layer L-M', and the remaining portion of the first layer L1' may not overlap with the metal layer L-M'. The remaining portion of the first layer L1' that does not overlap with the metal layer L-M' may be disposed on the circuit layer DP-CL.

[0126] Fig. 8A is a cross-sectional view of a partial configuration of a first electrode according to an embodiment supported by the present disclosure. Figure 8B is a plan view of a partial structure of a first electrode according to an embodiment supported by the present disclosure. Fig. 8A and Figure 8B , a shape according to a cross-sectional view and a shape according to a plan view of a portion of a first layer L1 included in a first electrode according to an embodiment supported by the present disclosure are schematically illustrated.

[0127] Reference together Fig. 7A and Fig. 8A , the first layer L1 included in the first electrode EL1 of the embodiment includes a first area A1 and a second area A2 adjacent to the first area A1.

[0128] The surface FS of the first layer L1 includes a first surface US1 corresponding to the first area A1 and a second surface US2 corresponding to the second area A2. In some embodiments, the surface FS of the first layer L1 may be Fig. 7A In some examples, the surface FS of the first layer L1 may be Figure 7BThe base layer BL on which the first layer L1 providing the surface FS is disposed may be an element providing a base surface on which the first layer L1 is disposed. For example, the base layer BL may be Fig. 7A The metal layer LM or the second layer L2 shown in the figure. The base layer BL can be Figure 7B The insulating layer included in the circuit layer DP-CL shown in the figure.

[0129] The first surface US1 and the second surface US2 may have an integral shape, but may be slightly different in their respective component contents and physical properties. In an embodiment, the indium content of the first surface US1 may be greater than the indium content of the second surface US2. In an embodiment, the surface roughness of the first surface US1 may be greater than the surface roughness of the second surface US2.

[0130] The first area A1 may correspond to a region where the aggregation pattern AP is formed in the step of etching the preliminary layer for forming the first layer L1 (see Fig. 12B ). The first surface US1 corresponding to the first area A1 may correspond to the area after forming the aggregation pattern AP (see Fig. 12B ) and may be a surface having higher surface roughness and higher indium content than the second surface US2 corresponding to the second area A2.

[0131] Reference together Fig. 8A and Figure 8B , the second area A2 may surround at least a portion of the first area A1. The first area A1 may be provided in plurality, and the second area A2 may surround at least a portion of each of the plurality of first areas A1. The first area A1 may include a plurality of first sub-areas SA1 spaced apart from each other. The second area A2 may surround each of the plurality of first sub-areas SA1. In some embodiments, Figure 8B In the figure, each of the plurality of first sub-regions SA1 included in the first area A1 is illustrated as a circular shape having the same size on a plane, but is not limited thereto, and each of the plurality of first sub-regions SA1 included in the first area A1 may have various shapes on a plane. In an embodiment, each of the plurality of first sub-regions SA1 may have a different size and various randomly formed shapes. The shape of each of the plurality of first sub-regions SA1 may correspond to the aggregation pattern AP formed in the step of etching the preliminary layer for forming the first layer L1 (see Fig. 12B ) shape.

[0132] Fig. 9is a cross-sectional view illustrating another embodiment supported by the present disclosure, and is a cross-sectional view illustrating a display panel DP-a. Fig. 9 In the description of Figures 1 to 8B The content described is a description of the content that is repeated, and the differences will be mainly explained.

[0133] and Figure 6 Compared with the display panel DP shown in the figure, Fig. 9 The display panel DP-a shown in FIG. 1 is different in that the light emitting element ED includes first to third light emitting elements ED-1, ED-2 and ED-3. Fig. 9 In the embodiment, the optical layer PP may include a polarizing layer or Figure 6 The first to third filters CF1, CF2 and CF3 are shown in the figure.

[0134] The first to third light emitting elements ED-1, ED-2, and ED-3 may be spaced apart in a second direction DR2 perpendicular to the thickness direction, and the thickness direction may be a direction parallel to the third direction DR3. Each of the first to third light emitting elements ED-1, ED-2, and ED-3 may include a first electrode EL1, a second electrode EL2 disposed on the first electrode EL1, and a functional layer FL-a disposed between the first electrode EL1 and the second electrode EL2. Figure 6 Compared with the functional layer FL shown in the figure, Fig. 9 The functional layer FL-a in FIG. 1 is different in that it includes a red emission layer EML-R, a green emission layer EML-G, and a blue emission layer EML-B that are patterned and provided in the pixel opening OH.

[0135] The first light-emitting element ED-1 may include a red emission layer EML-R and emit red light. The first light-emitting element ED-1 may be arranged corresponding to the red light-emitting region PXA-R. The second light-emitting element ED-2 may include a green emission layer EML-G and emit green light. The second light-emitting element ED-2 may be arranged corresponding to the green light-emitting region PXA-G. The third light-emitting element ED-3 may include a blue emission layer EML-B and emit blue light. The third light-emitting element ED-3 may be arranged corresponding to the blue light-emitting region PXA-B.

[0136] exist Fig. 9 In the embodiment, each of the first to third light-emitting elements ED-1, ED-2 and ED-3 includes one emission layer, but the embodiments of the present disclosure are not limited thereto. For example, each of the first to third light-emitting elements ED-1, ED-2 and ED-3 may include multiple emission layers that emit light within the same wavelength range.

[0137] The first electrode EL1 included in the display panel of the embodiment may be manufactured by a method of manufacturing an electrode of the embodiment which will be explained below.

[0138] Fig. 10A is a flow chart illustrating a method of manufacturing an electrode according to an embodiment supported by the present disclosure. Fig. 10B is a flow chart illustrating some steps in a method of manufacturing an electrode according to an embodiment supported by the present disclosure. Fig. 10B The diagram illustrates each step included in step S300 of etching a preliminary first layer to form a first layer in the method of manufacturing an electrode according to an embodiment supported by the present disclosure.

[0139] In the description of the methods and processes herein, the operations may be performed in an order different from the order shown and / or described, or may be performed in a different order or at a different time. Specific operations may also be excluded from these methods and processes, one or more operations may be repeated, or other operations may be added. According to the exemplary aspects described herein, descriptions of elements "may be set", "may be formed", and "may be etched", etc. include methods, processes, and techniques for setting, forming, positioning, and modifying elements, etc.

[0140] refer to Fig. 10A , the method of manufacturing an electrode according to an embodiment supported by the present disclosure includes: a step S100 of forming a preliminary first layer; a step S200 of forming a photoresist pattern having an opening portion formed therein on the preliminary first layer; and a step S300 of etching the preliminary first layer using the photoresist pattern as a mask to form a first layer. Accordingly, for example, the photoresist pattern formed at step S200 may include an opening portion, and at step S300, the method may include forming the first layer by etching the preliminary first layer using the photoresist pattern as a mask.

[0141] refer to Fig. 10B The step S300 of etching the preliminary first layer to form the first layer includes a first step S310 of providing a first plasma to the preliminary first layer and a second step S320 of providing a second plasma to the preliminary first layer after the first step.

[0142] FIG. 11A to FIG. 11C are cross-sectional views sequentially illustrating a method of manufacturing an electrode according to an embodiment supported by the present disclosure. FIG. 12A to FIG. 12C is a cross-sectional view illustrating some steps in a method of manufacturing an electrode according to an embodiment supported by the present disclosure. FIG. 12A to FIG. 12C , the diagram shows the steps included in the step of etching a preliminary first layer to form a first layer in the method of manufacturing an electrode according to an embodiment supported by the present disclosure.

[0143] refer to Fig. 10A , Fig.11A and Fig. 11B , the method of manufacturing an electrode according to an embodiment supported by the present disclosure includes a step S100 of forming a preliminary first layer L1-I and a step S200 of forming a photoresist pattern PRP having an opening portion OP-P formed therein on the preliminary first layer L1-I. For example, the formed photoresist pattern PRP may include an opening portion OP-P.

[0144] In an example, the preliminary first layer L1-I is formed of a transparent conductive oxide. In some examples, the preliminary first layer L1-I may be formed of a transparent conductive oxide containing indium. The preliminary first layer L1-I may be formed of, for example, indium tin oxide (ITO). In an alternative example, the preliminary first layer L1-I may include indium zinc oxide (IZO) or indium zinc tin oxide (IZTO). The preliminary first layer L1-I may be a single layer composed of a transparent conductive oxide containing indium. That is, the preliminary first layer L1-I may not include materials other than the transparent conductive oxide containing indium, and may have a single-layer structure that does not include multiple layers or sections in which a recognizable interface is defined.

[0145] The method may include forming a preliminary first layer L1-I on the preliminary metal layer L-MI. The method may include forming the preliminary metal layer L-MI from a conductive metal. The preliminary metal layer L-MI may be formed of, for example, aluminum. The preliminary metal layer L-MI may be formed of an aluminum alloy. The preliminary metal layer L-MI may be formed of an aluminum alloy consisting of aluminum atoms and alloy atoms. In some examples, the aluminum alloy may include one or more alloy atoms. The method may include using at least one of titanium (Ti), nickel (Ni) and lanthanum (La) as alloy atoms to form an aluminum alloy constituting the preliminary metal layer L-MI. For example, the method may include forming the preliminary metal layer L-MI from an alloy consisting of aluminum and titanium. In addition, the method may include forming the preliminary metal layer L-MI from an alloy consisting of aluminum, nickel and lanthanum.

[0146] In the process of forming the preliminary first layer L1-I on the preliminary metal layer L-MI, the method may include forming a preliminary second layer L2-I between the preliminary first layer L1-I and the preliminary metal layer L-MI. The preliminary second layer L2-I may be a layer formed by oxidizing a portion of the metal included in the preliminary metal layer L-MI through contact between the preliminary metal layer L-MI and the preliminary first layer L1-I. According to forming the preliminary first layer L1-I from indium tin oxide or the like, the preliminary second layer L2-I may be an aluminum oxide layer formed by oxidizing a portion of the aluminum included in the preliminary metal layer L-MI.

[0147] The method may include forming a photoresist pattern PRP on the preliminary first layer L1-I. The photoresist pattern PRP may be a pattern formed by exposing a portion of the photosensitive layer using a mask. The method may include using the photoresist pattern PRP as a mask pattern for etching the preliminary first layer L1-I. The method may include forming the photoresist pattern PRP using a positive photosensitive solution or a negative photosensitive solution.

[0148] Reference together Fig. 11B and Fig. 11C , the method may include dry etching the preliminary first layer L1-I. The method may include using the photoresist pattern PRP as a mask to dry-etch the preliminary first layer L1-I by plasma PS. In an example, the method may include using a first plasma (e.g., hydrogen (H 2 ) plasma) and a second plasma (e.g., argon (Ar) plasma) to dry etch the preliminary first layer L1-I. FIG. 12A to FIG. 12C In the explanation of , the process for dry etching the preliminary first layer L1-I will be explained in more detail. The method may include forming the first layer L1 by dry etching the preliminary first layer L1-I.

[0149] In the step of dry etching the preliminary first layer L1-I, the preliminary metal layer L-MI may also be etched to form the metal layer LM. That is, the method may include forming the metal layer LM and the first layer L1 together through one etching process. In the process of etching the preliminary first layer L1-I and the preliminary metal layer L-MI together, the method may further include etching the preliminary second layer L2-I to form the second layer L2. For example, the method may include etching the preliminary first layer L1-I, the preliminary metal layer L-MI, and the preliminary second layer L2-I in the same etching process.

[0150] Reference together Fig. 10B , Fig. 12A and Fig. 12B The step S300 of forming the first layer includes a first step S310 of providing a first plasma PS1 to the preliminary first layer L1-P1 and a second step S320 of providing a second plasma PS2 to the preliminary first layer L1-P2. The first plasma PS1 includes hydrogen (H 2 )plasma.

[0151] After the first step S310 of providing the first plasma PS1 to the preliminary first layer L1-P1, indium in the transparent conductive oxide included in the preliminary first layer L1-P1 aggregates and forms the aggregated pattern AP. In the first step S310 of providing the first plasma PS1, the transparent conductive oxide included in the preliminary first layer L1-P1 includes an indium element, and the indium oxide in the transparent conductive oxide included in the preliminary first layer L1-P1 can be heated by hydrogen (H 2 ) is metalized. Then, the shape of at least a portion of the metalized indium elements may change due to surface tension, etc., and an aggregation pattern AP in which the indium elements are aggregated may be formed. The aggregation pattern AP may have a shape protruding from the top of the preliminary first layer L1-P2. In some embodiments, Fig. 12B , the focusing pattern AP is illustrated in the cross-sectional view as having a semicircular shape, but the focusing pattern AP is not limited thereto. For example, the focusing pattern AP may protrude from the top of the preliminary first layer L1-P2 and may have various shapes supporting various aspects of the present disclosure.

[0152] In an example, the method may include performing the first step S310 for providing the first plasma PS1 to the preliminary first layer L1-P1 for more than about 30 seconds. The method may include, for example, performing the first step S310 within a duration range of about 30 seconds to about 200 seconds. If the first step S310 is performed for less than about 30 seconds, the time for providing the hydrogen plasma is insufficient, and thus the size of the aggregation pattern AP may not be sufficient, and this may reduce etching efficiency. If the first step S310 is performed for more than about 200 seconds, the process time may be excessively increased, which may reduce process efficiency.

[0153] In the first step S310, hydrogen (H 2 ) plasma can have a range from about 0.5×10 17 cm -2 to less than about 1.5×10 17 cm -2 The ion injection range of hydrogen (H 2 ) The ion injection of the plasma can be, for example, about 1.0×10 17 cm -2 In some aspects, hydrogen (H 2 ) The ion injection amount of the plasma can prevent damage to the preliminary first layer L1-P1 (for example, can prevent reduction in the film quality of the preliminary first layer L1-P1) and ensure high etching selectivity.

[0154] Fig.13Ais a graph illustrating an aggregation depth of an aggregation pattern and a strain rate of a photoresist pattern according to hydrogen ion capacity of hydrogen plasma in the first step S310. Fig.13A , it can be confirmed that the hydrogen ion capacity is less than about 1.5×10 17 cm -2 At the point where the strain rate of the photoresist pattern is small and less than about 10%, and the aggregation depth of the aggregation pattern is controlled to be less than about 100 nm, but if the hydrogen ion capacity is increased to about 1.5×10 17 cm -2 Above, the strain rate of the photoresist pattern increases. In particular, when the hydrogen ion capacity is about 2.9×10 17 cm -2 At the point where the aggregation depth of the aggregation pattern is excessively large to a degree of about 100 nm to about 200 nm, and the strain rate of the photoresist pattern increases to more than about 30%, it can be expected that defects such as damage to the film quality of the preliminary first layer L1-P1 may occur.

[0155] refer to Fig. 10B , Fig. 12A and Fig. 12B The aggregation of the indium element and the formation of the aggregation pattern AP after the first step S310 may result in a thickness t-I2 of the preliminary first layer L1-P2. The thickness t-I2 of the preliminary first layer L1-P2 may be less than the thickness t-I1 of the preliminary first layer L1-P1 before the first step S310.

[0156] exist Fig. 12B , the formation of one focusing pattern AP is illustrated as an example, but a plurality of focusing patterns AP may be formed in the first step S310 of providing the first plasma PS1.

[0157] Reference together Fig. 11B , Fig. 12B and Fig. 12C After forming the aggregation pattern AP, the method may include providing a second plasma PS2 to the preliminary first layer L1-P2 to etch the aggregation pattern AP. The aggregation pattern AP may be physically etched by the second plasma PS2. The second plasma PS2 may include a reactive gas having low reactivity with the transparent conductive oxide containing indium included in the preliminary first layer L1-P2. The second plasma PS2 may include a gas such as a gas containing nitrogen (N 2 ) gas as an example of an inert gas. The second plasma PS2 may include, for example, argon (Ar) plasma. Regarding the argon gas included in the second plasma PS2, the method may include providing the argon gas in an ion state and physically etching the aggregation pattern AP through a sputtering process.

[0158] The method may include etching and removing at least a portion of the aggregation pattern AP by an argon (Ar) plasma included in the second plasma PS2. Removing the aggregation pattern AP by the second plasma PS2 may provide a first layer L1 having a surface FS as a planar surface. As described herein, the first layer L1 includes a first area A1 and a second area A2 adjacent to the first area A1, and the surface FS of the first layer L1 includes a first surface US1 corresponding to the first area A1 and a second surface US2 corresponding to the second area A2. The first surface US1 and the second surface US2 have an integral shape, but may be slightly different in terms of the respective component contents and physical properties of the first surface US1 and the second surface US2. In an embodiment, the indium content of the first surface US1 may be greater than the indium content of the second surface US2. In an embodiment, the surface roughness of the first surface US1 may be greater than the surface roughness of the second surface US2.

[0159] The first area A1 may be an area corresponding to a portion where the aggregation pattern AP is formed after the first step S310. The first surface US1 corresponding to the first area A1 may correspond to a surface etched after the aggregation pattern AP is formed. The first surface US1 corresponds to a surface where the aggregation pattern AP formed by the aggregation of indium elements is etched, and the first surface US1 may be a surface having a larger indium content and a higher surface roughness than the second surface US2. The second surface US2 does not correspond to a portion where the indium elements are aggregated, and the second surface US2 may have a lower indium content than the first surface US1.

[0160] In some embodiments, the method may include removing a portion of the top of the preliminary first layer L1-P2 where the gathering pattern AP is not formed and removing the gathering pattern AP by etching through argon (Ar) plasma. Accordingly, the thickness t1 of the first layer L1 may be less than the thickness t-I2 of the preliminary first layer L1-P2.

[0161] The method may include performing a second step S320 for providing the second plasma PS2 to the preliminary first layer L1-P2 within a duration range of about 60 seconds to about 200 seconds. If the second step S320 is performed for less than about 60 seconds, the aggregation pattern AP may not be sufficiently removed, the etching efficiency may be reduced, and the layer quality of the first layer L1 may be deteriorated. If the second step S320 is performed for more than about 200 seconds, the process time may be excessively increased, which may reduce the process efficiency.

[0162] In the second step S320, the argon (Ar) plasma may have an ion energy of less than about 600 eV. The ion energy of the argon (Ar) plasma may be, for example, in the range of about 150 eV to less than about 600 eV. In some aspects, adjusting the ion energy of the argon (Ar) plasma according to the above range may prevent damage to the first layer L1 (for example, may prevent reduction in the film quality of the first layer L1) and ensure high etching selectivity.

[0163] Fig. 13B is a graph illustrating the strain rate of a photoresist pattern according to the ion energy of argon plasma. Fig. 13B , it can be confirmed that at the point where the ion energy of the argon plasma is less than about 600 eV, the change (%) in the strain rate of the photoresist pattern is relatively small and less than about 10%, but if the ion energy of the argon plasma increases to above about 600 eV, the strain rate of the photoresist pattern increases to above about 100%. In particular, at the point where the ion energy of the argon plasma is above about 700 eV, the strain rate of the photoresist pattern increases to above about 70%, and defects such as damage to the film quality of the first layer L1 are expected to be likely to occur. In some embodiments, in the method of manufacturing an electrode of an embodiment, the step S300 of forming the first layer may include performing each of the first step S310 and the second step S320 multiple times. As Fig. 11B In the step S300 of forming the first layer, since the first step S310 and the second step S320 are alternately performed, the formation process and the removal process of the aggregation pattern AP described above can be repeated, which can realize the first electrode EL1 to be formed (see Fig. 11C ) of the first layer L1 (see Fig. 11C ) structure.

[0164] In the method of manufacturing an electrode included in the display panel of the embodiment, manufacturing the first layer formed of a transparent conductive oxide containing indium may include providing hydrogen (H 2 ) plasma and a second step of providing argon (Ar) plasma. In the method for manufacturing an electrode of the embodiment, in the first step, the indium element contained in the transparent conductive oxide is metallized and aggregated to form an aggregated pattern, and in the second step, the aggregated pattern is etched by argon plasma, thereby improving etching efficiency, preventing the formation of a multilayer film structure, and shortening the process time.

[0165] In a conventional method of manufacturing an electrode, during the manufacturing of a first layer formed of a transparent conductive oxide, a recovery process is implemented by injecting oxygen atoms such as oxygen plasma to suppress the generation of hydrogen (H 2 ) plasma, or the conventional method may include limiting the ion flux. Accordingly, for example, due to the formation of a multilayer structure of an oxide layer, a metallization layer, and an oxide layer, the conventional method may cause defects, which may reduce the etching efficiency and significantly reduce the layer quality of the first layer. In particular, in the case of injecting oxygen atoms to suppress the formation of the aggregation pattern, a defect of oxidizing the metal layer provided under the first layer occurs, which significantly reduces the etching efficiency of the oxidized metal layer, and contamination of the interior of the reaction chamber by the oxidized metal particles may occur.

[0166] The method of manufacturing an electrode of the embodiment includes a first step in which the electrode is not inhibited from being heated by supplying hydrogen (H 2 ) plasma to form a collection pattern, and by providing hydrogen (H 2 ) plasma to form a clustered pattern. The method includes a second step in which the clustered pattern is removed by providing an inert gas plasma such as argon plasma, and the implantation process of oxygen atoms can be omitted. Accordingly, for example, the method can be implemented without limiting the ion flux in the etching process. Accordingly, defects caused by the influence of limited ion flux on etching efficiency can be prevented, or defects caused by the formation of an oxidized metal layer can be prevented, and therefore, in the method for manufacturing an electrode of an embodiment, etching efficiency can be improved and process time can be reduced.

[0167] Fig.14A and Fig. 14B is a microscope image illustrating states of some steps in a method of manufacturing an electrode according to an embodiment supported by the present disclosure. Fig.14A The diagram shows a method for providing hydrogen (H) to the preliminary first layer in the step of forming the first layer described above. 2 ) The first step of plasma ( Fig. 10B FIG. 5 is a diagram showing a microscope image observed from the side and a microscope image observed from the top over time in S310 of FIG. 5 . Fig. 14B FIG. 2 shows a second step ( Fig. 10B FIG. 5 is a diagram showing a microscope image observed from the side and a microscope image observed from the top over time in S320 of FIG. 5 .

[0168] refer to Fig.14A It can be confirmed that in the step of forming the first layer in the method for manufacturing an electrode of the embodiment ( Fig. 10AIn S300 of the present invention, a cluster pattern is formed on the indium tin oxide in the first step for providing hydrogen plasma, and the size of the cluster pattern increases as the process time increases. In particular, in the first step, it can be confirmed that a plurality of cluster patterns are formed after a process time of about 60 seconds, and the sizes of the cluster patterns greatly increase after about 180 seconds.

[0169] Afterwards, refer to Fig. 14B It can be confirmed that in the step of forming the first layer in the method for manufacturing an electrode of the embodiment ( Fig. 10A In S300 of FIG. 1 , the size of the clustered patterns formed on the indium tin oxide gradually decreases in the second step. In particular, in the second step, it can be confirmed that the size of these clustered patterns is greatly reduced as the process time of about 60 seconds passes.

[0170] In the electrode and the method for manufacturing the electrode according to the embodiment of the present disclosure, the method comprises providing hydrogen (H 2 ) plasma to form a gathering pattern and a second step to remove the gathering pattern by providing argon (Ar) plasma, and therefore, etching efficiency can be improved and process time can be shortened.

[0171] The display panel of the embodiment of the present disclosure includes the electrode manufactured by the manufacturing method and can show excellent manufacturing efficiency and manufacturing reliability.

[0172] Although the embodiments of the present invention have been described, it should be understood that the present invention should not be limited to the example embodiments, but a person skilled in the art may make various changes and modifications within the spirit and scope of the present invention as claimed.

Claims

1. An electrode comprising a first layer, the first layer comprising a transparent conductive oxide containing indium, wherein: The first layer includes a first region and a second region surrounding at least a portion of the first region, and An indium content of a surface of the first layer corresponding to the first region is greater than an indium content of a surface of the first layer corresponding to the second region.

2. The electrode according to claim 1, further comprising: The metal layer is disposed below the first layer and includes aluminum.

3. The electrode according to claim 2, further comprising: The second layer is disposed between the metal layer and the first layer and includes aluminum oxide.

4. The electrode according to claim 1, wherein The transparent conductive oxide includes indium tin oxide.

5. The electrode according to claim 1, wherein The surface roughness of the surface of the first layer corresponding to the first region is greater than the surface roughness of the surface of the first layer corresponding to the second region.

6. The electrode according to claim 1, wherein The first region includes a plurality of first sub-regions spaced apart from each other.

7. The electrode according to claim 6, wherein The second region surrounds each of the plurality of first sub-regions.

8. The electrode according to claim 1, wherein The first layer is provided as a single layer consisting of the transparent conductive oxide.

9. The electrode according to any one of claims 1 to 8, wherein The thickness of the first layer is in the range of 2 nm to 12 nm.

10. A display panel comprising a pixel defining layer and a light emitting element, wherein a pixel opening is defined in the pixel defining layer, wherein: The light emitting element includes a first electrode exposed through the pixel opening, a second electrode disposed on the first electrode, and at least one functional layer disposed between the first electrode and the second electrode. The first electrode includes a first layer including a transparent conductive oxide containing indium, The first layer includes a first region and a second region surrounding at least a portion of the first region, and An indium content of a surface of the first layer corresponding to the first region is greater than an indium content of a surface of the first layer corresponding to the second region.

11. The display panel according to claim 10, wherein: The first electrode further comprises: a metal layer disposed below the first layer and comprising aluminum; and The second layer is disposed between the metal layer and the first layer and includes aluminum oxide.

12. The display panel according to claim 10, wherein: The at least one functional layer comprises: A first emission layer that emits a first light; and The second emission layer is disposed on the first emission layer and emits second light different from the first light.

13. The display panel according to claim 10, wherein: The light emitting element includes a first light emitting element, a second light emitting element, and a third light emitting element spaced apart in a direction perpendicular to the thickness direction, and The first light emitting element emits red light, the second light emitting element emits green light, and the third light emitting element emits blue light.

14. A method for manufacturing an electrode, the method comprising: forming a preliminary first layer, the preliminary first layer comprising a transparent conductive oxide containing indium; forming a photoresist pattern on the preliminary first layer, wherein the photoresist pattern includes an opening portion; as well as forming a first layer by etching the preliminary first layer using the photoresist pattern as a mask, in: The forming of the first layer comprises: a first step of providing a first plasma comprising hydrogen plasma to the preliminary first layer; and a second step of providing a second plasma to the preliminary first layer after the first step, In the first step, the indium in the transparent conductive oxide is aggregated by the first plasma and forms an aggregated pattern, and The second plasma is provided in the second step to etch the aggregation pattern.

15. The method for manufacturing an electrode according to claim 14, wherein: Each of the first step and the second step is performed a plurality of times, and the first step and the second step are performed alternately.

16. The method for manufacturing an electrode according to claim 14, wherein: The first layer includes a first region and a second region surrounding at least a portion of the first region, and An indium content of a surface of the first layer corresponding to the first region is greater than an indium content of a surface of the first layer corresponding to the second region.

17. The method for manufacturing an electrode according to claim 16, wherein: The first region corresponds to a region where the aggregation pattern is formed in the first step.

18. The method for manufacturing an electrode according to claim 14, wherein: The first step of providing the first plasma is performed for more than 30 seconds.

19. The method for manufacturing an electrode according to any one of claims 14 to 18, further comprising: forming a preliminary metal layer containing aluminum before said forming of said preliminary first layer, Wherein, the preliminary first layer is formed on the preliminary metal layer.

20. The method for manufacturing an electrode according to claim 19, further comprising: The preliminary metal layer is etched to form a metal layer, wherein the etching of the preliminary metal layer is performed together with the etching of the preliminary first layer to form the first layer.

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