Liquid crystal display panel and display device

Abstract

The invention discloses a liquid crystal display panel and a display device. The liquid crystal display panel comprises an array substrate, an opposite substrate and a liquid crystal layer, the array substrate and the opposite substrate are oppositely arranged, the liquid crystal layer is arranged between the array substrate and the opposite substrate, the array substrate comprises a first substrate body and a plurality of pixel structures located on the first substrate body, and the opposite substrate comprises a second substrate body and an anti-overflow structure. The anti-overflow structure is arranged on the side, facing the array substrate, of the second substrate and is configured to prevent liquid crystal in the liquid crystal layer from overflowing. The liquid crystal display panel comprises a display area and a peripheral area surrounding the display area, the liquid crystal display panel further comprises frame sealing glue located in the peripheral area and arranged between the array substrate and the opposite substrate, and the anti-overflow structure surrounds the display area and is arranged on the side, close to the display area, of the frame sealing glue. After the liquid crystal liquid drops are dripped on the opposite substrate, the anti-overflow structure can prevent the liquid crystal from overflowing, the liquid crystal is prevented from diffusing to the boundary of the frame sealing glue and impacting the frame sealing glue, and the yield of products is improved.

Description

Liquid crystal display panel and display device

[0001] Embodiments of the present disclosure relate to a liquid crystal display panel and a display device.

[0002] In the field of display technology, liquid crystal display (LCD) has the advantages of lightness, thinness, low power consumption, high brightness and high image quality.

[0003] Typically, a thin film transistor liquid crystal display comprises an array substrate, an opposing substrate, a liquid crystal layer sandwiched between the array substrate and the opposing substrate, and a frame sealant for bonding the outer edges of the array substrate and the opposing substrate. The thin film transistor liquid crystal display can use the change in the electric field strength on the liquid crystal layer between the array substrate and the opposing substrate to change the orientation of the liquid crystal molecules in the liquid crystal layer, thereby controlling the intensity of light transmission to display images.

[0004] In recent years, the trend of miniaturization of display screens has become increasingly obvious. Small screens below 1 inch are commonly used in application scenarios such as scanning pens, e-cigarettes, and knobs. Under the premise of low cost, thin-film transistor liquid crystal displays can meet the requirements of small-screen product updates and improve product display effects.

[0005]

[0006] In order to solve the problem of normal box alignment caused by the diffusion of liquid crystal droplets in a miniaturized liquid crystal display panel, an embodiment of the present disclosure provides a liquid crystal display panel, and an anti-overflow structure is arranged on the opposing substrate of the liquid crystal display panel, which can prevent liquid crystal overflow and avoid liquid crystal diffusion to the boundary of the frame sealing glue, and can also buffer the impact of liquid crystal droplets on the frame sealing glue, improve the puncture problem, and improve the product yield.

[0007] At least one embodiment of the present disclosure provides a liquid crystal display panel, comprising an array substrate and an opposing substrate arranged opposite to each other, and a liquid crystal layer arranged between the array substrate and the opposing substrate, the array substrate comprising a first base substrate and a plurality of pixel structures located on the first base substrate, the opposing substrate comprising: a second base substrate; and an anti-overflow structure, which is arranged on a side of the second base substrate facing the array substrate and is configured to prevent liquid crystal in the liquid crystal layer from overflowing, the liquid crystal display panel comprising a display area and a peripheral area surrounding the display area, the liquid crystal display panel further comprising a frame sealing glue located in the peripheral area and arranged between the array substrate and the opposing substrate, the anti-overflow structure surrounds the display area, and is arranged on a side of the frame sealing glue close to the display area.

[0008] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, a maximum size of the display area of ​​the liquid crystal display panel on a plane parallel to the second base substrate is less than or equal to 30 mm.

[0009] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, on a plane parallel to the second base substrate, the distance between the anti-overflow structure and the display area ranges from 100μm to 300μm, and the distance between the anti-overflow structure and the frame sealing glue ranges from 100μm to 300μm.

[0010] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, the opposing substrate further includes a spacer, which is located in the display area and is arranged on a side of the second base substrate facing the array substrate, and the anti-overflow structure is configured to be formed by the same material and the same patterning process as the spacer.

[0011] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, the anti-overflow structure includes at least one anti-overflow cofferdam.

[0012] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, the anti-overflow dam includes a polygon on a plane parallel to the second substrate, and the anti-overflow dam includes a plurality of notches.

[0013] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, the anti-overflow dam includes a notch, the opposing substrate also includes an orientation layer, the orientation layer is arranged on the side of the second base substrate facing the array substrate, and has an orientation direction, and the notch is located at a position of the anti-overflow dam that is farthest from a center line of the display area in the orientation direction.

[0014] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, the anti-overflow cofferdam includes: a first anti-overflow cofferdam having a first opening; and a second anti-overflow cofferdam having a second opening, the first opening and the second opening are arranged relative to each other, the first anti-overflow cofferdam and the second anti-overflow cofferdam have an interlaced area, and in the interlaced area, the first anti-overflow cofferdam and the second anti-overflow cofferdam are spaced apart to form a channel.

[0015] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, the opposing substrate further includes an orientation layer, which is disposed on a side of the second base substrate facing the array substrate and has an orientation direction, and the staggered area is disposed at a position of the anti-overflow cofferdam that is farthest from a center line of the display area in the orientation direction.

[0016] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, the first anti-overflow cofferdam includes a first sub-portion and a second sub-portion that are relatively arranged, and a first connecting portion connecting the first sub-portion and the second sub-portion, the second anti-overflow cofferdam includes a third sub-portion and a fourth sub-portion that are relatively arranged, and a second connecting portion connecting the third sub-portion and the fourth sub-portion, the first sub-portion and the third sub-portion have an interlaced area and are spaced apart to form a channel, and the second sub-portion and the fourth sub-portion have an interlaced area and are spaced apart to form a channel.

[0017] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, the anti-overflow dam includes a plurality of first anti-overflow parts and a plurality of second anti-overflow parts, and in a direction perpendicular to the second substrate, the size of the first anti-overflow part is larger than the size of the second anti-overflow part, and in an extension direction of the anti-overflow dam, the first anti-overflow parts and the second anti-overflow parts are alternately arranged.

[0018] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, in a direction perpendicular to the second base substrate, a height difference between the first anti-overflow portion and the second anti-overflow portion ranges from 0.5 μm to 0.65 μm.

[0019] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, the opposing substrate further includes a planarization layer, and the planarization layer is arranged on a side of the second base substrate facing the array substrate, and the anti-overflow structure includes at least one anti-overflow groove formed in the planarization layer and recessed toward the second base substrate.

[0020] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, the depth of the anti-overflow groove ranges from 0.5 μm to 1.5 μm, and the width of the anti-overflow groove ranges from 200 μm to 400 μm.

[0021] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, the opposing substrate further includes: an electrostatic release layer, which is arranged on the side of the second base substrate facing the array substrate, the sealing frame is at least partially connected to the electrostatic release layer, and the sealing frame is configured to have conductivity so that the electrostatic release layer is connected to the array substrate through the sealing frame.

[0022] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, the array substrate further includes a common electrode layer, which is arranged on the side of the first base substrate facing the opposing substrate, the common electrode layer includes a common electrode located in the display area and a conductive structure located in the peripheral area, and the frame sealing glue is at least partially connected to the conductive structure.

[0023] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, the array substrate further includes a first common electrode line surrounding the display area and a second common electrode line surrounding the first common electrode line, the first common electrode line is connected to the second common electrode line, the first common electrode line is connected to the common electrode, the second common electrode line is connected to a signal input port of the liquid crystal display panel, and the array substrate further includes a via, and the second common electrode line is connected to the conductive structure through the via.

[0024] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, an orthographic projection of the frame sealant on the first base substrate at least partially overlaps with an orthographic projection of the second common electrode line on the first base substrate, and the second common electrode line includes a metal grid line.

[0025] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, the array substrate also includes a first common electrode line surrounding the display area and a second common electrode line surrounding the first common electrode line, the first common electrode line is connected to the second common electrode line, the first common electrode line is connected to the common electrode of the display area, the second common electrode line is connected to a first signal input port of the liquid crystal display panel to be provided with a first voltage signal, and the conductive structure is connected to a second signal input port of the liquid crystal display panel through a lead to be provided with a second voltage signal.

[0026] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, on a plane parallel to the second base substrate, the conductive structure is located on a side of the second common electrode line away from the display area, and on a side of the second common electrode line close to the input port of the liquid crystal display panel.

[0027] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, the difference between the first voltage signal and the second voltage signal ranges from 0 to 3 volts.

[0028] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, the plurality of pixel structures are arranged along a first direction and a second direction, the second direction intersecting with the first direction, and in the pixel structure, the common electrode includes a plurality of first slits extending along the first direction and arranged along the second direction, and the electrostatic release layer includes a plurality of electrostatic release parts corresponding to the plurality of pixel structures, each of the electrostatic release parts including a plurality of second slits extending along the first direction and arranged along the second direction.

[0029] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, in the pixel structure, the plurality of second slits are arranged at equal intervals, and in the second direction, the ratio of the size between two adjacent second slits to the size of the second slit is in the range of 1.0-1.5.

[0030] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, in the pixel structure, the plurality of first slits are arranged in one-to-one correspondence with the plurality of second slits, and in the second direction, the first slits and the second slits arranged in correspondence with each other have the same size.

[0031] For example, in a liquid crystal display panel provided in an embodiment of the present disclosure, in the pixel structure, the array substrate further includes a block pixel electrode, and the block pixel electrode is located between the second base substrate and the common electrode layer.

[0032] For example, in the liquid crystal display panel provided in one embodiment of the present disclosure, the opposing substrate also includes: a black matrix layer, arranged on the side of the second base substrate facing the array substrate; a color film layer, arranged on the side of the second base substrate facing the array substrate; and a planarization layer, arranged on the side of the black matrix layer and the color film layer facing the array substrate, and the anti-overflow structure is arranged on the side of the planarization layer facing the array substrate.

[0033] At least one embodiment of the present disclosure provides a liquid crystal display panel including any one of the above-mentioned ones.

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0035] Figure 1 is a schematic diagram of the diffusion of a 0.2 mg liquid crystal droplet;

[0036] FIG2 is a schematic cross-sectional view of a liquid crystal display panel provided by an embodiment of the present disclosure;

[0037] FIG3 is a schematic diagram of an anti-overflow structure of an opposing substrate provided by an embodiment of the present disclosure;

[0038] FIG4 is a schematic diagram of another anti-overflow structure of an opposing substrate provided by an embodiment of the present disclosure;

[0039] FIG5 is a schematic diagram of another anti-overflow structure of an opposing substrate provided by an embodiment of the present disclosure;

[0040] FIG6 is a schematic cross-sectional view of the liquid crystal display panel shown in FIG5 ;

[0041] FIG7 is a schematic diagram of another anti-overflow cofferdam of an opposing substrate provided by an embodiment of the present disclosure;

[0042] FIG8 is a schematic diagram of another anti-overflow structure of an opposing substrate provided by an embodiment of the present disclosure;

[0043] FIG9 is a schematic diagram of another anti-overflow structure of an opposing substrate provided by an embodiment of the present disclosure;

[0044] FIG10 is a schematic diagram of another anti-overflow structure of an opposing substrate provided by an embodiment of the present disclosure;

[0045] FIG. 11A is a schematic diagram of another anti-overflow cofferdam provided by an embodiment of the present disclosure;

[0046] FIG11B is a partial schematic diagram of the anti-overflow cofferdam shown in FIG11A ;

[0047] FIG12 is a schematic diagram of another anti-overflow cofferdam provided by an embodiment of the present disclosure;

[0048] FIG13 is a schematic diagram of another anti-overflow structure of an opposing substrate provided by an embodiment of the present disclosure;

[0049] FIG14 is a schematic diagram of another anti-overflow structure of an opposing substrate provided by an embodiment of the present disclosure;

[0050] FIG15 is a schematic diagram of static electricity on an opposing substrate of a liquid crystal display panel;

[0051] FIG16 is a cross-sectional schematic diagram of a liquid crystal display panel provided in one embodiment of the present disclosure;

[0052] FIG17 is a schematic diagram of a partial structure of a liquid crystal display panel of FIG16 ;

[0053] FIG18 is a partial enlarged view of FIG17 at position A and position B;

[0054] FIG19 is a partial enlarged view of FIG17 at position C and position D;

[0055] FIG20 is a partial enlarged view of FIG17;

[0056] FIG21 is a cross-sectional schematic diagram of the conductive layers of FIG17 being connected;

[0057] FIG22 is a partial enlarged view of FIG17 at position E;

[0058] FIG23 is a schematic cross-sectional view of FIG22 ;

[0059] FIG24 is a schematic diagram of an electric field of a liquid crystal display panel;

[0060] FIG25 is a schematic diagram of a partial structure of another liquid crystal display panel of FIG16;

[0061] FIG26 is a partial enlarged schematic diagram of FIG25;

[0062] FIG27 is a partial enlarged view of FIG25 at position F and position G;

[0063] FIG28 is a partial enlarged view of FIG25 at position J;

[0064] FIG29 is a partial enlarged view of FIG25 at position K;

[0065] FIG30 is a schematic cross-sectional view of FIG28;

[0066] FIG31 is a partial cross-sectional schematic diagram of another liquid crystal display panel provided by an embodiment of the present disclosure;

[0067] FIG32 is a schematic top view of a portion of a pixel structure corresponding to FIG31 ;

[0068] FIG33 is a partial cross-sectional schematic diagram of another liquid crystal display panel 100 provided in one embodiment of the present disclosure;

[0069] FIG34 is a schematic top view of a portion of a pixel structure corresponding to FIG33 ;

[0070] FIG35 is a partial cross-sectional schematic diagram of another liquid crystal display panel provided by an embodiment of the present disclosure;

[0071] FIG36 is a partial top view schematic diagram of a pixel structure corresponding to FIG35 ;

[0072] FIG37 is a light effect diagram of two solutions of the embodiment of the present disclosure at the L255 gray scale;

[0073] FIG38 is a schematic diagram of a simulation of liquid crystal deflection of the liquid crystal display panel shown in FIG31 at gray scale L0;

[0074] FIG39 is a light effect diagram of the liquid crystal display panel shown in FIG35 at the L255 gray scale;

[0075] FIG40 is a schematic diagram of a liquid crystal deflection simulation of the liquid crystal display panel shown in the figure at the L255 gray scale;

[0076] FIG41 is a schematic diagram of a display device provided by an embodiment of the present disclosure; and

[0077] FIG. 42 is a flow chart of a method for manufacturing a liquid crystal display panel provided in accordance with an embodiment of the present disclosure.

[0078] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0079] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0080] Unless otherwise defined, the features such as "parallel", "perpendicular" and "same" used in the embodiments of the present disclosure include the situations of "parallel", "perpendicular", "same" in a strict sense, as well as the situations of "approximately parallel", "approximately perpendicular", "approximately the same", etc., which contain certain errors. For example, the above-mentioned "approximately" may mean that the difference of the compared objects is within 10% or 5% of the average value of the compared objects. When the number of a component or element is not specifically indicated in the following text of the embodiments of the present disclosure, it means that the component or element may be one or more, or may be understood as at least one. "At least one" refers to one or more, and "multiple" refers to at least two. The "same-layer arrangement" in the embodiments of the present disclosure refers to the relationship between multiple film layers formed by the same material after the same step (for example, a one-step patterning process). The "same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same.

[0081] Currently, there are very few miniaturized TFT-LCD displays of 1 inch or less in the market, and the market for TFT-LCD displays between 0.4 and 0.8 inches is in a blank stage, with no product channels available.

[0082] There are many problems to overcome in the production process of miniaturized LCDs. In the One Drop Filling (ODF) stage, the liquid crystal dripping equipment cannot drip accurately because the amount of liquid crystal in the product is too small, and the liquid tension will also limit the dripping speed. The position accuracy of the liquid crystal droplet, the upper limit of the number of stable dripping, the accuracy of the dripping amount, the dripping time, etc. all require a lot of testing and verification.

[0083] Typically, the process of the liquid crystal dripping stage of a miniaturized thin-film transistor liquid crystal display is to drip the liquid crystal on the array substrate, apply the sealing glue on the opposing substrate, and then perform the box alignment in a vacuum environment, and finally release the atmospheric pressure to enter the cutting stage. Taking the development of a product with a size of 0.42 inches as an example, Figure 1 is a schematic diagram of the diffusion of a 0.2mg liquid crystal droplet. As shown in Figure 1, the diffusion diameter D01 of the liquid crystal droplet (about 0.2mg) on ​​the array substrate of this product before the box alignment is about 9mm, which has exceeded the minimum inner spacing D02 (about 6.4mm) of the sealing frame in the liquid crystal box.

[0084] During the liquid crystal dripping stage, for example, if the liquid crystal droplet is 0.2mg / dot, a piece of glass with a size of 1300mm*1100mm needs more than 10,000 cuts. If the liquid crystal is dripped completely, the first dripped droplet has spread beyond the area of ​​the panel's sealing frame, making it impossible to assemble the panel normally. In addition, the smaller the size of the thin-film transistor liquid crystal display, the greater the impact of the liquid crystal droplet on the sealing frame glue when the array substrate and the counter substrate are assembled, which will bring the risk of poor puncture and even lead to the risk of the sealing frame glue penetrating and breaking.

[0085] In this regard, the embodiments of the present disclosure provide a liquid crystal display panel and a display device. The liquid crystal display panel includes an array substrate and an opposing substrate that are arranged opposite to each other, and a liquid crystal layer arranged between the array substrate and the opposing substrate, the array substrate includes a first substrate substrate and a plurality of pixel structures located on the first substrate substrate, the opposing substrate includes a second substrate substrate and an anti-overflow structure, the anti-overflow structure is arranged on a side of the second substrate substrate facing the array substrate, and is configured to prevent liquid crystal in the liquid crystal layer from overflowing. The liquid crystal display panel includes a display area and a peripheral area surrounding the display area, the liquid crystal display panel also includes a frame sealant located in the peripheral area and arranged between the array substrate and the opposing substrate, the anti-overflow structure surrounds the display area, and is arranged on a side of the frame sealant close to the display area.

[0086] In the liquid crystal display panel provided by the embodiment of the present disclosure, an anti-overflow structure is provided on the opposing substrate, and the anti-overflow structure is provided on the side of the frame sealant close to the display area. After the liquid crystal droplets are injected on the opposing substrate, the anti-overflow structure can prevent the liquid crystal from overflowing, prevent the liquid crystal from diffusing to the boundary of the frame sealant, and prevent the diffusion of the liquid crystal from affecting the alignment of the array substrate and the opposing substrate. In addition, the anti-overflow structure can also buffer the impact of the liquid crystal droplets on the frame sealant, improve the puncture problem, and improve the product yield.

[0087] The liquid crystal display panel and the display device provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0088] An embodiment of the present disclosure provides a liquid crystal display panel. FIG2 is a cross-sectional schematic diagram of a liquid crystal display panel provided by an embodiment of the present disclosure. As shown in FIG2, the liquid crystal display panel 100 includes an array substrate 110 and an opposing substrate 120 arranged opposite to each other, and a liquid crystal layer 130 arranged between the array substrate 110 and the opposing substrate 120, the array substrate 110 includes a first base substrate 111 and a plurality of pixel structures located on the first base substrate 111, the opposing substrate 120 includes a second base substrate 121 and an anti-overflow structure 122, the anti-overflow structure 122 is arranged on the side of the second base substrate 121 facing the array substrate 110, and is configured to prevent the liquid crystal in the liquid crystal layer 130 from overflowing. The liquid crystal display panel 100 includes a display area AA and a peripheral area BB surrounding the display area AA, the liquid crystal display panel 100 also includes a sealant 140 located in the peripheral area BB and arranged between the array substrate 110 and the opposing substrate 120, the anti-overflow structure 122 surrounds the display area AA, and is arranged on the side of the sealant 140 close to the display area AA.

[0089] In the liquid crystal display panel 100 provided in the embodiment of the present disclosure, an anti-overflow structure 122 is provided on the opposing substrate 120, and the anti-overflow structure 122 is provided on the side of the frame-sealing glue 140 close to the display area AA. After the liquid crystal droplets are dripped on the opposing substrate 120, the anti-overflow structure 122 can prevent the liquid crystal from overflowing, prevent the liquid crystal from diffusing to the boundary of the frame-sealing glue 140, and prevent the diffusion of the liquid crystal from affecting the alignment of the array substrate 110 and the opposing substrate 120. In addition, the anti-overflow structure 122 can also buffer the impact of the liquid crystal droplets on the frame-sealing glue 140, improve the puncture problem, and improve the yield rate of the product. It should be noted that the anti-overflow structure 122 is used to prevent the liquid crystal from overflowing during the liquid crystal dripping (ODF, One Drop Filling) stage, so that the array substrate 110 and the opposing substrate 120 can be normally aligned.

[0090] In the present disclosure, the pixel structure on the array substrate 110 includes a pixel driving circuit and a pixel electrode. For example, the pixel driving circuit can be connected to the pixel electrode to load a pixel driving signal to control the deflection of the liquid crystal. For example, multiple pixel structures correspond to multiple sub-pixels to achieve different colors of light-emitting display. In some examples, the pixel structure also includes a common electrode for generating an electric field with the pixel electrode.

[0091] In some examples, the maximum size of the display area AA of the liquid crystal display panel 100 on a plane parallel to the second base substrate 121 is less than or equal to 30 mm. The smaller the area of ​​the display area AA of the liquid crystal display panel 100, the smaller the distance between the liquid crystal and the sealant 140 is due to the size of the entire liquid crystal display panel 100, and the liquid crystal is more likely to overflow to the sealant 140; and the smaller the area of ​​the display area AA, the smaller the number of liquid crystal droplets, for example, the number of liquid crystal droplets may be only 1 or 2 drops, and if the liquid crystal dripping stage is completed, the first dripped droplet may have spread to the sealant 140. Therefore, for a small-sized liquid crystal display panel 100, an anti-overflow structure 122 is more needed to prevent liquid crystal from overflowing and avoid liquid crystal from spreading to the boundary of the sealant 140. In addition, the smaller the size of the liquid crystal display panel 100, the greater the impact of the liquid crystal droplets on the sealant 140, and it is more necessary to set an anti-overflow structure 122 to reduce the impact of the liquid crystal droplets on the sealant 140 and improve the puncture problem.

[0092] For example, the display area AA of the liquid crystal display panel 100 may be a rectangle, and the length of the diagonal of the rectangle is less than or equal to 30 mm. For example, the display area AA of the liquid crystal display panel 100 may be a circle, and the diameter of the circle is less than or equal to 30 mm.

[0093] In some examples, as shown in FIG. 2 , on a plane parallel to the second base substrate 121 , the distance D1 between the anti-overflow structure 122 and the display area AA ranges from 100 μm to 300 μm, thereby preventing the alignment layer from accumulating on the anti-overflow structure 122 due to the small distance between the two, preventing the anti-overflow structure 122 from affecting the alignment layer, and avoiding the resulting uneven display.

[0094] In some examples, as shown in FIG. 2 , the distance D2 between the anti-overflow structure 122 and the sealant 140 is in the range of 100 μm-300 μm on a plane parallel to the second base substrate 121. Thus, the sealant 140 can be prevented from accumulating on the anti-overflow structure 122 due to the small distance between the two caused by the fluctuation of the coating accuracy of the sealant 140, thereby preventing the thickness of the peripheral area BB of the liquid crystal display panel 100 from becoming larger and preventing the display from yellowing.

[0095] In some examples, as shown in FIG. 2 , the counter substrate 120 further includes a spacer 123, the spacer 123 is located in the display area AA and is disposed on the side of the second base substrate 121 facing the array substrate 110, and the anti-overflow structure 122 is configured to be formed by the same material and the same patterning process as the spacer 123. The anti-overflow structure 122 and the spacer 123 are formed by the same material and the same patterning process, so that the formation of the anti-overflow structure 122 does not require additional process steps and production costs. For example, as shown in the figure, the anti-overflow structure 122 and the spacer 123 formed by the same material and the same patterning process have the same cross-section.

[0096] In some examples, as shown in FIG2 , the spacer 123 includes a main spacer 1231 and an auxiliary spacer 1232, and in a direction perpendicular to the second base substrate 121, the height of the main spacer 1231 is greater than the height of the auxiliary spacer 1232. When the anti-overflow structure 122 and the spacer 123 are formed by the same material and the same patterning process, the height of the anti-overflow structure 122 can be the same as the height of the main spacer 1231, and can also be the same as the height of the auxiliary spacer 1232.

[0097] In some examples, as shown in FIG2 , the anti-overflow structure 122 includes an anti-overflow weir 1221. The anti-overflow structure 122 is configured as a weir to more effectively prevent the overflow of liquid crystal. Of course, the embodiment of the present disclosure does not limit the height of the anti-overflow weir 1221 in a direction perpendicular to the second base substrate 121, and can be designed according to the size and process requirements of the product.

[0098] In some examples, when the total volume of the liquid crystal in the liquid crystal layer 130 accounts for a large volume of the display area, for example, when the inner spacing of the sealant 140 is less than 6 mm, the height of the anti-overflow cofferdam 1221 can be set higher in the direction perpendicular to the second base substrate 121. The higher anti-overflow cofferdam 1221 can ensure that the liquid crystal will not overflow, and the anti-puncture ability is also stronger. For example, the anti-overflow cofferdam 1221 can be the same height as the main spacer 1231. When the total volume of the liquid crystal in the liquid crystal layer 130 accounts for a moderate volume of the display area, for example, when the inner spacing of the sealant 140 is greater than 6 mm, the height of the anti-overflow cofferdam 1221 can be moderate in the direction perpendicular to the second base substrate 121. For example, the anti-overflow cofferdam 1221 can be the same height as the auxiliary spacer 1232, so that the BB gap in the peripheral area caused by the accumulation of the sealant 140 on the anti-overflow structure 122 can be reduced to the greatest extent possible, and the resulting yellowing of the display can be avoided. The display area volume component refers to the product of the area of ​​the display area AA and the cell thickness after the array substrate 110 and the counter substrate 120 are assembled.

[0099] In addition, the anti-overflow cofferdam 1221 has a moderate height or is the same as the height of the auxiliary spacer 1232, which can also make the liquid crystal droplets have better fluidity after dripping onto the opposing substrate 120, so that the liquid crystal is more evenly filled in the display area AA, avoiding the formation of vacuum bubbles after the array substrate 110 and the opposing substrate 120 are assembled.

[0100] FIG3 is a schematic diagram of an anti-overflow structure of an opposing substrate provided in an embodiment of the present disclosure. As shown in FIG3 , the anti-overflow structure 122 includes a closed structure surrounding the display area AA, so that the anti-overflow structure 122 can effectively prevent the overflow of liquid crystal. In this example, the display area AA of the liquid crystal display panel 100 is rectangular.

[0101] In some examples, as shown in FIG3 , the liquid crystal display panel 100 is rectangular, the inner spacing of the sealant 140 of the liquid crystal display panel 100 is 6.4 mm and 10.2 mm respectively, and the liquid crystal droplet of the liquid crystal display panel 100 dripping onto the opposite substrate 120 is 0.2 mg. Therefore, the overflow prevention structure 122 in any of the above embodiments can effectively prevent the overflow of liquid crystal and the impact on the sealant 140.

[0102] FIG4 is a schematic diagram of another anti-overflow structure of an opposing substrate provided in an embodiment of the present disclosure. As shown in FIG4 , the anti-overflow structure 122 includes a closed structure surrounding the display area AA, so that the anti-overflow structure 122 can effectively prevent the overflow of liquid crystal. In this example, the display area AA of the liquid crystal display panel 100 is circular. Of course, the embodiment of the present disclosure does not limit the shape of the display area AA of the liquid crystal display panel 100. For example, the display area AA can also be elliptical, polygonal or irregular, and the shape of the anti-overflow structure 122 can follow the shape of the display area AA.

[0103] FIG5 is a schematic diagram of another anti-overflow structure of an opposing substrate provided in an embodiment of the present disclosure; FIG6 is a cross-sectional schematic diagram of the liquid crystal display panel shown in FIG5. As shown in FIG5 and FIG6, the liquid crystal display panel 100 includes two circles of anti-overflow structure 122, and the two circles of anti-overflow structure 122 are closed structures. Of course, the embodiment of the present disclosure does not limit the number of circles of the anti-overflow structure 122.

[0104] In some examples, as shown in Figures 5 and 6, the sizes of the multi-circle anti-overflow structure 122 may be the same in a direction perpendicular to the second base substrate 121. Of course, the sizes of the multi-circle anti-overflow structure 122 may also be different in a direction perpendicular to the second base substrate 121.

[0105] In some examples, as shown in FIG. 6 , the width D3 of the multi-circle anti-overflow structure 122 ranges from 50 μm to 150 μm.

[0106] FIG7 is a schematic diagram of another anti-overflow cofferdam of an opposing substrate provided in an embodiment of the present disclosure. As shown in FIG7 , the display area AA of the liquid crystal display panel 100 is rectangular, and the anti-overflow cofferdam 1221 is roughly a rectangle surrounding the display area AA on a plane parallel to the second base substrate 121, and the display area AA includes two oppositely arranged long sides and two oppositely arranged short sides, and the anti-overflow cofferdam 1221 includes two notches 1222, and the two notches 1222 of the anti-overflow structure 122 are arranged on the side where the short side of the display area AA is located. The notch 1222 of the anti-overflow cofferdam 1221 on the short side is far away from the center of the display area AA. The notch 1222 on the short side can effectively prevent the overflow of liquid crystal, and can also improve the fluidity of the liquid crystal toward the short side far away from the center of the display area, so that the liquid crystal is more evenly filled in the display area AA, and the vacuum bubble is avoided after the array substrate 110 and the opposing substrate 120 are boxed.

[0107] For example, as shown in FIG7 , the two notches 1222 of the anti-overflow structure 122 can be arranged at the center of the side where the short side of the display area AA is located. When the array substrate 110 and the counter substrate 120 are assembled, the liquid crystal is squeezed and diffuses toward the periphery. Compared with arranging the notch 1222 at the edge of the side where the short side is located, arranging the notch 1222 at the center of the side where the short side is located is more conducive to uniform diffusion of the liquid crystal to avoid vacuum bubbles after assembly.

[0108] For example, the notch 1222 shown in FIG. 7 penetrates the anti-overflow cofferdam 1221 in a direction perpendicular to the second base substrate 121 . However, the notch 1222 may not penetrate the anti-overflow cofferdam 1221 in a direction perpendicular to the second base substrate 121 .

[0109] For example, as shown in FIG7 , the position where the liquid crystal droplets flow toward the opposing substrate 120 is at the center of the display area AA, and the distance between the position and the short side is greater than the distance between the position and the long side. By providing a notch 1222 at the center of the side where the short side is located, the liquid crystal can be effectively prevented from overflowing, and the fluidity of the liquid crystal droplets diffusing toward the short side can be improved. Of course, the embodiment of the present disclosure does not limit the position and number of the notches 1222, and verification can be performed based on the size of the actual product and the number and position of the droplets to determine the optimal position and number of the notches 1222.

[0110] For example, there are multiple positions where the liquid crystal droplets flow toward the opposing substrate 120, at least one of which is not at the center of the display area AA, and the distance between the position and the long side is greater than the distance between the position and the short side, so that the notch 1222 can be set on the side where the long side of the display area AA is located. For example, multiple notches 1222 can be set on the side where the long side is located to increase the fluidity of the liquid crystal droplets.

[0111] The embodiment of the present disclosure does not limit the number, shape and position of the notches 1222 on the anti-overflow cofferdam 1221. For example, the anti-overflow cofferdam 1221 may include a plurality of notches 1222, the anti-overflow cofferdam 1221 includes a polygon on a plane parallel to the second substrate 121, and the plurality of notches 1222 are arranged at the center of the plurality of sides of the anti-overflow cofferdam 1221. For example, the number of notches 1222 of the anti-overflow cofferdam 1221 is half the number of sides of the anti-overflow cofferdam 1221. For example, the plurality of notches 1222 are arranged opposite to each other.

[0112] In some examples, as shown in Fig. 7, the dimension D4 of the notch 1222 in the extension direction of the anti-overflow cofferdam 1221 may account for 15% to 25% of the length of the side where the notch 1222 is located. Of course, the embodiment of the present disclosure is not limited to this, and the optimal value can be obtained by testing and verification based on actual products.

[0113] FIG8 is a schematic diagram of another anti-overflow structure of an opposing substrate provided by an embodiment of the present disclosure. As shown in FIG8 , the anti-overflow cofferdam 1221 includes a plurality of notches 1222, and the plurality of notches 1222 are respectively arranged on the side where the long sides of the display area AA of the anti-overflow cofferdam 1221 are located, and the plurality of notches 1222 are also arranged at the four corners of the display area AA, so as to better improve the fluidity of the liquid crystal droplets.

[0114] FIG9 is a schematic diagram of another anti-overflow structure of an opposing substrate provided by an embodiment of the present disclosure. As shown in FIG9 , the opposing substrate 120 further includes an orientation layer, which is arranged on the side of the second base substrate 121 facing the array substrate 110 and has an orientation direction a1. The display area AA has a center line a2 passing through the center in the orientation direction a1, and the notch 1222 is located at the position of the anti-overflow cofferdam 1221 that is farthest from the center line a2. In the figure, the shape of the anti-overflow cofferdam 1221 is rectangular, and the notch 1222 is located at the center position of the side of the anti-overflow cofferdam 1221 that is farthest from the center line a2. For example, when the shape of the anti-overflow cofferdam 1221 is circular, the notch 1222 is located at the position of the anti-overflow cofferdam 1221 that is farthest from the center line a2. In this example, the fluidity of the liquid crystal is related to the orientation direction a1 of the orientation layer. The fluidity of the liquid crystal along the orientation direction a1 is better than the fluidity of the liquid crystal perpendicular to the orientation direction a1. Setting a notch 1222 at the position farthest from the center line a2 on the orientation direction a1 can improve the fluidity of the liquid crystal perpendicular to the orientation direction a1.

[0115] The embodiment of the present disclosure does not limit the position of the alignment layer, which may be located on the side of the spacer 123 facing the array substrate 110 , or between the spacer 123 and the second base substrate 121 .

[0116] FIG10 is a schematic diagram of another anti-overflow structure of a counter substrate provided by an embodiment of the present disclosure. As shown in FIG10 , the anti-overflow cofferdam 1221 includes a first anti-overflow cofferdam 1223 and a second anti-overflow cofferdam 1224, the first anti-overflow cofferdam 1223 has a first opening 1223a, and the second anti-overflow cofferdam 1224 has a second opening 1224a. The first opening 1223a and the second opening 1224a are arranged opposite to each other, and the first anti-overflow cofferdam 1223 and the second anti-overflow cofferdam 1224 have a staggered area, and in the staggered area, the first anti-overflow cofferdam 1223 and the second anti-overflow cofferdam 1224 are arranged at intervals to form a channel a3. When the liquid crystal display panel 100 is relatively small, for example, when the inner spacing of the frame sealant 140 is less than 9 mm, referring to FIG. 1 , the diffusion range of the liquid crystal droplets is greater than the inner spacing of the frame sealant 140. In this case, there is a risk of overflow even if the gap 1222 on the anti-overflow cofferdam 1221 is set at the position farthest from the center. By setting the first anti-overflow cofferdam 1223 and the second anti-overflow cofferdam 1224, the two have staggered areas and are spaced apart to form a channel a3, thereby improving the fluidity of the liquid crystal through the channel a3 and avoiding the overflow of the liquid crystal through the staggered areas, thereby avoiding the diffusion problem of the liquid crystal as much as possible.

[0117] In some examples, as shown in FIG. 10 , the display area AA has a center line a2 passing through the center in the orientation direction a1, and the staggered area is arranged at the position of the anti-overflow cofferdam 1221 that is farthest from the center line a2. In the figure, the shape of the anti-overflow cofferdam 1221 is roughly rectangular, and the staggered area is located at the center of the side of the anti-overflow cofferdam 1221 that is farthest from the center line a2. For example, when the shape of the anti-overflow cofferdam 1221 is circular, the staggered area is located at the position of the anti-overflow cofferdam 1221 that is farthest from the center line a2. In this example, the fluidity of the liquid crystal is related to the orientation direction a1 of the orientation layer. The fluidity of the liquid crystal along the orientation direction a1 is better than the fluidity of the liquid crystal perpendicular to the orientation direction a1. The staggered area is arranged at the position farthest from the center line a2 on the orientation direction a1, which can improve the fluidity of the liquid crystal perpendicular to the orientation direction a1.

[0118] In some examples, as shown in FIG10 , the first anti-overflow cofferdam 1223 includes a first sub-portion 1223b and a second sub-portion 1223c disposed oppositely, and a first connecting portion 1223d connecting the first sub-portion 1223b and the second sub-portion 1223c, and the second anti-overflow cofferdam 1224 includes a third sub-portion 1224b and a fourth sub-portion 1224c disposed oppositely, and a second connecting portion 1224d connecting the third sub-portion 1224b and the fourth sub-portion 1224c. The first sub-portion 1223b and the third sub-portion 1224b have an interlaced area and are spaced to form a channel a3, and the second sub-portion 1223c and the fourth sub-portion 1224c have an interlaced area and are spaced to form a channel a3.

[0119] FIG. 11A is a schematic diagram of another anti-overflow cofferdam provided by an embodiment of the present disclosure; FIG. 11B is a partial schematic diagram of the anti-overflow cofferdam shown in FIG. 11A. As shown in FIG. 11A and FIG. 11B, the anti-overflow cofferdam 1221 includes a plurality of first anti-overflow portions 1225 and a plurality of second anti-overflow portions 1226. In the direction perpendicular to the second substrate 121, the size of the first anti-overflow portion 1225 is larger than the size of the second anti-overflow portion 1226. In the extension direction a4 of the anti-overflow cofferdam 1221, the first anti-overflow portion 1225 and the second anti-overflow portion 1226 are alternately arranged. By alternately arranging the first anti-overflow portion 1225 and the second anti-overflow portion 1226, the overflow of the liquid crystal can be avoided and the fluidity of the liquid crystal can be improved. The embodiment of the present disclosure does not limit the number, height, and length of the first anti-overflow portion 1225 and the second anti-overflow portion 1226 along the extension direction a4 of the anti-overflow cofferdam 1221, and can be designed and matched according to the size of the liquid crystal display panel 100 and the orientation direction a1 of the alignment layer.

[0120] For example, the height of the first anti-overflow portion 1225 may be the same as the height of the main spacer 1231 , and the height of the second anti-overflow portion 1226 may be the same as the height of the auxiliary spacer 1232 .

[0121] In some examples, as shown in FIG. 12 , in the direction Z perpendicular to the second base substrate 121 , a difference D5 between the height of the first anti-overflow portion 1225 and the height of the second anti-overflow portion 1226 ranges from 0.5 μm to 0.65 μm.

[0122] In some examples, along the extension direction a4 of the anti-overflow cofferdam 1221, the length of the first anti-overflow portion 1225 is greater than 15 μm, and the length of the second anti-overflow portion 1226 is greater than 15 μm, so that the first anti-overflow portion 1225 and the second anti-overflow portion 1226 that are staggered with each other can have more obvious size characteristics, can better avoid the overflow of liquid crystal, and can also better improve the fluidity of liquid crystal.

[0123] FIG12 is a schematic diagram of another anti-overflow cofferdam provided by an embodiment of the present disclosure. As shown in FIG12, one set of opposite sides of the anti-overflow cofferdam 1221 is a first anti-overflow portion 1225, and the other set of opposite sides is a second anti-overflow portion 1226. The two adjacent sides of the anti-overflow cofferdam 1221 are respectively the first anti-overflow portion 1225 and the second anti-overflow portion 1226. The multiple sides of the anti-overflow cofferdam 1221 can be set to different heights in combination with the size of the liquid crystal display panel 100, the position of the liquid crystal droplets, and the alignment direction a1 of the alignment layer, so as to prevent the liquid crystal from overflowing and improve the fluidity of the liquid crystal.

[0124] For example, as shown in FIG12 , the side of the anti-overflow cofferdam 1221 perpendicular to the alignment direction a1 is the first anti-overflow portion 1225, and the side of the anti-overflow cofferdam 1221 parallel to the alignment direction a1 is the second anti-overflow portion 1226, which can ensure the fluidity of the liquid crystal and prevent the liquid crystal from overflowing. For example, the side of the anti-overflow cofferdam 1221 perpendicular to the alignment direction a1 can have the same height as the main spacer 1231, and the side of the anti-overflow cofferdam 1221 parallel to the alignment direction a1 can have the same height as the auxiliary spacer 1232.

[0125] In some examples, as shown in FIG. 2 , the counter substrate 120 further includes a black matrix layer 124, a color filter layer 125, and a planarization layer 126. The black matrix layer 124 is disposed on the side of the second base substrate 121 facing the array substrate 110, the color filter layer 125 is disposed on the side of the second base substrate 121 facing the array substrate 110, and the planarization layer 126 is disposed on the side of the black matrix layer 124 and the color filter layer 125 facing the array substrate 110. The spacer 123 and the anti-overflow cofferdam 1221 are disposed on the side of the planarization layer 126 close to the array substrate 110.

[0126] In some examples, as shown in FIG. 2 , the counter substrate 120 may further include a peripheral spacer 1233 located in the peripheral area BB and surrounding the display area AA, the peripheral spacer 1233 being a columnar structure, and the peripheral spacer 1233 being disposed on the side of the planarization layer 126 facing the array substrate 110. For example, the peripheral spacer 1233 is configured to be formed by the same material and the same patterning process as the spacer 123. Thus, the formation of the peripheral spacer 1233 does not require additional process steps and production costs. For example, in a direction perpendicular to the second base substrate 121, the height of the peripheral spacer 1233 may be the same as the height of the main spacer 1231.

[0127] In some examples, as shown in FIG2 , the color filter layer 125 is located on the side of the anti-overflow structure 122 close to the display area AA. For example, the color filter layer 125 is also located on the side of the peripheral spacer 1233 close to the display area AA. Thus, the thickness of the peripheral area BB may be prevented from increasing due to the superposition of the color filter layer 125, thereby preventing problems such as yellowing of the display.

[0128] In some examples, the material of the planarization layer 126 may be photoresist. Of course, the embodiment of the present disclosure does not limit the material of the planarization layer 126. For example, the planarization layer 126 may also be other functional layers on the opposing substrate 120.

[0129] In some examples, as shown in FIG2 , the counter substrate 120 may be a black matrix layer 124, a color filter layer 125, and a planarization layer 126 formed sequentially on a second base substrate 121, and then a spacer 123 and an anti-overflow cofferdam 1221 are formed by using the same material through the same patterning process. For example, a conductive layer may be formed on the side of the second base substrate 121 away from the array substrate 110 to release static electricity on the side of the counter substrate 120 away from the array substrate 110.

[0130] FIG13 is a schematic diagram of another anti-overflow structure of an opposing substrate provided in an embodiment of the present disclosure. As shown in FIG13 , the opposing substrate 120 further includes a planarization layer 126, and the planarization layer 126 is arranged on the side of the second base substrate 121 facing the array substrate 110, and the anti-overflow structure 122 includes an anti-overflow groove 1227 formed in the planarization layer 126 and recessed toward the second base substrate 121. The anti-overflow groove 1227 can carry a certain volume of liquid crystal, which can effectively prevent the liquid crystal from diffusing into the sealant 140, and can also prevent the liquid crystal from impacting the sealant 140, thereby improving the puncture problem and improving the yield rate of the product. In addition, the design of the anti-overflow groove 1227 can make the liquid crystal droplets have good fluidity, so that the liquid crystal is better filled in the display area AA. For example, the planarization layer 126 can be the outermost layer of the opposing substrate 120 facing the array substrate 110.

[0131] In some examples, as shown in FIG. 13 , the anti-overflow groove 1227 may be a closed structure surrounding the display area AA, thereby more effectively preventing the liquid crystal from diffusing into the sealant 140 and better preventing the liquid crystal from impacting the sealant 140 .

[0132] In some examples, as shown in FIG13 , the depth D6 of the anti-overflow groove 1227 ranges from 0.5 μm to 1.5 μm, and the width D7 of the anti-overflow groove 1227 ranges from 200 μm to 400 μm. By properly setting the depth D6 and width D7 of the anti-overflow groove 1227, the anti-overflow groove 1227 can have a larger carrying volume.

[0133] In some examples, as shown in FIG13 , the depth D6 of the anti-overflow groove 1227 may be 40% to 60% of the thickness of the planarization layer 126. According to the actual product and the material and thickness of the planarization layer 126, the depth D6 of the anti-overflow groove 1227 may be reasonably designed and verified to allow the anti-overflow groove 1227 to have a larger carrying volume.

[0134] In some examples, as shown in FIG13 , the counter substrate 120 further includes a black matrix layer 124 and a color filter layer 125, and the black matrix layer 124 and the color filter layer 125 are located between the second base substrate 121 and the planarization layer 126. For example, the counter substrate 120 may further include a peripheral spacer, which may be specifically referred to as shown in FIG2 and will not be described in detail herein.

[0135] In some examples, as shown in FIG13 , the color filter layer 125 is located on a side of the anti-overflow structure 122 close to the display area AA, so that the anti-overflow groove 1227 can have a larger bearing volume.

[0136] In some examples, as shown in FIG13 , the material of the planarization layer 126 may be photoresist. Of course, the disclosed embodiment does not limit the material of the planarization layer 126. For example, the planarization layer 126 may also be other functional layers on the opposing substrate 120, which also have a planarization function.

[0137] The disclosed embodiment does not limit the material of the anti-overflow structure 122 . For example, the material of the anti-overflow structure 122 may be the same as that of the color filter layer 125 , the same as that of the planarization layer 126 , or the same as that of the conductive layer on the opposing substrate 120 .

[0138] It is worth noting that although the above embodiments respectively show the case where the anti-overflow structure is an anti-overflow cofferdam and an anti-overflow groove, the embodiments of the present disclosure include but are not limited to this, and the anti-overflow structure may include an anti-overflow cofferdam and an anti-overflow groove at the same time. Figure 14 is a schematic diagram of an anti-overflow structure of another opposing substrate provided in an embodiment of the present disclosure. As shown in Figure 14, the anti-overflow structure of the opposing substrate of the liquid crystal display panel includes an anti-overflow cofferdam and an anti-overflow groove. For example, the anti-overflow groove is arranged on the side of the anti-overflow cofferdam close to the display area. Thus, the liquid crystal display panel can have the beneficial technical effects of the anti-overflow groove and the beneficial technical effects of the anti-overflow cofferdam at the same time, which will not be repeated here. The anti-overflow cofferdam of the liquid crystal display panel can be any of the anti-overflow cofferdams described above, and the anti-overflow groove of the liquid crystal display panel can be any of the anti-overflow grooves shown above.

[0139] FIG15 is a schematic diagram of static electricity on a counter substrate of a liquid crystal display panel. As shown in FIG15 , if there is no metal on the side of the counter substrate 12 facing the array substrate 11, the static electricity on the counter substrate 12 cannot be diffused and is easily accumulated, as shown by the arrows circled by the dotted line in the figure. In particular, the display area of ​​a miniaturized liquid crystal display panel is small, and the liquid crystal between the counter substrate 12 and the array substrate 11 is more susceptible to static electricity, resulting in abnormal initial orientation of the liquid crystal, resulting in uneven display, and also reducing the contrast and transmittance of the liquid crystal display panel.

[0140] FIG16 is a cross-sectional schematic diagram of a liquid crystal display panel provided by an embodiment of the present disclosure. As shown in FIG16, the opposing substrate 120 of the liquid crystal display panel 100 further includes an electrostatic release layer 127, and the electrostatic release layer 127 is arranged on the side of the second base substrate 121 facing the array substrate 110. The frame sealant 140 is at least partially connected to the electrostatic release layer 127, and the frame sealant 140 is configured to have conductivity so that the electrostatic release layer 127 is connected to the array substrate 110 through the frame sealant 140.

[0141] In the liquid crystal display panel 100 of the embodiment of the present disclosure, liquid crystal droplets are dripped onto the counter substrate 120, and an anti-overflow structure 122 is provided on the counter substrate 120. The anti-overflow structure 122 can prevent the liquid crystal from overflowing and the impact of the liquid crystal on the sealant 140. An electrostatic release layer 127 is formed on the counter substrate 120, and the electrostatic release layer 127 is connected to the array substrate 110 through the conductive sealant 140, so that the static electricity on the counter substrate 120 can be released through the electrostatic release layer 127, so that the static electricity on the counter substrate 120 can be prevented from affecting the liquid crystal dripped onto the counter substrate 120, and the abnormal orientation of the liquid crystal can be prevented, thereby improving the display performance of the liquid crystal display panel 100.

[0142] It should be noted that the embodiment of the present disclosure does not limit the form of the anti-overflow structure 122, which can be any of the anti-overflow structures 122 described above. The embodiment of the present disclosure does not limit the structure or film layer setting of the opposing substrate 120, which can be any of the opposing substrates 120 described above.

[0143] In some examples, as shown in FIG. 16 , the electrostatic release layer 127 may be a conductive layer disposed on a whole layer of the counter substrate 120. For example, on a plane parallel to the second base substrate 121, the size of the electrostatic release layer 127 may be the same as the size of the second base substrate 121. A large-area electrostatic release layer 127 can diffuse the static electricity on the counter substrate 120, and is not prone to large-scale accumulation and poor display. In addition, a whole layer of electrostatic release layer 127 does not require mask costs, and can also reduce costs. Of course, the embodiment of the present disclosure does not limit the shape of the electrostatic release layer 127. It can be a whole layer, or it can be hollowed out at the position corresponding to the pixel structure, and can be designed according to the performance requirements of the actual product.

[0144] For example, the material of the electrostatic release layer 127 may be a transparent conductive material, for example, the material of the electrostatic release layer 127 may be indium tin oxide.

[0145] For example, the thickness of the electrostatic release layer 127 ranges from

[0146] For example, the frame sealant 140 may contain conductive gold balls or silver balls to have conductivity.

[0147] In some examples, as shown in FIG. 16 , the array substrate 110 of the liquid crystal display panel 100 further includes a common electrode layer 116, which is disposed on the side of the first base substrate 111 facing the counter substrate 120, and includes a common electrode 1161 located in the display area AA and a conductive structure 1162 located in the peripheral area BB, and the sealant 140 is at least partially connected to the conductive structure 1162. Thus, the static electricity release layer 127 can be connected to the conductive structure 1162 of the common electrode layer 116 through the conductive sealant 140 to release static electricity on the counter substrate 120.

[0148] In this embodiment, the pixel structure on the array substrate 110 includes a common electrode 1161, a pixel electrode 117, and a driving transistor TFT. For example, the driving transistor TFT may be connected to the pixel electrode 117 to achieve deflection of liquid crystal.

[0149] Fig. 17 is a schematic diagram of a partial structure of a liquid crystal display panel of Fig. 16. As shown in Figs. 16 and 17, the array substrate 110 of the liquid crystal display panel 100 further includes a first common electrode line 118 surrounding the display area AA and a second common electrode line 119 surrounding the first common electrode line 118, the first common electrode line 118 is connected to the second common electrode line 119, the first common electrode line 119 is connected to the common electrode 1161 of the display area AA, the second common electrode line 119 is connected to the signal input port 190 of the liquid crystal display panel 100, and the array substrate 110 further includes a via hole, and the second common electrode line 119 is connected to the conductive structure 1162 through the via hole. In this example, the electrostatic release layer 127 is connected to the second common electrode line 119 through the conductive sealant 140 and the conductive structure 1162 of the common electrode layer 116 in sequence, and the second common electrode line 119, the first common electrode line 118 and the common electrode 1161 of the display area AA are connected, so that the electrostatic release layer 127 and the common electrode 1161 of the display area AA have the same voltage signal, and there is no vertical electric field between the electrostatic release layer 127 and the common electrode 1161 of the display area AA, thereby further avoiding the influence of the potential difference between the electrostatic release layer 127 and the common electrode 1161 on the liquid crystal deflection. Moreover, the electrostatic release layer 127 is connected to the second common electrode line 119, and no additional circuit design is required. The liquid crystal display panel shown in Figure 17 is described in detail below.

[0150] FIG18 is a partial enlarged view of FIG17 at position A and position B; FIG19 is a partial enlarged view of FIG17 at position C and position D; FIG20 is a partial enlarged view of FIG17; and FIG21 is a cross-sectional schematic diagram of the conductive layers connected in FIG17. As shown in FIG17 to FIG21, the first common electrode line 118 and the second common electrode line 119 are connected at position A, position B, position C and position D.

[0151] In some examples, as shown in FIG. 16 and FIG. 21 , the array substrate 110 of the liquid crystal display panel 100 includes a first conductive layer 112 disposed on a side of the first base substrate 111 facing the opposite substrate 120 and a second conductive layer 114 disposed on a side of the first conductive layer 112 facing the opposite substrate 120, and the first conductive layer 112 and the second conductive layer 114 are located between the first base substrate 111 and the common electrode layer 116. A first insulating layer 113 is disposed between the first conductive layer 112 and the second conductive layer 114, and a second insulating layer 115 is disposed between the second conductive layer 114 and the common electrode layer 116. For example, the first conductive layer 112 is disposed in the same layer as the gate layer in the pixel structure of the display area AA, the second conductive layer 114 is disposed in the same layer as the source and drain conductive layer in the pixel structure, the first insulating layer 113 may be a gate insulating layer, and the second insulating layer 115 may be a passivation layer.

[0152] In some examples, as shown in FIGS. 17 , 18 , 20 , and 21 , at position A and position B, the second common electrode line 119 is connected to the first common electrode line 118 through the lead line L1. The second common electrode line 119 and the lead line L1 are located in the first conductive layer 112, the upper side 1183 and the lower side 1184 of the first common electrode line 118 are located in the first conductive layer 112, and the left side 1181 and the right side 1182 of the first common electrode line 118 are located in the second conductive layer 114. The upper side 1183 and the lower side 1184 of the first common electrode line 118 are connected to the common electrode layer 116 through the via hole H1, and the left side 1181 and the right side 1182 of the first common electrode line 118 are connected to the common electrode layer 116 through the via hole H2, so that the first common electrode line 118 is connected to the common electrode 1161 of the display area AA. The lead L1 of the second common electrode line 119 is connected to the common electrode layer 116 through the via H1, so that the first common electrode line 118 and the second common electrode line 119 are connected, and the first common electrode line 118, the second common electrode line 119 and the common electrode 1161 of the display area AA have the same voltage signal. Of course, the embodiment of the present disclosure does not limit the conductive layer where the first common electrode line 118 and the second common electrode line 119 are located.

[0153] It should be noted that Figure 21 only schematically shows that the first conductive layer 112 and the common electrode layer 116 are connected through the via H1, and the second conductive layer 114 and the common electrode layer 116 are connected through the via H2. It does not limit the position and number of the via H1 and the via H2, nor does it limit the routing on the first conductive layer 112 and the second conductive layer 114. The required number of vias are set at the corresponding positions according to different routings, connection positions and sizes of positions.

[0154] In some examples, as shown in FIGS. 17 , 19 and 21 , the first common electrode line 118 further includes a connection line 1180 extending from the display area AA, and the connection line 1180 may be located in the first conductive layer 112. At position C and position D, since there are other signal lines between the first common electrode line 118 and the second common electrode line 119, in order to avoid other signal lines, the second common electrode line 119 is connected to the first common electrode line 118 through the common electrode layer 116, the second common electrode line 119 located in the first conductive layer 112 is connected to the common electrode layer 116 through the via hole H1, and the first common electrode line 118 located in the first conductive layer 112 is connected to the common electrode layer 116 through the via hole H1, so that the first common electrode line 118 and the second common electrode line 119 are connected.

[0155] In some examples, as shown in FIG. 17 , the second common electrode line 119 is connected to the signal input port 190 of the liquid crystal display panel 100 in the binding region CC, so that a common voltage signal can be provided to the common electrode 1161 and the electrostatic release layer 127 through the second common electrode 1161 .

[0156] Fig. 22 is a partial enlarged view of Fig. 17 at position E; Fig. 23 is a cross-sectional schematic diagram of Fig. 22. As shown in Fig. 17, Fig. 22 and Fig. 23, the second common electrode line 119 located in the first conductive layer 112 is connected to the conductive structure 1162 of the common electrode layer 116 through the via H1, so that the electrostatic release layer 127 is connected to the second common electrode line 119, and further, the electrostatic release layer 127 and the common electrode 1161 of the display area AA have the same voltage signal.

[0157] In some examples, as shown in FIG17 , in the area surrounded by the outermost boundary of the sealant 140, the shape of the conductive structure 1162 can be the same as the shape of the second common electrode line 119, so that the second common electrode line 119 can be better connected to the conductive structure 1162 and the sealant 140. Of course, the embodiment of the present disclosure does not limit the shape of the conductive structure 1162, as long as the conductive structure 1162 can achieve the connection between the second common electrode line 119 and the sealant 140.

[0158] In some examples, as shown in FIGS. 17 , 18 and 22 , the second common electrode lines 119 may be metal grid lines, so that the area where the orthographic projection of the sealant 140 on the first base substrate 111 overlaps with the orthographic projection of the metal grid lines on the first base substrate 111 has better transmittance, which facilitates the curing of the sealant 140. Of course, the present disclosure does not limit the form of the second common electrode lines 119.

[0159] In the embodiment of the present disclosure, the first common electrode line 118 and the second common electrode line 119 are connected, however, the first common electrode line 118 and the second common electrode line 119 may not be connected, and the first common electrode line 118 may be connected to the signal port of the liquid crystal display panel 100 to provide a common voltage signal to the first common electrode line 118, and the common voltage signal may be the same as the voltage signal of the second common electrode line 119, so that the electrostatic release layer 127 and the common electrode 1161 may have the same voltage signal. The embodiment of the present disclosure does not limit the connection form and connection position of the first common electrode line 118 and the second common electrode line 119.

[0160] Figure 24 is a schematic diagram of the electric field of a liquid crystal display panel. As shown in Figure 24, the conductive layer 13 on the inner side of the counter substrate 120 will form a vertical electric field ② and other coupled electric fields with the pixel electrode 14 on the array substrate 11, which will interfere with the electric field ① between the common electrode 15 driving the liquid crystal deflection and the pixel electrode 14, and ultimately cause the pixel transmittance to decrease.

[0161] FIG25 is a schematic diagram of a partial structure of another liquid crystal display panel of FIG16; FIG26 is a schematic diagram of a partial enlargement of FIG25. As shown in FIG16, FIG25 and FIG26, the array substrate 110 further includes a first common electrode line 118 surrounding the display area AA and a second common electrode line 119 surrounding the first common electrode line 118, the first common electrode line 118 is connected to the second common electrode line 119, the first common electrode line 118 is connected to the common electrode 1161 of the display area AA, the second common electrode line 119 is connected to the first signal input port 1901 of the liquid crystal display panel 100 to be provided with a first voltage signal, and the conductive structure 1162 is connected to the second signal input port 1902 of the liquid crystal display panel 100 through the lead line L2 to be provided with a second voltage signal.

[0162] In this example, the electrostatic release layer 127 is sequentially connected to the second signal input port 1902 through the conductive sealant 140, the conductive structure 1162 of the common electrode layer 116, and the lead L2 to be provided with a second voltage signal, and the common electrode 1161 of the display area AA is sequentially connected to the first signal input port 1901 through the first common electrode line 118 and the second common electrode line 119 to be provided with a first voltage signal, so that the electrostatic release layer 127 and the common electrode 1161 can be provided with voltage signals respectively to separately control the electrostatic release layer 127 and the common electrode 1161. For example, different or the same voltage signals can be set through software simulation to improve performance such as transmittance or contrast.

[0163] For example, the difference between the first voltage signal and the second voltage signal has a value range of 0-3 V. Of course, the first voltage signal and the second voltage signal and their difference are not limited in the embodiment of the present disclosure, and different voltage signals can be matched according to factors such as the size, structural design, cost and user needs of the actual product to meet the requirements.

[0164] FIG27 is a partial enlarged view of FIG25 at position F and position G. As shown in FIG25 and FIG27, the first common electrode line 118 and the second common electrode line 119 are connected at position F, position G, position H and position I, and the connection method of the four positions is the same as that of the embodiment of FIG17, and the partial enlarged view of position H and position I is the same as that of FIG19, and the description thereof will not be repeated. In addition, the connection method of the first common electrode line 118 and the common electrode 1161 of the display area AA is also the same as that of the embodiment of FIG17, and the description thereof will not be repeated. Of course, the embodiments of the present disclosure are not limited to the above-mentioned connection method, and can be adaptively adjusted according to the actual wiring situation.

[0165] FIG28 is a partial enlarged view of FIG25 at position J. As shown in FIG25 and FIG28, different from the partial enlarged view at position E in FIG22, the second common electrode line 119 located in the first conductive layer 112 of this embodiment is not connected to the conductive structure 1162 of the common electrode layer 116 through the via H1, so that the second common electrode line 119 is not connected to the electrostatic release layer 127.

[0166] In some examples, as shown in FIGS. 25, 27, and 28, the second common electrode line 119 may be a metal grid line, so that the area where the orthographic projection of the sealant 140 on the first base substrate 111 overlaps with the orthographic projection of the second common electrode line 119 on the first base substrate 111 has better transmittance, which facilitates the curing of the sealant 140. Of course, the present disclosure does not limit the form of the second common electrode line 119.

[0167] FIG29 is a partial enlarged view of FIG25 at position K; FIG30 is a cross-sectional schematic diagram of FIG28. As shown in FIG25, FIG26, FIG29 and FIG30, the conductive structure 1162 located in the common electrode layer 116 is connected to the first conductive layer 112 through the via H1, the first conductive layer 112 is provided with a lead L2 and a second signal input port 1902 of the liquid crystal display panel 100, and the electrostatic release layer 127 is connected to the second signal input port 1902 through the conductive sealant 140, the conductive structure 1162, and the lead L2 of the first conductive layer 112 in sequence to be provided with a second voltage signal, so that the electrostatic release layer 127 can be controlled separately. Of course, the embodiment of the present disclosure does not limit the conductive layer where the lead L2 is located, and does not limit the shape of the conductive structure 1162 and the number of vias H2.

[0168] In some examples, as shown in FIG. 25 and FIG. 26 , on a plane parallel to the second base substrate 121 , the conductive structure 1162 is located on a side of the second common electrode line 119 away from the display area AA, and is located on a side of the second common electrode line 119 close to the signal input port of the liquid crystal display panel 100, so that the conductive structure 1162 and the lead L2 can be arranged more conveniently. Of course, the embodiment of the present disclosure does not limit the position and extension trend of the conductive structure 1162 and the lead L2, and can be reasonably arranged and designed according to the actual product. For example, as shown in FIG. 25 and FIG. 26 , the lead L2 can extend roughly along the second common electrode line 119 to the second signal input port 1902.

[0169] 25 and 26, the second signal input port 1902 is closer to the end of the binding area CC than the first signal input port 1901. Of course, the embodiment of the present disclosure does not limit the positions of the first signal input port 1901 and the second signal input port 1902, and they can be reasonably arranged and designed according to actual products.

[0170] FIG31 is a partial cross-sectional schematic diagram of another liquid crystal display panel provided by an embodiment of the present disclosure; FIG32 is a partial top view schematic diagram of a pixel structure in FIG31. As shown in FIG31 and FIG32, the opposing substrate 120 of the liquid crystal display panel is provided with a whole layer of electrostatic release layer 127, and the electrostatic release layer 127 may have the same voltage signal as the common electrode 1161 on the array substrate 110, or may have a different voltage signal from the common electrode 1161 on the array substrate 110. In this embodiment, a whole layer of electrostatic release layer 127 can disperse and extract charges to the greatest extent to avoid affecting the liquid crystal.

[0171] In some examples, as shown in FIG. 31 , the array substrate 110 further includes a plurality of pixel electrodes 117 , the plurality of pixel electrodes 117 correspond to the plurality of common electrodes 1161 , and the pixel electrodes 117 of the pixel structure may be block-shaped pixel electrodes.

[0172] The display performance of the liquid crystal display panel 0 with a whole layer of electrostatic release layer and the liquid crystal display panel without the electrostatic release layer is simulated and analyzed. When the liquid crystal display panel without the electrostatic release layer simulates the L255 transmittance, the voltage V3 of the pixel electrode is 98% of the working voltage, and the voltage V3 is 4.1V; when simulating the L0 transmittance, the voltage V3 of the pixel electrode is 0% of the working voltage, and the voltage V3 is 0V; when simulating the L127 grayscale, the voltage V3 of the pixel electrode is 2.36V. In this embodiment, the electrostatic release layer and the common electrode have the same voltage signal.

[0173] According to simulation verification, at the L0 grayscale, the transmittance of the liquid crystal display panel is reduced by 0.56% after adding the electrostatic release layer compared to when no electrostatic release layer is provided. Therefore, the liquid crystal display panel is darker in the normally black mode after adding the static release layer. At the L127 grayscale, the voltage of the pixel electrode is reduced from 2.36V to 2.12V, thereby reducing power consumption. At the L255 grayscale, the transmittance of the liquid crystal display panel has a relatively large loss, which is reduced by 40.4%. Therefore, setting a whole layer of electrostatic release layer can be used in products that do not require high transmittance but have high requirements on appearance and energy consumption.

[0174] FIG33 is a partial cross-sectional schematic diagram of another liquid crystal display panel 100 provided by an embodiment of the present disclosure; FIG34 is a partial top view schematic diagram corresponding to a pixel structure in FIG33. As shown in FIG33 and FIG34, a plurality of pixel structures are arranged along a first direction X and a second direction Y, and the second direction Y intersects with the first direction X. In a pixel structure, the common electrode 1161 includes a plurality of first slits 1161a extending along the first direction X and arranged along the second direction Y, and the electrostatic release layer 127 includes a plurality of electrostatic release portions 1271 corresponding to the plurality of pixel structures, and each electrostatic release portion 1271 includes a plurality of second slits 1271a extending along the first direction X and arranged along the second direction Y. By providing the second slits 1271a at the position corresponding to the pixel structure of the electrostatic release layer 127, the static electricity on the counter substrate 120 can be effectively dispersed and guided out, and the transmittance of the liquid crystal display panel 100 can also be improved. In this example, the electrostatic release layer 127 may have the same voltage signal as the common electrode 1161 on the array substrate 110 , or may have a different voltage signal from the common electrode 1161 on the array substrate 110 .

[0175] In some examples, as shown in FIG. 33 and FIG. 34 , in a pixel structure, a plurality of second slits 1271a are arranged at equal intervals, and in the second direction Y, the ratio of the dimension D8 between two adjacent second slits 1271a to the dimension D9 of the second slit 1271a is in the range of 1.0-1.5. Thus, the dimension D9 of the second slit 1271a in the second direction Y can be appropriately reduced, and the ratio of the conductive area of ​​the electrostatic release portion 1271 to the total area surrounded by the electrostatic release portion 1271 can be greater than 50%, so that the static electricity on the counter substrate 120 can be better dispersed and guided out on the basis of improving the transmittance. It should be noted that the total area surrounded by the electrostatic release portion 1271 refers to the sum of the conductive area of ​​the electrostatic release portion 1271 and the area of ​​all the second slits 1271a of the electrostatic release portion 1271, that is, the total area surrounded by the outermost boundary of the electrostatic release portion 1271.

[0176] For example, by setting the size between the second slits 1271a and the size of the second slits 1271a, the ratio of the conductive area of ​​the electrostatic release portion 1271 to the total area surrounded by the electrostatic release portion 1271 can be between 50% and 65%, so that the electrostatic release layer 127 can better disperse and conduct static electricity on the opposing substrate 120 on the basis of improving transmittance.

[0177] In some examples, as shown in Fig. 34 , the dimension D8 between the two second slits 1271a in the second direction Y may be in the range of 2 μm to 3 μm. For example, in the second direction Y, the dimension D10 of the edge of the electrostatic discharge portion 1271 is half of the dimension D8 between the two second slits 1271a.

[0178] In some examples, as shown in FIG. 34 , the arrangement of the slits on the electrostatic discharge portion 1271 is symmetrical about the center line of the electrostatic discharge portion 1271 along the first direction X, and is also aligned about the center line of the electrostatic discharge portion 1271 along the second direction Y.

[0179] In some examples, as shown in FIG34 , in the first direction X, the second slit 1271a does not penetrate the electrostatic release portion 1271, and the minimum distance D11 between the end of the second slit 1271a and the boundary of the electrostatic release portion 1271 is greater than or equal to 1 μm. For example, the distance D11 may range from 1 μm to 1.5 μm.

[0180] In some examples, as shown in FIG. 33 , the array substrate 110 further includes a plurality of pixel electrodes 117 , the plurality of pixel electrodes 117 correspond to the plurality of common electrodes 1161 , and the pixel electrodes 117 of the pixel structure may be block-shaped pixel electrodes.

[0181] The display performance of the liquid crystal display panel provided with the electrostatic release layer shown in FIG33 and the liquid crystal display panel without the electrostatic release layer is simulated and analyzed. The voltage magnitude of the pixel electrode of the liquid crystal display panel without the electrostatic release layer is the same as described above, and will not be repeated here. In this embodiment, the electrostatic release layer and the common electrode have the same voltage signal.

[0182] According to simulation verification, at the L127 grayscale, compared with not providing an electrostatic release layer, after the electrostatic release layer is added to the liquid crystal display panel, the voltage of the pixel electrode is reduced from 2.36V to 2.16V, thereby reducing power consumption. At the L0 grayscale, the transmittance of the liquid crystal display panel is reduced by 3.18%, so that the liquid crystal display panel is darker in the normally black mode after adding the static release layer. At the L255 grayscale, the transmittance of the liquid crystal display panel is also lost, reduced by 34.54%. Compared with providing a whole layer of electrostatic release layer, this embodiment is darker in the normally black mode, and the reduction in transmittance is also improved at the L255 grayscale.

[0183] FIG35 is a partial cross-sectional schematic diagram of another liquid crystal display panel provided by an embodiment of the present disclosure; FIG36 is a partial top view schematic diagram of a corresponding pixel structure in FIG35. As shown in FIG35 and FIG36, in a pixel structure, a plurality of first slits 1161a and a plurality of second slits 1271a are arranged one by one, and in the second direction Y, the sizes of the first slits 1161a and the second slits 1271a arranged corresponding to each other are the same. By setting the sizes of the first slits 1161a and the second slits 1271a in the second direction Y to be the same, the ratio of the conductive area of ​​the electrostatic release part 1271 to the total area surrounded by the electrostatic release part 1271 can be made less than 50%. By appropriately reducing the ratio of the conductive area of ​​the electrostatic release part 1271 to the total panel surrounded by the electrostatic release part 1271, the light efficiency of the pixel can be better and the transmittance can be better. In this example, the electrostatic release layer 127 may have the same voltage signal as the common electrode 1161 on the array substrate 110 , or may have a different voltage signal from the common electrode 1161 on the array substrate 110 .

[0184] In some examples, as shown in FIGS. 35 and 36 , the array substrate 110 further includes a plurality of pixel electrodes 117 , the plurality of pixel electrodes 117 correspond to the plurality of common electrodes 1161 , and the pixel electrodes 117 of the pixel structure may be block-shaped pixel electrodes.

[0185] The display performance of the liquid crystal display panel provided with the electrostatic release layer shown in FIG35 and the liquid crystal display panel without the electrostatic release layer is simulated and analyzed. The voltage magnitude of the pixel electrode of the liquid crystal display panel without the electrostatic release layer is the same as described above, and will not be repeated here. In this embodiment, the electrostatic release layer and the common electrode have the same voltage signal.

[0186] According to simulation verification, at the L127 grayscale, compared with not having an electrostatic release layer, the voltage of the pixel electrode of the LCD panel is reduced from 2.36V to 2.17V after the electrostatic release layer is added, thereby reducing power consumption. At the L0 grayscale, the transmittance of the LCD panel is reduced by 0.58%, so that the LCD panel is darker in the normally black mode after adding the static release layer. At the L255 grayscale, the transmittance loss of the LCD panel is very small, reduced by 8.44%. Compared with the corresponding schemes of Figures 31 and 33 in the previous text, the transmittance has been greatly improved. Therefore, this embodiment can be used not only for products with high requirements on appearance and energy consumption, but also for products with higher requirements on transmittance.

[0187] Figure 37 is a light effect diagram of two schemes of the embodiment of the present disclosure at the L255 grayscale. As shown in Figure 37, (a) corresponds to the light effect diagram of Figure 33, and (b) corresponds to the light effect diagram of Figure 35. (b) has a greater transmittance than (a) at the L255 grayscale.

[0188] In the liquid crystal display panel shown in Figure 31, the electrostatic release layer 127 can be connected to a separate signal input port through a lead, and the common electrode 1161 is connected to another signal input port through a first common electrode line or a second common electrode line, so that the voltage signals of the electrostatic release layer 127 and the common electrode 1161 can be controlled separately.

[0189] The display performance of a liquid crystal display panel provided with an electrostatic release layer as shown in FIG31 and a liquid crystal display panel not provided with the electrostatic release layer is simulated and analyzed. The voltage magnitude of the pixel electrode of the liquid crystal display panel not provided with the electrostatic release layer is the same as described above and will not be repeated here. In this example, the voltage of the electrostatic release layer is V1, the voltage of the common electrode is V2, the voltage of the pixel electrode is V3, and V1-V2 represents the difference between the voltage V1 and the voltage V2. In this embodiment, the voltage signals of the electrostatic release layer and the common electrode are controlled separately.

[0190] At the L0 grayscale, the value range of V1-V2 can be 1.7V to 1.9V, or the value range of V1-V2 can be -1.8V to -1.6V. For example, the value of V1-V2 can be 1.8V or -1.8V. The voltage V3 of the pixel electrode is set to 0V. At this time, the transmittance of the liquid crystal display panel is reduced by 72.2%, so that the liquid crystal display panel is darker in the normally black mode, and compared with the aforementioned embodiment, there is a more obvious reduction. Compared with the case without an electrostatic release layer, the contrast is greatly improved. For example, it can be used for products with high requirements for the L0 grayscale and high requirements for the contrast.

[0191] At the L255 grayscale, the value range of V1-V2 can be 1.8 V to 2.0 V, for example, the value of V1-V2 can be 1.8 V. The voltage V3 of the pixel electrode is set to 98% of the working voltage. At this time, the transmittance of the liquid crystal display panel only loses 6.48%, and the transmittance is greatly improved.

[0192] FIG38 is a schematic diagram of a simulation of liquid crystal deflection at grayscale L0 of the liquid crystal display panel shown in FIG31. As shown in FIG38, at grayscale L0, referring to the voltage setting described above, the difference between voltage V1 and voltage V2 is 1.8V, the liquid crystal substrate has no deflection, the liquid crystal is basically perpendicular to the paper surface, the liquid crystal display panel is darker in the normally black mode, and the transmittance curve also shows that the transmittance is basically 0 in this state, so that the contrast of the liquid crystal display panel is greatly improved.

[0193] In the liquid crystal display panel shown in Figure 33, the electrostatic release layer 127 can be connected to a separate signal input port through a lead, and the common electrode 1161 is connected to another signal input port through a first common electrode line or a second common electrode line, so that the voltage signals of the electrostatic release layer 127 and the common electrode 1161 can be controlled separately.

[0194] The display performance of a liquid crystal display panel provided with an electrostatic release layer as shown in FIG33 and a liquid crystal display panel not provided with the electrostatic release layer is simulated and analyzed. The voltage magnitude of the pixel electrode of the liquid crystal display panel not provided with the electrostatic release layer is the same as described above and will not be repeated here. In this example, the voltage of the electrostatic release layer is V1, the voltage of the common electrode is V2, the voltage of the pixel electrode is V3, and V1-V2 represents the difference between the voltage V1 and the voltage V2. In this embodiment, the voltage signals of the electrostatic release layer and the common electrode are controlled separately.

[0195] At the L0 grayscale, the value range of V1-V2 can be -0.1V to 0.1V. For example, the value of V1-V2 can be 0V, and the voltage of the electrostatic release layer is the same as the voltage of the common electrode. The voltage V3 of the pixel electrode is set to 0V. At this time, the transmittance of the liquid crystal display panel is reduced by 3.18%, so that the liquid crystal display panel is darker in the normally black mode.

[0196] At the L255 gray scale, the value range of V1-V2 may be 1.9 V to 2.1 V, for example, the value of V1-V2 may be 2 V. The voltage V3 of the pixel electrode is set to 98% of the working voltage, at which time, the transmittance of the liquid crystal display panel is only lost by 3.88%.

[0197] In this embodiment, the electrostatic release layer can improve the transmittance in the L0 state and minimize the impact on the transmittance of L255 and the impact on the contrast.

[0198] In the liquid crystal display panel shown in Figure 35, the electrostatic release layer 127 can be connected to a separate signal input port 0 through a lead, and the common electrode is connected to another signal input port through a first common electrode line or a second common electrode line, so that the voltage signals of the electrostatic release layer 127 and the common electrode 1161 can be controlled separately.

[0199] The display performance of a liquid crystal display panel provided with an electrostatic release layer as shown in FIG35 and a liquid crystal display panel not provided with the electrostatic release layer is simulated and analyzed. The voltage magnitude of the pixel electrode of the liquid crystal display panel not provided with the electrostatic release layer is the same as described above and will not be repeated here. In this example, the voltage of the electrostatic release layer is V1, the voltage of the common electrode is V2, the voltage of the pixel electrode is V3, and V1-V2 represents the difference between the voltage V1 and the voltage V2. In this embodiment, the voltage signals of the electrostatic release layer and the common electrode are controlled separately.

[0200] At the L0 grayscale, the value range of V1-V2 may be 1.0 V to 1.2 V, or the value range of V1-V2 may be -1.0 V to -1.2 V. For example, the value of V1-V2 may be 1.1 V or -1.1 V. The voltage V3 of the pixel electrode is set to 0 V. At this time, the transmittance of the liquid crystal display panel is reduced by 22.1%, so that the liquid crystal display panel is darker in the normally black mode.

[0201] At the L255 grayscale, the value range of V1-V2 can be 1.0 V to 1.3 V, for example, the value of V1-V2 can be 1.1 V. The voltage V3 of the pixel electrode is set to 98% of the working voltage. At this time, the transmittance of the liquid crystal display panel only loses 2.59%, and the transmittance is greatly improved.

[0202] Figure 39 is a light effect diagram of the liquid crystal display panel shown in Figure 35 at the grayscale of L255. As shown in Figure 39, (b) is a light effect diagram of the liquid crystal display panel shown in Figure 35 at the grayscale of L255, and (a) is a light effect diagram of (b) at the grayscale of L255 without the electrostatic release layer. As shown by the dotted line box in the figure, the dark area of ​​(b) is significantly reduced compared with (a), thereby improving the contrast.

[0203] FIG40 is a schematic diagram of a simulated liquid crystal deflection of the liquid crystal display panel shown in FIG35 at a grayscale of L255. As shown in the figure, (b) is a schematic diagram of a simulated liquid crystal deflection of the liquid crystal display panel shown in FIG35 at a grayscale of L255, and (a) is a schematic diagram of a simulated liquid crystal deflection of (b) at a grayscale of L255 without the electrostatic release layer 127. As shown in the dotted box in the figure, the transmittance of (b) is improved compared with (a), thereby improving the contrast.

[0204] An embodiment of the present disclosure further provides a display device. Figure 41 is a schematic diagram of a display device provided by an embodiment of the present disclosure. As shown in Figure 41, the display device 200 includes the above-mentioned liquid crystal display panel 100.

[0205] For example, the display device 200 may be a display device 200 having a display function, such as a television, a computer monitor, a laptop computer, a tablet computer, a smart phone, a navigation system, an electronic picture frame, or a car display.

[0206] An embodiment of the present disclosure also provides a method for manufacturing a liquid crystal display panel. FIG42 is a flow chart of a method for manufacturing a liquid crystal display panel provided by an embodiment of the present disclosure. As shown in FIG42, the method for manufacturing a liquid crystal display panel includes the following steps:

[0207] S110: providing an array substrate, including a first base substrate and a plurality of pixel structures and a sealing glue located on the first base substrate;

[0208] S120: providing an opposing substrate, including a second base substrate and an anti-overflow structure, wherein the anti-overflow structure is disposed on a side of the second base substrate facing the array substrate and is configured to prevent liquid crystal in the liquid crystal layer from overflowing;

[0209] S130: dripping liquid crystal droplets on the opposite substrate; and

[0210] S140: Align the array substrate with the opposing substrate to form a liquid crystal display panel, the liquid crystal display panel includes a display area and a peripheral area surrounding the display area, the anti-overflow structure surrounds the display area and is arranged on the side of the frame sealant close to the display area. An anti-overflow structure is arranged on the opposing substrate, and the anti-overflow structure is arranged on the side of the frame sealant close to the display area. After the liquid crystal droplets are injected on the opposing substrate, the anti-overflow structure can prevent the liquid crystal from overflowing, prevent the liquid crystal from diffusing to the boundary of the frame sealant, and prevent the diffusion of the liquid crystal from affecting the alignment of the array substrate and the opposing substrate. In addition, the anti-overflow structure can also buffer the impact of the liquid crystal droplets on the frame sealant, improve the puncture problem, and improve the product yield.

[0211] There are a few points to note:

[0212] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0213] (2) In the absence of conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0214] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

A liquid crystal display panel comprises an array substrate and an opposing substrate arranged opposite to each other, and a liquid crystal layer arranged between the array substrate and the opposing substrate, wherein the array substrate comprises a first base substrate and a plurality of pixel structures located on the first base substrate, and the opposing substrate comprises: a second substrate base plate; and an anti-overflow structure, which is arranged on a side of the second base substrate facing the array substrate and is configured to prevent liquid crystal in the liquid crystal layer from overflowing, wherein the liquid crystal display panel includes a display area and a peripheral area surrounding the display area, and the liquid crystal display panel also includes a frame sealing glue located in the peripheral area and arranged between the array substrate and the opposing substrate, and the anti-overflow structure surrounds the display area and is arranged on a side of the frame sealing glue close to the display area. The liquid crystal display panel according to claim 1, wherein The maximum size of the display area of ​​the liquid crystal display panel on a plane parallel to the second base substrate is less than or equal to 30 mm. The liquid crystal display panel according to claim 1, wherein On a plane parallel to the second base substrate, the distance between the anti-overflow structure and the display area ranges from 100 μm to 300 μm, and the distance between the anti-overflow structure and the frame sealing glue ranges from 100 μm to 300 μm. The liquid crystal display panel according to claim 1, wherein The counter substrate further includes a spacer, which is located in the display area and arranged on a side of the second base substrate facing the array substrate. The anti-overflow structure is configured to be formed with the spacer through the same material and the same patterning process. The liquid crystal display panel according to any one of claims 1 to 4, wherein: The anti-overflow structure includes at least one anti-overflow cofferdam. The liquid crystal display panel according to claim 5, wherein: The anti-overflow cofferdam includes a polygon on a plane parallel to the second substrate, and the anti-overflow cofferdam includes a plurality of notches. The liquid crystal display panel according to claim 5, wherein: The anti-overflow dam includes a notch, and the opposing substrate also includes an orientation layer, which is arranged on the side of the second base substrate facing the array substrate and has an orientation direction. The notch is located at a position of the anti-overflow dam that is farthest from a center line of the display area in the orientation direction. The liquid crystal display panel according to claim 5, wherein: The anti-overflow cofferdam includes: a first anti-overflow cofferdam having a first opening; and a second anti-overflow cofferdam having a second opening, wherein the first opening and the second opening are arranged opposite to each other, and the first anti-overflow cofferdam and the second anti-overflow cofferdam have an interlaced area, in which the first anti-overflow cofferdam and the second anti-overflow cofferdam are spaced apart to form a channel. The liquid crystal display panel according to claim 8, wherein: The opposing substrate further includes an orientation layer, which is disposed on a side of the second base substrate facing the array substrate and has an orientation direction, and the staggered area is disposed at a position of the anti-overflow cofferdam that is farthest from a center line of the display area in the orientation direction. The liquid crystal display panel according to claim 8, wherein: The first anti-overflow cofferdam includes a first sub-section and a second sub-section arranged opposite to each other, and a first connecting section connecting the first sub-section and the second sub-section, the second anti-overflow cofferdam includes a third sub-section and a fourth sub-section arranged opposite to each other, and a second connecting section connecting the third sub-section and the fourth sub-section, the first sub-section and the third sub-section have an interlaced area and are arranged at intervals to form a channel, and the second sub-section and the fourth sub-section have an interlaced area and are arranged at intervals to form a channel. The liquid crystal display panel according to claim 5, wherein: The anti-overflow cofferdam includes multiple first anti-overflow parts and multiple second anti-overflow parts. In the direction perpendicular to the second substrate, the size of the first anti-overflow part is larger than the size of the second anti-overflow part. In the extension direction of the anti-overflow cofferdam, the first anti-overflow part and the second anti-overflow part are alternately arranged. The liquid crystal display panel according to claim 11, wherein In a direction perpendicular to the second base substrate, a height difference between the first anti-overflow portion and the second anti-overflow portion ranges from 0.5 μm to 0.65 μm. The liquid crystal display panel according to any one of claims 1 to 3, wherein: The counter substrate further includes a planarization layer, which is disposed on a side of the second base substrate facing the array substrate. The anti-overflow structure includes at least one anti-overflow groove formed in the planarization layer and recessed toward the second base substrate. The liquid crystal display panel according to claim 13, wherein: The depth of the anti-overflow groove ranges from 0.5 μm to 1.5 μm, and the width of the anti-overflow groove ranges from 200 μm to 400 μm. The liquid crystal display panel according to any one of claims 1 to 14, wherein: The opposing substrate further includes: an electrostatic release layer, which is arranged on a side of the second base substrate facing the array substrate, wherein the sealing frame is at least partially connected to the electrostatic release layer, and the sealing frame is configured to have conductivity so that the electrostatic release layer is connected to the array substrate through the sealing frame. The liquid crystal display panel according to claim 15, wherein The array substrate further comprises a common electrode layer disposed on a side of the first base substrate facing the opposing substrate. The common electrode layer comprises a common electrode in the display area and a conductive structure in the peripheral area. The frame sealant is at least partially connected to the conductive structure. The liquid crystal display panel according to claim 16, wherein The array substrate also includes a first common electrode line surrounding the display area and a second common electrode line surrounding the first common electrode line, the first common electrode line is connected to the second common electrode line, the first common electrode line is connected to the common electrode, the second common electrode line is connected to the signal input port of the liquid crystal display panel, and the array substrate also includes a via hole, and the second common electrode line is connected to the conductive structure through the via hole. The liquid crystal display panel according to claim 17, wherein: The orthographic projection of the frame sealing adhesive on the first base substrate at least partially overlaps with the orthographic projection of the second common electrode line on the first base substrate, and the second common electrode line includes a metal grid line. The liquid crystal display panel according to claim 16, wherein The array substrate also includes a first common electrode line surrounding the display area and a second common electrode line surrounding the first common electrode line, the first common electrode line is connected to the second common electrode line, the first common electrode line is connected to the common electrode of the display area, the second common electrode line is connected to the first signal input port of the liquid crystal display panel to be provided with a first voltage signal, and the conductive structure is connected to the second signal input port of the liquid crystal display panel through a lead to be provided with a second voltage signal. The liquid crystal display panel according to claim 19, wherein On a plane parallel to the second base substrate, the conductive structure is located on a side of the second common electrode line away from the display area and on a side of the second common electrode line close to an input port of the liquid crystal display panel. The liquid crystal display panel according to claim 19, wherein The difference between the first voltage signal and the second voltage signal has a value range of 0-3 volts. The liquid crystal display panel according to any one of claims 1 to 21, wherein: The multiple pixel structures are arranged along a first direction and a second direction, the second direction intersects with the first direction, and in the pixel structure, the common electrode includes a plurality of first slits extending along the first direction and arranged along the second direction, and the electrostatic release layer includes a plurality of electrostatic release parts corresponding to the multiple pixel structures, each of the electrostatic release parts includes a plurality of second slits extending along the first direction and arranged along the second direction. The liquid crystal display panel according to claim 22, wherein In the pixel structure, the plurality of second slits are arranged at equal intervals, and in the second direction, a ratio of a size between two adjacent second slits to a size of the second slit is in a range of 1.0-1.

5. The liquid crystal display panel according to claim 22, wherein In the pixel structure, the plurality of first slits are arranged in one-to-one correspondence with the plurality of second slits, and in the second direction, the first slits and the second slits arranged in correspondence with each other have the same size. The liquid crystal display panel according to claim 22, wherein In the pixel structure, the array substrate further includes a block pixel electrode, and the block pixel electrode is located between the second base substrate and the common electrode layer. The liquid crystal display panel according to any one of claims 1 to 25, wherein: The opposing substrate also includes: a black matrix layer, which is arranged on the side of the second base substrate facing the array substrate; a color filter layer, which is arranged on the side of the second base substrate facing the array substrate; and a planarization layer, which is arranged on the side of the black matrix layer and the color filter layer facing the array substrate, wherein the anti-overflow structure is arranged on the side of the planarization layer facing the array substrate. A display device comprising a liquid crystal display panel according to any one of claims 1-26.

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