Barrier structure for dispersion reduction in transistor devices

Abstract

A transistor device is provided. In one example, a transistor device includes a channel layer. The transistor device includes a multi-layer barrier structure on a channel layer. The multilayer barrier structure includes a first group III nitride layer and a second group III nitride layer on the first group III nitride layer opposite the channel layer. A thickness of the first group III nitride layer is greater than a thickness of the second group III nitride layer. The aluminum concentration of the first group III nitride layer is at least twice greater than the aluminum concentration of the second group III nitride layer.

Description

[0001] Related Applications

[0002] Priority declaration

[0003] This application is based upon and claims the benefit of priority of U.S. Patent Application No. 17 / 951,708, filed on September 23, 2022. This application claims the benefit of priority to, and incorporates by reference the entire contents of, the cited application. Technical Field

[0004] The present disclosure relates generally to semiconductor devices and, more particularly, to transistor devices. Background Art

[0005] Power semiconductor devices are widely used to carry large currents, support high voltages and / or operate at high frequencies (such as radio frequencies). A wide variety of power semiconductor devices can be used for different applications, including, for example, power switching devices and power amplifiers. Many power semiconductor devices are implemented using various types of field effect transistor (FET) devices, including MOSFET (metal oxide semiconductor field effect transistor), DMOS (double diffused metal oxide semiconductor) transistor, HEMT (high electron mobility transistor), MESFET (metal semiconductor field effect transistor), LDMOS (laterally diffused metal oxide semiconductor) transistor, etc.

[0006] Power semiconductor devices can be made of wide bandgap semiconductor materials (e.g., band gap greater than 1.40 eV). For example, power HEMTs can be made of gallium nitride (GaN) or other Group III nitride-based material systems, which are formed, for example, on silicon carbide (SiC) substrates or other substrates. As used herein, the term "Group III nitrides" refers to those semiconductor compounds formed between nitrogen and Group III elements of the periodic table, typically aluminum (Al), gallium (Ga), and / or indium (In). These compounds have an empirical formula in which one mole of nitrogen is combined with a total of one mole of Group III elements. For high power, high temperature, and / or high frequency applications, devices formed in wide bandgap semiconductor materials, such as silicon carbide (e.g., 2.996 eV bandgap of alpha silicon carbide at room temperature) and Group III nitrides (e.g., 3.36 eV bandgap of gallium nitride at room temperature) can provide higher electric field breakdown strength and higher electron saturation velocity compared to gallium arsenide (GaAs) and silicon (Si) based devices. Summary of the invention

[0007] Aspects and advantages of embodiments of the present disclosure will be set forth in part in the following description, or may be learned from the description, or may be learned through practice of the embodiments.

[0008] An exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multilayer barrier structure on the channel layer. The multilayer barrier structure includes a first Group III nitride layer and a second Group III nitride layer on the first Group III nitride layer and opposite to the channel layer. The thickness of the first Group III nitride layer is greater than the thickness of the second Group III nitride layer. The aluminum concentration of the first Group III nitride layer is at least twice as large as the aluminum concentration of the second Group III nitride layer.

[0009] Another exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multilayer barrier structure on the channel layer. The multilayer barrier structure includes a first Group III nitride layer and a second Group III nitride layer on the first Group III nitride layer and opposite to the channel layer. The thickness of the first Group III nitride layer is at least four times greater than the thickness of the second Group III nitride layer. The aluminum concentration of the first Group III nitride layer is greater than the aluminum concentration of the second Group III nitride layer.

[0010] Another exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multilayer barrier structure on the channel layer. The multilayer barrier structure includes a first layer on the channel layer, a second layer on the first layer, and a third layer on the second layer. The first layer is an AlxGa1-xN layer, where x≥0.5. The second layer is an AlyGa1-yN layer, where 0.2≤y<1. The third layer is an AlzGa1-zN layer, where 0 <z≤0.1。

[0011] Another exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multilayer III-nitride-based barrier structure on the channel layer. The multilayer III-nitride-based barrier structure includes a first layer and a second layer on the first layer. The thickness of the second layer or the aluminum concentration of the second layer is such that the current collapse of the transistor device after the stress condition is about 30% or less at a gate voltage of 0V relative to the operation of the transistor device before the stress condition, wherein the stress condition includes a 10 millisecond pulse of a drain voltage of 100V and a gate voltage of -8V.

[0012] Another exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multilayer III-nitride-based barrier structure on the channel layer. The multilayer III-nitride-based barrier structure includes a first layer and a second layer on the first layer. The thickness of the second layer or the aluminum concentration of the second layer is such that the transistor device has a pinch-off voltage shift of about 0.4V or less at a drain voltage of 50V after the stress condition relative to the operation of the transistor device before the stress condition, wherein the stress condition includes a 10 millisecond pulse of a drain voltage of 100V and a gate voltage of -8V.

[0013] These and other features, aspects and advantages of various embodiments will be better understood with reference to the following description and appended claims.The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and together with the description, explain the relevant principles. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] A detailed discussion of implementations for those of ordinary skill in the art is set forth in the specification, which refers to the accompanying drawings, in which:

[0015] Figure 1 Depicted is a cross-sectional view of an exemplary transistor device according to an exemplary embodiment of the present disclosure.

[0016] Figure 2 A multilayer barrier structure according to an exemplary embodiment of the present disclosure is depicted.

[0017] Figure 3 A multilayer barrier structure according to an exemplary embodiment of the present disclosure is depicted.

[0018] Figure 4 A multilayer barrier structure according to an exemplary embodiment of the present disclosure is depicted.

[0019] Figure 5 A multilayer barrier structure according to an exemplary embodiment of the present disclosure is depicted.

[0020] Figure 6 Depicted is a graphical representation of the dispersion of a transistor device under stress conditions.

[0021] Figure 7 Depicted display Figure 6 The dispersion of the traditional barrier structure of transistor devices.

[0022] Figure 8 Depicted is a graphical representation of the dispersion of a transistor device according to an exemplary embodiment of the present disclosure.

[0023] Fig.9A Depicted is the electric field of a transistor device with a conventional barrier structure.

[0024] Fig. 9B An electric field of a transistor device having a barrier structure according to an exemplary embodiment of the present disclosure is depicted. DETAILED DESCRIPTION

[0025] Reference will now be made in detail to the embodiments, one or more examples of which are illustrated in the accompanying drawings. Each example is provided by way of explanation of the embodiments, and not as a limitation of the present disclosure. Indeed, it will be apparent to those skilled in the art that various modifications and variations may be made to the embodiments without departing from the scope or spirit of the present disclosure. For example, a feature illustrated or described as part of one embodiment may be used together with another embodiment to produce yet another embodiment. Therefore, aspects of the present disclosure are intended to encompass such modifications and variations.

[0026] Transistor devices, such as high electron mobility transistors (HEMTs), can be used in power electronics applications. HEMTs fabricated in Group III nitride-based material systems can have the potential to generate large amounts of radio frequency (RF) power due to a combination of material properties, including high breakdown field, wide bandgap, large conduction band offset, and / or high saturated electron drift velocity. Thus, Group III nitride-based HEMTs can be promising candidates for high frequency and / or high power RF applications, as well as for low frequency high power switching applications, either as discrete transistors or coupled with other circuit elements, such as in monolithic microwave integrated circuit (MMIC) devices.

[0027] Field effect transistors, such as HEMT devices, can be classified as depletion mode and enhancement mode, corresponding to whether the transistor is in the on state or the off state when the gate-source voltage is zero. In an enhancement mode device, the device is off at zero gate-source voltage, while in a depletion mode device, the device is on at zero gate-source voltage. Typically, high performance III-nitride-based HEMT devices can be implemented as depletion mode (normally-on) devices because they are conductive at zero gate-source bias due to the polarization-induced charge at the interface of the device's barrier layer and channel layer.

[0028] When a HEMT device is in the on state, a two-dimensional electron gas (2DEG) is formed at the heterojunction of two semiconductor materials with different bandgap energies, where the material with the smaller bandgap has a higher electron affinity. The 2DEG is an accumulation layer in the material with the smaller bandgap and can include a very high concentration of sheet electrons. In addition, electrons originating from the wider bandgap semiconductor material transfer to the 2DEG layer, allowing high electron mobility due to reduced scattering from ionized impurities. This combination of high carrier concentration and high carrier mobility can provide a very large transconductance (which can refer to the relationship between output current and input voltage) for HEMT devices and can provide a strong performance advantage over MOSFETs for high-frequency applications.

[0029] The HEMT device may include a channel layer of a Group III nitride material (e.g., GaN). The HEMT device may include a barrier layer disposed on the channel layer. The barrier layer may include, for example, a Group III nitride material having a band gap different from that of the channel layer. For example, the barrier layer may include an AlGaN layer and / or an AlN layer. The arrangement of the barrier layer on the channel layer may result in a very high electric field located below the gate region of the HEMT device. Under high stress conditions (e.g., high power switching conditions), the HEMT device may experience dispersion, such as pinch-off voltage or current collapse. The pinch-off voltage may refer to a change in the gate voltage, below which the HEMT device transitions to an off state. Current collapse refers to a reduction in the drain current of the HEMT device when the HEMT device is in a fully on state.

[0030] In high frequency and / or high power RF applications, switching of transistor devices may subject the transistor devices to high stress conditions. Transistor devices subjected to higher dispersion under stress conditions may result in performance degradation. For example, dispersion in transistor devices may result in gain variation over time and / or reduced power gain of RF amplifiers (e.g., power amplifiers and low noise amplifiers). Amplifiers may also lose linearity.

[0031] Exemplary aspects of the present disclosure relate to transistor devices (e.g., HEMT devices) that reduce dispersion under stress conditions. The transistor device may have a multilayer barrier structure. The multilayer barrier structure may be disposed on a channel layer of the transistor device. The multilayer barrier structure may include a first III-nitride layer and a second III-nitride layer on the first III-nitride layer. The thickness of the first III-nitride layer may be greater than the thickness of the second III-nitride layer. For example, the ratio of the thickness of the first III-nitride layer to the thickness of the second III-nitride layer may be about 4:1 or greater. The aluminum concentration of the first III-nitride layer may be greater than the aluminum concentration of the second III-nitride layer. For example, the aluminum concentration of the first III-nitride layer may be at least twice as large as the aluminum concentration of the second III-nitride layer, such as at least five times as large as the aluminum concentration of the second III-nitride layer, such as at least eight times as large as the aluminum concentration of the second III-nitride layer, such as at least two times as large as the aluminum concentration of the second III-nitride layer in the range of about ten times as large.

[0032] Examples of the present disclosure provide technical effects and benefits. For example, without being bound by any operating theory, the inventors have found that the multilayer barrier structure according to the examples of the present disclosure can significantly reduce the electric field around the gate region of the transistor device. The reduction of the electric field around the gate region reduces the dispersion (e.g., current collapse and pinch-off voltage offset) of the transistor device under stress conditions, resulting in more consistent operation of the transistor device as a discrete device or in combination with other circuit elements (e.g., as an MMIC device) in various applications. The reduction in dispersion can make the transistor device useful in many high-stress applications, such as high-power and / or high-frequency RF applications.

[0033] It should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more related listed items.

[0034] The terms used herein are used only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprises", "comprising", "includes" and / or "including" when used herein, clearly indicate the presence of the features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the invention belongs. It should be further understood that the terms used herein should be interpreted as having the same meaning as they have in the context of this specification and the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0036] It should be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "on" another element, it may be directly on or extending directly onto the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly on" or extending directly "on" another element, there are no intervening elements. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0037] As shown in the figures, relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "lateral" or "vertical" may be used herein to describe the relationship of one element, layer or region to another element, layer or region. It should be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0038] Embodiments of the invention are described herein with reference to cross-sectional illustrations, which are schematic diagrams of idealized embodiments of the invention (and intermediate structures). For clarity, the thickness of layers and regions in the drawings may be exaggerated. In addition, variations in the illustrated shapes may be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be interpreted as being limited to the specific shapes of the regions shown herein, but should include shape deviations, such as those caused by manufacturing. Similarly, it is understood that variations in size are expected based on standard deviations in the manufacturing process. As used herein, "approximately" or "about" includes values ​​within 10% of the nominal value.

[0039] Throughout the text, the same number refers to the same element. Therefore, even if neither mentioned nor described in the corresponding figure, the same or similar numbers can be described with reference to other figures. In addition, elements not represented by reference numbers can be described with reference to other figures.

[0040] Some embodiments of the present invention are described with reference to semiconductor layers and / or regions, characterized by having a conductivity type, such as n-type or p-type, which refers to the majority carrier concentration in the layer and / or region. Therefore, N-type materials have a majority equilibrium concentration of negatively charged electrons, while P-type materials have a majority equilibrium concentration of positively charged holes. Some materials may be marked as "+" or "-" (such as in N+, N-, P+, P-, N++, N--, P++, P--, etc.) to indicate that the concentration of majority carriers is relatively large ("+") or small ("-") compared to another layer or region. However, this symbol does not mean that there is a specific concentration of majority carriers or minority carriers in a layer or region.

[0041] For purposes of illustration and discussion, aspects of the present disclosure are discussed with reference to HEMT transistor devices. One of ordinary skill in the art using the disclosure provided herein will appreciate that certain aspects of the present disclosure may be applied to other transistor devices without departing from the scope of the present disclosure.

[0042] In the drawings and specification, typical embodiments have been disclosed, and although specific terms are employed, they are used in a generic and descriptive sense only and not for the purpose of limiting the scope set forth in the following claims.

[0043] Referring now to the drawings, exemplary embodiments of the present disclosure will now be described.

[0044] Figure 1 Depicted is a cross-sectional view of an exemplary HEMT device 100 according to an exemplary embodiment of the present disclosure. Figure 1 The structures are intended to be used for identification and description and are not intended to represent physical scale.The HEMT device 100 may include a semiconductor structure 102. The semiconductor structure 102 may be a Group III nitride semiconductor structure.

[0045] As used herein, the term "Group III nitride" refers to those semiconductor compounds formed between nitrogen (N) and elements of Group III of the periodic table, such as typically aluminum (Al), gallium (Ga), and / or indium (In). The term also refers to ternary and quaternary (or higher) compounds, such as AlGaN and AlInGaN. As is well understood by those skilled in the art, Group III elements can combine with nitrogen to form binary (e.g., GaN), ternary (e.g., AlGaN, AlInN), and quaternary (e.g., AlInGaN) compounds. These compounds all have an empirical formula in which one mole of nitrogen is combined with a total of one mole of the Group III element.

[0046] The semiconductor structure 102 may be on a substrate 104. The substrate 104 may be a semiconductor material. For example, the substrate 104 may be a silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, or other suitable substrate. In some embodiments, the substrate 104 may be a semi-insulating SiC substrate, which may be, for example, a 4H polytype of silicon carbide. Other SiC candidate polytypes may include 3C, 6H, and 15R polytypes. The substrate may be a high purity semi-insulating (HPSI) substrate available from Wolfspeed, Inc. The term "semi-insulating" is used descriptively herein, rather than in an absolute sense.

[0047] In some embodiments, the resistivity of the SiC bulk crystal of the substrate 104 at room temperature may be equal to or higher than about 1×10 5ohm-cm. Exemplary SiC substrates that may be used in some embodiments are manufactured, for example, by Wolfspeed, Inc., and methods for producing such substrates are described, for example, in U.S. Pat. No. Re. 34,861, U.S. Pat. Nos. 4,946,547, 5,200,022, and 6,218,680, the disclosures of which are incorporated herein by reference. Although SiC may be used as a substrate material, embodiments of the present disclosure may utilize any suitable substrate, such as sapphire (Al2O3), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, indium phosphide (InP), etc. The substrate 104 may be a SiC wafer, and the HEMT device 100 may be formed at least in part by wafer-level processing, and the wafer may then be diced to provide a plurality of individual HEMT devices 100.

[0048] The substrate 104 may have a lower surface 104A and an upper surface 104B. In some embodiments, the substrate 104 of the HEMT device 100 may be a thinned substrate 104. In some embodiments, the thickness of the substrate 104 (e.g., Figure 1 The diameter (in the vertical Z direction) can be about 100 μm or less, for example, about 75 μm or less, for example, about 50 μm or less.

[0049] The HEMT device 100 may include a channel layer 106 on the upper surface 104B of the substrate 104 (or on an optional layer further described herein, such as an optional buffer layer or nucleation layer). The HEMT device 100 may include a barrier structure 108 on the upper surface of the channel layer 106. In some embodiments, the channel layer 106 and the barrier structure 108 may each be formed by epitaxial growth. Epitaxial growth techniques for Group III nitrides have been described, for example, in U.S. Pat. Nos. 5,210,051, 5,393,993, and 5,523,589, the disclosures of which are incorporated herein by reference. The band gap of the channel layer 106 may be smaller than the band gap of the barrier structure 108. The channel layer 106 may have a greater electron affinity than the barrier structure 108. The channel layer 106 and the barrier structure 108 may include Group III nitride-based materials.

[0050] In some embodiments, the channel layer 106 may be a Group III nitride, such as Al w Ga 1-wN, where 0≤w<1, provided that at the interface between the channel layer 106 and the barrier structure 108, the energy of the conduction band edge of the channel layer 106 is less than the energy of the conduction band edge of the barrier structure 108. In some embodiments, the aluminum mole fraction w is about 0, indicating that the channel layer 106 is GaN. The channel layer 106 may or may include other Group III nitrides, such as InGaN, AlInGaN, etc. The channel layer 106 may be undoped ("unintentionally doped") and may be grown to a thickness in the range of about 0.5 μm to about 5 μm, for example, about 2 μm. The channel layer 106 may be a multilayer structure, such as a superlattice structure or a combination of GaN, AlGaN, etc. In some embodiments, the channel layer 106 may be under compressive strain.

[0051] The barrier structure 108 may be a multi-layer barrier structure 108. Figure 2-5 Details regarding an exemplary barrier structure 108 are discussed. The channel layer 106 and / or the barrier layer 108 may be deposited, for example, by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE). A 2DEG 110 may be induced in the channel layer 106 at the interface between the channel layer 106 and the barrier structure 108. The 2DEG 110 has high conductivity and allows conduction between the source region and the drain region of the HEMT device 100.

[0052] Although the HEMT device 100 is shown as having a substrate 104, a channel layer 106, and a barrier layer 108 for illustrative purposes, the HEMT device 100 may include additional layers / structures / elements. For example, the HEMT device 100 may include a buffer layer and / or a nucleation layer between the substrate 104 and the channel layer 106. For example, an AlN buffer layer may be on the upper surface 104B of the substrate 104 to provide a suitable crystal structure transition between the SiC substrate 104 and the channel layer 106. The optional buffer layer / nucleation layer / transition layer may be deposited by MOCVD, MBE, and / or HYPE.

[0053] The HEMT device 100 may include a capping layer on the barrier structure 108. The HEMT structure, including the substrate, channel layer, barrier layer, and other layers, is discussed by way of example in U.S. Pat. Nos. 5,192,987, 5,296,395, 6,316,793, 6,548,333, 7,544,963, 7,548,112, 7,592,211, 7,615,774, 7,709,269, 7,709,859, and 10,971,612, the disclosures of which are incorporated herein by reference. In addition, a strain-balancing transition layer may also and / or alternatively be provided as described, for example, in U.S. Pat. No. 7,030,428, the disclosure of which is incorporated herein by reference.

[0054] The HEMT device 100 may include a source contact 112 on the upper surface 108A of the barrier structure 108 or otherwise contacting the barrier structure 108. The HEMT device 100 may include a drain contact 114 on the upper surface 108A of the barrier structure 108 or otherwise contacting the barrier structure 108. The source contact 112 and the drain contact 114 may be laterally spaced apart from each other. In some embodiments, the source contact 112 and the drain contact 114 may include a metal that may form an ohmic contact with a Group III nitride based semiconductor material. Suitable metals may include refractory metals such as titanium (Ti), tungsten (W), titanium tungsten (TiW), silicon (Si), titanium tungsten nitride (TiWN), tungsten silicide (WSi), rhenium (Re), niobium (Nb), Ni, gold (Au), aluminum (Al), tantalum (Ta), molybdenum (Mo), NiSi x , titanium silicide (TiSi), titanium nitride (TiN), tungsten silicon nitride (WSiN), platinum (Pt), etc. In some embodiments, the source contact 112 can be an ohmic source contact 112. The drain contact 114 can be an ohmic drain contact 114. Therefore, the source contact 112 and / or the drain contact 114 can include an ohmic contact portion that is in direct contact with the barrier structure 108. In some embodiments, the source contact 112 and / or the drain contact 114 can include multiple layers to form an ohmic contact, which can be provided as described in, for example, U.S. Patent Nos. 8,563,372 and 9,214,352, the disclosures of which are incorporated herein by reference.

[0055] The HEMT device 100 may include a gate contact 116 on the upper surface 108A of the barrier structure 108 or otherwise contacting the barrier structure 108 (eg, recessed into the barrier structure 108). The gate contact 116 may have a gate length L G . Gate length L G may be the length of the gate contact 116 at the portion of the gate contact 116 on the semiconductor structure 102, such as Figure 1 In some embodiments, the gate length L G The gate length L may be in the range of about 100 nm to about 200 nm, for example about 150 nm. G The gate length L may be about 100 nm or less, such as about 90 nm or less, such as about 60 nm or less. G It may be in the range of about 40 nm to about 90 nm.

[0056] The material of the gate contact 116 can be selected based on the composition of the barrier structure 108, and in some embodiments can be a Schottky contact. Materials that can form a Schottky contact with a Group III nitride based semiconductor material, such as nickel (Ni), platinum (Pt), nickel silicide (NiSi x ), copper (Cu), palladium (Pd), chromium (Cr), tungsten (W) and / or tungsten silicon nitride (WSiN).

[0057] The source contact 112 may be coupled to a reference signal, such as a ground voltage or other reference signal. Coupling to the reference signal may be provided by a through hole 118 extending from the lower surface 104A of the substrate 104, through the substrate 104 and the channel layer 106 to the upper surface 108A of the barrier structure 108. The through hole 118 may expose the bottom surface of the ohmic portion 112A of the source contact 112. The back metal layer 120 may be on the lower surface 104A of the substrate 104 and on the sidewalls of the through hole 118. The back metal layer 120 may directly contact the ohmic portion 112A of the source contact 112. In some embodiments, the contact area between the back metal layer 120 and the bottom surface of the ohmic portion 112A of the source contact 112 may be 50% or more of the bottom surface area of ​​the ohmic portion 112A of the source contact 112. Therefore, the back metal layer 120 and the signal coupled thereto may be electrically connected to the source contact 112 .

[0058] In some embodiments, when viewed in plan view, the through hole 118 may have an elliptical or circular cross-section. However, the present disclosure is not limited thereto. In some embodiments, the cross-section of the through hole 118 may be a polygon or other shape, as understood by one of ordinary skill in the art using the disclosure provided herein. In some embodiments, the size (e.g., length and / or width) of the through hole may be such that the maximum cross-sectional area A1 of the through hole 118 is approximately 1000 μm 2 The cross-sectional area A1 may be parallel to the lower surface 104A of the substrate 104 (eg, Figure 1 In some embodiments, the maximum cross-sectional area A1 of the through hole 118 may be a portion of the through hole 118 adjacent to the lower surface 104A of the substrate 104 (e.g., the opening of the through hole 118). For example, in some embodiments, the maximum width (e.g., Figure 1 in the X direction) may be about 16 μm and the maximum length (e.g., in Figure 1 In some embodiments, the sidewalls of the through hole 118 may be inclined and / or skewed relative to the lower surface 104A of the substrate 104. In some embodiments, the sidewalls of the through hole 118 may be substantially perpendicular to the lower surface 104A of the substrate 104.

[0059] According to an embodiment, drain contact 114 may be formed on, in, and / or through barrier structure 108, and ions may be implanted into the material surrounding drain contact 114 to reduce resistivity and provide improved ohmic contact with the semiconductor material. In yet another embodiment, there is no source via 118, and source contact 112 is formed on, in, and / or through barrier structure 108, and ions may be implanted into the material surrounding source contact 112 to reduce resistivity and provide improved ohmic contact with the semiconductor material. In the absence of source via 118, electrical connection to source contact 112 may be made on the same side as gate contact 116 and drain contact 114. In some examples, connections to source contact 112, drain contact 114, and / or gate contact 116 may be made from the top and / or bottom to provide a flip-chip configuration of HEMT device 100. In some examples, thermal paths may be provided from the top and / or bottom to provide a flip-chip configuration of the HEMT device 100 .

[0060] The HEMT device 100 may include a first insulating layer 122. The first insulating layer 122 may directly contact an upper surface of the semiconductor structure 102 (e.g., contact an upper surface 108A of the barrier structure 108). The HEMT device 100 may include a second insulating layer 124. The second insulating layer 124 may be on the first insulating layer 122. It should also be understood that more than two insulating layers may be included in some embodiments. The first insulating layer 122 and / or the second insulating layer 124 may serve as a passivation layer for the HEMT device 100. The first insulating layer 122 and / or the second insulating layer 124 may be a dielectric layer. Different dielectric materials may be used, such as SiN, SiO2, Si, Ge, MgOx, MgNx, ZnO, SiNx, SiOx, alloys or layer sequences thereof, or epitaxial materials.

[0061] The source contact 112, the drain contact 114, and the gate contact 116 can be in the first insulating layer 122. In some embodiments, at least a portion of the gate contact 116 can be on the first insulating layer 122. In some embodiments, the gate contact 116 can be a T-shaped gate and / or a gamma gate, the formation of which is discussed by way of example in U.S. Patent Nos. 8,049,252, 7,045,404, and 8,120,064, the disclosures of which are incorporated herein by reference. A second insulating layer 124 can be on the first insulating layer 122 and on portions of the source contact 112, the drain contact 114, and the gate contact 116. The protrusion of the gate can also be referred to as a field plate integrated with the gate.

[0062] like Figure 1As shown, depending on the number of insulating layers included in the HEMT device, the field plate 126 can be on the second insulating layer 124, or on another insulating layer. At least a portion of the field plate 126 can be on the gate contact 116. At least a portion of the field plate 126 can be on a portion of the second insulating layer 124 between the gate contact 116 and the drain contact 114. The field plate 126 can reduce the peak electric field in the HEMT device 100, which can result in an increase in breakdown voltage and reduced charge trapping. The reduction in the electric field can also produce other benefits, such as reduced leakage current and improved reliability. Field plates and techniques for forming field plates are discussed by way of example in U.S. Patent No. 8,120,064, the disclosure of which is incorporated herein by reference.

[0063] like Figure 1 As shown, depending on the number of insulating layers included in the HEMT device, the metal contact 128 can be disposed in the second insulating layer 124, or on another insulating layer. The metal contact 128 can provide interconnections between the source contact 112, the drain contact 114, the gate contact 116, and other portions of the HEMT device 100. A respective one of the metal contacts 128 can directly contact the drain contact 114 and / or the respective one of the source contact 112. The metal contact 128 can include metal or other highly conductive materials, including, for example, copper, cobalt, gold, and / or composite metals.

[0064] A HEMT transistor may be formed from an active region between the source contact 112 and the drain contact 114 under the control of a gate contact 116 between the source contact 112 and the drain contact 114 . Figure 1 A cross-sectional view of one cell of the HEMT device 100 is depicted for illustration purposes. The HEMT device 100 may be formed adjacent to additional HEMT device cells and may share, for example, a source contact 112 with the adjacent HEMT device cells.

[0065] Figure 2 Depicts a method that can be used, for example, Figure 1 FIG. 1 is a diagram of an exemplary semiconductor structure 102 in a HEMT device 100 according to exemplary aspects of the present disclosure. Figure 2The structure is intended to be used for identification and description, and is not intended to represent a physical scale. The semiconductor structure 102 includes a multilayer barrier structure 108 on a channel layer 106. The multilayer barrier structure 108 includes a first Group III nitride layer 132 having a first surface 132A disposed on a surface 106A of the channel layer 106. The multilayer barrier structure 108 includes a second Group III nitride layer 134 on the first Group III nitride layer 132, such that a first surface 134A of the second Group III nitride layer 134 is disposed on a second surface 132B of the first Group III nitride layer 132 opposite the channel layer 106. The multilayer barrier structure 108 including the first Group III nitride layer 132 and the second Group III nitride layer 134 may also be referred to as a multilayer Group III nitride-based barrier structure.

[0066] The multilayer barrier structure 108 may have a thickness T1. The thickness T1 may be, for example, in a range of about 150 angstroms to about 350 angstroms, for example, in a range of about 200 angstroms to about 350 angstroms, for example, in a range of about 200 angstroms to about 300 angstroms, for example, in a range of about 200 angstroms to about 250 angstroms. In some embodiments, the thickness T1 may be about 310 angstroms. In some embodiments, the thickness T1 may be about 280 angstroms. In some embodiments, the thickness T1 may be about 250 angstroms. The thickness T1 of the multilayer barrier structure 108 is equal to the thickness T1 of the channel layer 106. B The ratio of may be, for example, in a range of about 1:12 to about 1:250, for example, in a range of about 1:50 to about 1:90. The multilayer barrier structure 108 may be sufficiently thick and may have a sufficiently high aluminum (Al) composition and doping to induce significant carrier concentration at the interface between the channel layer 106 and the multilayer barrier structure 108 through a polarization effect.

[0067] In some embodiments, the multilayer barrier structure 108 may have a thickness T1 of about 150 angstroms or less. For example, in high frequency applications, the gate length L of the gate contact 116 of the HEMT device 100 may be G The thickness T1 of the multilayer barrier structure 108 may be about 100 nm or less, such as about 90 nm or less, such as about 60 nm or less, or in the range of about 40 nm to about 90 nm. In these applications, the thickness T1 of the multilayer barrier structure 108 may be reduced so that the gate length L of the gate contact 116 G The ratio of the thickness T1 of the multilayer barrier structure 108 is in the range of 8: 1 to 16: 1. For example, the multilayer barrier structure 108 may have a thickness T1 of about 50 angstroms to about 120 angstroms.

[0068] The first III-nitride layer 132 may be a III-nitride, such as Al y Ga 1-yN, where y is the aluminum mole fraction in the first group-III nitride layer 132. At the interface between the channel layer 106 and the multi-barrier structure 108, the energy of the conduction band edge of the first group-III nitride layer 132 is greater than the energy of the conduction band edge of the channel layer 106. In some embodiments, the aluminum mole fraction y is such that 0.2 ≤ y < 1 (e.g., the aluminum mole fraction is in the range of about 20% to about 100%), indicating that the first group-III nitride layer 132 is an AlGaN layer. However, the first group-III nitride layer 132 may include other group-III elements (e.g., In) without departing from the scope of the present disclosure.

[0069] The second group-III nitride layer 134 may be a group-III nitride, such as Al z Ga 1-z N, where z is the aluminum mole fraction in the second group-III nitride layer 134. The aluminum concentration of the second group-III nitride layer 134 may be less than the aluminum concentration of the first group-III nitride layer 132. For example, in some embodiments, the aluminum concentration of the first group-III nitride layer 132 may be at least about twice as large as the aluminum concentration of the second group-III nitride layer 134, such as at least five times as large as the aluminum concentration of the second group-III nitride layer 134, such as at least eight times as large as the aluminum concentration of the second group-III nitride layer 134, such as in the range of at least twice as large to about ten times as large as the aluminum concentration of the second group-III nitride layer 134. In some embodiments, the aluminum mole fraction z is such that 0 < z ≤ 0.1 (e.g., the aluminum mole fraction is in the range of about 1% to about 10%), indicating that the second group-III nitride layer 134 is an AlGaN layer. However, the second group-III nitride layer 134 may include other group-III elements (e.g., In) without departing from the scope of the present disclosure.

[0070] In some embodiments, the second group-III nitride layer 134 may have an increasing aluminum graded concentration from the second surface 134B to the first surface 134A of the second group-III nitride layer 134. For example, the second group-III nitride layer 134 may have an aluminum graded concentration such that at the interface between the first group-III nitride layer 132 and the second group-III nitride layer 134, the aluminum concentration of the second group-III nitride layer 134 at the first surface 134A is higher than that of the second surface 134B of the second group-III nitride layer 134 opposite the first group-III nitride layer 132. The aluminum graded concentration may increase from the second surface 134B to the first surface 134A with a uniform change in concentration, a different change in concentration, or a combination thereof. For example, the aluminum graded concentration may increase from an aluminum mole fraction of about 0% at the second surface 134B to an aluminum mole fraction of about 10% at the first surface 134A.

[0071] In some embodiments, there may be a difference in aluminum concentration between the first Group III nitride layer 132 and the second Group III nitride layer 134 at the interface between the first Group III nitride layer 132 and the second Group III nitride layer 134. For example, in some embodiments, the aluminum concentration of the first Group III nitride layer 132 may be at least twice as large as the aluminum concentration of the second Group III nitride layer 134 at the interface between the first Group III nitride layer 132 and the second Group III nitride layer 134, such as at least five times as large as the aluminum concentration of the second Group III nitride layer 134 at the interface between the first Group III nitride layer 132 and the second Group III nitride layer 134, such as at least eight times as large as the aluminum concentration of the second Group III nitride layer 134, such as at least two times as large as the aluminum concentration of the second Group III nitride layer 134 in the range of about ten times as large.

[0072] The first III-nitride layer 132 may have a thickness T2, and the second III-nitride layer 134 may have a thickness T3. In some embodiments, a ratio of the thickness T2 of the first III-nitride layer 132 to the thickness T3 of the second III-nitride layer 134 may be in a range of about 3:1 or greater, such as about 4:1 or greater, such as in a range of about 3:1 to about 15:1. In some embodiments, the thickness T2 of the first III-nitride layer 132 may be about four times greater than the thickness T3 of the second III-nitride layer 134. In some embodiments, the thickness T2 may be in a range of about 200 angstroms to about 250 angstroms, such as about 230 angstroms. The thickness T3 of the second III-nitride layer 134 may be about 50 angstroms or less, such as about 30 angstroms or less, such as about 30 angstroms.

[0073] The gate length L G In embodiments where the thickness T1 of the multilayer barrier structure 108 is 100 nm or less, the total thickness T1 of the multilayer barrier structure 108 may be in the range of about 50 angstroms to about 120 angstroms. In these embodiments, the thickness T2 of the first III-nitride layer 132 and the thickness T3 of the second III-nitride layer 134 may be reduced accordingly to maintain the ratio of the thickness T2 of the first III-nitride layer 132 to the thickness T3 of the second III-nitride layer 134 in the range of about 3:1 or greater, such as about 4:1 or greater, such as in the range of about 3:1 to about 15:1.

[0074] Figure 3 Depicted are exemplary aspects of the present disclosure that can be used, for example, Figure 1 Another exemplary semiconductor structure 102 in the HEMT device 100 is shown. Figure 3The semiconductor structure 102 includes a multilayer barrier structure 108 on a channel layer 106. The multilayer barrier structure 108 includes a plurality of channels 106 and a plurality of channels 108 having ... Figure 2 The first and second Group III nitride layers 132 and 134 are similarly configured.

[0075] The multilayer barrier structure 108 further includes a spacer layer or interface layer 136 (referred to herein as an "interface layer") (e.g., a third layer, such as a third Group III nitride layer) disposed between the channel layer 106 and the first Group III nitride layer 132. The interface layer 136 has a first surface 136A disposed on the surface 106A of the channel layer 106. The first Group III nitride layer 132 is disposed on the interface layer 136, such that the first surface 132A of the first Group III nitride layer 132 is on a second surface 136B of the interface layer 136 opposite to the channel layer 106.

[0076] The interface layer 136 may be a Group III nitride, such as Al x Ga 1-x N, where x is the aluminum mole fraction in the interface layer 136. In some embodiments, the aluminum mole fraction x is such that x ≥ 0.5 (e.g., the aluminum mole fraction is greater than 50%), indicating that the interface layer 136 is an AlGaN layer. In some embodiments, the aluminum mole fraction x is such that x ≥ 0.75 (e.g., the aluminum mole fraction is greater than 75%), indicating that the interface layer 136 is an AlGaN layer. In some embodiments, the aluminum mole fraction is 1 (e.g., the aluminum mole fraction is 100%), indicating that the interface layer 136 is an AlN layer. However, the interface layer 136 may include other Group III elements (e.g., In) without departing from the scope of the present disclosure.

[0077] The interface layer 136 may have a thickness T4. The thickness T4 may be about 50 angstroms or less, such as about 30 angstroms or less, such as in a range of about 3 angstroms to about 50 angstroms, such as in a range of about 3 angstroms to about 30 angstroms.

[0078] The multilayer barrier structure 108 may have a thickness T1, which includes a thickness T2 of the first Group III nitride layer 132, a thickness T3 of the second Group III nitride layer 134, and a thickness T4 of the interface layer 136. The thickness T1 may be, for example, in a range of about 150 angstroms to about 350 angstroms, such as in a range of about 200 angstroms to about 350 angstroms, such as in a range of about 200 angstroms to about 300 angstroms, such as in a range of about 200 angstroms to about 250 angstroms. In some embodiments, the thickness T1 may be about 310 angstroms. In some embodiments, the thickness T1 may be about 280 angstroms. In some embodiments, the thickness T1 may be about 250 angstroms. The thickness T1 of the multilayer barrier structure 108 is equal to the thickness T2 of the channel layer 106. B The ratio of may be, for example, in a range of about 1:12 to about 1:250, for example, in a range of about 1:50 to about 1:90. The multilayer barrier structure 108 may be sufficiently thick and may have a sufficiently high aluminum (Al) composition and doping to induce significant carrier concentration at the interface between the channel layer 106 and the multilayer barrier structure 108 through a polarization effect.

[0079] In some embodiments, the multilayer barrier structure 108 may have a thickness T1 of about 150 angstroms or less. For example, in high frequency applications, the gate length L of the gate contact 116 of the HEMT device 100 may be G The thickness T1 of the multilayer barrier structure 108 can be reduced so that the gate length L of the gate contact is less than 100 nm, such as about 90 nm or less, such as about 60 nm or less, such as in the range of about 40 nm to about 90 nm. G The ratio of the thickness T1 of the multilayer barrier structure 108 is in the range of 8: 1 to 16: 1. For example, the multilayer barrier structure 108 may have a thickness T1 of about 50 angstroms to about 120 angstroms.

[0080] The gate length L G In embodiments where the thickness T1 of the multilayer barrier structure 108 is 100 nm or less, the total thickness T1 of the multilayer barrier structure 108 may be in the range of about 50 angstroms to about 120 angstroms. In these embodiments, the thickness T2 of the first III-nitride layer 132 and the thickness T3 of the second III-nitride layer 134 may be reduced accordingly to maintain the ratio of the thickness T2 of the first III-nitride layer 132 to the thickness T3 of the second III-nitride layer 134 in the range of about 3:1 or greater, such as about 4:1 or greater, such as in the range of about 3:1 to about 15:1.

[0081] Figure 4 Depicted are exemplary embodiments of the present disclosure that can be used, for example, Figure 1 Another exemplary semiconductor structure 102 in the HEMT device 100 is shown. Figure 4 The semiconductor structure 102 includes a multilayer barrier structure 108 on a channel layer 106. The multilayer barrier structure 108 includes a plurality of channels having a plurality of channels. Figure 2 The first and second Group III nitride layers 132 and 134 are similarly configured.

[0082] If disposed between the multi-layer barrier structure 108 and the gate contact 116, the semiconductor structure 102 further includes a capping layer T1. The capping layer 138 may include a single layer or multiple layers. The thickness of the capping layer 138 may be, for example, in the range of about 20 angstroms to about 50 angstroms. The capping layer 138 may be a Group III nitride, such as Al c Ga 1-c N, where c is the aluminum mole fraction of the capping layer 138. In some embodiments, the aluminum mole fraction c is such that 0≤c≤0.15. In some embodiments, the capping layer 138 is a GaN layer. In some embodiments, the capping layer 138 is an AlGaN layer. In some embodiments, the capping layer 138 is an AlN layer. The capping layer 138 may include other Group III elements (e.g., In) without departing from the scope of the present disclosure.

[0083] In some embodiments, the capping layer 138 may have a graded concentration of aluminum or different concentrations of aluminum. For example, the capping layer 138 may have a different aluminum concentration at a first surface 138A of the capping layer 138 at an interface between the capping layer 138 and the multilayer barrier structure 108 relative to a second surface 138B of the capping layer 138 opposite the multilayer barrier structure 108.

[0084] Figure 4 The gate contact 116 is depicted disposed on the capping layer 138. The gate contact 116 may be recessed into the capping layer 138 without departing from the scope of the present disclosure. The capping layer 138 may be deposited, for example, by MOCVD, MBE, or HVPE.

[0085] Figure 5 Depicted are exemplary embodiments of the present disclosure that can be used, for example, Figure 1 Another exemplary semiconductor structure 102 in the HEMT device 100 is shown. Figure 5 The semiconductor structure 102 includes a multilayer barrier structure 108 on a channel layer 106. The multilayer barrier structure 108 includes a plurality of channels having a plurality of channels. Figure 3 The first Group III nitride layer 132, the second Group III nitride layer 134 and the interface layer 136 are similarly configured.

[0086] exist Figure 5 In the embodiment, the semiconductor structure 102 further includes a capping layer 138 disposed between the multilayer barrier structure 108 and the gate contact 116. The capping layer 138 may include a single layer or multiple layers. The thickness T5 of the capping layer 138 may be, for example, in the range of about 20 angstroms to about 50 angstroms. The capping layer 138 may be a group III nitride, such as Al c Ga 1-c N, where c is the aluminum mole fraction of the capping layer 138. In some embodiments, the aluminum mole fraction c is such that 0≤c≤.15. In some embodiments, the capping layer 138 is a GaN layer. In some embodiments, the capping layer 138 is an AlGaN layer. In some embodiments, the capping layer 138 is an AlN layer. The capping layer 138 may include other Group III elements (e.g., In) without departing from the scope of the present disclosure.

[0087] In some embodiments, the capping layer 138 may have a graded concentration of aluminum or different concentrations of aluminum. For example, the capping layer 138 may have a different aluminum concentration at a first surface 136A of the capping layer 138 at an interface between the capping layer 138 and the multilayer barrier structure 108 relative to a second surface 138B of the capping layer 138 opposite the multilayer barrier structure 108.

[0088] Figure 5 The gate contact 116 is depicted disposed on the capping layer 138. The gate contact 116 may be recessed into the capping layer 138 without departing from the scope of the present disclosure. The capping layer 138 may be deposited, for example, by MOCVD, MBE, or HVPE.

[0089] according to Figure 2-5 The transistor device incorporating the multilayer barrier structure 108 of the example can show less dispersion under stress conditions. In this regard, according to the exemplary embodiments of the present disclosure, the transistor device incorporating the multilayer barrier structure 108 can provide increased performance in applications involving high stress conditions, such as high frequency and / or high power RF switching applications.

[0090] More specifically, Figure 6 Plot 140 depicts an exemplary dispersion of a conventional HEMT device having a conventional barrier structure after being subjected to stress conditions. Figure 7 Depicted with Figure 6 An exemplary conventional barrier structure 208 associated with drawing 140 . Figure 7 The barrier structure 208 is on the channel layer 206. The barrier structure 208 has an AlGaN layer 232 disposed on an AlN interface layer 236. The thickness T6 of the AlGaN layer 232 is about 250 angstroms and the aluminum mole fraction is about 22%. The thickness T7 of the AlN interface layer 236 is about 50 angstroms or less.

[0091] Figure 6 The gate voltage Vg (V) along the horizontal axis and the drain current density Id (A / mm) along the vertical axis are plotted. Curve 142 is associated with the unstressed condition. Curve 142 is obtained by applying a 50V drain voltage to the drain contact of the HEMT device and sweeping the gate voltage applied to the gate contact of the HEMT device from 0V to -6V. Curve 142 plots the drain current density at each gate voltage.

[0092] Curve 144 is associated with a stress condition. The stress condition includes applying a 100V drain voltage to the drain contact of the HEMT device and a 10 millisecond pulse of a -8V gate voltage to the gate contact of the HEMT device. After the stress condition, curve 144 is obtained by applying a 50V drain voltage to the drain contact of the HEMT and sweeping the gate voltage applied to the gate contact of the HEMT device from 0V to -6V. Curve 144 plots the drain current density at each gate voltage.

[0093] As shown by the difference between curve 142 and curve 144, Figure 7 The HEMT device with the barrier structure 208 experienced dispersion under stress conditions. More specifically, the HEMT device experienced a pinch-off voltage shift 146 of about 0.8 V. The HEMT device experienced a current collapse 148 of about 34% (e.g., the drain current density decreased from about 0.6 A / mm to a drain current density of about 0.4 A / mm).

[0094] Figure 8 A plot 150 depicts an exemplary dispersion of a HEMT device according to an exemplary embodiment of the present disclosure. The plot 150 may be compared to a HEMT device having Figure 3 1. The barrier structure 108 is associated with a HEMT device having a barrier structure 108 depicted in FIG. More specifically, the barrier structure 108 may have a first III-nitride layer 132, a second III-nitride layer 134, and an interface layer 136. The first III-nitride layer 132 may have a thickness T2 of about 220 angstroms and an aluminum mole fraction of about 25%. The second III-nitride layer 134 may have a thickness T3 of about 30 angstroms and an aluminum mole fraction of about 5%. The interface layer 136 may be an AlN layer having a thickness T4 of about 50 angstroms or less.

[0095] Figure 8 The gate voltage Vg (V) along the horizontal axis and the drain current density Id (A / mm) along the vertical axis are plotted. Curve 152 is associated with the unstressed condition. Curve 152 is obtained by applying a 50V drain voltage to the drain contact of the HEMT device and sweeping the gate voltage applied to the gate contact of the HEMT device from 0V to -6V. Curve 152 plots the drain current density at each gate voltage.

[0096] Curve 154 is associated with a stress condition. The stress condition includes a 100V drain voltage applied to the drain contact of the HEMT device and a 10 millisecond pulse of a -8V gate voltage applied to the gate contact of the HEMT device. After applying the stress condition, curve 154 is obtained by applying a 50V drain voltage to the drain contact of the HEMT and sweeping the gate voltage applied to the gate contact of the HEMT device from 0V to -6V. Curve 154 plots the drain current density at each gate voltage.

[0097] As shown by the difference between curve 152 and curve 154, the HEMT device according to exemplary aspects of the present disclosure experiences dispersion after the stress condition. More specifically, at a drain voltage of 50V, the HEMT device experiences a pinch-off voltage shift 156 after the stress condition of about 0.4V or less, relative to the operation of the HEMT device before the stress condition. At a gate voltage of 0V, the HEMT device experiences a current collapse 158 after the stress condition of about 30% or less (e.g., 26%), relative to the operation of the HEMT device before the stress condition.

[0098] like Figure 8 As shown, according to exemplary aspects of the present disclosure, a HEMT device incorporating a barrier structure experiences less dispersion after a stress condition. For example, the pinch-off voltage shifts from Figure 7 In the example, the 0.8V is reduced to Figure 8 In the example, the current collapses from Figure 7 The example of about 34% is reduced to less than 30%, for example Figure 8 About 26% of the examples.

[0099] Without being bound by any particular theory, the inventors have found that the multilayer barrier structure according to exemplary aspects of the present disclosure may result in a reduction in the electric field near the gate region of the HEMT device. The reduction in the electric field near the gate region of the HEMT device results in reduced dispersion of the HEMT device after stress conditions.

[0100] Fig.9A Describes the Figure 7 208 depicted in FIG. 2 . The electric field in an exemplary HEMT device having a barrier structure similar to the conventional barrier structure 208 depicted in FIG. Fig.9A A strong electric field 162 in the gate region 160 near the gate region 160 is depicted. For ease of illustration, electric field lines are added in the gate region 160 to represent the electric field 162. The electric field 162 in the gate region 160 penetrates into the channel layer 106.

[0101] Fig. 9B Depicted are exemplary aspects of the present disclosure having Figure 3The electric field in the exemplary HEMT device of the barrier structure 108 is similar to the barrier structure. Fig. 9B As shown, the electric field 164 in the same gate region 160 has been reduced. For ease of illustration, electric field lines are added in the gate region 160 to represent the electric field 164. The strength of the electric field 164 is reduced relative to the electric field 162, and the depth of penetration into the channel layer 106 is less.

[0102] The following paragraphs describe exemplary aspects of the disclosure.

[0103] An exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multilayer barrier structure on the channel layer. The multilayer barrier structure includes a first Group III nitride layer and a second Group III nitride layer on the first Group III nitride layer and opposite to the channel layer. The thickness of the first Group III nitride layer is greater than the thickness of the second Group III nitride layer. The aluminum concentration of the first Group III nitride layer is at least twice as large as the aluminum concentration of the second Group III nitride layer.

[0104] In some examples, the thickness of the second Group III nitride layer or the aluminum concentration of the second Group III nitride layer is such that the current collapse of the transistor device after the stress condition is about 30% or less at a gate voltage of 0 V relative to the operation of the transistor device before the stress condition, wherein the stress condition includes a 10 millisecond pulse of a drain voltage of 100 V and a gate voltage of -8 V.

[0105] In some examples, the thickness of the second Group III nitride layer or the aluminum concentration of the second Group III nitride layer is such that the pinch-off voltage shift of the transistor device after the stress condition is approximately 0.4 V or less at a drain voltage of 50 V relative to operation of the transistor device before the stress condition, wherein the stress condition includes a 10 millisecond pulse of a drain voltage of 100 V and a gate voltage of -8 V.

[0106] In some examples, the aluminum concentration of the first Group III-nitride layer is at least five times greater than the aluminum concentration of the second Group III-nitride layer.

[0107] In some examples, the aluminum mole fraction of the first Group III nitride layer is in a range from about 20% to about 100%. The aluminum mole fraction of the second Group III nitride layer is in a range from about 1% to about 10%.

[0108] In some examples, a ratio of a thickness of the first Group III-nitride layer to a thickness of the second Group III-nitride layer is about 4:1 or greater.

[0109] In some examples, the first Group III-nitride layer has a thickness of about 200 angstroms to about 250 angstroms, and the second Group III-nitride layer has a thickness of about 50 angstroms or less.

[0110] In some examples, the multilayer barrier structure includes an interface layer. The first group III nitride layer is disposed on the interface layer and is opposite to the channel layer. The aluminum concentration of the interface layer is greater than the aluminum concentration of the first group III nitride layer and the aluminum concentration of the second group III nitride layer. In some examples, the thickness of the interface layer is in the range of about 50 angstroms or less.

[0111] In some examples, a transistor device includes a source contact and a drain contact on a multi-layer barrier structure.

[0112] In some instances, the second Group III nitride layer has an increased graded aluminum concentration such that the second Group III nitride layer has a higher aluminum concentration at an interface between the first Group III nitride layer and the second Group III nitride layer relative to a surface of the second Group III nitride layer opposite the first Group III nitride layer.

[0113] In some examples, the transistor device has a capping layer on the multi-layer barrier structure.

[0114] In some examples, the transistor device is a high electron mobility transistor. In some examples, the first Group III nitride layer and the second Group III nitride layer each include AlGaN. In some examples, the channel layer is disposed on a silicon carbide substrate.

[0115] Another exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multilayer barrier structure on the channel layer. The multilayer barrier structure includes a first Group III nitride layer and a second Group III nitride layer on the first Group III nitride layer and opposite to the channel layer. The thickness of the first Group III nitride layer is at least four times greater than the thickness of the second Group III nitride layer. The aluminum concentration of the first Group III nitride layer is greater than the aluminum concentration of the second Group III nitride layer.

[0116] In some examples, the thickness of the second Group III nitride layer or the aluminum concentration of the second Group III nitride layer is such that the current collapse of the transistor device after the stress condition is about 30% or less at a gate voltage of 0 V relative to the operation of the transistor device before the stress condition, wherein the stress condition includes a 10 millisecond pulse of a drain voltage of 100 V and a gate voltage of -8 V.

[0117] In some examples, the thickness of the second Group III nitride layer or the aluminum concentration of the second Group III nitride layer is such that the pinch-off voltage shift of the transistor device after the stress condition is approximately 0.4 V or less at a drain voltage of 50 V relative to operation of the transistor device before the stress condition, wherein the stress condition includes a 10 millisecond pulse of a drain voltage of 100 V and a gate voltage of -8 V.

[0118] In some examples, the aluminum concentration of the first Group III-nitride layer is at least five times greater than the aluminum concentration of the second Group III-nitride layer.

[0119] In some examples, the aluminum mole fraction of the first Group III nitride layer is in a range from about 20% to about 100%. The aluminum mole fraction of the second Group III nitride layer is in a range from about 1% to about 10%.

[0120] In some examples, the first Group III-nitride layer has a thickness of about 200 angstroms to about 250 angstroms, and the second Group III-nitride layer has a thickness of about 50 angstroms or less.

[0121] In some examples, the multilayer barrier structure includes an interface layer. The first group III nitride layer is disposed on the interface layer and is opposite to the channel layer. The aluminum concentration of the interface layer is greater than the aluminum concentration of the first group III nitride layer and the aluminum concentration of the second group III nitride layer. In some examples, the thickness of the interface layer is in the range of about 50 angstroms or less.

[0122] In some examples, a transistor device includes a source contact and a drain contact on a multi-layer barrier structure.

[0123] In some examples, the second Group III nitride layer has a graded aluminum concentration such that the second Group III nitride layer has a higher aluminum concentration at an interface between the first Group III nitride layer and the second Group III nitride layer relative to a surface of the second Group III nitride layer opposite the first Group III nitride layer.

[0124] In some examples, the transistor device includes a capping layer on the multi-layer barrier structure.

[0125] In some examples, the transistor device is a high electron mobility transistor. In some examples, the first Group III nitride layer and the second Group III nitride layer each include AlGaN. In some examples, the channel layer is disposed on a silicon carbide substrate.

[0126] Another exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multilayer barrier structure on the channel layer. The multilayer barrier structure includes a first layer on the channel layer, a second layer on the first layer, and a third layer on the second layer. The first layer is an AlxGa1-xN layer, where x≥0.5. The second layer is an AlyGa1-yN layer, where 0.2≤y<1. The third layer is an AlzGa1-zN layer, where 0 <z≤0.1。

[0127] In some examples, the ratio of the thickness of the second layer to the thickness of the third layer is 4:1 or greater.

[0128] In some examples, the second layer has a thickness of about 200 angstroms to about 250 angstroms, and the third layer has a thickness of about 50 angstroms or less.

[0129] In some examples, a transistor device includes a source contact and a drain contact on a multi-layer barrier structure.

[0130] In some examples, x ≥ 0.7.

[0131] Another exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multilayer III-nitride-based barrier structure on the channel layer. The multilayer III-nitride-based barrier structure includes a first layer and a second layer on the first layer. The thickness of the second layer or the aluminum concentration of the second layer is such that the current collapse of the transistor device after the stress condition is about 30% or less at a gate voltage of 0V relative to the operation of the transistor device before the stress condition, wherein the stress condition includes a 10 millisecond pulse of a drain voltage of 100V and a gate voltage of -8V.

[0132] In some examples, the thickness of the second layer or the aluminum concentration of the second layer is such that the pinch-off voltage of the transistor device after the stress condition shifts by about 0.4 V or less at a drain voltage of 50 V relative to operation of the transistor device before the stress condition.

[0133] In some examples, the ratio of the thickness of the first layer to the thickness of the second layer is about 4:1.

[0134] In some examples, the aluminum concentration of the first layer is at least twice as great as the aluminum concentration of the second layer at an interface between the first layer and the second layer.

[0135] Another exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multilayer III-nitride-based barrier structure on the channel layer. The multilayer III-nitride-based barrier structure includes a first layer and a second layer on the first layer. The thickness of the second layer or the aluminum concentration of the second layer is such that the transistor device has a pinch-off voltage shift of about 0.4V or less at a drain voltage of 50V after the stress condition relative to the operation of the transistor device before the stress condition, wherein the stress condition includes a 10 millisecond pulse of a drain voltage of 100V and a gate voltage of -8V.

[0136] In some examples, the ratio of the thickness of the first layer to the thickness of the second layer is about 4:1.

[0137] In some examples, the aluminum concentration of the first layer is at least twice as great as the aluminum concentration of the second layer at an interface between the first layer and the second layer.

[0138] Although the subject matter has been described in detail with respect to specific exemplary embodiments of the subject matter, it should be understood that those skilled in the art, after obtaining an understanding of the foregoing, can easily make changes, variations and equivalents to these embodiments. Therefore, the scope of the present disclosure is by way of example rather than limitation, and the subject disclosure does not exclude such modifications, variations and / or additions to the subject matter, as would be apparent to one of ordinary skill in the art.

Claims

1. A transistor device, comprising: Channel layer; and A multilayer barrier structure on the channel layer, the multilayer barrier structure comprising a first Group III nitride layer and a second Group III nitride layer, the second Group III nitride layer being on the first Group III nitride layer and opposite to the channel layer, the thickness of the first Group III nitride layer being greater than the thickness of the second Group III nitride layer, wherein the aluminum concentration of the first Group III nitride layer is at least twice as large as the aluminum concentration of the second Group III nitride layer.

2. The transistor device of claim 1 , wherein the thickness of the second Group III nitride layer or the aluminum concentration of the second Group III nitride layer is such that, relative to the operation of the transistor device before the stress condition, at a gate voltage of 0 V, the current collapse of the transistor device after the stress condition is approximately 30% or less, wherein the stress condition comprises a 10 millisecond pulse of a drain voltage of 100 V and a gate voltage of -8 V.

3. The transistor device of claim 1 , wherein the thickness of the second Group III nitride layer or the aluminum concentration of the second Group III nitride layer is such that relative to the operation of the transistor device before the stress condition, at a drain voltage of 50 V, the pinch-off voltage shift of the transistor device after the stress condition is approximately 0.4 V or less, wherein the stress condition comprises a 10 millisecond pulse of a drain voltage of 100 V and a gate voltage of -8 V. 4 . The transistor device of claim 1 , wherein the aluminum concentration of the first Group III-nitride layer is at least five times greater than the aluminum concentration of the second Group III-nitride layer. 5 . The transistor device of claim 1 , wherein the aluminum mole fraction of the first Group III-nitride layer is in a range from about 20% to about 100%. 6 . The transistor device of claim 5 , wherein the aluminum mole fraction of the second Group III-nitride layer is in a range from about 1% to about 10%. 7 . The transistor device of claim 1 , wherein a ratio of a thickness of the first Group III-nitride layer to a thickness of the second Group III-nitride layer is 4:1 or greater. 8 . The transistor device of claim 1 , wherein the first Group III-nitride layer has a thickness of about 200 angstroms to about 250 angstroms, and the second Group III-nitride layer has a thickness of about 50 angstroms or less.

9. The transistor device of claim 1 , wherein the multilayer barrier structure comprises an interface layer, the first Group III nitride layer is disposed on the interface layer and opposite to the channel layer, wherein an aluminum concentration of the interface layer is greater than an aluminum concentration of the first Group III nitride layer and an aluminum concentration of the second Group III nitride layer.

10. The transistor device of claim 9, wherein the thickness of the interfacial layer is in the range of about 50 angstroms or less.

11. The transistor device of claim 1, further comprising a source contact and a drain contact on the multi-layer barrier structure.

12. The transistor device of claim 1 , wherein the second Group III nitride layer has an increased graded aluminum concentration such that the second Group III nitride layer has a higher aluminum concentration at an interface between the first Group III nitride layer and the second Group III nitride layer relative to a surface of the second Group III nitride layer opposite to the first Group III nitride layer. 13 . The transistor device according to claim 1 , further comprising a capping layer on the multi-layer barrier structure.

14. The transistor device of claim 1, wherein the transistor device is a high electron mobility transistor.

15. The transistor device according to claim 1, wherein the channel layer is provided on a silicon carbide substrate.

16. A transistor device comprising: Channel layer; and A multilayer barrier structure on the channel layer, the multilayer barrier structure comprising a first Group III nitride layer and a second Group III nitride layer, the second Group III nitride layer being on the first Group III nitride layer and opposite to the channel layer, the thickness of the first Group III nitride layer being at least four times the thickness of the second Group III nitride layer, wherein the aluminum concentration of the first Group III nitride layer is greater than the aluminum concentration of the second Group III nitride layer.

17. The transistor device of claim 16, wherein the thickness of the second Group III nitride layer or the aluminum concentration of the second Group III nitride layer is such that, relative to the operation of the transistor device before the stress condition, at a gate voltage of 0V, the current collapse of the transistor device after the stress condition is approximately 30% or less, wherein the stress condition comprises a 10 millisecond pulse of a drain voltage of 100V and a gate voltage of -8V.

18. The transistor device of claim 16, wherein the thickness of the second Group III nitride layer or the aluminum concentration of the second Group III nitride layer is such that relative to the operation of the transistor device before the stress condition, at a drain voltage of 50V, the pinch-off voltage shift of the transistor device after the stress condition is approximately 0.4V or less, wherein the stress condition comprises a 10 millisecond pulse of a drain voltage of 100V and a gate voltage of -8V.

19. The transistor device of claim 16, wherein the multilayer barrier structure comprises an interface layer, the first Group III nitride layer being disposed on the interface layer and opposite to the channel layer, wherein an aluminum concentration of the interface layer is greater than an aluminum concentration of the first Group III nitride layer and an aluminum concentration of the second Group III nitride layer.

20. The transistor device of claim 19, wherein the thickness of the interfacial layer is in the range of about 50 angstroms or less.

21. The transistor device of claim 16, wherein the aluminum concentration of the first Group III-nitride layer is at least twice as great as the aluminum concentration of the second Group III-nitride layer.

22. A transistor device comprising: Channel layer; and a multilayer barrier structure on the channel layer, the multilayer barrier structure comprising a first layer on the channel layer, a second layer on the first layer, and a third layer on the second layer; The first layer is Al x Ga 1-x N layers, where x ≥ 0.5; The second layer is Al y Ga 1-y N layers, where 0.2≤y<1; The third layer is Al z Ga 1-z N layers, where 0 <z≤0.1。 23 . The transistor device of claim 22 , wherein a ratio of a thickness of the second layer to a thickness of the third layer is 4:1 or greater.

24. The transistor device of claim 22, further comprising a silicon carbide substrate.

25. A transistor device comprising: Channel layer; and A multilayer III-nitride-based barrier structure on the channel layer, the multilayer III-nitride-based barrier structure comprising a first layer and a second layer on the first layer, wherein the thickness of the second layer or the aluminum concentration of the second layer is such that relative to the operation of the transistor device before the stress condition, at a gate voltage of 0V, the current collapse of the transistor device after the stress condition is approximately 30% or less, wherein the stress condition comprises a 10 millisecond pulse of a drain voltage of 100V and a gate voltage of -8V.

26. The transistor device of claim 25, wherein a ratio of a thickness of the first layer to a thickness of the second layer is about 4:

1.

27. The transistor device of claim 25, wherein the aluminum concentration of the first layer is at least twice as great as the aluminum concentration of the second layer at an interface between the first layer and the second layer.

28. A transistor device comprising: Channel layer; and A multi-layer III-nitride-based barrier structure on the channel layer, the multi-layer III-nitride-based barrier structure includes a first layer and a second layer on the first layer, wherein the thickness of the second layer or the aluminum concentration of the second layer makes the transistor device have a pinch-off voltage shift of about 0.4V or less after the stress condition at a drain voltage of 50V relative to the operation of the transistor device before the stress condition, wherein the stress condition includes a 10 millisecond pulse of a drain voltage of 100V and a gate voltage of -8V.

29. The transistor device of claim 28, wherein a ratio of a thickness of the first layer to a thickness of the second layer is about 4:

1.

30. The transistor device of claim 28, wherein the aluminum concentration of the first layer is at least twice as great as the aluminum concentration of the second layer at an interface between the first layer and the second layer.

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