Semiconductor device, manufacturing method thereof and storage system

Abstract

The embodiment of the invention discloses a semiconductor device, a manufacturing method thereof and a storage system. The device comprises a stacked structure; the stacked structure comprises a first region and a second region; the channel structure is located in the first region and penetrates through the stacking structure in the first direction; the grid line isolation structure is located in the second area and extends in the second direction, the grid line isolation structure penetrates through the stacking structure in the first direction, and the grid line isolation structure is in a concave-convex shape in the third direction.

Description

Semiconductor device and manufacturing method thereof and storage system

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and a storage system.

[0002] As the feature size of memory cells approaches the process lower limit, planar processes and manufacturing technologies become challenging and costly, which causes the storage density of 2D structured memories to approach an upper limit.

[0003] To overcome the limitations of 2D structured memories, the industry has developed memories with three-dimensional structures, which increase storage density by arranging storage cells three-dimensionally on a substrate.

[0004] A three-dimensional memory may include a semiconductor structure as a memory array and peripheral devices. How to improve the manufacturing yield and reliability of the semiconductor structure is an issue to be resolved.

[0005]

[0006] The present application provides a semiconductor device and a manufacturing method and a storage system thereof, which improve the yield and reliability of the semiconductor device.

[0007] In a first aspect, the present application provides a method for manufacturing a semiconductor device, comprising:

[0008] Providing a stacked layer; the stacked layer comprises a dielectric layer and a sacrificial layer that are alternately stacked, and the stacked layer comprises a first region and a second region;

[0009] Forming a plurality of channel holes penetrating the stacked layer along a first direction in the first region, and forming a plurality of first virtual channel holes penetrating the stacked layer along the first direction in the second region;

[0010] forming a plurality of channel structures in the plurality of channel holes;

[0011] forming a gate line gap groove extending in a second direction and surrounding the plurality of first dummy channel holes, wherein the second direction intersects the first direction;

[0012] A gate line isolation structure is formed in the gate line gap groove, and the gate line isolation structure is concave-convex along a third direction; the third direction intersects the first direction and the second direction.

[0013] In one embodiment of the present application, the step of forming a gate line gap groove extending in the second direction and surrounding the plurality of first dummy channel holes comprises:

[0014] The plurality of first virtual channel holes are etched to form a plurality of second virtual channel holes, and the plurality of second virtual channel holes are connected in the second direction to form the gate line gap grooves.

[0015] In one embodiment of the present application, before the step of forming a plurality of channel structures in the plurality of channel holes, the method further includes:

[0016] A sacrificial material is filled in the channel hole and the first dummy channel hole, and the sacrificial material in the channel hole is removed.

[0017] In one embodiment of the present application, after the sacrificial material is filled in the channel hole and the first dummy channel hole, and before the step of removing the sacrificial material in the channel hole, the method further includes:

[0018] A capping layer is formed on the top of the stacked layer, and the capping layer located above the channel hole is removed.

[0019] In one embodiment of the present application, before the step of forming a gate line slit trench extending in the second direction and surrounding the plurality of first dummy channel holes, the method further includes:

[0020] The sacrificial material in the first dummy channel hole is removed.

[0021] In one embodiment of the present application, after the step of forming a plurality of channel structures in the plurality of channel holes and before the step of removing the sacrificial material in the first virtual channel hole, the method further includes: forming a protective layer on top of the stacked layer.

[0022] In one embodiment of the present application, the protection layer includes polysilicon.

[0023] In one embodiment of the present application, before forming the gate line isolation structure in the gate line gap trench, the method further includes:

[0024] The sacrificial layer in the stacked layer is replaced with a gate line layer.

[0025] In one embodiment of the present application, the shape of the first virtual channel hole includes any one of an ellipse and a circle, and the shape of the channel hole includes a circle.

[0026] In one embodiment of the present application, the stacked layer includes a core region and a stepped region;

[0027] A plurality of first dummy channel holes having the same aperture along the third direction are formed in the core region and the step region.

[0028] In one embodiment of the present application, the stacked layer includes a core region and a stepped region;

[0029] The apertures of the plurality of first dummy channel holes formed in the core region along the third direction are smaller than the apertures of the plurality of first dummy channel holes formed in the step region along the third direction.

[0030] In one embodiment of the present application, the step of forming a plurality of channel holes penetrating the stacked layer in the first region along the first direction, and forming a plurality of first virtual channel holes penetrating the stacked layer in the second region along the first direction includes:

[0031] Forming a composite photolithography layer on the dielectric layer at the top of the stacked layers; and forming a plurality of first grooves and a plurality of second grooves in the composite photolithography layer; the first grooves are located in the first region, and the second grooves are located in the second region;

[0032] Etching the stacked layer in the first region through the first groove to form a plurality of channel holes; and,

[0033] The stacked layer in the second region is etched through the second trench to form a plurality of first dummy channel holes.

[0034] In one embodiment of the present application, the plurality of channel holes and the plurality of first dummy channel holes are formed in the same process.

[0035] In one embodiment of the present application, the step of forming a composite photolithography layer on the top dielectric layer in the stacked layers comprises:

[0036] forming a stop layer on the top dielectric layer, and forming a first mask layer on the stop layer;

[0037] The first mask layer is etched through the stop layer until the dielectric layer on top of the stacked layer is exposed to form the composite photolithography layer.

[0038] In one embodiment of the present application, the first mask layer includes a hard mask layer or a photoresist layer.

[0039] In order to solve the above problem, an embodiment of the present invention further provides a semiconductor device, including:

[0040] A stacked structure; the stacked structure comprises a dielectric layer and a gate line layer that are staggered and stacked, and the stacked structure comprises a first region and a second region;

[0041] A channel structure located in the first region and penetrating the stack structure along a first direction;

[0042] A gate line isolation structure is located in the second area and extends along the second direction, the gate line isolation structure penetrates the stacking structure along the first direction, and the shape of the gate line isolation structure along the third direction is concave and convex, wherein the second direction intersects with the first direction, and the third direction intersects with the first direction and the second direction.

[0043] In one embodiment of the present application, the semiconductor device further includes: a protection layer is provided on the top of the stack structure.

[0044] In one embodiment of the present application, the gate line isolation structure includes a sidewall extending along the second direction, the sidewall includes a plurality of substructures connected end to end, and two adjacent substructures are not coplanar.

[0045] In one embodiment of the present application, the stacked structure includes a core region and a stepped region;

[0046] The size of the gate line isolation structure located in the core area along the third direction is equal to the size of the gate line isolation structure located in the step area along the third direction.

[0047] In one embodiment of the present application, the stacked structure includes a core region and a stepped region;

[0048] A size of the gate line isolation structure located in the core region along the third direction is smaller than a size of the gate line isolation structure located in the step region along the third direction.

[0049] In order to solve the above problems, an embodiment of the present invention further provides a storage system, comprising: a controller and a three-dimensional memory, wherein the controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data, and the three-dimensional memory includes any one of the semiconductor devices described above.

[0050] The beneficial effects of the present application are as follows: the stacked layer includes a first region and a second region, a plurality of channel holes penetrating the stacked layer along a first direction are formed in the first region, and a plurality of first virtual channel holes penetrating the stacked layer along the first direction are formed in the second region. Then, a plurality of channel structures are formed in the plurality of channel holes, and a gate line gap groove extending in a second direction and surrounding the plurality of first virtual channel holes is formed, the second direction intersects the first direction, a gate line isolation structure is formed in the gate line gap groove, and the shape of the gate line isolation structure along the third direction is concave-convex. The present application can improve the yield and reliability of the device.

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0052] FIG1 is a schematic top view of a semiconductor device exemplified in the present application;

[0053] 2-3 are schematic diagrams of the structure of the semiconductor device in several stages of the example of FIG. 1;

[0054] 4 to 16 are schematic diagrams of structures of semiconductor devices at several stages provided by embodiments of the present application;

[0055] 17 to 26 are schematic top views of a semiconductor device at several stages provided by an embodiment of the present application;

[0056] 27 is a schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0057] FIG. 28 is a schematic diagram of the structure of the storage system provided in an embodiment of the present application.

[0058] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0059] In the description of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present application, "plurality" means two or more, unless otherwise clearly and specifically defined.

[0060] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0061] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0062] As used in this application, the term "layer" refers to a material portion including a region with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far away from the substrate. The layer can extend over the entire lower layer or upper structure, or can have a range less than the lower layer or upper structure range. In addition, the layer can be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure or between any group of horizontal planes at the top surface and the bottom surface. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, wherein one or more layers can be included, and / or one or more layers can be provided thereon, above and / or below. The layer can include multiple layers. For example, an interconnect layer can include one or more gate line layers and a contact layer (wherein contacts, interconnects and one or more dielectric layers are formed).

[0063] It should be noted that the illustrations provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0064] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0065] Three-dimensional memory has high storage density and high storage capacity, and thus has been used more and more widely. In the related art, the preparation process of three-dimensional memory generally includes the following main process steps: forming a channel hole (CH) in the core area of ​​the stacked structure, forming a step area (SS) on the periphery of the core area, forming a dummy channel hole (DCH) in the step area, then replacing the sacrificial layer in the stacked layer to form a gate line structure (GL), and forming a gate contact (CT) leading out of each gate line layer in the step area.

[0066] For example, FIG. 1 is a schematic diagram of a top view of a 3D NAND memory, FIG. 2-FIG. 3 are schematic diagrams of a structure of a 3D NAND memory, and FIG. 2-FIG. 3 are schematic cross-sectional views of the 3D NAND memory along the X-Cut line and along the Y-Cut line in FIG. 1. As shown in FIG. 2 to FIG. 3, a channel hole 33 is first formed to penetrate the stacked layer 201, a channel structure 330 is formed in the channel hole 33, and then a gate line gap groove 101 extending along a second direction (e.g., the X-axis direction) and penetrating the stacked layer 201 needs to be formed at a preset position between the channel structures 330. Then, a gate line isolation structure 102 is formed in the gate line gap groove 101 to obtain the 3D NAND memory as shown in FIG. 1.

[0067] However, since the depth-to-width ratio of the formed gate line gap groove 101 is larger than the depth-to-width ratio of the communication hole, and the side wall of the gate line isolation structure 102 formed in the gate line gap groove 101 is straight, the incision of the gate line isolation structure 102 is very fragile, and the gate line isolation structure 102 extends for a long time along its extension direction. The side wall of the gate line isolation structure 102 is equivalent to a very high wall. Under the action of stress, it is easy to tilt or twist, causing the gate line isolation structure 102 to be unable to maintain its shape. This will result in the inability to ensure the continuity of the conductive material in the gate line isolation structure 102 after filling with the conductive material, thereby causing the problem of gate line short circuit and device failure.

[0068] In addition, as the number of storage layers increases, the aspect ratio of the etched channel hole 33 and the gate line gap groove 101 continues to increase, which makes the etching process more difficult. As shown in Figures 2 and 3, etching the channel hole 33 and the gate line gap groove 101 separately is not only costly, but also causes mutual interference due to tilting, resulting in certain yield damage. Due to the problem of mutual interference due to the increasing aspect ratio of the etched channel hole 33 and the gate line gap groove 101, it is also impossible to further develop and produce 3D NAND memory with more storage layers.

[0069] In order to solve the above problems, with reference to FIGS. 4 to 28, an embodiment of the present application provides a semiconductor device 100, a method for manufacturing the same, and a storage system. When the stacked layer 201 is etched in the first region 202 to form a channel hole 33, the stacked layer 201 is etched in the second region 203 by the same process to form a first virtual channel hole 34. Subsequently, through a series of processes, the gate line gap groove 101 is formed using the first virtual channel hole 34 in the second region 203, thereby realizing the one-time etching of the channel hole 33 in the first region 202 and the gate line gap groove 101 in the second region 203. The semiconductor device 100 of the present application has a low manufacturing cost and solves the problem of yield loss caused by the inclination of the channel structure 330 and the gate line isolation structure 102.

[0070] Please refer to FIG. 27 , which is a schematic flow chart of a method for manufacturing a semiconductor device 100 according to an embodiment of the present application. The specific flow chart is based on the structural diagrams of FIGS. 4 to 26 , and may include the following steps:

[0071] Step S100 , providing a stacked layer 201 ; the stacked layer 201 includes alternately stacked dielectric layers 30 and sacrificial layers 40 , and the stacked layer 201 includes a first region 202 and a second region 203 .

[0072] In some embodiments of the present application, a stacked layer 201 as shown in FIG. 4 is provided, and the stacked layer 201 includes dielectric layers 30 and sacrificial layers 40 that are staggered and stacked in a first direction and extend along a second direction and a third direction. The second direction intersects the first direction, and the third direction intersects the first direction and the second direction. Here, the second direction intersecting the first direction can be understood as the angle between the second direction and the first direction is less than or equal to 90 degrees, and the third direction intersecting the first direction and the second direction can be understood as the angle between the third direction and the plane where the first direction and the second direction are located is less than or equal to 90 degrees. In some specific examples of the present application, the angle between the second direction and the first direction is equal to 90 degrees, and the angle between the third direction and the plane where the first direction and the second direction are located is equal to 90 degrees.

[0073] In some specific examples, the first direction can be understood as the Z-axis direction shown in Figures 4-26, the second direction can be understood as the X-axis direction shown in Figures 4-26, and the third direction can be understood as the Y-axis direction shown in Figures 4-26.

[0074] Specifically, a substrate 50 is first provided, and the substrate 50 extends in the second direction (X-axis direction) and the third direction (Y-axis direction) to form a substrate stacking surface, and a stacking layer 201 is formed on the stacking surface. As an example, the substrate 50 can be selected according to the actual needs of the device, for example, it can include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate or a GOI (Germanium-on-Insulator) substrate, etc. Preferably, in this embodiment, the substrate 50 includes a single crystal silicon substrate.

[0075] In some embodiments of the present application, the substrate 50 is a semiconductor substrate. For example, the substrate may be a single crystal silicon (Si) substrate, a single crystal germanium (Ge) substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate, etc. It should be noted that the substrate may be a substrate after ion doping, specifically, a P-type doped substrate or an N-type doped substrate. Suitable materials may be selected as substrates according to actual needs, and the present application does not impose specific restrictions on this. Of course, in other embodiments, the material of the substrate may also be a semiconductor or compound including other elements. For example, the substrate may be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, or a silicon carbide (SiC) substrate, etc.

[0076] In some embodiments of the present application, a deposition method is selected according to actual needs to form a stacking layer 201 having a multi-layer structure on a stacking surface. The number of stacking layers 201 in Figures 4 to 16 is only an example. For example, the number of dielectric layers 30 and sacrificial layers 40 in the stacking layer 201 may include 32 layers, 64 layers, 96 layers or 128 layers, etc. Specifically, the number of dielectric layers 30 and sacrificial layers 40 in the stacking layer 201 can be set according to actual needs, that is, the number of stacking layers 201 is not limited.

[0077] In some embodiments of the present application, a substrate may be provided, and a stacked layer 201 may be formed on the substrate, wherein the stacked layer 201 includes dielectric layers 30 and sacrificial layers 40 extending along a second direction (e.g., an X-axis direction) and a third direction (e.g., a Y-axis direction) and stacked alternately along a first direction (e.g., a Z-axis direction). In some embodiments, the substrate may be removed in a subsequent process to obtain a semiconductor device 100 that does not include a substrate 50, or may be retained to form a substrate 50 to obtain a semiconductor device 100 that includes a substrate 50, which is not specifically limited herein.

[0078] In some embodiments of the present application, the materials of the sacrificial layer 40 and the dielectric layer 30 are made of insulating materials, and the insulating materials include but are not limited to any one of polysilicon, silicon nitride, silicon oxide, and aluminum oxide, or any combination of multiple thereof. Silicon oxide here refers to silicon oxide compounds, such as SixOy, and silicon nitride refers to nitrogen silicon compounds, such as SixNy. Exemplarily, the sacrificial layer 40 can be silicon nitride, and the dielectric layer 30 can be silicon oxide. The sacrificial layer 40 and the dielectric layer 30 have different etching selectivities, and the deposition methods of the sacrificial layer 40 and the dielectric layer 30 can be but are not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD).

[0079] 4 to 19 , 25 and 26 , the stacked layer 201 is divided into a first region 202 and a second region 203. It should be noted that the first region 202 and the second region 203 are distinguished only for convenience of description and do not represent the physical division of the stacked layer 201 or the size of the stacked layer 201.

[0080] Step S200 , forming a plurality of channel holes 33 penetrating the stacked layer 201 along a first direction (eg, Z-axis direction) in the first region 202 , and forming a plurality of first dummy channel holes 34 penetrating the stacked layer 201 along the first direction in the second region 203 .

[0081] In some embodiments of the present application, the step of forming a plurality of channel holes 33 penetrating the stacked layer 201 in the first region 202 in the stacked layer 201 along the first direction, and forming a plurality of first virtual channel holes 34 penetrating the stacked layer 201 in the second region 203 along the first direction, includes:

[0082] Step S210, forming a composite photolithography layer 11 on the dielectric layer 30 at the top of the stacked layer 201; and forming a plurality of first grooves 31 and a plurality of second grooves 32 in the composite photolithography layer 11; the first grooves 31 are located in the first region 202, and the second grooves 32 are located in the second region 203.

[0083] In some embodiments of the present application, referring to FIG. 4 to FIG. 6 showing the structure formed in step S210, the structure shown in FIG. 5 and FIG. 6 includes a substrate 50, a stacked layer 201 arranged in a first direction (Z-axis direction), a plurality of first regions 202 arranged in the stacked layer 201, and a second region 203 located between the two first regions 202, a composite photolithography layer 11 is provided on the dielectric layer 30 on the top of the stacked layer 201, a plurality of first grooves 31 formed in the composite photolithography layer 11 are located in the first region 202, and the channel holes 33 in the following embodiments are formed by etching the stacked layer 201 with the first grooves 31 aligned with the first region 202, and the plurality of second grooves 32 in the composite photolithography layer 11 are located in the second region 203, and the first virtual channel holes 34 in the following embodiments are formed by etching the stacked layer 201 with the second grooves 32 aligned with the second region 203.

[0084] In some embodiments of the present application, the step of forming the composite photolithography layer 11 on the dielectric layer 30 at the top of the stacked layer 201 in S210 includes:

[0085] Step S211 , forming a stop layer 20 on the top dielectric layer 30 , and forming a first mask layer 10 on the stop layer 20 .

[0086] Step S212 , etching the first mask layer 10 through the stop layer 20 until the dielectric layer 30 on the top of the stacked layer is exposed, so as to form the composite photolithography layer 11 .

[0087] In some embodiments of the present application, referring to FIGS. 4 to 6, the present application adopts an etching process to form a plurality of channel holes 33 penetrating the stacked layer 201 in the first region 202 along a first direction (e.g., the Z-axis direction), and adopts an etching process to form a plurality of first virtual channel holes 34 penetrating the stacked layer 201 in the second region 203 along a first direction (e.g., the Z-axis direction). The etching process adopted in the embodiments of the present application may be dry etching or wet etching.

[0088] In some embodiments of the present application, as shown in FIG4 , a stop layer 20 and a patterned first mask layer 10 may be sequentially formed on the dielectric layer 30 at the top of the stacked layer 201 by a deposition process. The dielectric layer 30 may be silicon oxide, and the material of the stop layer 20 includes silicon nitride or silicon oxynitride. In practical applications, the stop layer 20 and the first mask layer 10 may be formed by a deposition process, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD) or atomic layer deposition (ALD).

[0089] In some embodiments of the present application, the first mask layer 10 includes a hard mask layer or a photoresist layer.

[0090] In some embodiments of the present application, the first mask layer 10 may be a photoresist layer (abbreviated as PR), and the photoresist layer is formed on the stop layer 20, and the photoresist layer is exposed through a photomask, and the exposed photoresist layer is developed to remove the photoresist layer that is not exposed to light, thereby forming a patterned photoresist layer on the stop layer 20. In some embodiments, the first mask layer 10 may also be a hard mask layer (abbreviated as HM).

[0091] In some embodiments of the present application, as shown in FIG5 and FIG6, the patterned first mask layer 10 has a photolithographic opening, and the patterned first mask layer 10 is used as a mask to etch the stop layer 20 to form a first groove 31 and a second groove 32 corresponding to the photolithographic opening on the stop layer 20, wherein the first groove 31 exposes the dielectric layer 30 at the top of the stacked layer 201 in the first region 202, and the second groove 32 exposes the dielectric layer 30 at the top of the stacked layer 201 in the second region 203. Here, etching the stop layer 20 is performed, for example, by a dry etching process. In practical applications, the etching process may be one of sputtering etching, chemical etching, or high-density plasma etching.

[0092] In some embodiments of the present application, the process of etching the stop layer 20 is: using the patterned first mask layer 10 as a mask, etching the stop layer 20, and forming the first groove 31 and the second groove 32b with a bottom opening size greater than or equal to the top opening size as shown in Figure 6, or forming the first groove 31 and the second groove 32a with a bottom opening size smaller than the top opening size as shown in Figure 5.

[0093] In some embodiments of the present application, since there is a stop layer 20 under the first mask layer 10, the etching time can be extended so that the bottom opening size of the formed first groove 31 is greater than or equal to the top opening size, and the bottom opening size of the formed second groove 32b is greater than or equal to the top opening size.

[0094] In actual application, when etching the stop layer 20, the opening size at the bottom of the first groove 31 and the opening size at the bottom of the second groove 32 are widened, thereby avoiding the footing (root defect or bottom defect) phenomenon caused by the edge etching rate of the first mask layer 10 being lower than the center etching rate of the first mask layer 10.

[0095] In the embodiment of the present application, the patterned first mask layer 10 is used as a mask to etch the stop layer 20 to form the second groove 32b whose bottom opening size is greater than or equal to the top opening size. In practical applications, since there is a stop layer 20 under the first mask layer 10, the etching time can be extended to achieve the effect of widening the opening size at the bottom of the second groove 32b, so that the bottom opening size of the second groove 32b formed in the first mask layer 10 is greater than or equal to the top opening size. The present application adds a stop layer 20 between the first mask layer 10 and the substrate, thereby avoiding the footing phenomenon caused by excessive byproducts generated by the reaction between the etching gas and the dielectric layer 30 of the stacked layer 201, and when the first mask layer 10 is etched, the opening size at the bottom of the second groove 32b is widened, thereby avoiding the footing phenomenon caused by the edge etching rate of the first mask layer 10 being less than the center etching rate of the first mask layer 10.

[0096] In the embodiment of the present application, the stop layer 20 is etched by, for example, a dry etching process or a wet etching process. In practical applications, the etching medium selected by the wet etching process may be a phosphoric acid solution, which has a high etching selectivity ratio, and has a high etching rate for the stop layer 20 (e.g., silicon nitride), while the etching rate for the first mask layer 10 (e.g., silicon oxide) is almost zero.

[0097] In actual application, when the stop layer 20 is etched by a dry etching process, the opening size of the second groove can be controlled by controlling the dry etching time; when the stop layer 20 is etched by a wet etching process, the opening size of the second groove can be controlled by controlling the wet etching time and the concentration of the etching solution.

[0098] In the embodiment of the present application, before etching the stop layer 20 through the second groove 32 b , the patterned first mask layer 10 may be removed, thereby reducing pollutants generated by the first mask layer 10 being bombarded by etching gas during the etching process.

[0099] Step S220 , etching the stacked layer 201 in the first region 202 through the first trench 31 to form a plurality of channel holes 33 .

[0100] Step S230 , etching the stacked layer 201 in the second region 203 through the second trench 32 to form a plurality of first virtual channel holes 34 .

[0101] In some embodiments of the present application, referring to FIG. 5 to FIG. 7 and FIG. 17 to FIG. 22, structures formed by steps S220 to S230 are shown. The structure shown in FIG. 7 includes a substrate 50, a stacked layer 201 arranged in a first direction (Z-axis direction), a plurality of first regions 202 arranged in the stacked layer 201, and a second region 203 located between two first regions 202. The first region 202 includes a plurality of channel holes 33 penetrating the stacked layer 201, and the second region 203 includes a plurality of first virtual channel holes 34 penetrating the stacked layer 201. Region 53 in FIG. 7 is a schematic cross-sectional view of the semiconductor device 100 along line AA' in FIG. 17 to FIG. 19, region 52 in FIG. 7 is a schematic cross-sectional view of the semiconductor device 100 along line BB' in FIG. 17 to FIG. 19, and region 51 in FIG. 7 is a schematic cross-sectional view of the semiconductor device 100 along line CC' in FIG. 17 to FIG. 19.

[0102] Some embodiments of the present application use an etching process to form a plurality of channel holes 33 that penetrate the stacked layer 201 located in the first region 202 along a first direction (for example, the Z-axis direction), and use an etching process to form a plurality of first virtual channel holes 34 that penetrate the stacked layer 201 located in the second region 203 along a first direction (for example, the Z-axis direction). The etching process used in some embodiments of the present application may be dry etching or wet etching.

[0103] In some embodiments, the channel hole 33 may further extend into the substrate 50 without passing through the substrate 50 , and the first dummy channel hole 34 may further extend into the substrate 50 without passing through the substrate 50 .

[0104] In some embodiments of the present application, a plurality of channel holes 33 may be arranged in an array.

[0105] In some embodiments, the plurality of channel holes 33 in the first region 202 and the plurality of first dummy channel holes 34 in the second region 203 may be formed in the same process to simultaneously form the plurality of channel holes 33 and the plurality of first dummy channel holes 34 in the first region 202 and the second region 203 .

[0106] In some embodiments of the present application, the plurality of channel holes 33 and the plurality of first dummy channel holes 34 are staggered and arranged in an alternating manner in the second direction.

[0107] In some embodiments of the present application, the shape of the first virtual channel hole 34 includes but is not limited to any one of an ellipse and a circle, and the shape of the channel hole 33 includes a circle. For example, as shown in Figures 17 to 20, the shape of the first virtual channel hole 34 includes an ellipse, and the major diameter of the ellipse is located in the third direction (Y-axis direction).

[0108] In some alternative embodiments, the above-mentioned ellipse can also be replaced by other shapes (such as oblate, rectangular, rhombus, etc.) that can be obtained by compressing a centrally symmetrical shape (such as a circle or a square) in a certain direction, or stretching it by a certain proportion.

[0109] Exemplarily, as shown in FIG. 7 , the aperture of the first virtual channel hole 34 is represented as D, and the aperture of the channel hole 33 is represented as L. The aperture D of the first virtual channel hole 34 and the aperture L of the channel hole 33 may be the same or different.

[0110] In some embodiments, the number of layers of the stacked layer 201 may be 8 layers, 32 layers, 64 layers, or 128 layers, etc. When the number of layers of the stacked layer 201 is small, such as 8 layers, the stacked layer 201 may be directly deposited, and the channel hole 33 and the first virtual channel hole 34 may be formed by synchronous etching again. When the number of layers of the stacked layer 201 is large, such as 128 layers, the stacked layer 201 may be split into multiple parts, and the first sub-stacked layer 201 and the second sub-stacked layer 201 may be formed by two deposition processes, and the first sub-stacked layer 201 is located above the second sub-stacked layer 201. At this time, the channel hole 33 and the first virtual channel hole 34 are also formed by two etchings, that is, the channel hole 33 and the first virtual channel hole 34 are formed in the first sub-stacked layer 201 and the second sub-stacked layer 201 in sequence.

[0111] In addition, it should be noted that the dotted lines in the figures are used to distinguish different structural parts, and do not mean that the dotted lines actually exist. The dotted arrows in the figures are used to mark the distance or size between two parts, and do not mean that there is a connection relationship in reality.

[0112] For example, in some embodiments of the present application, before forming a channel hole 33 penetrating the stacked layer 201 in the first region 202 and forming a first virtual channel hole 34 penetrating the stacked layer 201 in the second region 203, a patterned first mask layer 10 is formed on the top surface of the stacked layer 201 to form a first trench 31 and a second trench 32 through the patterned first mask layer 10. The vertical projection of the first trench 31 on the top of the stacked layer 201 may at least substantially overlap with the position of the channel hole 33, and the vertical projection of the second trench 32 on the top of the stacked layer 201 may at least substantially overlap with the position of the first virtual channel hole 34.

[0113] An appropriate etching process is performed through the first mask layer 10, for example, dry etching or wet etching, to remove the portion of the dielectric layer 30 and the sacrificial layer 40 of the stacked layer 201 in the first region 202 exposed by the first groove 31 to form a channel hole 33 as shown in FIG7 , until the channel hole 33 formed by etching exposes the substrate 50. In addition, the portion of the dielectric layer 30 and the sacrificial layer 40 of the stacked layer 201 in the second region 203 exposed by the second groove 32 is removed to form a first virtual channel hole 34 as shown in FIG7 , until the first virtual channel hole 34 formed by etching exposes the substrate 50. In other words, the channel hole 33 and the first virtual channel hole 34 extend from the surface of the stacked layer 201 facing away from the substrate 50 to the stacking surface of the substrate 50 to expose the substrate 50, and a portion of the channel hole 33 and the first virtual channel hole 34 are located in the substrate 50, but do not penetrate the substrate 50. After the channel hole 33 and the first dummy channel hole 34 are formed, the first mask layer 10 may be removed.

[0114] It should be noted that a plurality of channel holes 33 and a first virtual channel hole 34 can be formed on the stacked layer 201 at the same time, that is, the first mask layer 10 can form a plurality of first grooves 31 corresponding to the plurality of channel holes 33, and a plurality of second grooves 32 corresponding to the plurality of first virtual channel holes 34, and the positions of the plurality of first grooves 31 correspond to the positions of the plurality of channel holes 33 formed subsequently, and the positions of the plurality of second grooves 32 correspond to the positions of the plurality of first virtual channel holes 34 formed subsequently. In some embodiments of the present application, no specific restrictions are imposed on the number, size and arrangement of the channel holes 33 and the first virtual channel holes 34. That is, the channel holes 33 and the first virtual channel holes 34 shown in FIG. 7 and FIG. 17 to FIG. 26 are only examples and are not used to limit the position and number of the channel holes 33 and the first virtual channel holes 34.

[0115] In some embodiments of the present application, a first virtual channel hole 34 penetrating the stacked layer 201 along a first direction (e.g., Z-axis direction) is formed by, for example, a dry / wet etching process, and the first virtual channel hole 34 can further extend into the substrate 50. The formation process of the first virtual channel hole 34 is essentially the same as that of the channel hole 33, that is, in the embodiments of the present application, the first virtual channel hole 34 can be regarded as the channel hole 33, except that the first virtual channel hole 34 located in the second region 203 is not used to form a channel structure 330, but to form a gate line gap groove 101 for isolating a plurality of channel structures 330.

[0116] In some embodiments of the present application, when the stacked layer 201 is etched in the first region 202 to form the channel hole 33, the stacked layer 201 is etched in the second region 203 by the same process to form the first virtual channel hole 34, so that the channel hole 33 in the first region 202 and the first virtual channel hole 34 in the second region 203 are etched and formed at the same time. Subsequently, through a series of processes, a channel structure 330 is formed in the channel hole 33 in the first region 202, and a gate line isolation structure 102 is formed in the first virtual channel hole 34 in the second region 203. The semiconductor device 100 formed according to some embodiments of the present application has a low manufacturing cost and solves the problem of yield loss caused by the inclination of the channel structure 330 and the gate line isolation structure 102.

[0117] Step S300 , forming a plurality of channel structures 330 in the plurality of channel holes 33 .

[0118] In some embodiments of the present application, before the step S300 of forming a plurality of channel structures 330 in the plurality of channel holes 33, the method further includes:

[0119] Step S250 , filling the channel hole 33 and the first dummy channel hole 34 with a sacrificial material 60 .

[0120] In some embodiments of the present application, FIG8 shows a structure formed in step S250. The structure shown in FIG8 includes a substrate 50, a stacked layer 201 arranged in a first direction (Z-axis direction), a plurality of first regions 202 arranged in the stacked layer 201, and a second region 203 located between two first regions 202, the first region 202 includes a plurality of channel holes 33 penetrating the stacked layer 201, the second region 203 includes a plurality of first virtual channel holes 34 penetrating the stacked layer 201, and the plurality of channel holes 33 and the plurality of first virtual channel holes 34 are both filled with a sacrificial material 60.

[0121] Step S270 , removing the sacrificial material 60 in the channel hole 33 .

[0122] In some embodiments of the present application, after the step S250 of filling the sacrificial material 60 in the channel hole 33 and the first dummy channel hole 34 and before the step S270 of removing the sacrificial material 60 in the channel hole 33, the method further includes:

[0123] Step S260 , forming a capping layer 71 on the top of the stacked layer 201 , and removing the capping layer 71 located above the channel hole 33 .

[0124] In some embodiments of the present application, FIG9 to FIG11 show the structure formed by steps S260 to S270. The structure shown in FIG9 includes a substrate 50, a stacked layer 201 arranged in a first direction (Z-axis direction), a plurality of first regions 202 arranged in the stacked layer 201, and a second region 203 located between two first regions 202, the first region 202 includes a plurality of channel holes 33 penetrating the stacked layer 201, the second region 203 includes a plurality of first virtual channel holes 34 penetrating the stacked layer 201, the channel holes 33 and the first virtual channel holes 34 are both filled with sacrificial material 60, and a cap layer 71 is further provided above the stacked layer 201, the cap layer 71 covers the channel holes 33 filled with sacrificial material 60 and the first virtual channel holes 34 filled with sacrificial material 60. FIG10 shows the structure formed by step S260, and the cap layer 71 located above the channel holes 33 is removed relative to the structure shown in FIG9. Compared with the structure shown in FIG. 10 , the sacrificial material 60 filled in the channel hole 33 in FIG. 8 is removed in the structure shown in FIG. 11 , the sacrificial material 60 is filled in the first dummy channel hole 34 , and a cap layer 71 a is provided above the first dummy channel hole 34 .

[0125] In some embodiments, a cap layer 71 may be formed on a side of the stack layer 201 away from the substrate 50 by a thin film deposition process to cover the top of the stack layer 201. The cap layer 71 may be made of a dielectric material such as silicon oxide.

[0126] As shown in FIG8 , the sacrificial material 60 can be filled in the channel hole 33 and the first virtual channel hole 34 shown in FIG7 by a deposition process, and then a cap layer 71 as shown in FIG9 can be formed on the top of the stacked layer 201 by a deposition process. As shown in FIG10 , a portion of the cap layer 71 located above the channel hole 33 is removed by an etching process, and the cap layer 71a located above the first virtual channel hole 34 is retained, the cap layer 71a covers the first virtual channel hole 34, and the cap layer 71a does not overlap with the projection of the channel hole 33 on the substrate 50, that is, as shown in FIG10 , the cap layer 71a covers the first virtual channel hole 34, but does not cover the channel hole 33. Among them, the material of the cap layer 71a is different from the sacrificial material 60. The sacrificial material 60 located in the channel hole 33 can be removed by an etching process to obtain a semiconductor structure as shown in FIG11 .

[0127] In some embodiments, the sacrificial material 60 may include, but is not limited to, any one of carbon, polysilicon, silicon nitride, silicon oxide, aluminum oxide, or any combination thereof. In this embodiment, the sacrificial material 60 may be carbon or polysilicon.

[0128] In some embodiments, both the channel hole 33 and the first dummy channel hole 34 may further extend into the substrate 50 without passing through the substrate 50 .

[0129] In addition, it should be noted that after removing the sacrificial material 60 in the channel hole 33 , the cap layer 71 a above the first dummy channel hole 34 may be removed.

[0130] In some embodiments of the present application, FIG. 12 shows the steps of forming step S300. The structure shown in FIG. 12 includes a substrate 50, a stacked layer 201 arranged in a first direction (Z-axis direction), a plurality of first regions 202 arranged in the stacked layer 201, and a second region 203 located between two first regions 202. The first region 202 includes a plurality of channel structures 330 penetrating the stacked layer 201, and the second region 203 includes a plurality of first virtual channel holes 34 penetrating the stacked layer 201. The first virtual channel holes 34 are filled with sacrificial materials 60, and a cap layer 71a is provided above the first virtual channel holes 34. The top of the stacked layer 201 is covered with a conductive layer 75, that is, the conductive layer 75a shown in FIG. 12 covers the channel structure 330, and the conductive layer 75b covers the cap layer 71a above the first virtual channel holes 34 filled with the sacrificial material 60.

[0131] In actual applications, as shown in Figure 12, a conductive layer 75 is deposited on the cap layer 71a and the channel structure 330 through a deposition process, and the deposition rate of the conductive layer 75b deposited on the cap layer 71a is lower than the deposition rate of the conductive layer 75a deposited on the channel structure 330, so that the thickness of the conductive layer 75b deposited on the cap layer 71a along the first direction is lower than the thickness of the conductive layer 75a deposited on the channel structure 330 along the first direction.

[0132] In some embodiments, the conductive layer 75 may include but is not limited to ruthenium (Ru), iridium (Ir), tungsten (W), tantalum (Ta), copper (Cu), aluminum (Al), doped silicon, silicide or any one or more combinations of the above materials.

[0133] Specifically, the channel structure 330 can be formed by depositing in the channel hole 33 through multiple deposition processes. In some embodiments, the channel structure 330 includes a functional layer (poly channel layer) and a channel layer, that is, the functional layer (poly channel layer) and the channel layer can be deposited in the channel hole 33 in sequence through multiple deposition processes to form a channel structure 330 with a storage function. The functional layer in the channel structure 330 is a key structure for the three-dimensional memory to complete the storage function. Specifically, the functional layer includes a silicon oxide-silicon nitride-silicon oxide (ONO) structure sequentially formed on the outer wall of the channel structure 330, that is, the side wall of the channel structure 330 has a silicon oxide-silicon nitride-silicon oxide (ONO) structure sequentially formed from the outside to the inside in the radial direction. Each gate line layer 41 can contact with the corresponding ONO structure functional layer, thereby forming a plurality of storage cells. In each storage cell, the gate line layer 41 can contact with the corresponding ONO structure functional layer, and the gate line layer 41 can control the corresponding ONO structure to achieve the storage function in a way of capturing charges. The functional layers of the ONO structure include a blocking layer, a charge trapping layer, and a tuning layer. Furthermore, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to sequentially deposit the blocking layer, the charge trapping layer, the tunneling layer and the channel layer on the inner wall of the channel hole 33.

[0134] Among them, the blocking layer can be formed on the surface of the inner wall of the channel hole 33 to block the outflow of charges (electrons or holes) stored in the charge capture layer and provide electrical insulation between the charge capture layer and the stacked structure 204. Optionally, the material of the blocking layer may include but is not limited to silicon oxide (SiO2) and high-k dielectrics. In some embodiments, the material of the blocking layer can be a high-k dielectric. High-k dielectric materials have a thinner equivalent oxide thickness (EOT, Equivalence Oxide Thickness), which can effectively reduce gate leakage while maintaining transistor performance. The high-k dielectric can be, for example, aluminum oxide, hafnium oxide, or zirconium oxide. The blocking layer can be a single-layer dielectric oxide, or a multi-layer model, such as high-k oxide and silicon oxide.

[0135] The charge trapping layer may be formed on the inner surface of the blocking layer. Optionally, the material of the charge trapping layer may include but is not limited to silicon nitride (SiN). In another embodiment, the charge trapping layer may be a multilayer structure, such as a multilayer structure of SiN / SiON / SiN.

[0136] The tunneling layer may be formed on the surface of the charge trapping layer. Optionally, the material of the tunneling layer may include but is not limited to silicon oxide (SiO2). In some embodiments, the tunneling layer may also be a multilayer structure, such as a SiO / SiON / SiO2 multilayer structure.

[0137] The above-mentioned blocking layer, charge trapping layer and tunneling layer may be referred to as a functional layer. It should be understood that the functional layer may be a storage structure of a three-dimensional memory after preparation, and the portion of the functional layer corresponding to each gate line layer 41 may form an independent storage unit. Each storage unit may be controlled by the gate line layer 41. Charges are stored or released in the functional layer corresponding to the gate line layer 41 to realize the function of a single storage unit.

[0138] The channel layer may be formed on the surface of the tunnel layer. Optionally, the material of the channel layer includes but is not limited to doped polysilicon.

[0139] It should be understood that some embodiments of the present application may form a plurality of channel structures 330 that penetrate the stacked layer 201 and extend to the substrate 50. The number and arrangement of the channel structures 330 may be prepared according to actual storage requirements. The number and arrangement of the channel structures 330 shown in the figure are merely examples and do not represent the number and arrangement of the channel structures 330 of the final semiconductor structure.

[0140] Step S400 , forming a gate line slit trench 101 extending in a second direction (eg, X-axis direction) and surrounding the plurality of first dummy channel holes 34 , wherein the second direction intersects the first direction.

[0141] In some embodiments of the present application, before the step S400 of forming the gate line slit trench 101 extending in the second direction (eg, the X-axis direction) and surrounding the plurality of first dummy channel holes 34, the method further includes:

[0142] Step S350 , removing the sacrificial material 60 in the first dummy channel hole 34 .

[0143] In some embodiments of the present application, after the step S300 of forming a plurality of channel structures 330 in the plurality of channel holes 33 and before the step S350 of removing the sacrificial layer 40 in the first dummy channel hole 34, the method further includes:

[0144] Step S310 , forming a protection layer 80 on the top of the stacked layer 201 .

[0145] In some embodiments of the present application, FIG. 13 shows a structure formed by step S310. The structure shown in FIG. 13 includes a substrate 50, a stacked layer 201 arranged in a first direction (Z-axis direction), a plurality of first regions 202 arranged in the stacked layer 201, and a second region 203 located between two first regions 202, the first region 202 includes a plurality of channel structures 330 penetrating the stacked layer 201, for example, referring to the embodiment corresponding to step S300 above to form a channel structure 330 of an ONO structure, the second region 203 includes a plurality of first virtual channel holes 34 penetrating the stacked layer 201, the first virtual channel holes 34 are filled with sacrificial materials 60, a cap layer 71a is provided above the first virtual channel holes 34, and a conductive layer 75 is covered on the top of the stacked layer 201. In addition, a protective layer 80 is provided above the conductive layer 75.

[0146] In practical applications, a protective layer 80 is deposited on the conductive layer 75 by a deposition process, and the protective layer 80 may include any one of carbon, polysilicon, silicon nitride, silicon oxide, and aluminum oxide, or any combination thereof. In the embodiment of the present application, the protective layer 80 includes polysilicon.

[0147] In some embodiments of the present application, FIG14 shows a structure formed in step S350. The structure shown in FIG14 includes a substrate 50, a stacked layer 201 arranged in a first direction (Z-axis direction), a plurality of first regions 202 arranged in the stacked layer 201, and a second region 203 located between two first regions 202, the first region 202 includes a plurality of channel structures 330 penetrating the stacked layer 201, the second region 203 includes a plurality of first virtual channel holes 34 penetrating the stacked layer 201, a cap layer 71a is provided above the top dielectric layer 30 on both sides of the first virtual channel holes 34, a conductive layer 75 is provided above the channel structure 330, and a protective layer 80 is provided above the conductive layer 75. In practical applications, the sacrificial material 60 filled in the first virtual channel holes 34 of the second region 203 is removed by an etching process.

[0148] In some embodiments of the present application, the step S400 of forming the gate line slit trench 101 extending in the second direction (eg, the X-axis direction) and surrounding the plurality of first dummy channel holes 34 specifically includes:

[0149] Step S410 , etching the plurality of first dummy channel holes 34 to form a plurality of second dummy channel holes 35 , and connecting the plurality of second dummy channel holes 35 in the second direction to form the gate line gap trench 101 .

[0150] In some embodiments of the present application, FIG. 14 shows that the step S410 forms a structure including a plurality of second virtual channel holes 35. The structure shown in FIG. 14 includes a substrate 50, a stacked layer 201 arranged in a first direction (Z-axis direction), a plurality of first regions 202 arranged in the stacked layer 201, and a second region 203 located between two first regions 202, wherein the first region 202 includes a plurality of channel structures 330 penetrating the stacked layer 201, a conductive layer 75 is arranged above the channel structure 330, and a protective layer 80 is arranged above the conductive layer 75. The second region 203 includes a plurality of second virtual channel holes 35 penetrating the stacked layer 201.

[0151] In some embodiments of the present application, FIG. 15, FIG. 23 to FIG. 26 show that the step S410 forms a structure including a gate line slit groove 101. The structure shown in FIG. 15, FIG. 23 to FIG. 26 includes a substrate 50, a stacked layer 201 arranged in a first direction (Z-axis direction), a plurality of first regions 202 arranged in the stacked layer 201, and a second region 203 located between two first regions 202, the first region 202 includes a plurality of channel structures 330 penetrating the stacked layer 201, a conductive layer 75 is arranged above the channel structure 330, and a protective layer 80 is arranged above the conductive layer 75. The second region 203 includes a plurality of gate line slit grooves 101 penetrating the stacked layer 201, the gate line slit grooves 101 extend along the second direction and surround a plurality of second virtual channel holes 35 as shown in FIG. 23 and FIG. 24.

[0152] The present application can isotropically etch the multiple first virtual channel holes 34 shown in FIG. 13 by an etching process to expand the aperture of the multiple first virtual channel holes 34, thereby forming multiple second virtual channel holes 35 as shown in FIG. 23 and FIG. 24. The process of forming the second virtual channel hole 35 in the present application can be to sequentially penetrate the protective layer 80 and the conductive layer 75 deposited on the top of the stacked layer 201 in the second region 203 by a dry etching process, and then form multiple second virtual channel holes 35 by a wet etching process, the second virtual channel hole 35 penetrates the stacked layer 201 located in the second region 203 along the first direction (for example, the Z-axis direction), and the aperture of the second virtual channel hole 35 is greater than or equal to the aperture of the first virtual channel hole 34, so that the multiple second virtual channel holes 35 extend along the second direction, and two adjacent second virtual channel holes 35 partially overlap or partially overlap along the second direction to form a gate line gap groove 101 that is connected along the second direction and surrounds the multiple first virtual channel holes 34.

[0153] Exemplarily, as shown in Figures 7 and 14, the aperture of the second virtual channel hole 35 is represented as M, the aperture of the first virtual channel hole 34 is represented as D, and the aperture of the channel hole 33 is represented as L. The aperture M of the second virtual channel hole 35 is greater than or equal to the aperture D of the first virtual channel hole 34, that is, M≥D.

[0154] For example, in some embodiments of the present application, before forming the second virtual channel hole 35 penetrating the stacked layer 201 in the second region 203, a patterned second mask layer (not shown in the figure) is formed on the top surface of the stacked layer 201. A third groove (not shown in the figure) corresponding to the second virtual channel hole 35 is formed in the patterned second mask layer, and the vertical projection of the third groove on the top of the stacked layer 201 can at least substantially overlap with the position of the second virtual channel hole 35. By setting the second mask layer, the etching position of the second virtual channel hole 35 can be quickly and accurately determined.

[0155] After the etching position of the second virtual channel hole 35 is exposed, an appropriate etching process is performed, for example, dry etching or wet etching, to remove the portion of the dielectric layer 30 and the sacrificial layer 40 of the stacked layer 201 in the second region 203 exposed by the third groove to form the second virtual channel hole 35 as shown in Figures 14, 23 and 24, until the first virtual channel hole 34 formed by etching exposes the substrate 50, so that the plurality of second virtual channel holes 35 extend along the second direction, and two adjacent second virtual channel holes 35 partially overlap or partially overlap along the second direction, so as to form a gate line gap groove 101 that is connected along the second direction and surrounds the plurality of first virtual channel holes 34. Among them, the second virtual channel hole 35 extends from the surface of the stacked layer 201 away from the substrate 50 to the stacking surface of the substrate 50 to expose the substrate 50, and a portion of the second virtual channel hole 35 is located in the substrate 50, but does not penetrate the substrate 50. After the second virtual channel hole 35 is formed, the second mask layer can be removed.

[0156] In some embodiments, the shape of the second virtual channel hole 35 includes any one of an ellipse and a circle. In some alternative embodiments, the above-mentioned ellipse can also be replaced by other shapes (for example, oblate, rectangular, diamond, etc.) that can be obtained by compressing a centrally symmetrical shape (for example, a circle or a square) in a certain direction, or stretching it by a certain proportion.

[0157] Step S500 , forming a gate line isolation structure 102 in the gate line gap trench 101 , wherein the gate line isolation structure 102 has a concave-convex shape along a third direction; the third direction intersects the first direction and the second direction.

[0158] In some embodiments of the present application, FIG. 16 and FIG. 23 to FIG. 26 show the structure formed in step S500. The formed structure includes a substrate 50, a stacked layer 201 arranged in a first direction (Z-axis direction), a plurality of first regions 202 arranged in the stacked layer 201, and a second region 203 located between two first regions 202, the first region 202 includes a plurality of channel structures 330 penetrating the stacked layer 201, a conductive layer 75 is arranged above the channel structure 330, and a protective layer 80 is arranged above the conductive layer 75. The second region 203 includes a plurality of gate line gap grooves 101 penetrating the stacked layer 201.

[0159] The present application can fill the plurality of gate line gap trenches 101 shown in FIG. 15 with a conductive material by a deposition process, thereby forming a plurality of gate line isolation structures 102 in the second region 203 as shown in FIG. 16 and FIG. 23 to FIG. 26. The gate line isolation structure 102 penetrates the stacked structure 204 along the first direction, extends along the second direction, and has a concave-convex shape along the second direction.

[0160] In some embodiments, the conductive material may include ruthenium (Ru), iridium (Ir), tungsten (W), tantalum (Ta), copper (Cu), aluminum (Al), doped silicon, silicide, or any one or more combinations thereof.

[0161] It should be understood that the present application may form a plurality of gate line isolation structures 102 that penetrate the stacked structure 204 and extend to the substrate 50 but do not pass through the substrate 50, wherein the plurality of gate line isolation structures 102 and the plurality of channel structures 330 are staggered in a third direction (e.g., the Y-axis direction) to separate the plurality of channel structures 330 by the gate line isolation structures 102. The number and arrangement of the gate line isolation structures 102 in the embodiment of the present application may be prepared according to actual storage requirements.

[0162] In some embodiments of the present application, before forming the gate line isolation structure 102 in the gate line gap trench 101 in S500 , the step further includes: replacing the sacrificial layer 40 in the stacked layer 201 with a gate line layer 41 .

[0163] In some embodiments of the present application, the stacked structure 204 located in the first region 202 and the stacked structure 204 located in the second region 203 both include alternately stacked dielectric layers 30 and gate line layers 41. It can be understood that when the stacked structure 204 located in the first region 202 and the stacked structure 204 located in the second region 203 are initially formed, they both include alternately stacked dielectric layers 30 and sacrificial layers 40 stacked in layers 201, and in subsequent processes, the sacrificial layers 40 are replaced with gate line layers 41 to obtain the stacked structure 204.

[0164] In some embodiments of the present application, the material of the gate line layer 41 may include ruthenium (Ru), iridium (Ir), tungsten (W), tantalum (Ta), copper (Cu), aluminum (Al), doped silicon, silicide or any one or more combinations of the above materials. The gate line layer 41 of the present application may be metal tungsten.

[0165] In some embodiments of the present application, the stacked layer 201 includes a core region 301 and a step region 302;

[0166] A plurality of first dummy channel holes 34 having the same aperture along the third direction are formed in the core region 301 and the step region 302 .

[0167] In some embodiments of the present application, the semiconductor device 100 may have a core region, a stair step region 302 (Stair Step) and a peripheral region (periphery) (not shown in the figure). The core region 301 is a region for forming a memory cell, the stair step region 302 is a region for forming a word line connection circuit, and the peripheral region is a region for forming a peripheral circuit. Adjacent first regions 202 are separated by a gate line isolation structure 102, and the gate line isolation structure 102 can extend through the core region 301 and the stair step region 302.

[0168] As shown in FIG. 17 , in the present embodiment, the core region 301 and the step region 302 of the stacking layer 201 are both provided with a plurality of first virtual channel holes 34 arranged in an interlaced manner along the second direction, and the plurality of first virtual channel holes 34 penetrate the stacking layer 201 along the first direction. A plurality of the first virtual channel holes 34 having equal apertures along the third direction are formed in the core region 301, and a plurality of the first virtual channel holes 34 having equal apertures along the third direction are formed in the step region 302, and the size of each first virtual channel hole 34 in the core region 301 along the third direction is the same as the size of each first virtual channel hole 34 in the step region 302 along the third direction. The process of forming a plurality of first virtual channel holes 34 in the stacking layer 201 refers to the embodiment corresponding to the above step S230, and will not be described one by one here.

[0169] In some embodiments of the present application, the stacked layer 201 includes a core region 301 and a step region 302;

[0170] The aperture of the plurality of first dummy channel holes 34 formed in the core region 301 along the third direction is smaller than the aperture of the plurality of first dummy channel holes 34 formed in the step region 302 along the third direction.

[0171] In some embodiments of the present application, as shown in FIG. 18 and FIG. 19 , the core region 301 and the step region 302 of the stacked layer 201 in this embodiment are both provided with a plurality of first virtual channel holes 34 arranged in an interlaced manner along the second direction, and the plurality of first virtual channel holes 34 penetrate the stacked layer 201 along the first direction. A plurality of the first virtual channel holes 34 with equal apertures along the third direction are formed in the core region 301, and a plurality of the first virtual channel holes 34 with equal apertures along the third direction are formed in the step region 302, and the size of each first virtual channel hole 34 in the core region 301 along the third direction is smaller than the size of each first virtual channel hole 34 in the step region 302 along the third direction. The process of forming a plurality of first virtual channel holes 34 in the stacked layer 201 refers to the embodiment corresponding to the above step S230, and will not be repeated here.

[0172] As shown in FIG. 18 , the size of each first dummy channel hole 34 in the core region 301 along the third direction is smaller than the size of each first dummy channel hole 34 in the step region 302 along the third direction.

[0173] As shown in reference figure 19, the size of each first virtual channel hole 34 in the core area 301 along the third direction is smaller than the total size of multiple first virtual channel holes 34 connected side by side in the third direction in the step area 302 along the third direction, that is, the size and value of multiple first virtual channel holes 34 along the third direction.

[0174] In some embodiments, the first virtual channel hole 34 in the core region 301 and the first virtual channel hole 34 in the step region 302 can be formed in the same process, so as to achieve the purpose of forming the first virtual channel hole 34 in the core region 301 and the step region 302 at the same time without additionally increasing the cost. In some embodiments, the first virtual channel hole 34 can penetrate the stacked layer 201 and extend into the substrate 50 without passing through the substrate 50.

[0175] The step area 302 may be located on both sides of the core area 301 , or the core area 301 may be located on both sides of the step area 302 , and there is no specific limitation.

[0176] When the stacked layer 201 is etched in the first region 202 to form the channel hole 33, the stacked layer 201 is etched in the second region 203 by the same process to form the first virtual channel hole 34, thereby realizing the one-time etching of the channel hole 33 in the first region 202 and the first virtual channel hole 34 in the second region 203. Subsequently, through a series of processes, the channel hole 33 in the first region 202 is used to form the channel structure 330, and the first virtual channel hole 34 in the second region 203 is used to form the gate line isolation structure 102. The semiconductor device 100 of the present application has a low manufacturing cost and solves the problem of yield loss caused by the inclination of the channel structure 330 and the gate line isolation structure 102.

[0177] The layout design of the first mask of the present application is shown in Figure 17. A channel structure 330 for realizing a storage function can be formed in the channel hole 33 in Figure 17. The first virtual channel hole 34 in Figure 17 is for forming a gate line gap groove 101. The present application etches to form the channel hole 33 located in the first area 202 while etching to form the first virtual channel hole 34 located in the second area 203. From the perspective of the overall process, one etching operation can be reduced, thereby significantly reducing the device manufacturing cost.

[0178] In the embodiment of the present application, a gate line slit groove 101 is formed in the first virtual channel hole 34 formed synchronously with the channel hole 33, so that the inclination degree of the formed channel hole 33 and the formed first virtual channel hole 34 is basically consistent, and the yield loss caused by the mutual inclination of the channel hole 33 and the first virtual channel hole 34 is effectively avoided. Moreover, since the channel hole 33 and the first virtual channel hole 34 are formed synchronously, the function of the first virtual channel hole 34 is equivalent to the function of the gate line slit hole, so that the subsequent process steps of forming the gate line slit hole are omitted, and the process cost is effectively reduced. In addition, since the channel hole 33 and the first virtual channel hole 34 are formed synchronously, the gate line isolation structure 102 is formed through the first virtual channel hole 34 of the second area 203, which solves the influence of the mutual inclination of the channel structure 330 of the first area 202 and the gate line isolation structure 102 of the second area 203.

[0179] Exemplarily, as shown in FIG. 4 to FIG. 16, a stacked layer 201 is first deposited, and the stacked layer 201 includes a dielectric layer 30 and a sacrificial layer 40, the dielectric layer 30 may be SIN, and the sacrificial layer 40 may be SiO, and then a first mask layer 10 (e.g., a hard mask layer or a photoresist layer) is formed on the top of the stacked layer 201. The first mask layer 10 is subjected to photolithographic patterning, and holes are opened in the first region 202 and the second region 203 at the same time, forming a first groove 31 and a second groove 32, respectively. A plurality of channel holes 33 are formed in the first region 202 through a plurality of first grooves 31, and a plurality of first virtual channel holes 34 are formed in the second region 203 through a plurality of second grooves 32. Sacrificial material 60 is filled in the channel hole 33 and the first virtual channel hole 34, respectively, and then a cap oxide (Cap Oxide) is filled. Afterwards, the cap oxide (Cap Oxide) formed on the top of the channel hole 33 of the first region 202 and the sacrificial material 60 filled in the channel hole 33 are removed in sequence. Afterwards, a channel structure 330 is formed in the channel hole 33, and a protective layer 80 is formed on the stacked layer 201, and the material of the protective layer 80 may include polysilicon. Then, the protective layer 80 formed on the top of the stacked layer 201 in the second region 203 is removed, and then the sacrificial material 60 previously filled in the first virtual channel hole 34 is removed, and the stacked layer 201 in the second region 203 is removed through the first virtual channel hole 34 by a wet etching process, so as to form a gate line gap groove 101 with a concave-convex shape along the second direction. Then, the sacrificial layer 40 of the stacked layer 201 is replaced with the gate line layer 41 to obtain a stacked structure 204. Finally, a gate line isolation structure 102 is formed in the gate line gap groove 101.

[0180] The layout design of the first mask layer 10 of the present application is shown in Figures 17 to 19. In some embodiments, the shape and size of the first virtual channel hole 34 located in the second area 203 can be set at will, as long as the first virtual channel hole 34 located in the second area 203 and the channel hole 33 located in the first area 202 are formed in the same process. In this way, a gate line isolation structure 102 with a concave-convex shape along the second direction can be formed through the first virtual channel hole 34.

[0181] The first virtual channel hole 34 in the embodiment of the present application can have various sizes and shapes, so that the gate line gap groove 101 shown in Figures 23 to 26 is formed by the first virtual channel holes 34 of respective sizes and shapes. Exemplarily, as shown in Figure 20, it is a top view schematic diagram of the opening size of the first virtual channel hole 34 and the channel hole 33 at the top of the stacked layer 201 along the X-axis direction and the Y-axis direction after development measurement (After Development Inspection, ADI), that is, ADI TOP View. In Figure 20, the shape of the upper and lower rows of channel holes 33 along the Y-axis direction is circular, and the first virtual channel hole 34 located between the upper and lower rows of channel holes 33 is elliptical, and the major axis of the ellipse is along the Y-axis direction, and the minor axis of the ellipse is along the X-axis direction. After etching the stacked layer 201 according to the layout design shown in Figure 20, the first virtual channel hole 34 and the channel hole 33 as shown in Figures 21 and 22 are obtained, Figure 21 is a top view schematic diagram of the opening dimensions of the first virtual channel hole 34 and the channel hole 33 measured after etching (After Development Inspection, AEI) at the top of the stacked layer 201 along the X-axis direction and the Y-axis direction, that is, AEI TOP CD, and Figure 22 is a top view schematic diagram of the opening dimensions of the first virtual channel hole 34 and the channel hole 33 measured after etching (After Development Inspection, AEI) at the bottom of the stacked layer 201 along the X-axis direction and the Y-axis direction, that is, AEI Bottom CD. As shown in Figures 21 and 22, the first virtual channel hole 34 and the channel hole 33 are formed based on the etching shown in Figure 20, and the opening size of the first virtual channel hole 34 and the channel hole 33 at the top of the stack layer 201 (that is, the side of the stack layer 201 away from the substrate 50) along the first direction and the second direction is larger than the opening size of the first virtual channel hole 34 and the channel hole 33 at the bottom of the stack layer 201 (that is, the side of the stack layer 201 away from the substrate 50) along the first direction and the second direction.

[0182] In the present application, the T / B (Top / Bottom remove distance ratio, i.e., the top / bottom removal size ratio) of the wet etching process for etching is greater than 0.9, and the B / T (Bottom / Top, i.e., the ratio of the size of the bottom of the gate line gap groove 101 along the third direction divided by the size of the top of the gate line gap groove 101 along the third direction) of the equivalent gate line gap groove 101 formed is approximately 0.83. The spacing distance between the gate line gap groove 101 and the adjacent channel structure 330 along the second direction is controlled by the wet etching time, and sufficient Window needs to be left.

[0183] Table 1. Top removal size and bottom removal size of the gate line gap groove 101 formed by wet etching

[0184] Among them, F satisfies the difference between J minus half of G and P, and G satisfies the sum of twice of E and Q. That is, the above parameters satisfy the following formula: F = (JGP) / 2

[0185] For example, F1 = (J-G1-P1) / 2, F2 = (J-G2-P2) / 2.

[0186] G satisfies the sum of twice E and Q. In other words, the above parameters satisfy the following formula: G = Q + 2E

[0187] For example, G1=Q1+2E1, G2=Q2+2E2.

[0188] G satisfies the sum of twice R and I. That is, the above parameters satisfy the following formula: G = I + 2R

[0189] Generally, G is greater than I, for example, G1=I1+2R1, G2=I2+2R2, and R1 and R2 are both greater than zero.

[0190] H satisfies the square root value of one half of G minus one half, and the square root value is the square value of G minus the square value of K. In other words, the above parameters satisfy the following formula:

[0191] For example,

[0192] Based on the manufacturing method of the semiconductor device 100 of the embodiment of the present application, the embodiment of the present application further provides a semiconductor device 100. The semiconductor device 100 in some embodiments of the present application includes:

[0193] The stack structure 204 includes a dielectric layer 30 and a gate line layer 41 that are staggered and stacked, and the stack structure 204 includes a first region 202 and a second region 203;

[0194] A channel structure 330 located in the first region 202 and penetrating the stack structure 204 along a first direction;

[0195] A gate line isolation structure 102 is located in the second area 203 and extends along the second direction, the gate line isolation structure 102 passes through the stacking structure 204 along the first direction, and the shape of the gate line isolation structure 102 along the third direction is concave and convex, wherein the second direction intersects with the first direction, and the third direction intersects with the first direction and the second direction.

[0196] In some embodiments of the present application, the material of the gate line layer 41 may include ruthenium (Ru), iridium (Ir), tungsten (W), tantalum (Ta), copper (Cu), aluminum (Al), doped silicon, silicide or any one or more combinations of the above materials.

[0197] It should be understood that the structures and manufacturing processes of the various components of the semiconductor device 100 in the embodiment of the present invention can refer to the above-mentioned embodiment of the manufacturing method of the semiconductor device 100, and will not be repeated here.

[0198] In some embodiments, a protection layer 80 is disposed on top of the stack structure 204 .

[0199] In some embodiments, the protection layer 80 includes polysilicon.

[0200] In some embodiments, the gate line isolation structure 102 includes a sidewall extending along the second direction, and the sidewall includes a plurality of substructures 70 connected end to end, and two adjacent substructures 70 are not coplanar.

[0201] In some embodiments of the present application, it should be noted that the concavo-convex shape described in the embodiments of the present application is the projection of the gate line isolation structure 102 on the bottom of the stacked structure 204 or the surface of the substrate 50, and its sidewall is not straight, but a line segment with a certain angle bend or curve. Optionally, in this embodiment, the sidewall includes a plurality of substructures 70 connected end to end along the extension direction of the gate line isolation structure 102, that is, the second direction, and two adjacent substructures 70 are not coplanar.

[0202] Please continue to refer to FIG. 25 and FIG. 26. The shape of the gate isolation structure 102 provided in the embodiment of the present application is shown in FIG. 25 and FIG. 26. The projection of the side wall of the gate isolation structure 102 on the bottom surface of the stacked structure 204 or the surface of the substrate 50 is a broken line or curve composed of multiple line segments. That is, in the present embodiment, by changing the shape of the gate isolation structure 102, the side wall of the gate isolation structure 102 finally obtained is a concave-convex curved surface, that is, a structure formed by multiple substructures 70 with different directions. The specific shape of the concave-convex shape is not limited in the embodiment of the present application, and the concave-convex shape includes concave parts and convex parts adjacent to each other. Optionally, the concave-convex shape may include a wave shape with different curvatures, a broken line shape with different angles, etc. as shown in FIG. 25 and FIG. 26. It should be noted that FIG. 25 and FIG. 26 are only examples of the shape of the gate isolation structure 102, and do not indicate that the gate isolation structure 102 of multiple shapes shown in FIG. 25-FIG. 26 needs to appear in the same semiconductor device 100 at the same time.

[0203] In this embodiment, the bending directions of the multiple substructures 70 are not limited. Since the position where the gate line groove is set in the prior art is relatively wide, the bending directions of the multiple substructures 70 can be set according to the width of the position. Since the bending direction of each substructure 70 is different, and the internal stress of the material is perpendicular to the side wall of the gate line isolation structure 102, each substructure 70 has its own corresponding material internal stress, and the directions of the material internal stress of the substructures 70 in different directions are different, and finally the directions of the material internal stress of the multiple substructures 70 are not single, thereby reducing the sum of the material internal stress of the side wall of the gate line isolation structure 102 as a whole, and avoiding the side wall of the gate line isolation structure 102 from tilting or twisting under the action of the large material internal stress, resulting in insufficient subsequent metal filling and device failure.

[0204] Different from the design of the gate line isolation structure 102 shown in FIG1 , as shown in FIG25 and FIG26 , during the graphic design, the original long strip-shaped gate line isolation structure 102 is designed to be a gate line isolation structure 102 with a concave-convex shape along the second direction. The sidewall of the gate line isolation structure 102 of the present application is set as a concave-convex curved surface, so that the direction of the material internal stress perpendicular to the sidewall of each part of the sidewall is different, so that the material internal stress perpendicular to the sidewall is not in the same single direction, reducing the degree of concentrated stress release, thereby weakening the compression of the sidewall of the gate line isolation structure 102 by the material internal stress, so that the gate line isolation structure 102 will not be excessively deformed. In this way, when the gate line isolation structure 102 has a stress mismatch, the stress can be effectively released through the gate line isolation structure 102 through the substructures 70 set in different directions, so that the gate line isolation structure 102 is not easy to tilt or twist, reduce leakage, so as to improve the yield of the finished product, thereby improving the stability of the gate line isolation structure 102.

[0205] In some embodiments, the stacked structure 204 includes a core region 301 and a step region 302 ; the size of the gate line isolation structure 102 located in the core region 301 along the third direction is equal to the size of the gate line isolation structure 102 located in the step region 302 along the third direction.

[0206] In some embodiments of the present application, the semiconductor device 100 may have a core region, a stair step region 302 (Stair Step) and a peripheral region (periphery) (not shown in the figure). The core region 301 is a region for forming a memory cell, the stair step region 302 is a region for forming a word line connection circuit, and the peripheral region is a region for forming a peripheral circuit. Adjacent first regions 202 are separated by a gate line isolation structure 102, and the gate line isolation structure 102 can extend through the core region 301 and the stair step region 302.

[0207] As shown in FIGS. 23 to 25 , in the present embodiment, the core region 301 and the step region 302 of the stacked structure 204 are both provided with a gate line isolation structure 102 extending along the second direction, and a plurality of gate line isolation structures 102 penetrate the stacked structure 204 along the first direction to divide the stacked structure 204 into a plurality of parts. The gate line isolation structures 102 in the core region 301 and the step region 302 have the same size along the third direction. The process of forming the gate line isolation structure 102 in the core region 301 and the step region 302 of the stacked structure 204 refers to the embodiment corresponding to the above-mentioned step S500, which will not be described one by one here.

[0208] Exemplarily, as shown in FIG. 25 , the multiple substructures 70 a located in the core area 301 of the stacked structure 204 and the multiple substructures 70 b located in the step area 302 of the stacked structure 204 have the same shape and size along the X-axis and Y-axis directions, and the multiple substructures 70 a in the core area 301 and the multiple substructures 70 b in the step area 302 along the X-axis direction are connected end to end to form a gate line isolation structure 102 with a concave-convex shape along the Y-axis direction.

[0209] In some embodiments, the stacked structure 204 includes a core region 301 and a step region 302 ; a size of the gate line isolation structure 102 located in the core region 301 along the third direction is smaller than a size of the gate line isolation structure 102 located in the step region 302 along the third direction.

[0210] In some embodiments of the present application, as shown in FIG. 26 , in the present embodiment, the core region 301 and the step region 302 of the stacked structure 204 are both provided with a gate line isolation structure 102 extending along the second direction, and a plurality of gate line isolation structures 102 penetrate the stacked structure 204 along the first direction to divide the stacked structure 204 into a plurality of parts. The size of the gate line isolation structure 102 in the core region 301 along the third direction is smaller than the size of the gate line isolation structure 102 in the step region 302 along the third direction. The process of forming the gate line isolation structure 102 in the core region 301 and the step region 302 of the stacked structure 204 is described in the following embodiments, which will not be described one by one here.

[0211] As shown in FIG. 23 , FIG. 24 and FIG. 26 , in this embodiment, the width of the gate line isolation structure 102 in the step region 302 (i.e., the dimension along the third direction) is increased relative to the width of the gate line isolation structure 102 in the core region 301 (i.e., the dimension along the third direction). The present application does not need to add other steps or masks, and only needs to increase the width of the gate line isolation structure 102 on the top surface of the step region 302 to increase the width of the bottom of the gate line isolation structure 102 in the step region 302. The present application increases the width of the gate line isolation structure 102 in the step region 302 to help uniformly etch the conductive material at the bottom of the gate line isolation structure 102, and avoids the conductive material at the bottom of the gate line isolation structure 102 in the step region 302 from agglomerating, thereby avoiding interference between adjacent gate line isolation structures 102 to cause short circuits or leakage currents.

[0212] Exemplarily, as shown in FIG26, the multiple substructures 70a located in the core region 301 of the stacked structure 204 and the multiple substructures 70b located in the step region 302 of the stacked structure 204 have the same shape along the X-axis and Y-axis directions, but the size of each substructure 70a in the core region 301 along the Y-axis direction is smaller than the size of each substructure 70b in the step region 302 along the Y-axis direction. The multiple substructures 70a in the core region 301 and the multiple substructures 70b in the step region 302 are connected end to end along the X-axis direction to form a gate line isolation structure 102 with a concave-convex shape along the Y-axis direction.

[0213] In some embodiments, the conductive material may include ruthenium (Ru), iridium (Ir), tungsten (W), tantalum (Ta), copper (Cu), aluminum (Al), doped silicon, silicide, or any one or more combinations thereof. Preferably, the conductive material may be tungsten (W).

[0214] In some embodiments, increasing the width of the gate line isolation structure 102 will reduce the separation distance between the width of the gate line isolation structure 102 and the adjacent structure (for example, the channel structure 330 of the adjacent first region 202), and the reduction in the separation distance leads to an increase in etching risk and causes poor electrical contact between the width of the gate line isolation structure 102 and the adjacent structure. In addition, increasing the width of the gate line isolation structure 102 will also occupy more device space, resulting in the space occupied by the channel structure 330 being squeezed, thereby affecting the storage density of the device. In the embodiment of the present application, the width design of the gate line isolation structure 102 needs to at least consider and weigh the above two factors to design a suitable width of the gate line isolation structure 102 for a specific device.

[0215] In this embodiment, a gate line slit groove 101 can be formed in the stacked layer 201 located in the core area 301, and a gate line slit groove 101 can also be formed in the stacked layer 201 located in the step area 302, wherein the gate line slit groove 101 extends along the second direction and penetrates the stacked layer 201 along the first direction to divide the stacked layer 201 into a plurality of parts. In this embodiment. After forming the gate line slit groove 101, the gate line slit groove 101 can be filled by a deposition process to form a gate line isolation structure 102. Wherein, in some embodiments, a conductive material can be filled in the gate line slit groove 101. In some embodiments, the gate line isolation structure 102 can penetrate the stacked structure 204 and extend to the substrate 50 without passing through the substrate 50.

[0216] In some embodiments, the gate line isolation structure 102 located in the core area 301 and the gate line isolation structure 102 located in the step area 302 are formed in the same process, so as to achieve the purpose of forming the gate line gap trench 101 without increasing the cost.

[0217] It should be understood that the structures and manufacturing processes of the various components of the semiconductor device 100 in the embodiment of the present invention can refer to the above-mentioned embodiment of the manufacturing method of the semiconductor device 100, and will not be repeated here.

[0218] Based on the above-mentioned semiconductor device 100 and its manufacturing method and storage system, an embodiment of the present invention further provides a three-dimensional memory, which includes an array storage structure and a peripheral circuit, wherein the array storage structure includes any one of the above-mentioned semiconductor devices 100.

[0219] Specifically, the three-dimensional memory (3D NAND Flash) includes an array storage structure (Array) and a peripheral circuit (Periphery Circuit), and the semiconductor device 100 of any of the above items is located in the array storage structure. Among them, the array storage structure is used to store information, and the peripheral circuit can be located above or below the array storage structure, or it can be located around the array storage structure, and the peripheral circuit is used to control the corresponding array storage structure. In addition, the semiconductor device 100 can also be applied to other microelectronic devices, such as non-volatile flash memory (Nor Flash), etc., without specific limitation. In addition, the semiconductor device 100 of the embodiment of the present invention can be a three-dimensional memory, and can be a part of a peripheral memory, without special limitation.

[0220] Based on the above-mentioned semiconductor device 100, its manufacturing method and storage system, an embodiment of the present invention also provides a storage system, including a controller and a three-dimensional memory, the controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data, and the three-dimensional memory includes any one of the above-mentioned semiconductor devices 100.

[0221] 28 , the storage system 300 includes a controller 310 and one or more three-dimensional memories 320, wherein the three-dimensional memories 320 include one or more array storage structures 321 and a peripheral circuit 322. The storage system 300 can communicate with the host 400 through the controller 310, wherein the controller 310 can be connected to the one or more three-dimensional memories 320 via channels in the one or more three-dimensional memories 320. Each three-dimensional memory 320 can be managed by the controller 310 via channels in the three-dimensional memory 320.

[0222] The above is a detailed introduction to a semiconductor device and its manufacturing method and storage system, memory and storage system, memory and storage system provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, according to the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

A method for manufacturing a semiconductor device, wherein: include: providing a stacking layer; The stacked layer includes alternately stacked dielectric layers and sacrificial layers, and the stacked layer includes a first region and a second region; A plurality of channel holes are formed in the first region and penetrate the stacked layer along a first direction, and a plurality of first virtual channel holes are formed in the second region and penetrate the stacked layer along the first direction; a plurality of channel structures are formed in the plurality of channel holes; a gate line gap groove is formed and extends in a second direction and surrounds the plurality of first virtual channel holes, and the second direction intersects the first direction; forming a gate line isolation structure in the gate line gap groove, wherein the gate line isolation structure has a concave-convex shape along the third direction; The third direction intersects the first direction and the second direction. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming a gate line slit groove extending in the second direction and surrounding the plurality of first virtual channel holes comprises: etching the plurality of first virtual channel holes to form a plurality of second virtual channel holes, and connecting the plurality of second virtual channel holes in the second direction to form the gate line slit groove. The method for manufacturing a semiconductor device according to claim 1, wherein: Before the step of forming a plurality of channel structures in the plurality of channel holes, the method further includes: filling the channel holes and the first dummy channel holes with a sacrificial material, and removing the sacrificial material in the channel holes. The method for manufacturing a semiconductor device according to claim 3, wherein: After filling the sacrificial material in the channel hole and the first virtual channel hole, and before the step of removing the sacrificial material in the channel hole, the method further includes: forming a cap layer on the top of the stacked layer, and removing the cap layer above the channel hole. The method for manufacturing a semiconductor device according to claim 4, wherein: Before the step of forming a gate line slit trench extending in the second direction and surrounding the plurality of first dummy channel holes, the method further includes: removing the sacrificial material in the first dummy channel holes. The method for manufacturing a semiconductor device according to claim 5, wherein: After the step of forming a plurality of channel structures in the plurality of channel holes and before the step of removing the sacrificial material in the first dummy channel hole, the method further includes: forming a protection layer on top of the stacked layer. The method for manufacturing a semiconductor device according to claim 6, wherein: The protection layer includes polysilicon. The method for manufacturing a semiconductor device according to claim 1, wherein: Before forming the gate line isolation structure in the gate line gap groove, the method further includes: replacing the sacrificial layer in the stacked layer with a gate line layer. The method for manufacturing a semiconductor device according to claim 1, wherein: The shape of the first virtual channel hole includes any one of an ellipse and a circle, and the shape of the channel hole includes a circle. The method for manufacturing a semiconductor device according to claim 1, wherein: The stacked layer includes a core region and a step region; a plurality of first virtual channel holes having equal apertures along the third direction are formed in the core region and the step region. The method for manufacturing a semiconductor device according to claim 1, wherein: The stacked layer includes a core region and a step region; the aperture of the plurality of first virtual channel holes formed in the core region along the third direction is smaller than the aperture of the plurality of first virtual channel holes formed in the step region along the third direction. The method for manufacturing a semiconductor device according to claim 1, wherein: The steps of forming a plurality of channel holes penetrating the stacked layer in the first region along the first direction, and forming a plurality of first virtual channel holes penetrating the stacked layer in the second region along the first direction, include: forming a composite photolithography layer on the dielectric layer at the top of the stacked layer; and forming a plurality of first grooves and a plurality of second grooves in the composite photolithography layer; the first grooves are located in the first region, and the second grooves are located in the second region; etching the stacked layer in the first region through the first grooves to form the plurality of channel holes; and etching the stacked layer in the second region through the second grooves to form the plurality of first virtual channel holes. The method for manufacturing a semiconductor device according to claim 12, wherein: The plurality of channel holes and the plurality of first dummy channel holes are formed in a same process. The method for manufacturing a semiconductor device according to claim 12, wherein: The step of forming a composite photolithography layer on the dielectric layer at the top of the stacked layers includes: forming a stop layer on the dielectric layer at the top, and forming a first mask layer on the stop layer; etching the first mask layer through the stop layer until the dielectric layer at the top of the stacked layers is exposed to form the composite photolithography layer. A semiconductor device, wherein: The semiconductor device includes: a stacking structure; the stacking structure includes staggered dielectric layers and gate line layers, the stacking structure includes a first region and a second region; a channel structure located in the first region and penetrating the stacking structure along a first direction; a gate line isolation structure located in the second region and extending along a second direction, the gate line isolation structure penetrating the stacking structure along the first direction, and the shape of the gate line isolation structure along a third direction is concave-convex, wherein the second direction intersects with the first direction, and the third direction intersects with the first direction and the second direction. The semiconductor device according to claim 15, wherein Also includes: A protective layer is disposed on the top of the stacked structure. The semiconductor device according to claim 15, wherein The gate line isolation structure includes a side wall extending along the second direction, the side wall includes a plurality of sub-structures connected end to end, and two adjacent sub-structures are not coplanar. The semiconductor device according to claim 15, wherein The stacked structure comprises a core region and a step region; a size of the gate line isolation structure located in the core region along the third direction is equal to a size of the gate line isolation structure located in the step region along the third direction. The semiconductor device according to claim 15, wherein The stacked structure comprises a core region and a step region; a size of the gate line isolation structure located in the core region along the third direction is smaller than a size of the gate line isolation structure located in the step region along the third direction. A storage system, wherein include: A controller and a three-dimensional memory, wherein the controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data, and the three-dimensional memory includes the semiconductor device according to any one of claims 15 to 19.

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