Display substrate, preparation method thereof and display device

Abstract

The invention discloses a display substrate, a preparation method thereof and a display device. The display substrate comprises a plurality of circuit units, at least one circuit unit comprises a pixel driving circuit, the pixel driving circuit at least comprises a first storage capacitor (C1) and a second storage capacitor (C2), the first storage capacitor (C1) comprises at least two first capacitor polar plates (71, 73), orthographic projections of the two first capacitor polar plates (71, 73) on a substrate (101) are at least partially overlapped, and the second storage capacitor polar plates (C2) are at least partially overlapped with the first capacitor polar plates (71, 73). The second storage capacitor (C2) comprises at least two second capacitor plates (72, 74), and orthographic projections of the two second capacitor plates (72, 74) on the substrate (101) are at least partially overlapped; in a plane perpendicular to the display substrate, the display substrate comprises a plurality of conductive layers, one of the at least two first capacitor plates (71, 73) and one of the at least two second capacitor plates (72, 74) are arranged in the same conductive layer, and the other first capacitor plate and the other second capacitor plate are arranged in the same conductive layer. And one first capacitor plate in the first storage capacitor is connected with one second capacitor plate in the second storage capacitor.

Description

Display substrate and manufacturing method thereof, and display device

[0001] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device.

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field.

[0003]

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, including multiple circuit units, at least one circuit unit including a pixel driving circuit, the pixel driving circuit including at least a first storage capacitor and a second storage capacitor, the first storage capacitor including at least two first capacitor plates, the orthographic projections of the two first capacitor plates on the substrate at least partially overlap, the second storage capacitor including at least two second capacitor plates, the orthographic projections of the two second capacitor plates on the substrate at least partially overlap; on a plane perpendicular to the display substrate, the display substrate includes multiple conductive layers, a first capacitor plate in the first storage capacitor and a second capacitor plate in the second storage capacitor are arranged in the same conductive layer, another first capacitor plate in the first storage capacitor and another second capacitor plate in the second storage capacitor are arranged in the same conductive layer, and a first capacitor plate in the first storage capacitor and a second capacitor plate in the second storage capacitor are connected to each other.

[0006] In an exemplary embodiment, the multiple conductive layers include at least a first conductive layer and a second conductive layer sequentially arranged on a substrate; the at least two first capacitor plates include a first plate and a third plate, the first plate is arranged in the first conductive layer, the third plate is arranged in the second conductive layer, and the orthographic projection of the first plate on the substrate at least partially overlaps with the orthographic projection of the third plate on the substrate; the at least two second capacitor plates include a second plate and a fourth plate, the second plate is arranged in the first conductive layer, the fourth plate is arranged in the second conductive layer, the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate, and the third plate is connected to the fourth plate.

[0007] In an exemplary embodiment, the third plate of the first storage capacitor and the fourth plate of the second storage capacitor are an integral structure connected to each other.

[0008] In an exemplary embodiment, the pixel driving circuit also includes a first initialization transistor, a compensation transistor, a data writing transistor and a first reference transistor of a dual-gate structure, the first electrode of the first initialization transistor is connected to the first initial signal line, the second electrode of the first initialization transistor is respectively connected to the first electrode and the first electrode plate of the data writing transistor, the first electrode of the data writing transistor is connected to the data signal line, the second electrode of the data writing transistor is respectively connected to the second electrode, the third electrode plate and the fourth electrode plate of the first reference transistor, and the first electrode of the first reference transistor is connected to the first reference signal line.

[0009] In an exemplary embodiment, at least one circuit unit further includes a first shielding electrode, wherein an orthographic projection of the first shielding electrode on the substrate at least partially overlaps with an orthographic projection of a node between two gate electrodes of the first initialization transistor on the substrate, and an orthographic projection of the first shielding electrode on the substrate at least partially overlaps with an orthographic projection of a node between two gate electrodes of the compensation transistor on the substrate.

[0010] In an exemplary embodiment, the display substrate further includes at least one first power connection line extending along a first direction and at least one first power connection line extending along a second direction, the first direction intersecting the second direction; the first power line and the first power connection line are arranged in different conductive layers, the first power line and the first power connection line are connected to each other through a via to form a mesh structure for transmitting a first power signal, and the first shielding electrode is connected to the first power connection line.

[0011] In an exemplary embodiment, the first shielding electrode includes a first extension segment and a first shielding segment; the first extension segment is shaped like a strip extending along the second direction, and the first shielding segment is shaped like a strip extending along the first direction; the first end of the first extension segment is connected to the first power connection line, and the second end of the first extension segment is connected to the first shielding segment; the first shielding segment includes a first shielding end and a second shielding end, the orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of a node between two gate electrodes of the first initialization transistor in the present circuit unit on the substrate, and the orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of a node between two gate electrodes of the compensation transistor in the adjacent circuit unit on the substrate.

[0012] In an exemplary embodiment, the first shielding electrode and the first power connection line are an integral structure connected to each other.

[0013] In an exemplary embodiment, an orthographic projection of the first power connection line on the substrate at least partially overlaps an orthographic projection of the fourth electrode plate on the substrate.

[0014] In an exemplary embodiment, the display substrate further includes at least one second power connection line extending along a first direction and at least one second power connection line extending along a second direction, the first direction intersecting the second direction; the second power line and the second power connection line are arranged in different conductive layers, the second power line and the second power connection line are connected to each other through a via to form a mesh structure for transmitting a second power signal, and the first shielding electrode is connected to the second power connection line.

[0015] In an exemplary embodiment, the first shielding electrode includes a first extension segment and a first shielding segment; the first extension segment is shaped like a strip extending along the second direction, and the first shielding segment is shaped like a strip extending along the first direction; the first end of the first extension segment is connected to the second power connection line, and the second end of the first extension segment is connected to the first shielding segment; the first shielding segment includes a first shielding end and a second shielding end, the orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of a node between two gate electrodes of the first initialization transistor in the present circuit unit on the substrate, and the orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of a node between two gate electrodes of the compensation transistor in the adjacent circuit unit on the substrate.

[0016] In an exemplary embodiment, the first shielding electrode and the second power connection line are an integral structure connected to each other.

[0017] In an exemplary embodiment, an orthographic projection of the second power connection line on the substrate at least partially overlaps an orthographic projection of the third electrode plate on the substrate.

[0018] In an exemplary embodiment, at least one circuit unit further includes a second shielding electrode, an orthographic projection of the second shielding electrode on the substrate at least partially overlapping an orthographic projection of a node between two gate electrodes of the data writing transistor on the substrate.

[0019] In an exemplary embodiment, at least one circuit unit further includes a third shielding electrode, an orthographic projection of the third shielding electrode on the substrate at least partially overlaps an orthographic projection of a node between two gate electrodes of the first reference transistor on the substrate.

[0020] In an exemplary embodiment, the display substrate also includes at least one reference signal connection line extending along a first direction and at least one reference signal line extending along a second direction, and the first direction intersects with the second direction; the reference signal line and the reference signal connection line are arranged in different conductive layers, and the reference signal connection line is connected to the reference signal line through a via to form a mesh structure for transmitting the reference signal.

[0021] In an exemplary embodiment, the display substrate also includes at least one initial signal line extending along a first direction and at least one initial connection line extending along a second direction, and the first direction intersects with the second direction; the initial signal line and the initial connection line are arranged in different conductive layers, and the initial connection line is connected to the initial signal line through a via to form a mesh structure for transmitting the initial signal.

[0022] On the other hand, the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0023] On the other hand, the present disclosure also provides a method for preparing a display substrate, wherein the display substrate includes multiple circuit units, at least one circuit unit includes a pixel driving circuit, the pixel driving circuit includes at least a first storage capacitor and a second storage capacitor, the first storage capacitor includes at least two first capacitor plates, and the orthographic projections of the two first capacitor plates on the substrate at least partially overlap, and the second storage capacitor includes at least two second capacitor plates, and the orthographic projections of the two second capacitor plates on the substrate at least partially overlap; the preparation method includes: forming multiple conductive layers on the substrate, a first capacitor plate in the first storage capacitor and a second capacitor plate in the second storage capacitor are arranged in the same conductive layer, another first capacitor plate in the first storage capacitor and another second capacitor plate in the second storage capacitor are arranged in the same conductive layer, and a first capacitor plate in the first storage capacitor and a second capacitor plate in the second storage capacitor are connected to each other.

[0024] Other aspects will be apparent upon reading and understanding the drawings and detailed description.

[0025] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0026] FIG1 is a schematic structural diagram of a display device;

[0027] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0028] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0029] FIG4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0030] FIG5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0031] FIG6 is a schematic diagram of the structure of the first storage capacitor and the second storage capacitor region in FIG5;

[0032] FIG7 is a schematic diagram of a display substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0033] 8A and 8B are schematic diagrams of a display substrate after a first conductive layer pattern is formed according to the present disclosure;

[0034] 9A and 9B are schematic diagrams of a display substrate after a second conductive layer pattern is formed according to the present disclosure;

[0035] FIG10 is a schematic diagram of a display substrate after a fourth insulating layer pattern is formed according to the present disclosure;

[0036] 11A and 11B are schematic diagrams of a display substrate after a third conductive layer pattern is formed on the substrate according to the present disclosure;

[0037] FIG12 is a schematic diagram of a display substrate after a fifth insulating layer pattern is formed according to the present disclosure;

[0038] 13A and 13B are schematic diagrams of a display substrate after a fourth conductive layer pattern is formed according to the present disclosure;

[0039] FIG14 is a schematic diagram of another planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0040] FIG15 is a schematic diagram of the structure of the first storage capacitor and the second storage capacitor region in FIG14;

[0041] 16A and 16B are schematic diagrams of another display substrate after a third conductive layer pattern is formed on the substrate according to the present disclosure;

[0042] FIG17 is a schematic diagram of another display substrate after a fifth insulating layer pattern is formed in the present disclosure;

[0043] 18A and 18B are schematic diagrams of another display substrate after forming a fourth conductive layer pattern according to the present disclosure.

[0044] Description of the accompanying drawings: 10—first active connection line; 11—first active layer; 12—second active layer; 13—third active layer; 14—fourth active layer; 15—fifth active layer; 16—sixth active layer; 17—seventh active layer; 18—eighth active layer; 19—ninth active layer; 20—second active connection line; 21—first gate electrode; 22—second gate electrode; 24—fourth gate electrode; 25—fifth gate electrode; 26—sixth gate electrode; 29—ninth gate electrode; 31—first light-emitting signal line; 31-1—first light-emitting connection block; 32—second light-emitting signal line; 32-1—second light-emitting connection block; 33—repair line; 36—first shielding electrode; 36-1—first extension segment; 36-2—first shielding segment; 37—second shielding electrode; 38—third shielding electrode; 41—first connection electrode; 42—second connection electrode; 43—third connection electrode; 44—fourth connection electrode; 45—fifth connection electrode; 46—sixth connection electrode; 47—seventh connection electrode; 48—eighth connection electrode; 49—ninth connection electrode; 51—first power line; 51-1—power shielding block; 52—second power line; 53—data signal line; 54—reference signal connection line; 55—anode connection electrode; 56—second initial connection line; 61—first scan signal line; 62—second scan signal line; 63—third scan signal line; 64—fourth scan signal line; 65—fifth scan signal line; 68—first power connection line; 68-1—first power connection block; 68-2—second power connection block; 69—second power connection line; 69-1—third power connection block; 71—first plate; 72—second plate; 72-1—protrusion; 72-2—plate connecting line; 73—third plate; 74—fourth plate; 74-2—plate connecting block; 75—first opening; 76—second opening; 81—first initial signal line; 81-1—first initial connecting block; 82—second initial signal line; 82-1—second initial connecting block; 91—first reference signal line; 91-1—first reference connecting block; 92—second reference signal line; 92-1—second reference connecting block; 101—substrate; 102—driving circuit layer; 103—light-emitting structure layer; 104—packaging structure layer.

[0045] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0046] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0047] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0048] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0049] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0050] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0051] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged.

[0052] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0053] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0054] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0055] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0056] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0057] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line, the light emitting signal line and the data signal line, the light emitting unit may include a light emitting device, and the light emitting device is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal, and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm. For example, the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number. The light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0058] FIG2 is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a display area and a frame area located around the display area. As shown in FIG2, the display area of ​​the display substrate may include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to a scanning signal line, a data signal line, and a light-emitting signal line, and the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting unit may include at least a light-emitting device, and the light-emitting device is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0059] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 may be a green sub-pixel (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged in a horizontal parallel, vertical parallel or triangular manner, which is not limited in the present disclosure.

[0060] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0061] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels in the display substrate. As shown in FIG4, on a plane perpendicular to the display substrate, the display area of ​​the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited in the present disclosure.

[0062] In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, the circuit units may include at least a pixel driving circuit, and the pixel driving circuit may include a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, the light-emitting units may include at least a light-emitting device, and the light-emitting device may include an anode, an organic light-emitting layer, and a cathode, the anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0063] In exemplary embodiments, the organic light emitting layer may include a light emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0064] An exemplary embodiment of the present disclosure provides a display substrate, comprising a plurality of circuit units, at least one of which comprises a pixel driving circuit, wherein the pixel driving circuit comprises at least a first storage capacitor and a second storage capacitor, wherein the first storage capacitor comprises at least two first capacitor plates, and the orthographic projections of the two first capacitor plates on the substrate at least partially overlap, and the second storage capacitor comprises at least two second capacitor plates, and the orthographic projections of the two second capacitor plates on the substrate at least partially overlap; on a plane perpendicular to the display substrate, the display substrate comprises a plurality of conductive layers, a first capacitor plate in the first storage capacitor and a second capacitor plate in the second storage capacitor are arranged in the same conductive layer, another first capacitor plate in the first storage capacitor and another second capacitor plate in the second storage capacitor are arranged in the same conductive layer, and a first capacitor plate in the first storage capacitor and a second capacitor plate in the second storage capacitor are connected to each other.

[0065] In an exemplary embodiment, the multiple conductive layers include at least a first conductive layer and a second conductive layer sequentially arranged on a substrate; the at least two first capacitor plates include a first plate and a third plate, the first plate is arranged in the first conductive layer, the third plate is arranged in the second conductive layer, and the orthographic projection of the first plate on the substrate at least partially overlaps with the orthographic projection of the third plate on the substrate; the at least two second capacitor plates include a second plate and a fourth plate, the second plate is arranged in the first conductive layer, the fourth plate is arranged in the second conductive layer, the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate, and the third plate is connected to the fourth plate.

[0066] In an exemplary embodiment, the third plate of the first storage capacitor and the fourth plate of the second storage capacitor are an integral structure connected to each other.

[0067] In an exemplary embodiment, the pixel driving circuit also includes a first initialization transistor, a compensation transistor, a data writing transistor and a first reference transistor of a dual-gate structure, the first electrode of the first initialization transistor is connected to the first initial signal line, the second electrode of the first initialization transistor is respectively connected to the first electrode and the first electrode plate of the data writing transistor, the first electrode of the data writing transistor is connected to the data signal line, the second electrode of the data writing transistor is respectively connected to the second electrode, the third electrode plate and the fourth electrode plate of the first reference transistor, and the first electrode of the first reference transistor is connected to the first reference signal line.

[0068] In an exemplary embodiment, at least one circuit unit further includes a first shielding electrode, wherein an orthographic projection of the first shielding electrode on the substrate at least partially overlaps with an orthographic projection of a node between two gate electrodes of the first initialization transistor on the substrate, and an orthographic projection of the first shielding electrode on the substrate at least partially overlaps with an orthographic projection of a node between two gate electrodes of the compensation transistor on the substrate.

[0069] In an exemplary embodiment, the display substrate further includes at least one first power connection line extending along a first direction and at least one first power connection line extending along a second direction, the first direction intersecting the second direction; the first power line and the first power connection line are arranged in different conductive layers, the first power line and the first power connection line are connected to each other through a via to form a mesh structure for transmitting a first power signal, and the first shielding electrode is connected to the first power connection line.

[0070] In an exemplary embodiment, the first shielding electrode includes a first extension segment and a first shielding segment; the first extension segment is shaped like a strip extending along the second direction, and the first shielding segment is shaped like a strip extending along the first direction; the first end of the first extension segment is connected to the first power connection line, and the second end of the first extension segment is connected to the first shielding segment; the first shielding segment includes a first shielding end and a second shielding end, the orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of a node between two gate electrodes of the first initialization transistor in the present circuit unit on the substrate, and the orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of a node between two gate electrodes of the compensation transistor in the adjacent circuit unit on the substrate.

[0071] In an exemplary embodiment, the first shielding electrode and the first power connection line are an integral structure connected to each other.

[0072] In an exemplary embodiment, an orthographic projection of the first power connection line on the substrate at least partially overlaps an orthographic projection of the fourth electrode plate on the substrate.

[0073] In an exemplary embodiment, the display substrate further includes at least one second power connection line extending along a first direction and at least one second power connection line extending along a second direction, the first direction intersecting the second direction; the second power line and the second power connection line are arranged in different conductive layers, the second power line and the second power connection line are connected to each other through a via to form a mesh structure for transmitting a second power signal, and the first shielding electrode is connected to the second power connection line.

[0074] In an exemplary embodiment, the first shielding electrode includes a first extension segment and a first shielding segment; the first extension segment is shaped like a strip extending along the second direction, and the first shielding segment is shaped like a strip extending along the first direction; the first end of the first extension segment is connected to the second power connection line, and the second end of the first extension segment is connected to the first shielding segment; the first shielding segment includes a first shielding end and a second shielding end, the orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of a node between two gate electrodes of the first initialization transistor in the present circuit unit on the substrate, and the orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of a node between two gate electrodes of the compensation transistor in the adjacent circuit unit on the substrate.

[0075] In an exemplary embodiment, the first shielding electrode and the second power connection line are an integral structure connected to each other.

[0076] In an exemplary embodiment, an orthographic projection of the second power connection line on the substrate at least partially overlaps an orthographic projection of the third electrode plate on the substrate.

[0077] In an exemplary embodiment, at least one circuit unit further includes a second shielding electrode, an orthographic projection of the second shielding electrode on the substrate at least partially overlapping an orthographic projection of a node between two gate electrodes of the data writing transistor on the substrate.

[0078] In an exemplary embodiment, at least one circuit unit further includes a third shielding electrode, an orthographic projection of the third shielding electrode on the substrate at least partially overlaps an orthographic projection of a node between two gate electrodes of the first reference transistor on the substrate.

[0079] In an exemplary embodiment, the display substrate also includes at least one reference signal connection line extending along a first direction and at least one reference signal line extending along a second direction, and the first direction intersects with the second direction; the reference signal line and the reference signal connection line are arranged in different conductive layers, and the reference signal connection line is connected to the reference signal line through a via to form a mesh structure for transmitting the reference signal.

[0080] In an exemplary embodiment, the display substrate also includes at least one initial signal line extending along a first direction and at least one initial connection line extending along a second direction, and the first direction intersects with the second direction; the initial signal line and the initial connection line are arranged in different conductive layers, and the initial connection line is connected to the initial signal line through a via to form a mesh structure for transmitting the initial signal.

[0081] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0082] FIG4 is an equivalent circuit diagram of a pixel driving circuit of an exemplary embodiment of the present disclosure. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C or 9T2C structure. As shown in FIG4, the pixel driving circuit of the exemplary embodiment of the present disclosure may be a 9T2C structure, which may include 9 transistors (a first transistor T1 to a ninth transistor T9) and 2 storage capacitors (a first storage capacitor C1 and a second storage capacitor C2), and the pixel driving circuit is respectively connected to 12 signal lines (a first scanning signal line S1, a second scanning signal line S2, a third scanning signal line S3, a fourth scanning signal line S4, a first light emitting signal line EM1, a second light emitting signal line EM2, a first initial signal line INIT1, a second initial signal line INIT2, a first reference signal line REF1, a second reference signal line REF2, a data signal line DATA and a first power line VDD).

[0083] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 is respectively connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the first storage capacitor C1, the second node N2 is respectively connected to the first electrode of the third transistor T3, the second electrode of the eighth transistor T8, and the second electrode of the fifth transistor T5, the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, the fourth node N4 is respectively connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the fifth node N5 is respectively connected to the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the second end of the first storage capacitor C1, and the second end of the second storage capacitor C2.

[0084] In an exemplary embodiment, a first end (lower plate) of the first storage capacitor C1 is connected to the first node N1, a second end (upper plate) of the first storage capacitor C1 is connected to the fifth node N5, a first end (upper plate) of the second storage capacitor C2 is connected to the first power line VDD, and a second end (lower plate) of the second storage capacitor C2 is connected to the fifth node N5.

[0085] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the fourth scan signal line S4, a first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and a second electrode of the first transistor is connected to the first node N1. When a turn-on signal is applied to the fourth scan signal line S4, the first transistor T1 transmits a first initial voltage to the gate electrode of the third transistor T3 and the first end of the first storage capacitor C1, so that the charge accumulated in the first storage capacitor C1 is released, and initialization is achieved.

[0086] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the second scan signal line S2, a first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to the third node N3. When a turn-on signal is applied to the second scan signal line S2, the second transistor T2 connects the gate electrode of the third transistor T3 to the second electrode.

[0087] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the first node N1, that is, the gate electrode of the third transistor T3 is connected to the first end of the first storage capacitor C1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor, and the third transistor T3 determines the size of the driving current according to the potential difference between its gate electrode and the first electrode.

[0088] In an exemplary embodiment, a gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the fifth node N5. When a turn-on signal is applied to the third scan signal line S3, the fourth transistor T4 enables the data voltage of the data signal line DATA to be input to the second end of the first storage capacitor C1 and the second end of the second storage capacitor C2.

[0089] In an exemplary embodiment, a gate electrode of the fifth transistor T5 is connected to the first light emitting signal line EM1, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2. A gate electrode of the sixth transistor T6 is connected to the second light emitting signal line EM2, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4. When a turn-on signal is applied to the first light emitting signal line EM1 and the second light emitting signal line EM2, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to make the light emitting device EL emit light.

[0090] In an exemplary embodiment, a gate electrode of the seventh transistor T7 is connected to the first scan signal line S1, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4. When a turn-on signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the second initial voltage to the first electrode of the light emitting device EL, so that the charge accumulated in the first electrode of the light emitting device EL is released to achieve initialization.

[0091] In an exemplary embodiment, a gate electrode of the eighth transistor T8 is connected to the first scan signal line S1, a first electrode of the eighth transistor T8 is connected to the second reference signal line REF2, and a second electrode of the eighth transistor T8 is connected to the second node N2. When a turn-on signal is applied to the first scan signal line S1, the eighth transistor T8 transmits the second reference signal to the second node N2.

[0092] In an exemplary embodiment, a gate electrode of the ninth transistor T9 is connected to the second scan signal line S2, a first electrode of the ninth transistor T9 is connected to the first reference signal line REF1, and a second electrode of the ninth transistor T9 is connected to the fifth node N5. When a turn-on signal is applied to the second scan signal line S2, the ninth transistor T9 transmits the first reference signal to the fifth node N5.

[0093] In an exemplary embodiment, the light emitting device EL may be an OLED, including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode), or may be a QLED, including a stacked first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode). The first electrode of the light emitting device EL is connected to the fourth node N4, the second electrode of the light emitting device EL is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low level signal, and the signal of the first power line VDD is a continuously provided high level signal.

[0094] In an exemplary embodiment, the first transistor T1 to the ninth transistor T9 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the ninth transistor T9 may include a P-type transistor and an N-type transistor.

[0095] In an exemplary embodiment, the first transistor T1 to the ninth transistor T9 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS for short), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide). The low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current. The low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate, that is, the LTPS+Oxide (LTPO for short) display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0096] In an exemplary embodiment, the operation process of the pixel driving circuit shown in FIG. 4 may include a first stage to a fifth stage.

[0097] Phase 1. The first phase may include multiple sub-phases that are repeatedly executed, and each sub-phase may include a first sub-phase and a second sub-phase that are executed in sequence.

[0098] In the first sub-stage, the signals of the fourth scan signal line S4 and the first light emitting signal line EM1 are on signals, and the signals of other signal lines are off signals. The signal of the fourth scan signal line S4 is an on signal, which can turn on the first transistor T1, and the first initial signal of the first initial signal line INIT1 can be provided to the first node N1 to initialize the first node N1. When the third transistor T3 is a P-type transistor, the third transistor T3 is turned on. The on signal of the first light emitting signal line EM1 can turn on the fifth transistor T5, and the first power signal of the first power line VDD can be provided to the second node N2.

[0099] In the second sub-stage, the signals of the second scan signal line S2 and the first light emitting signal line EM1 are on signals, and the signals of other signal lines are off signals. The signal of the second scan signal line S2 is an on signal, which can turn on the second transistor T2, connect the first node N1 and the third node N3, and write the threshold voltage of the third transistor T3 to the first node N1. The signal of the second scan signal line S2 is an on signal, which can turn on the ninth transistor T9, and the first reference signal of the first reference signal line REF1 is provided to the fifth node N5, and the fifth node N5 is initialized. The on signal of the first light emitting signal line EM1 can turn on the fifth transistor T5, and the first power signal of the first power line VDD can be provided to the second node N2.

[0100] Phase 2: The signal of the third scan signal line S3 is an on signal, and the signals of other signal lines are off signals. The signal of the third scan signal line S3 is an on signal, which can turn on the fourth transistor T4, and the data voltage provided by the data signal line DATA is written into the fifth node N5.

[0101] Phase 3. The signal of the first scan signal line S1 is a conduction signal, and the signals of other signal lines are disconnection signals. The signal of the first scan signal line S1 is a conduction signal, so that the seventh transistor T7 is turned on, and the second initial signal of the second initial signal line INIT2 can be written into the fourth node N4, and the fourth node N4 is initialized to prevent the residual signal of the previous frame from affecting the display of the current frame. The signal of the first scan signal line S1 is a conduction signal, so that the eighth transistor T8 is turned on, and the second reference signal of the second reference signal line REF2 can be written into the second node N2.

[0102] Phase 4: The signal of the second light emitting signal line EM2 is an on signal, and the signals of other signal lines are off signals. The signal of the second light emitting signal line EM2 is an on signal, so that the sixth transistor T6 is turned on, and the third node N3 and the fourth node N4 are connected, so that the potentials of the third node N3 and the fourth node N4 are the same.

[0103] Phase 5. The signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are on signals, and the signals of other signal lines are off signals. The signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are on signals, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the first power signal of the first power line VDD can provide a driving signal to the light-emitting device EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, so as to drive the light-emitting device EL to emit light.

[0104] In an exemplary embodiment, when the driving transistor (i.e., the third transistor T3) is in a state for a long time, electrons will be trapped in a trap, causing hysteresis. Therefore, in the first stage, by performing the initialization and threshold voltage writing process of the first node N1 multiple times (for example, three times), not only the hysteresis of the driving transistor can be reduced, but also the potential stability of the first node N1 can be ensured. In the third stage S3, the second reference signal is written into the second node N2, and by changing the potential of the second node N2, it can help reduce the hysteresis of the driving transistor. In the fourth stage S4, by connecting the third node N3 and the fourth node N4, the potential of the fourth node N4 can be increased, which is conducive to reducing the time required to reach the start-up voltage of the light-emitting device later.

[0105] The pixel driving circuit provided by the present disclosure can effectively improve the hysteresis of the driving transistor, which is beneficial to improving the display effect.

[0106] FIG5 is a schematic diagram of a planar structure of a display substrate of an exemplary embodiment of the present disclosure, illustrating the structure of a pixel driving circuit in three circuit units (a first circuit unit, a second circuit unit, and a third circuit unit) in the display substrate. In an exemplary embodiment, the display substrate may include a driving circuit layer disposed on a substrate and a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the driving circuit layer may include at least a plurality of circuit units, the light emitting structure layer may include at least a plurality of light emitting units, at least one circuit unit includes a pixel driving circuit, at least one light emitting unit includes a light emitting device, the light emitting device may include at least an anode, an organic light emitting layer, and a cathode, and the anode in the light emitting unit is connected to the pixel driving circuit in the corresponding circuit unit.

[0107] In an exemplary embodiment, the circuit unit mentioned in the present disclosure refers to an area divided according to a pixel driving circuit, and the light-emitting unit mentioned in the present disclosure refers to an area divided according to a light-emitting device. In an exemplary embodiment, the position of the orthogonal projection of the light-emitting unit on the substrate may correspond to the position of the orthogonal projection of the circuit unit on the substrate, or the position of the orthogonal projection of the light-emitting unit on the substrate may not correspond to the position of the orthogonal projection of the circuit unit on the substrate.

[0108] In an exemplary embodiment, a plurality of circuit units sequentially arranged along a first direction X may be referred to as a unit row, a plurality of circuit units sequentially arranged along a second direction Y may be referred to as a unit column, a plurality of unit rows and a plurality of unit columns constitute a circuit unit array arranged in an array, and the first direction X intersects with the second direction Y.

[0109] As shown in Figure 5, in an exemplary embodiment, at least one pixel driving circuit may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light emitting transistor, a sixth transistor T6 as a second light emitting transistor, a seventh transistor T7 as a second initialization transistor, an eighth transistor T8 as a second reference transistor, a ninth transistor T9 as a first reference transistor, a first storage capacitor and a second storage capacitor.

[0110] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the fourth scan signal line 64, the first electrode of the first transistor T1 is connected to the first initial signal line 81, and the second electrode of the first transistor T1 is respectively connected to the first electrode of the second transistor T2 and the first electrode plate 71 of the first storage capacitor. The gate electrode of the second transistor T2 is connected to the fifth scan signal line 65, and the second electrode of the second transistor T2 is respectively connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6. The gate electrode of the third transistor T3 serves as the first electrode plate 71 of the first storage capacitor, and the first electrode of the third transistor T3 is respectively connected to the second electrode of the fifth transistor T5 and the second electrode of the eighth transistor T8. The gate electrode of the fourth transistor T4 is connected to the third scan signal line 63, the first electrode of the fourth transistor T4 is connected to the data signal line 53, and the second electrode of the fourth transistor T4 is respectively connected to the second electrode of the ninth transistor T9, the third electrode plate 73 of the first storage capacitor, and the fourth electrode plate 74 of the second storage capacitor. The gate electrode of the fifth transistor T5 is connected to the first light emitting signal line 31, and the first electrode of the fifth transistor T5 is connected to the first power line 51. The gate electrode of the sixth transistor T6 is connected to the second light emitting signal line 32, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the first scanning signal line 61, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 82. The gate electrode of the eighth transistor T8 is connected to the first scanning signal line 61, and the first electrode of the eighth transistor T8 is connected to the second reference signal line 92. The gate electrode of the ninth transistor T9 is connected to the second scanning signal line 62, and the first electrode of the ninth transistor T9 is connected to the first reference signal line 91.

[0111] In an exemplary embodiment, the second scan signal line 62 and the fifth scan signal line 65 transmit the same scan signal.

[0112] In an exemplary embodiment, the shapes of the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first light-emitting signal line 31, the second light-emitting signal line 32, the first initial signal line 81, the second initial signal line 82, the first reference signal line 91 and the second reference signal line 92 can be line shapes whose main parts extend along the first direction X, and the shapes of the first power line 51 and the data signal line 53 can be line shapes whose main parts extend along the second direction Y.

[0113] In an exemplary embodiment, the display substrate may further include a repair line 33 , and the shape of the repair line 33 may be a line shape in which a main portion extends along the first direction X.

[0114] In an exemplary embodiment, the display substrate may further include at least one first power line 51 extending along the second direction Y and at least one first power connection line 68 extending along the first direction X. In an exemplary embodiment, the first power line 51 is connected to the pixel driving circuit in the plurality of circuit units, and the first power line 51 is configured to continuously provide a high level signal to the pixel driving circuit. In an exemplary embodiment, the first power line 51 extending along the second direction Y and the first power connection line 68 extending along the first direction X are connected to each other to form a mesh structure for transmitting the first power signal.

[0115] In the present disclosure, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.

[0116] In an exemplary embodiment, on a plane perpendicular to the display substrate, the driving circuit layer may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate. In an exemplary embodiment, the first power line 51 and the first power connection line 68 are disposed in different conductive layers, and the first power line 51 is connected to the first power connection line 68 through a via.

[0117] In an exemplary embodiment, the first power connection line 68 may be disposed in the third conductive layer, and the first power line 51 may be disposed in the fourth conductive layer.

[0118] In an exemplary embodiment, the display substrate may further include at least one second initial signal line 82 extending along the first direction X and at least one initial connection line 56 extending along the second direction Y, wherein the second initial signal line 82 is configured to provide a second initial signal to the pixel driving circuit. The initial connection line 56 extending along the second direction Y is connected to the second initial signal line 82 extending along the first direction X to form a mesh structure for transmitting the second initial signal.

[0119] In an exemplary embodiment, the second preliminary signal line 82 and the preliminary connection line 56 may be disposed in different conductive layers, and the preliminary connection line 56 and the second preliminary signal line 82 are connected through a via.

[0120] In an exemplary embodiment, the second preliminary signal line 82 may be disposed in the third conductive layer, and the preliminary connection line 56 may be disposed in the fourth conductive layer.

[0121] In an exemplary embodiment, the display substrate further includes at least one first reference signal line 91 extending along the first direction X and at least one reference signal connection line 54 extending along the second direction Y, and the first reference signal line 91 is configured to provide a reference signal to the pixel driving circuit. In an exemplary embodiment, the reference signal connection line 54 extending along the second direction Y is connected to the first reference signal line 91 extending along the first direction X to form a mesh structure for transmitting the first reference signal.

[0122] In an exemplary embodiment, the first reference signal line 91 and the reference signal connection line 54 are disposed in different conductive layers, and the reference signal connection line 54 is connected to the first reference signal line 91 through a via.

[0123] In an exemplary embodiment, the first reference signal line 91 may be disposed in the third conductive layer, and the reference signal connection line 54 may be disposed in the fourth conductive layer.

[0124] FIG6 is a schematic diagram of the structure of the first storage capacitor and the second storage capacitor region in FIG5. As shown in FIG5 and FIG6, in an exemplary embodiment, the at least two first capacitor plates of the first storage capacitor may be a first plate 71 and a third plate 73, and the orthographic projection of the first plate 71 on the substrate at least partially overlaps with the orthographic projection of the third plate 73 on the substrate. The at least two second capacitor plates of the second storage capacitor may be a second plate 72 and a fourth plate 74, and the orthographic projection of the second plate 72 on the substrate at least partially overlaps with the orthographic projection of the fourth plate 74 on the substrate, and the third plate 73 is connected to the fourth plate 74.

[0125] In an exemplary embodiment, the first electrode plate 71 and the second electrode plate 72 may be disposed in the first conductive layer, and the third electrode plate 73 and the fourth electrode plate 74 may be disposed in the second conductive layer.

[0126] In an exemplary embodiment, the third electrode plate 73 of the first storage capacitor and the fourth electrode plate 74 of the second storage capacitor may be an integral structure connected to each other.

[0127] As shown in Figures 5 and 6, in an exemplary embodiment, at least one circuit unit may also include a first connection electrode 41, which is respectively connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2 and the first electrode plate 71 of the first storage capacitor, and the first connection electrode 41 can serve as the first node of the pixel driving circuit.

[0128] In an exemplary embodiment, at least one circuit unit may further include a power shielding block 51-1, which is connected to the first power line 51, and the positive projection of the power shielding block 51-1 on the substrate at least partially overlaps with the positive projection of the first connecting electrode 41 on the substrate to shield the influence of other signals in the pixel driving circuit on the first node.

[0129] In an exemplary embodiment, at least one circuit unit may further include a second connection electrode 42, which is respectively connected to the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third electrode plate 73 of the first storage capacitor and the fourth electrode plate 74 of the second storage capacitor, and the second connection electrode 42 can serve as the fifth node N5 in the pixel driving circuit.

[0130] In an exemplary embodiment, an orthographic projection of the first power line 51 on the substrate at least partially overlaps an orthographic projection of the second connection electrode 42 on the substrate to shield the influence of other signals in the pixel driving circuit on the fifth node.

[0131] In an exemplary embodiment, at least one circuit unit further includes a first shielding electrode 36, the orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first transistor T1 on the substrate, and the orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the second transistor T2 on the substrate. In an exemplary embodiment, the first shielding electrode 36 is configured to shield the influence of the data voltage jump on the first transistor T1 and the second transistor T2, so as to prevent the data voltage jump from affecting the normal operation of the pixel driving circuit and improve the display effect.

[0132] In an exemplary embodiment, the first shield electrode 36 is connected to a first power connection line 68 .

[0133] In an exemplary embodiment, the first shielding electrode 36 includes a first extension segment 36-1 and a first shielding segment 36-2; the first extension segment 36-1 is in the shape of a strip extending along the second direction Y, and the first shielding segment 36-2 is in the shape of a strip extending along the first direction X; the first end of the first extension segment 36-1 is connected to the first power connection line 68, and the second end of the first extension segment 36-1 is connected to the first shielding segment 36-2. The first shielding segment 36-2 includes a first shielding end and a second shielding end, the orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first transistor T1 in the present circuit unit on the substrate, and the orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the second transistor T2 in the adjacent circuit unit on the substrate.

[0134] In an exemplary embodiment, the first shielding electrode 36 and the first power connection line 68 are an integral structure connected to each other.

[0135] In an exemplary embodiment, at least one circuit unit further includes a second shielding electrode 37, the second shielding electrode 37 is connected to the second reference signal line 92, and the positive projection of the second shielding electrode 37 on the substrate at least partially overlaps with the positive projection of the node between the two gate electrodes of the fourth transistor T4 on the substrate. In an exemplary embodiment, the second shielding electrode 37 is configured to shield the influence of the data voltage jump on the fourth transistor T4, prevent the data voltage jump from affecting the normal operation of the pixel driving circuit, and improve the display effect.

[0136] In an exemplary embodiment, the second shielding electrode 37 and the second reference signal line 92 are an integral structure connected to each other.

[0137] In an exemplary embodiment, at least one circuit unit further includes a third shielding electrode 38, the third shielding electrode 38 is connected to the second reference signal line 92, and the positive projection of the third shielding electrode 38 on the substrate overlaps at least partially with the positive projection of the node between the two gate electrodes of the ninth transistor T9 on the substrate. In an exemplary embodiment, the third shielding electrode 38 is configured to shield the influence of the data voltage jump on the ninth transistor T9, so as to prevent the data voltage jump from affecting the normal operation of the pixel driving circuit and improve the display effect.

[0138] In an exemplary embodiment, the third shielding electrode 38 and the second reference signal line 92 are an integral structure connected to each other.

[0139] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes the processes of coating photoresist, mask exposure, development, etching, stripping photoresist, etc. for metal materials, inorganic materials or transparent conductive materials, and includes the processes of coating organic materials, mask exposure and development, etc. for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0140] In an exemplary embodiment, taking three circuit units (a first circuit unit, a second circuit unit, and a third circuit unit) in an n-th unit row as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0141] (11) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process, forming a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, as shown in FIG. 7 .

[0142] In an exemplary embodiment, the semiconductor layer of each circuit unit in the display substrate may include at least a first active layer 11 of a first transistor T1, a second active layer 12 of a second transistor T2, a third active layer 13 of a third transistor T3, a fourth active layer 14 of a fourth transistor T4, a fifth active layer 15 of a fifth transistor T5, a sixth active layer 16 of a sixth transistor T6, a seventh active layer 17 of a seventh transistor T7, an eighth active layer 18 of an eighth transistor T8, and a ninth active layer 19 of a ninth transistor T9, and the first to third active layers 11 to 13 and the fifth to eighth active layers 15 to 18 may be an integral structure connected to each other, and the fourth active layer 14 and the ninth active layer 19 may be an integral structure connected to each other.

[0143] In an exemplary embodiment, the fourth active layer 14 and the ninth active layer 19 of the nth unit row may be located on a side of the third active layer 13 close to the n-1th unit row, that is, the fourth active layer 14 and the ninth active layer 19 may be located on a side of the third active layer 13 of the present circuit unit in the opposite direction of the second direction Y. The first active layer 11, the second active layer 12, and the fifth active layer 15 to the eighth active layer 18 of the nth unit row may be located on a side of the third active layer 13 close to the n+1th unit row, that is, the first active layer 11, the second active layer 12, the fifth active layer 15 to the eighth active layer 18 may be located on a side of the second direction Y of the third active layer 13 of the present circuit unit.

[0144] In an exemplary embodiment, the first active layer 11 may be located on one side of the third active layer 13 of the present circuit unit in the second direction Y, the fifth active layer 15 may be located on one side of the first active layer 11 of the present circuit unit in the second direction Y, and the eighth active layer 18 may be located on one side of the fifth active layer 15 of the present circuit unit in the second direction Y. The second active layer 12 may be located on one side of the third active layer 13 of the present circuit unit in the second direction Y, the sixth active layer 16 may be located on one side of the second active layer 12 of the present circuit unit in the second direction Y, and the seventh active layer 17 may be located on one side of the sixth active layer 16 of the present circuit unit in the second direction Y.

[0145] In an exemplary embodiment, the fifth active layer 15 and the eighth active layer 18 can be located on one side of the first direction X of the third active layer 13 of the present circuit unit (such as the side in the opposite direction of the first direction X), and the sixth active layer 16 and the seventh active layer 17 can be located on the other side of the first direction X of the third active layer 13 of the present circuit unit (such as one side of the first direction X).

[0146] In an exemplary embodiment, the first active layer 11 and the second active layer 12 may be shaped like an "L", the third active layer 13 may be shaped like a "C", the fourth active layer 14 and the ninth active layer 19 may be shaped like an "n", and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 may be shaped like an "I".

[0147] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be connected to each other, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 15-2 of the fifth active layer, and the second region 18-2 of the eighth active layer may be connected to each other, and the first region 13-1 of the third active layer may serve as the second region 15-2 of the fifth active layer and the second region 18-2 of the eighth active layer at the same time, constituting a second node N2 of the pixel driving circuit. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be connected to each other, and the second region 13-2 of the third active layer may serve as the second region 12-2 of the second active layer and the first region 16-1 of the sixth active layer at the same time, constituting a third node N3 of the pixel driving circuit. The second area 14-2 of the fourth active layer and the second area 19-2 of the ninth active layer may be connected to each other, and the second area 14-2 of the fourth active layer may serve as the second area 19-2 of the ninth active layer. The second area 16-2 of the sixth active layer and the second area 17-2 of the seventh active layer may be connected to each other. The second area 16-2 of the sixth active layer may serve as the second area 17-2 of the seventh active layer, constituting a fourth node N4 of the pixel driving circuit. The first area 11-1 of the first active layer, the first area 14-1 of the fourth active layer, the first area 15-1 of the fifth active layer, the first area 17-1 of the seventh active layer, the first area 18-1 of the eighth active layer, and the first area 19-1 of the ninth active layer may be provided separately.

[0148] In an exemplary embodiment, the display substrate may further include a first active connection line 10 and a second active connection line 20. The first active connection line 10 may be located at one side of the ninth active layer 19 in the second direction Y and connected to the first region 19-1 of the ninth active layer of each circuit unit. The second active connection line 20 may be located at one side of the seventh active layer 17 in the second direction Y and connected to the first region 17-1 of the seventh active layer of each circuit unit.

[0149] In an exemplary embodiment, the shape of the first active connection line 10 may be a zigzag shape with the main part extending along the first direction X, and the first active connection line 10 and the ninth active layer of the plurality of circuit units may be an integrated structure connected to each other. Since the first region of the ninth active layer is connected to the first reference signal line formed subsequently, the first active connection line 10 may be reused as the first reference signal line extending along the first direction X, which not only ensures that the first regions of the plurality of ninth active layers in a unit row have the same potential, but also reduces the voltage drop of the first reference signal, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0150] In an exemplary embodiment, the second active connection line 20 may be in the shape of a straight line with a main portion extending along the first direction X, and the second active connection line 20 and the seventh active layer of the plurality of circuit units may be an integral structure connected to each other. Since the first region of the seventh active layer is connected to the second initial signal line formed subsequently, the second active connection line 20 may be reused as the second initial signal line extending along the first direction X, which not only ensures that the first regions of the plurality of seventh active layers in a unit row have the same potential, but also reduces the voltage drop of the second initial signal, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0151] (12) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film by a patterning process, forming a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 8A and 8B , where FIG. 8B is a schematic diagram of the first conductive layer in FIG. 8A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0152] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate includes at least: a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, a fifth gate electrode 25, a sixth gate electrode 26, a ninth gate electrode 29, a first scan signal line 61, a first plate 71 of a first storage capacitor, and a second plate 72 of a second storage capacitor.

[0153] In an exemplary embodiment, the first gate electrode 21 may be in an "L" shape and may be located on one side of the first electrode plate 71 in the second direction Y. The region where the first gate electrode 21 overlaps with the first active layer may serve as the gate electrode of the first transistor T1 of the dual-gate structure.

[0154] In an exemplary embodiment, the second gate electrode 22 may be in a "T" shape and may be located on one side of the first electrode 71 in the second direction Y. The area where the second gate electrode 22 overlaps the second active layer may serve as the gate electrode of the second transistor T2 of the dual-gate structure.

[0155] In an exemplary embodiment, the fourth gate electrode 24 may be in an "L" shape and may be located on the side of the second electrode 72 in the opposite direction of the second direction Y. The area where the fourth gate electrode 24 overlaps with the fourth active layer may serve as the gate electrode of the fourth transistor T4 of the dual-gate structure.

[0156] In an exemplary embodiment, the fifth gate electrode 25 may be in the shape of a strip extending along the second direction Y and may be located on one side of the first gate electrode 21 in the second direction Y. The region where the fifth gate electrode 25 overlaps with the fifth active layer may serve as the gate electrode of the fifth transistor T5.

[0157] In an exemplary embodiment, the sixth gate electrode 26 may be in a strip shape extending along the first direction X and may be located on one side of the second gate electrode 22 in the second direction Y. The region where the sixth gate electrode 26 overlaps the sixth active layer may serve as the gate electrode of the sixth transistor T6.

[0158] In an exemplary embodiment, the ninth gate electrode 29 may be in the shape of a strip extending along the first direction X, and may be located on one side of the second electrode plate 72 in the opposite direction of the second direction Y. The area where the ninth gate electrode 29 overlaps with the ninth active layer may serve as the gate electrode of the ninth transistor T9 of the dual-gate structure.

[0159] In an exemplary embodiment, the shape of the first scan signal line 61 can be a line shape in which the main part extends along the first direction X, and can be located on one side of the fifth gate electrode 25 and the sixth gate electrode 26 in the second direction Y. The area where the first scan signal line 61 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7, and the area where the first scan signal line 61 overlaps with the eighth active layer can serve as the gate electrode of the eighth transistor T8.

[0160] In an exemplary embodiment, the shape of the first electrode 71 of the first storage capacitor can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the first electrode 71 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. The first electrode 71 can simultaneously serve as the lower electrode of the first storage capacitor and the gate electrode of the third transistor T3.

[0161] In an exemplary embodiment, the shape of the second electrode plate 72 of the second storage capacitor may be rectangular, and the corners of the rectangle may be chamfered, and may be located on one side of the first electrode plate 71 in the opposite direction of the second direction Y, and on one side of the fourth gate electrode 24 and the ninth gate electrode 29 in the second direction Y, that is, in the second direction Y, the second electrode plate 72 is located between the first electrode plate 71 and the fourth gate electrode 24 (ninth gate electrode 29), and the orthographic projection of the second electrode plate 72 on the substrate does not overlap with the orthographic projection of the semiconductor layer on the substrate. In an exemplary embodiment, the second electrode plate 72 may serve as the lower electrode plate of the second storage capacitor.

[0162] In an exemplary embodiment, the area where the first active connection line 10 is connected to the first area of ​​the ninth active layer is bent toward the ninth active layer, so that a concave portion is formed on the side of the first active connection line 10 away from the ninth active layer. A protrusion 72-1 is provided on the side of the second electrode plate 72 close to the first active connection line 10. The shape of the protrusion 72-1 can be rectangular. The first end of the protrusion 72-1 is connected to the second electrode plate 72, and the second end of the protrusion 72-1 extends into the concave portion of the first active connection line 10.

[0163] In an exemplary embodiment, the second electrode plate 72 and the protrusion 72-1 may be an integral structure connected to each other. The present disclosure can effectively increase the area of ​​the second electrode plate 72 and the capacitance of the second storage capacitor by providing the concave portion of the first active connection line 10 and the protrusion 72-1 of the second electrode plate 72.

[0164] In an exemplary embodiment, a plate connecting line 72-2 may be provided on one side of the second electrode plate 72 in the first direction X or in the opposite direction of the first direction X, and a first end of the plate connecting line 72-2 is connected to the second electrode plate 72 of the circuit unit, and a second end of the plate connecting line 72-2 is connected to the second electrode plate 72 of the adjacent circuit unit after extending along the first direction X or in the opposite direction of the first direction X, so that the second electrode plates 72 of adjacent circuit units in a unit row are connected to each other. Since the second electrode plate 72 is connected to the first power line formed later, the second electrode plates 72 and the plate connecting line 72-2 of the integrated structure of multiple circuit units can be reused as a horizontal power line extending along the first direction X, which can not only ensure that the multiple second electrode plates 72 in a unit row have the same potential, but also reduce the voltage drop of the first power signal, which is conducive to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0165] In an exemplary embodiment, the plurality of second electrode plates 72 and the plurality of electrode plate connection lines 72 - 2 spaced apart along the first direction X may be an integral structure connected to each other.

[0166] In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer can be conductorized using the first conductive layer as a shield, the semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the ninth transistor T9, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first and second areas of the first active layer to the ninth active layer, and the first active connecting line and the second active connecting line are all conductorized.

[0167] (13) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 9A and 9B , where FIG. 9B is a schematic diagram of the second conductive layer in FIG. 9A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0168] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: a first light-emitting signal line 31, a second light-emitting signal line 32, a repair line 33, a second shielding electrode 37, a third shielding electrode 38, a third plate 73 of a first storage capacitor, a fourth plate 74 of a second storage capacitor, a first initial signal line 81 and a second reference signal line 92.

[0169] In an exemplary embodiment, the shapes of the first light-emitting signal line 31, the second light-emitting signal line 32, the repair line 33, the first initial signal line 81 and the second reference signal line 92 can be line shapes in which the main part extends along the first direction X, the first light-emitting signal line 31, the second light-emitting signal line 32, the repair line 33 and the first initial signal line 81 can be located between the first gate electrode 21 and the first scanning signal line 61, and the second reference signal line 92 can be located on the side of the fourth gate electrode 24 in the opposite direction of the second direction Y.

[0170] In an exemplary embodiment, the first light-emitting signal line 31 can be located on one side of the second direction Y of the first gate electrode 21 of the present circuit unit, the first initial signal line 81 can be located on one side of the second direction Y of the first light-emitting signal line 31 of the present circuit unit, the second light-emitting signal line 32 can be located on one side of the second direction Y of the first initial signal line 81 of the present circuit unit, and the repair line 33 can be located on one side of the second direction Y of the second light-emitting signal line 32 of the present circuit unit, that is, the second light-emitting signal line 32 and the first initial signal line 81 can be located between the first light-emitting signal line 31 and the repair line 33.

[0171] In an exemplary embodiment, a first light-emitting connection block 31-1 is provided on one side of the first light-emitting signal line 31 close to the first initial signal line 81. The first light-emitting connection block 31-1 can be provided in each circuit unit. A first end of the first light-emitting connection block 31-1 is connected to the first light-emitting signal line 31, and a second end of the first light-emitting connection block 31-1 extends in the direction of the first initial signal line 81. The first light-emitting connection block 31-1 is configured to be connected to the fifth gate electrode 25 through a seventh connection electrode formed subsequently.

[0172] In an exemplary embodiment, the first light emitting signal line 31 and the plurality of first light emitting connection blocks 31 - 1 may be an integral structure connected to each other.

[0173] In an exemplary embodiment, a second light-emitting connection block 32-1 is provided on one side of the second light-emitting signal line 32 close to the first initial signal line 81, and the second light-emitting connection block 32-1 can be provided in each circuit unit, and a first end of the second light-emitting connection block 32-1 is connected to the second light-emitting signal line 32, and a second end of the second light-emitting connection block 32-1 extends in the direction of the first initial signal line 81, and the second light-emitting connection block 32-1 is configured to be connected to the sixth gate electrode 26 through an eighth connection electrode formed subsequently.

[0174] In an exemplary embodiment, the second light emitting signal line 32 and the plurality of second light emitting connection blocks 32 - 1 may be an integral structure connected to each other.

[0175] In an exemplary embodiment, a first initial connection block 81-1 is provided on one side of the first initial signal line 81 close to the first light-emitting signal line 31. The first initial connection block 81-1 can be provided in each circuit unit. A first end of the first initial connection block 81-1 is connected to the first initial signal line 81, and a second end of the first initial connection block 81-1 extends toward the direction of the first light-emitting signal line 31. The first initial connection block 81-1 is configured to be connected to the first region of the first active layer through a ninth connection electrode formed subsequently.

[0176] In an exemplary embodiment, the first preliminary signal line 81 and the plurality of first preliminary connection blocks 81 - 1 may be an integral structure connected to each other.

[0177] In an exemplary embodiment, a second reference connection block 92-1 is provided on a side of the second reference signal line 92 of the nth unit row away from the second electrode plate 72 of the nth unit row. The second reference connection block 92-1 may be provided in each circuit unit. A first end of the second reference connection block 92-1 is connected to the second reference signal line 92, and a second end of the second reference connection block 92-1 extends in a direction away from the second electrode plate 72, that is, in a direction toward the n-1th unit row. In an exemplary embodiment, the second reference connection block 92-1 of the second reference signal line 92 in the nth unit row is configured to be connected to the first region of the eighth active layer in the n-1th unit row through a sixth connection electrode formed subsequently, and provide a second reference signal to the first electrode of the eighth transistor T8 in the n-1th unit row.

[0178] In an exemplary embodiment, the second reference signal line 92 and the plurality of second reference connection blocks 92 - 1 may be an integral structure connected to each other.

[0179] In an exemplary embodiment, the second shielding electrode 37 and the third shielding electrode 38 may be rectangular in shape and may be located on a side of the second reference signal line 92 close to the fourth electrode plate 74. The second shielding electrode 37 and the third shielding electrode 38 may be provided in each circuit unit. The first ends of the second shielding electrode 37 and the third shielding electrode 38 are connected to the second reference signal line 92, and the second ends of the second shielding electrode 37 and the third shielding electrode 38 extend in the direction of the fourth electrode plate 74. The orthographic projection of the second shielding electrode 37 on the substrate overlaps at least partially with the orthographic projection of the fourth active layer between the two gate electrodes of the fourth transistor T4 in the present circuit unit on the substrate, and the orthographic projection of the third shielding electrode 38 on the substrate overlaps at least partially with the orthographic projection of the ninth active layer between the two gate electrodes of the ninth transistor T9 in the present circuit unit on the substrate. In an exemplary embodiment, the second shielding electrode 37 is configured to shield the influence of the data voltage jump on the fourth transistor T4, and the third shielding electrode 38 is configured to shield the influence of the data voltage jump on the ninth transistor T9, so as to prevent the data voltage jump from affecting the normal operation of the pixel driving circuit and improve the display effect.

[0180] In an exemplary embodiment, the contour shape of the third plate 73 of the first storage capacitor can be rectangular, the corners of the rectangle can be chamfered, and it can be located between the first light-emitting signal line 31 and the second reference signal line 92 of the circuit unit. The orthographic projection of the third plate 73 on the substrate at least partially overlaps with the orthographic projection of the first plate 71 on the substrate. The third plate 73 can serve as the upper plate of the first storage capacitor, and the first plate 71 and the third plate 73 constitute the first storage capacitor of the pixel driving circuit.

[0181] In an exemplary embodiment, a first opening 75 is provided on the third electrode plate 73 of each circuit unit. The first opening 75 may be located in the middle of the third electrode plate 73. The first opening 75 may be rectangular, so that the third electrode plate 73 forms a ring structure. The first opening 75 exposes the third insulating layer covering the first electrode plate 71, and the orthographic projection of the first electrode plate 71 on the substrate includes the orthographic projection of the first opening 75 on the substrate. In an exemplary embodiment, the first opening 75 is configured to accommodate a tenth via hole formed subsequently. The tenth via hole is located in the first opening 75 and exposes the first electrode plate 71, so that the first connection electrode formed subsequently is connected to the first electrode plate 71.

[0182] In an exemplary embodiment, the contour shape of the fourth plate 74 of the second storage capacitor can be rectangular, the corners of the rectangle can be chamfered, and it can be located between the third plate 73 and the second reference signal line 92 of the circuit unit. The orthographic projection of the fourth plate 74 on the substrate at least partially overlaps with the orthographic projection of the second plate 72 on the substrate. The fourth plate 74 can serve as the lower plate of the second storage capacitor, and the second plate 72 and the fourth plate 74 constitute the second storage capacitor of the pixel driving circuit.

[0183] In an exemplary embodiment, a second opening 76 is provided on the fourth electrode plate 74 of each circuit unit, and the second opening 76 may be located in the middle of the fourth electrode plate 74, and the second opening 76 may be rectangular, so that the fourth electrode plate 74 forms a ring structure. The second opening 76 exposes the third insulating layer covering the second electrode plate 72, and the orthographic projection of the second electrode plate 72 on the substrate includes the orthographic projection of the second opening 76 on the substrate. In an exemplary embodiment, the second opening 76 is configured to accommodate the eleventh via hole formed subsequently, and the eleventh via hole is located in the second opening 76 and exposes the second electrode plate 72, so that the first power connection line formed subsequently is connected to the second electrode plate 72.

[0184] In an exemplary embodiment, a plate connection block 74-2 is provided on one side of the fourth plate 74 close to the second reference signal line 92. The plate connection block 74-2 may be in an "I" shape, and the plate connection block 74-2 may be provided in each circuit unit. In an exemplary embodiment, a first end of the plate connection block 74-2 is connected to the fourth plate 74, a second end of the plate connection block 74-2 extends toward the second reference signal line 92, and the plate connection block 74-2 is configured to be connected to the second region of the fourth active layer (also the second region of the ninth active layer) through a second connection electrode formed subsequently.

[0185] In an exemplary embodiment, the fourth electrode plate 74 and the third electrode plate 73 may be an integrated structure connected to each other, that is, the third electrode plate 73 of the first storage capacitor and the fourth electrode plate 74 of the second storage capacitor share the same electrode plate.

[0186] In an exemplary embodiment, the repair line 33 is a pre-set repair line, and is configured to input a signal to the anode of the sub-pixel with the bright spot through the repair line 33 to repair it into a dark spot when a bright spot defect occurs on the display substrate.

[0187] (14) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, and providing a plurality of vias in each circuit unit, as shown in FIG. 10 .

[0188] In an exemplary embodiment, the multiple vias of each circuit unit in the display substrate include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, a twentieth via V20, a twenty-first via V21, a twenty-second via V22 and a twenty-third via V23.

[0189] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed ninth connecting electrode to the first region of the first active layer through the via hole.

[0190] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second area of ​​the first active layer (also the first area of ​​the second active layer) on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second area of ​​the first active layer (also the first area of ​​the second active layer), and the second via hole V2 is configured to connect a subsequently formed first connecting electrode to the second area of ​​the first active layer (also the first area of ​​the second active layer) through the via hole.

[0191] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first area of ​​the fourth active layer, and the third via hole V3 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the fourth active layer through the via hole.

[0192] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second area of ​​the fourth active layer (also the second area of ​​the ninth active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the second area of ​​the fourth active layer (also the second area of ​​the ninth active layer), and the fourth via hole V4 is configured to connect a subsequently formed second connecting electrode to the second area of ​​the fourth active layer (also the second area of ​​the ninth active layer) through the via hole.

[0193] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first area of ​​the fifth active layer, and the fifth via hole V5 is configured to connect a subsequently formed fourth connecting electrode to the first area of ​​the fifth active layer through the via hole.

[0194] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the sixth via hole V6 is configured to connect a subsequently formed fifth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0195] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first area of ​​the seventh active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the first area of ​​the seventh active layer, and the seventh via hole V7 is configured to connect a subsequently formed second initial signal line to the first area of ​​the seventh active layer through the via hole.

[0196] In an exemplary embodiment, the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via hole V8 are etched away to expose the surface of the first region of the eighth active layer, and the eighth via hole V8 is configured to connect a subsequently formed sixth connecting electrode to the first region of the eighth active layer through the via hole.

[0197] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first region of the ninth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via V9 are etched away to expose the surface of the first region of the ninth active layer, and the ninth via V9 is configured to connect a subsequently formed first reference signal line to the first region of the ninth active layer through the via.

[0198] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the first opening 75 of the third electrode plate 73 on the substrate, the fourth insulating layer and the third insulating layer in the tenth via hole V10 are etched away to expose the surface of the first electrode plate 71, and the tenth via hole V10 is configured to connect a subsequently formed first connecting electrode to the first electrode plate 71 through the via hole.

[0199] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second opening 76 of the fourth electrode plate 74 on the substrate, the fourth insulating layer and the third insulating layer in the eleventh via hole V11 are etched away to expose the surface of the second electrode plate 72, and the eleventh via hole V11 is configured to connect a subsequently formed first power connection line to the second electrode plate 72 through the via hole.

[0200] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the fourth electrode plate 74 on the substrate, the fourth insulating layer in the thirteenth via hole V13 is etched away to expose the surface of the fourth electrode plate 74, and the thirteenth via hole V13 is configured to connect a subsequently formed second connecting electrode to the fourth electrode plate 74 through the via hole.

[0201] In an exemplary embodiment, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the first gate electrode 21 on the substrate, the fourth insulating layer and the third insulating layer in the fourteenth via hole V14 are etched away to expose the surface of the first gate electrode 21, and the fourteenth via hole V14 is configured to connect a subsequently formed fourth scanning signal line to the first gate electrode 21 through the via hole.

[0202] In an exemplary embodiment, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the second gate electrode 22 on the substrate, the fourth insulating layer and the third insulating layer in the fifteenth via hole V15 are etched away to expose the surface of the second gate electrode 22, and the fifteenth via hole V15 is configured to connect the subsequently formed fifth scanning signal line to the second gate electrode 22 through the via hole.

[0203] In an exemplary embodiment, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the fourth gate electrode 24 on the substrate, the fourth insulating layer and the third insulating layer in the sixteenth via hole V16 are etched away to expose the surface of the fourth gate electrode 24, and the sixteenth via hole V16 is configured to connect a subsequently formed third scanning signal line to the fourth gate electrode 24 through the via hole.

[0204] In an exemplary embodiment, the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the fifth gate electrode 25 on the substrate, the fourth insulating layer and the third insulating layer in the seventeenth via hole V17 are etched away to expose the surface of the fifth gate electrode 25, and the seventeenth via hole V17 is configured to connect the subsequently formed seventh connecting electrode to the fifth gate electrode 25 through the via hole.

[0205] In an exemplary embodiment, the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the sixth gate electrode 26 on the substrate, the fourth insulating layer and the third insulating layer in the eighteenth via hole V18 are etched away to expose the surface of the sixth gate electrode 26, and the eighteenth via hole V18 is configured to connect the subsequently formed eighth connecting electrode to the sixth gate electrode 26 through the via hole.

[0206] In an exemplary embodiment, the orthographic projection of the nineteenth via hole V19 on the substrate is located within the range of the orthographic projection of the ninth gate electrode 29 on the substrate, the fourth insulating layer and the third insulating layer in the nineteenth via hole V19 are etched away to expose the surface of the ninth gate electrode 29, and the nineteenth via hole V19 is configured to connect a subsequently formed second scanning signal line to the ninth gate electrode 29 through the via hole.

[0207] In an exemplary embodiment, the orthographic projection of the twentieth via hole V20 on the substrate is located within the range of the orthographic projection of the first light-emitting connection block 31-1 of the first light-emitting signal line 31 on the substrate, the fourth insulating layer in the twentieth via hole V20 is etched away to expose the surface of the first light-emitting connection block 31-1, and the twentieth via hole V20 is configured to connect the subsequently formed seventh connection electrode to the first light-emitting connection block 31-1 through the via hole.

[0208] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the second light-emitting connection block 32-1 of the second light-emitting signal line 32 on the substrate, the fourth insulating layer in the twenty-first via hole V21 is etched away to expose the surface of the second light-emitting connection block 32-1, and the twenty-first via hole V21 is configured to connect the subsequently formed eighth connection electrode to the second light-emitting connection block 32-1 through the via hole.

[0209] In an exemplary embodiment, the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the second reference connection block 92-1 of the second reference signal line 92 on the substrate, the fourth insulating layer in the twenty-second via V22 is etched away to expose the surface of the second reference connection block 92-1, and the twenty-second via V22 is configured to connect the subsequently formed sixth connection electrode to the second reference connection block 92-1 through the via.

[0210] In an exemplary embodiment, the orthographic projection of the twenty-third via V23 on the substrate is located within the range of the orthographic projection of the first initial connection block 81-1 of the first initial signal line 81 on the substrate, the fourth insulating layer in the twenty-third via V23 is etched away to expose the surface of the first initial connection block 81-1, and the twenty-third via V23 is configured to connect the subsequently formed ninth connection electrode to the first initial connection block 81-1 through the via.

[0211] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, as shown in FIGS. 11A and 11B , where FIG. 11B is a schematic diagram of the third conductive layer in FIG. 11A . In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0212] In an exemplary embodiment, the third conductive layer patterns of multiple circuit units in the display substrate may include: a first shielding electrode 36, a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a sixth connecting electrode 46, a seventh connecting electrode 47, an eighth connecting electrode 48, a ninth connecting electrode 49, a second scanning signal line 62, a third scanning signal line 63, a fourth scanning signal line 64, a fifth scanning signal line 65, a first power supply connection line 68, a second initial signal line 82 and a first reference signal line 91.

[0213] In an exemplary embodiment, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first power connection line 68, the second initial signal line 82 and the first reference signal line 91 may be in the shape of a line whose main part extends along the first direction X. The second scan signal line 62, the third scan signal line 63 and the first reference signal line 91 may be located on one side of the fourth electrode plate 74 in the opposite direction of the second direction Y, the fourth scan signal line 64, the fifth scan signal line 65 and the second initial signal line 82 may be located on one side of the third electrode plate 73 in the second direction Y, and the first power connection line 68 may be located in the region where the third electrode plate 73 is located.

[0214] In an exemplary embodiment, the first reference signal line 91 can be located on the side of the fourth electrode 74 opposite to the second direction Y, the second scanning signal line 62 can be located on the side of the first reference signal line 91 opposite to the second direction Y, and the third scanning signal line 63 can be located on the side of the second scanning signal line 62 opposite to the second direction Y.

[0215] In an exemplary embodiment, the fourth scan signal line 64 can be located on one side of the third electrode plate 73 in the second direction Y, the fifth scan signal line 65 can be located on one side of the fourth scan signal line 64 in the second direction Y, and the second initial signal line 82 can be located on one side of the fifth scan signal line 65 in the second direction Y.

[0216] In an exemplary embodiment, the first power connection line 68 can be located between the fourth scanning signal line 64 and the first reference signal line 91, and the orthographic projection of the first power connection line 68 on the substrate can at least partially overlap with the orthographic projection of the third electrode 73 on the substrate, and the first power connection line 68 is configured to be connected to the first power line formed subsequently to form a high-voltage power grid structure with a mesh-like interconnected structure on the display substrate.

[0217] In an exemplary embodiment, the second scan signal line 62 is connected to the ninth gate electrode 29 in each circuit unit through the nineteenth via hole V19, thereby realizing that the second scan signal line 62 is connected to the ninth gate electrode 29 of the ninth transistor T9, and the second scan signal line 62 can control the conduction and disconnection of the ninth transistor T9.

[0218] In an exemplary embodiment, the fifth scan signal line 65 is connected to the second gate electrode 22 in each circuit unit through the fifteenth via hole V15, thereby realizing that the fifth scan signal line 65 is connected to the second gate electrode 22 of the second transistor T2, and the fifth scan signal line 65 can control the conduction and disconnection of the second transistor T2.

[0219] In an exemplary embodiment, the second scan signal line 62 and the fifth scan signal line 65 can be extended to the frame area and connected to the same gate driving circuit to output the same scan signal, that is, the second scan signal line 62 and the fifth scan signal line 65 output the same second scan signal.

[0220] In an exemplary embodiment, the third scan signal line 63 is connected to the fourth gate electrode 24 in each circuit unit through the sixteenth via hole V16, thereby realizing that the third scan signal line 63 is connected to the fourth gate electrode 24 of the fourth transistor T4, and the third scan signal line 63 can control the conduction and disconnection of the fourth transistor T4.

[0221] In an exemplary embodiment, the fourth scan signal line 64 is connected to the first gate electrode 21 in each circuit unit through the fourteenth via hole V14, thereby realizing that the fourth scan signal line 64 is connected to the first gate electrode 21 of the first transistor T1, and the fourth scan signal line 64 can control the conduction and disconnection of the first transistor T1.

[0222] In an exemplary embodiment, the second initial signal line 82 is connected to the first region of the seventh active layer in each circuit unit through the seventh via V7, thereby realizing that the second initial signal line 82 is connected to the first electrode of the seventh transistor T7, and the second initial signal line 82 can write the second initial signal into the first electrode of the seventh transistor T7.

[0223] In an exemplary embodiment, a second initial connection block 82-1 is disposed on one side of the second initial signal line 82 close to the fifth scan signal line 65, a first end of the second initial connection block 82-1 is connected to the second initial signal line 82, and a second end of the second initial connection block 82-1 extends toward the direction of the fifth scan signal line 65. In an exemplary embodiment, the second initial connection block 82-1 is configured to be connected to an initial connection line formed subsequently.

[0224] In an exemplary embodiment, since the second active connection line 20 of the semiconductor layer is directly connected to the first area of ​​the seventh active layer of multiple circuit units in a unit row, and the second initial signal line 82 of the third conductive layer is connected to the first area of ​​the seventh active layer in multiple circuit units in a unit row through a via, the second active connection line 20 and the second initial signal line 82 constitute a signal line with a double-layer structure, which can not only ensure that the first areas of multiple seventh active layers in a unit row have the same potential, but also reduce the resistance of the signal line and the voltage drop of the second initial signal, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0225] In an exemplary embodiment, the first reference signal line 91 is connected to the first region of the ninth active layer in each circuit unit through the ninth via V9, thereby realizing that the first reference signal line 91 is connected to the first electrode of the ninth transistor T9, and the first reference signal line 91 can write the first reference signal into the first electrode of the ninth transistor T9.

[0226] In an exemplary embodiment, a first reference connection block 91-1 is provided on one side of the first reference signal line 91 close to the first power connection line 68, a first end of the first reference connection block 91-1 is connected to the first reference signal line 91, a second end of the first reference connection block 91-1 extends toward the direction of the first power connection line 68, and the first reference connection block 91-1 is configured to be connected to a reference signal connection line formed subsequently.

[0227] In an exemplary embodiment, since the first active connection line 10 of the semiconductor layer is directly connected to the first area of ​​the ninth active layer of multiple circuit units in a unit row, and the first reference signal line 91 of the third conductive layer is connected to the first area of ​​the ninth active layer in multiple circuit units in a unit row through a via, the first active connection line 10 and the first reference signal line 91 constitute a signal line with a double-layer structure, which can not only ensure that the first areas of multiple ninth active layers in a unit row have the same potential, but also reduce the resistance of the signal line and the voltage drop of the first reference signal, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0228] In the exemplary embodiment, the first power connection line 68 is connected to the second electrode plate 72 in each circuit unit through the eleventh via hole V11, thereby realizing the connection of the first power connection line 68 to the second electrode plate 72. Since the first power connection line 68 is connected to the first power line formed subsequently, the first power connection line 68 can write the first power signal to the lower electrode plate (the first end of the second storage capacitor) of the second storage capacitor.

[0229] In an exemplary embodiment, a first power connection block 68-1 is provided on the side of the first power connection line 68 away from the fourth scan signal line 64, and a first end of the first power connection block 68-1 is connected to the first power connection line 68, and a second end of the first power connection block 68-1 extends in a direction away from the fourth scan signal line 64, and is connected to the second electrode plate 72 in each circuit unit through an eleventh via V11.

[0230] In an exemplary embodiment, a second power connection block 68 - 2 having a rectangular shape is further provided at the second end of the first power connection block 68 - 1 . The second power connection block 68 - 2 is configured to be connected to a first power line formed subsequently.

[0231] In an exemplary embodiment, the first power connection line 68 , the first power connection block 68 - 1 , and the second power connection block 68 - 2 may be an integral structure connected to each other.

[0232] In an exemplary embodiment, the first shielding electrode 36 may be in a "T" shape, may be located on a side of the first power connection line 68 close to the fourth scan signal line 64, and may be provided in each circuit unit. The "T"-shaped first shielding electrode 36 may include a first extension segment 36-1 and a first shielding segment 36-2, wherein a first end of the first extension segment 36-1 is connected to the first power connection line 68, and a second end of the first extension segment 36-1 is extended toward the fourth scan signal line 64 and connected to the first shielding segment 36-2. The shape of the first shielding segment 36-2 can be a strip extending along the first direction X. For the first shielding end of the first shielding segment 36-2 located on one side of the first extension segment 36-1 in the first direction X and the second shielding end located on one side of the first extension segment 36-1 in the opposite direction of the first direction X, the positive projection of the first shielding end on the substrate overlaps at least partially with the positive projection of the first active layer between the two gate electrodes of the first transistor T1 in the present circuit unit on the substrate, and the positive projection of the second shielding end on the substrate overlaps at least partially with the positive projection of the second active layer between the two gate electrodes of the second transistor T2 in the adjacent circuit unit on the substrate. In an exemplary embodiment, the first shielding electrode 36 is configured to shield the influence of the data voltage jump on the first transistor T1 and the second transistor T2, so as to prevent the data voltage jump from affecting the normal operation of the pixel driving circuit and improve the display effect.

[0233] In an exemplary embodiment, the first power connection line 68 and the first shielding electrode 36 may be an integral structure connected to each other. By providing the first shielding electrode 36 in the third conductive layer and forming an integral structure with the first power connection line 68, and combining the above-mentioned provision of the third electrode plate 73 and the fourth electrode plate 74 as an integral structure, the number of vias can be saved, so that the main body of the first power connection line 68 can be provided to extend along the first direction X, without the need to bend due to avoiding the vias, indirectly reducing the length of the first power connection line 68, and the line width of the first power connection line 68 can be provided to be relatively wide, which helps to reduce the voltage drop of the first power signal during transmission.

[0234] In an exemplary embodiment, the first connection electrode 41 may be in the shape of a strip having a main portion extending along the second direction Y, and may be located between the fourth scan signal line 64 and the first power connection line 68. The first end of the first connection electrode 41 is connected to the second region of the first active layer (also the first region of the second active layer) through the second via hole V2, and the second end of the first connection electrode 41 is connected to the first electrode plate 71 through the tenth via hole V10. In an exemplary embodiment, the first connection electrode 41 enables the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 71 of the first storage capacitor (i.e., the first end of the first storage capacitor) to have the same potential, and the first connection electrode 41 may serve as the first node N1 of the pixel driving circuit.

[0235] In an exemplary embodiment, the second connection electrode 42 may be in the shape of a zigzag line with a main portion extending along the second direction Y, and may be located between the first reference signal line 91 and the first power connection line 68. The first end of the second connection electrode 42 is connected to the second region of the fourth active layer (also the second region of the ninth active layer) through the fourth via hole V4, and the second end of the second connection electrode 42 is connected to the fourth electrode plate 74 through the thirteenth via hole V13. In an exemplary embodiment, the second connection electrode 42 enables the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third electrode plate 73 of the first storage capacitor (i.e., the second end of the first storage capacitor), and the fourth electrode plate 74 of the second storage capacitor (i.e., the second end of the second storage capacitor) to have the same potential, and the second connection electrode 42 may serve as the fifth node N5 of the pixel driving circuit.

[0236] In an exemplary embodiment, the third connection electrode 43 may be rectangular in shape and may be located between the first reference signal line 91 and the first power connection line 68. The third connection electrode 43 is connected to the first region of the fourth active layer through the third via hole V3. In an exemplary embodiment, the third connection electrode 43 may serve as a first electrode of the fourth transistor T4 and is configured to be connected to a subsequently formed data signal line.

[0237] In an exemplary embodiment, the fourth connection electrode 44 may be rectangular in shape and may be located between the fifth scan signal line 65 and the second initial signal line 82. The fourth connection electrode 44 is connected to the first region of the fifth active layer through the fifth via hole V5. In an exemplary embodiment, the fourth connection electrode 44 may serve as a first electrode of the fifth transistor T5 and is configured to be connected to a first power line formed subsequently.

[0238] In an exemplary embodiment, the fifth connection electrode 45 may be in an "L" shape and may be located between the fifth scan signal line 65 and the second initial signal line 82. The fifth connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the sixth via hole V6. In an exemplary embodiment, the fifth connection electrode 45 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and is configured to be connected to an anode connection electrode formed subsequently.

[0239] In an exemplary embodiment, the sixth connection electrode 46 may be in the shape of a strip having a main portion extending along the first direction X, and may be located between the fifth scan signal line 65 and the second initial signal line 82. A first end of the sixth connection electrode 46 is connected to the first region of the eighth active layer through an eighth via hole V8, and a second end of the sixth connection electrode 46 is connected to the second reference connection block 92-1 through a twenty-second via hole V22. In an exemplary embodiment, the sixth connection electrode 46 may serve as a first electrode of the eighth transistor T8. Since the second reference connection block 92-1 is connected to the second reference signal line 92, the second reference signal line 92 is connected to the first electrode of the eighth transistor T8. The second reference signal line 92 in the nth unit row may write the second reference signal into the first electrode of the eighth transistor T8 in the n-1th unit row.

[0240] In an exemplary embodiment, the seventh connection electrode 47 may be in the shape of a bar whose main part extends along the first direction X, and may be located between the fifth scan signal line 65 and the second initial signal line 82. The first end of the seventh connection electrode 47 is connected to the fifth gate electrode 25 through the seventeenth via hole V17, and the second end of the seventh connection electrode 47 is connected to the first light-emitting connection block 31-1 through the twentieth via hole V20. Since the first light-emitting connection block 31-1 is connected to the first light-emitting signal line 31, the first light-emitting signal line 31 is connected to the fifth gate electrode 25 of the fifth transistor T5, and the first light-emitting signal line 31 may control the conduction and disconnection of the fifth transistor T5.

[0241] In an exemplary embodiment, the eighth connection electrode 48 may be in the shape of a strip whose main part extends along the first direction X, and may be located between the fifth scan signal line 65 and the second initial signal line 82. The first end of the eighth connection electrode 48 is connected to the sixth gate electrode 26 through the eighteenth via hole V18, and the second end of the eighth connection electrode 48 is connected to the second light-emitting connection block 32-1 through the twenty-first via hole V21. Since the second light-emitting connection block 32-1 is connected to the second light-emitting signal line 32, the second light-emitting signal line 32 is connected to the sixth gate electrode 26 of the sixth transistor T6, and the second light-emitting signal line 32 can control the conduction and disconnection of the sixth transistor T6.

[0242] In an exemplary embodiment, the ninth connection electrode 49 may be in the shape of a strip having a main portion extending along the first direction X, and may be located between the fifth scan signal line 65 and the second initial signal line 82. A first end of the ninth connection electrode 49 is connected to the first region of the first active layer through a first via hole V1, and a second end of the ninth connection electrode 49 is connected to the first initial connection block 81-1 through a twenty-third via hole V23. Since the first initial connection block 81-1 is connected to the first initial signal line 81, the first initial signal line 81 is connected to the first electrode of the first transistor T1, and the first initial signal line 81 may write the first initial signal to the first electrode of the first transistor T1.

[0243] In an exemplary embodiment, a first electrode plate 71 of a first storage capacitor and a second electrode plate 72 of a second storage capacitor are disposed on a first conductive layer, the first electrode plate 71 has a potential of a first node, and the second electrode plate 72 has a potential of a first power line. A third electrode plate 73 of the first storage capacitor and a fourth electrode plate 74 of the second storage capacitor are disposed on a second conductive layer, the third electrode plate 73 and the fourth electrode plate 74 are an integral structure connected to each other, and the fourth electrode plate 74 is connected to the second electrode of the fourth transistor T4 and the second electrode of the ninth transistor T9 through a second connecting electrode, so that the third electrode plate 73 and the fourth electrode plate 74 of the integral structure have a potential of a fifth node, so that the second end of the first storage capacitor and the second end of the second storage capacitor can be connected without a via hole, which can effectively reduce the number of openings, not only can save the via hole space, help simplify the process, help improve the resolution of the display substrate, but also save the spacing space between the same layer of electrodes, help increase the area of ​​the first storage capacitor and the second storage capacitor, thereby improving the voltage stabilization effect on the first node N1 and the fifth node N5, and improving the yield of the display substrate.

[0244] (16) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern may include: depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer, and providing a plurality of vias in each circuit unit, as shown in FIG. 12 .

[0245] In an exemplary embodiment, the plurality of via holes of each circuit unit in the display substrate includes at least a thirty-first via hole V31 , a thirty-second via hole V32 , a thirty-third via hole V33 , a thirty-fourth via hole V34 , and a thirty-fifth via hole V35 .

[0246] In an exemplary embodiment, the orthographic projection of the thirty-first via hole V31 on the substrate is located within the range of the orthographic projection of the third connecting electrode 43 on the substrate, the fifth insulating layer in the thirty-first via hole V31 is removed to expose the surface of the third connecting electrode 43, and the thirty-first via hole V31 is configured to connect a subsequently formed data signal line to the third connecting electrode 43 through the via hole.

[0247] In an exemplary embodiment, the orthographic projection of the thirty-second via hole V32 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 44 on the substrate, the fifth insulating layer in the thirty-second via hole V32 is removed to expose the surface of the fourth connecting electrode 44, and the thirty-second via hole V32 is configured to connect a subsequently formed first power line to the fourth connecting electrode 44 through the via hole.

[0248] In an exemplary embodiment, the orthographic projection of the thirty-third via hole V33 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 45 on the substrate, the fifth insulating layer in the thirty-third via hole V33 is removed to expose the surface of the fifth connecting electrode 45, and the thirty-third via hole V33 is configured to connect a subsequently formed anode connecting electrode to the fifth connecting electrode 45 through the via hole.

[0249] In an exemplary embodiment, the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the first reference connection block 91-1 of the first reference signal line 91 on the substrate, the fifth insulating layer in the thirty-fourth via V34 is removed to expose the surface of the first reference connection block 91-1, and the thirty-fourth via V34 is configured to connect a subsequently formed reference signal connection line to the first reference connection block 91-1 through the via.

[0250] In an exemplary embodiment, the orthographic projection of the thirty-fifth via V35 on the substrate is located within the range of the orthographic projection of the second power connection block 68-2 of the first power connection line 68 on the substrate, the fifth insulating layer in the thirty-fifth via V35 is removed to expose the surface of the second power connection block 68-2, and the thirty-fifth via V35 is configured to connect the subsequently formed first power line to the second power connection block 68-2 through the via.

[0251] In an exemplary embodiment, at least one circuit unit may further include a thirty-sixth via hole V36. The orthographic projection of the thirty-sixth via hole V36 on the substrate is located within the range of the orthographic projection of the second initial connection block 82-1 of the second initial signal line 82 on the substrate, the fifth insulating layer in the thirty-sixth via hole V36 is removed, exposing the surface of the second initial connection block 82-1, and the thirty-sixth via hole V36 is configured to connect the second initial connection line formed subsequently to the second initial connection block 82-1 through the via hole.

[0252] In exemplary embodiments, the thirty-sixth via hole V36 may be located between the first circuit unit and the second circuit unit.

[0253] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the fifth insulating layer, as shown in FIGS. 13A and 13B , where FIG. 13B is a schematic diagram of the fourth conductive layer in FIG. 13A . In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0254] In an exemplary embodiment, the fourth conductive layer patterns of the plurality of circuit units in the display substrate may each include: a first power supply line 51 , a data signal line 53 , a reference signal connection line 54 , and an anode connection electrode 55 .

[0255] In an exemplary embodiment, the shape of the first power line 51, the data signal line 53 and the reference signal connection line 54 can be a strip shape with the main part extending along the second direction Y, the first power line 51 can be located on one side of the data signal line 53 in the first direction X, and the reference signal connection line 54 can be located on one side of the first power line 51 in the first direction X, that is, the first power line 51 can be located between the data signal line 53 and the reference signal connection line 54.

[0256] In an exemplary embodiment, the first power line 51 may be in the shape of a zigzag line with the main body extending along the second direction Y. The first power line 51 is connected to the fourth connection electrode 44 through the thirty-second via hole V32 on one hand, and is connected to the second power connection block 68-2 through the thirty-fifth via hole V35 on the other hand. Since the fourth connection electrode 44 is connected to the first region of the fifth active layer through the fifth via hole V5, the first power line 51 writes the first power signal into the first electrode of the fifth transistor T5. Since the second power connection block 68-2 is connected to the first power connection block 68-1, and the first power connection block 68-1 is connected to the first power connection line 68, the first power connection line 68 extending along the first direction X of the main part and the first power line 51 extending along the second direction Y of the main part are connected to each other, so that the first power line 51 and the first power connection line 68 form a mesh structure for transmitting the first power signal on the display substrate, which can not only effectively reduce the resistance of the first power line 51 and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0257] In an exemplary embodiment, a power shielding block 51-1 is provided on one side of the first power line 51 close to the reference signal connection line 54, a first end of the power shielding block 51-1 is connected to the first power line 51, and a second end of the power shielding block 51-1 extends in the direction of the reference signal connection line 54. The shape of the power shielding block 51-1 may be rectangular, and the positive projection of the power shielding block 51-1 on the substrate at least partially overlaps with the positive projection of the first connection electrode 41 on the substrate. Since the first connection electrode 41 serves as the first node N1 in the pixel driving circuit, the power shielding block 51-1 with a constant voltage can effectively shield the influence of other signals in the pixel driving circuit on the first node N1, thereby preventing other signals (such as data voltage jump) from affecting the potential of the first node N1 of the pixel driving circuit, thereby improving the display effect.

[0258] In an exemplary embodiment, the first power line 51 and the power shielding block 51 - 1 may be an integral structure connected to each other.

[0259] In an exemplary embodiment, the orthographic projection of the power shielding block 51 - 1 on the substrate may include the orthographic projection of the first connection electrode 41 on the substrate.

[0260] In an exemplary embodiment, the orthographic projection of the first power line 51 on the substrate at least partially overlaps with the orthographic projection of the second connection electrode 42 on the substrate. Since the second connection electrode 42 serves as the fifth node N5 in the pixel driving circuit, the first power line 51 with a constant voltage can effectively shield the influence of other signals in the pixel driving circuit on the fifth node N5, thereby preventing other signals from affecting the potential of the fifth node N5 of the pixel driving circuit and improving the display effect.

[0261] In an exemplary embodiment, the first power lines 51 may be designed with unequal widths. The unequal width design of the first power lines 51 may not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between the first power lines and the data signal lines.

[0262] In an exemplary embodiment, the data signal line 53 may be in the shape of a straight line with a main portion extending along the second direction Y, and the data signal line 53 is connected to the third connection electrode 43 through the thirty-first via hole V31. Since the third connection electrode 43 is connected to the first region of the fourth active layer through the third via hole V3, the data signal line 53 writes the data signal into the first electrode of the fourth transistor T4.

[0263] In an exemplary embodiment, the reference signal connection line 54 may be in the shape of a straight line with the main body extending along the second direction Y, and the reference signal connection line 54 is connected to the first reference connection block 91-1 through the thirty-fourth via hole V34. Since the first reference connection block 91-1 is connected to the first reference signal line 91, the first reference signal line 91 with the main body extending along the first direction X and the reference signal connection line 54 with the main body extending along the second direction Y are connected to each other, so that the first reference signal line 91 and the reference signal connection line 54 form a mesh structure for transmitting the first reference signal on the display substrate, which can not only effectively reduce the resistance of the first reference signal line and reduce the voltage drop of the first reference signal, but also effectively improve the uniformity of the first reference signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0264] In an exemplary embodiment, the shape of the anode connection electrode 55 may be rectangular, and the anode connection electrode 55 is connected to the fifth connection electrode 45 through the thirty-third via hole V33. Since the fifth connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the sixth via hole V6, the anode connection electrode 55 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In an exemplary embodiment, the anode connection electrode 55 is configured to be connected to the anode formed subsequently, so that the pixel driving circuit can drive the light-emitting device.

[0265] In an exemplary embodiment, at least one circuit unit may further include a second initial connection line 56. The second initial connection line 56 may be in the shape of a straight line extending along the second direction Y in the main part, and the second initial connection line 56 is connected to the second initial connection block 82-1 through the thirty-sixth via V36. Since the second initial connection block 82-1 is connected to the second initial signal line 82, the second initial signal line 82 extending along the first direction X in the main part and the second initial connection line 56 extending along the second direction Y in the main part are connected to each other, so that the second initial signal line 82 and the second initial connection line 56 form a mesh structure for transmitting the second initial signal on the display substrate, which can not only effectively reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal, but also effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality. In an exemplary embodiment, the second initial connection line 56 may be located between the reference signal connection line 54 of the first circuit unit and the data signal line 53 of the second circuit unit.

[0266] In an exemplary embodiment, the first power connection line 68 of the third conductive layer can be arranged in each unit row, and the first power line 51 of the fourth conductive layer can be arranged in each unit column. Multiple first power lines 51 are respectively connected to multiple first power connection lines 68 to form a mesh structure for transmitting the first power signal.

[0267] In an exemplary embodiment, the first reference signal line 91 of the third conductive layer can be arranged in each unit row, and the reference signal connection line 54 of the fourth conductive layer can be arranged in each unit column, and multiple first reference signal lines 91 are respectively connected to multiple reference signal connection lines 54 to form a mesh structure for transmitting the first reference signal.

[0268] In an exemplary embodiment, the second initial signal line 82 of the third conductive layer can be arranged in each unit row, and the second initial connection line 56 of the fourth conductive layer can be arranged every two unit columns, and the multiple second initial connection lines 56 are respectively connected to the multiple second initial signal lines 82 to form a mesh structure for transmitting the second initial signal.

[0269] The subsequent preparation process may include forming a first flat layer pattern, a plurality of anode vias are arranged on the first flat layer, the orthographic projection of the anode vias on the substrate is located within the range of the orthographic projection of the anode connecting electrode on the substrate, the first flat layer in the anode vias is removed to expose the surface of the anode connecting electrode, and the anode vias are configured to connect the subsequently formed anode to the anode connecting electrode through the vias.

[0270] At this point, the driving circuit layer of this embodiment is prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units, each of which may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a fourth scanning signal line, a fifth scanning signal line, a first light-emitting signal line, a second light-emitting signal line, a first initial signal line, a second initial signal line, a first reference signal line, a second reference signal line, a first power supply line, and a data signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include at least a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, and a fourth conductive layer stacked sequentially on the substrate. The first active connection line 10, the second active connection line 20, and the active layer of the first transistor T1 to the ninth transistor T9 can be arranged in the semiconductor layer, the first gate electrode 21, the second gate electrode 22, the fourth gate electrode 24, the fifth gate electrode 25, the sixth gate electrode 26, the ninth gate electrode 29, the first scanning signal line 61, the first electrode plate 71 and the second electrode plate 72 can be arranged in the first conductive layer, the first light-emitting signal line 31, the second light-emitting signal line 32, the repair line 33, the second shielding electrode 37, the third shielding electrode 38, the third electrode plate 73, the fourth electrode plate 74, the first The initial signal line 81 and the second reference signal line 92 can be set in the second conductive layer, the first shielding electrode 36, the first connecting electrode 41 to the ninth connecting electrode 49, the second scanning signal line 62, the third scanning signal line 63, the fourth scanning signal line 64, the fifth scanning signal line 65, the first power connection line 68, the second initial signal line 82, and the first reference signal line 91 can be set in the third conductive layer, and the first power line 51, the data signal line 53, the reference signal connection line 54, the anode connection electrode 55 and the second initial connection line 56 can be set in the fourth conductive layer.

[0271] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer and a packaging structure layer may be sequentially prepared on the driving circuit layer, which will not be described in detail herein.

[0272] Figure 14 is a schematic diagram of the planar structure of another display substrate of an exemplary embodiment of the present disclosure, illustrating the structure of the pixel driving circuit in three circuit units (a first circuit unit, a second circuit unit and a third circuit unit) in the display substrate, and Figure 15 is a schematic diagram of the structure of the first storage capacitor and the second storage capacitor area in Figure 14. As shown in Figures 14 and 15, the main structure of the pixel driving circuit of this exemplary embodiment is basically the same as that of the aforementioned embodiment, except that a second power line and a second power connection line are provided in this embodiment, and the second power connection line is connected to the first shielding electrode.

[0273] As shown in FIG. 14 , in an exemplary embodiment, the display substrate may further include at least one second power line 52 extending along the second direction Y and at least one second power connection line 69 extending along the first direction X. In an exemplary embodiment, the second power line 52 is connected to the cathodes of the plurality of light emitting units, and the second power line 52 is configured to continuously provide a low level signal to the cathodes. In an exemplary embodiment, the second power line 52 extending along the second direction Y and the second power connection line 69 extending along the first direction X are connected to each other to form a mesh structure for transmitting a second power signal.

[0274] In an exemplary embodiment, on a plane perpendicular to the display substrate, the driving circuit layer may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate. The second power line 52 and the second power connection line 69 may be disposed in different conductive layers, and the second power line 52 and the second power connection line 69 may be connected through a via.

[0275] In an exemplary embodiment, the first shielding electrode 36 and the second power connection line 69 may be disposed in the same layer and simultaneously formed through the same patterning process.

[0276] In an exemplary embodiment, the second power connection line 69 may be disposed in the third conductive layer, and the second power line 52 may be disposed in the fourth conductive layer.

[0277] As shown in Figures 14 and 15, in an exemplary embodiment, the orthographic projection of the first power connection line 68 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate 74 on the substrate, and the orthographic projection of the second power connection line 69 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 73 on the substrate.

[0278] In an exemplary embodiment, the first shielding electrode 36 may include a first extension segment 36-1 and a first shielding segment 36-2. The first extension segment 36-1 is in the shape of a strip extending along the second direction Y, and the first shielding segment 36-2 is in the shape of a strip extending along the first direction X. The first end of the first extension segment 36-1 is connected to the second power connection line 69, and the second end of the first extension segment 36-1 is connected to the first shielding segment 36-2; the first shielding segment 36-2 includes a first shielding end and a second shielding end, and the orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first transistor T1 in the present circuit unit on the substrate, and the orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the second transistor T2 in the adjacent circuit unit on the substrate.

[0279] In an exemplary embodiment, the first shielding electrode 36 and the second power connection line 69 are an integral structure connected to each other.

[0280] The positions and connection relationships of the remaining structures are substantially the same as those in the aforementioned embodiment and will not be described in detail here.

[0281] In an exemplary embodiment, this embodiment shows that the substrate preparation process may include the following operations.

[0282] (21) sequentially forming a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer and a fourth insulating layer pattern, wherein the semiconductor layer may include at least the first active layer 11 of the first transistor T1 to the ninth active layer 19 of the ninth transistor T9, and the first conductive layer pattern may include at least the first gate electrode 21, the second gate electrode 22, the fourth gate electrode 24, the fifth gate electrode 25, the sixth gate electrode 26, the ninth gate electrode 29, the first scan signal line 61, the first plate 71 of the first storage capacitor and the first plate 72 of the second storage capacitor. The second electrode 72, the second conductive layer pattern at least includes the first light-emitting signal line 31, the second light-emitting signal line 32, the repair line 33, the second shielding electrode 37, the third shielding electrode 38, the third electrode 73 of the first storage capacitor, the fourth electrode 74 of the second storage capacitor and the second reference signal line 92, and the multiple vias on the fourth insulating layer include at least: the first via V1 to the eleventh via V11, the thirteenth via V13 to the twenty-third via V23. The position, structure and connection relationship of the above patterns are basically the same as those in the aforementioned embodiment and will not be repeated here.

[0283] (22) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as shown in FIGS. 16A and 16B, wherein FIG. 16B is a schematic diagram of the third conductive layer in FIG. 16A.

[0284] In an exemplary embodiment, the third conductive layer patterns of multiple circuit units in the display substrate may include: a first shielding electrode 36, a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a sixth connecting electrode 46, a seventh connecting electrode 47, an eighth connecting electrode 48, a ninth connecting electrode 49, a second scanning signal line 62, a third scanning signal line 63, a fourth scanning signal line 64, a fifth scanning signal line 65, a first power connection line 68, a second power connection line 69, a second initial signal line 82 and a first reference signal line 91.

[0285] In the exemplary embodiment, the third conductive layer pattern in this embodiment is different from the previous embodiment in that the first shielding electrode 36, the first power connection line 68 and the second power connection line 69. The positions, structures and connection relationships of the remaining patterns are substantially the same as those in the previous embodiment and are not described in detail here.

[0286] In an exemplary embodiment, the first power connection line 68 can be located above the fourth electrode plate 74, and the orthographic projection of the first power connection line 68 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate 74 on the substrate. The first power connection line 68 is configured to be connected to the subsequently formed first power line to form a high-voltage power grid structure with a mesh-like interconnected structure on the display substrate.

[0287] In an exemplary embodiment, the first power connection line 68 is connected to the second electrode plate 72 in each circuit unit through the eleventh via hole V11, thereby realizing the connection of the first power connection line 68 to the second electrode plate 72. Since the first power connection line 68 is connected to the first power line formed subsequently, the first power connection line 68 can write the first power signal to the lower electrode plate of the second storage capacitor (the first end of the second storage capacitor). In this embodiment, since the first power connection line 68 is arranged above the fourth electrode plate 74, the first power connection line 68 can be directly connected to the second electrode plate 72 in each circuit unit through the eleventh via hole V11. Therefore, in this embodiment, the first power connection block 68-1 and the second power connection block 68-2 in the aforementioned embodiment can be removed, the structure of the first power connection line 68 is simplified, and the size of the first power connection line 68 along the second direction Y is larger, which helps to reduce the voltage drop on the first power connection line 68.

[0288] In an exemplary embodiment, the second power connection line 69 can be located above the third electrode plate 73, and the orthographic projection of the second power connection line 69 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 73 on the substrate, and the second power connection line 69 is configured to be connected to a subsequently formed second power line to form a low-voltage power grid structure with a mesh-like interconnected structure on the display substrate.

[0289] In an exemplary embodiment, in at least one circuit unit, a third power connection block 69-1 is provided on a side of the second power connection line 69 away from the first power connection line 68, a first end of the third power connection block 69-1 is connected to the second power connection line 69, a second end of the third power connection block 69-1 extends in a direction away from the first power connection line 68, and the third power connection block 69-1 is configured to be connected to a second power line formed subsequently. In an exemplary embodiment, the third power connection block 69-1 may be provided between the first circuit unit and the second circuit unit.

[0290] In an exemplary embodiment, the first shielding electrode 36 may be in a "T" shape and may be located on a side of the second power connection line 69 close to the fourth scan signal line 64. The first shielding electrode 36 may be provided in each circuit unit. The "T"-shaped first shielding electrode 36 may include a first extension segment 36-1 and a first shielding segment 36-2, wherein a first end of the first extension segment 36-1 is connected to the second power connection line 69, and a second end of the first extension segment 36-1 is extended toward the fourth scan signal line 64 and then connected to the first shielding segment 36-2. The shape of the first shielding segment 36-2 can be a strip extending along the first direction X. For the first shielding end of the first shielding segment 36-2 located on one side of the first extension segment 36-1 in the first direction X and the second shielding end located on one side of the first extension segment 36-1 in the opposite direction of the first direction X, the positive projection of the first shielding end on the substrate overlaps at least partially with the positive projection of the first active layer between the two gate electrodes of the first transistor T1 in the present circuit unit on the substrate, and the positive projection of the second shielding end on the substrate overlaps at least partially with the positive projection of the second active layer between the two gate electrodes of the second transistor T2 in the adjacent circuit unit on the substrate. In an exemplary embodiment, the first shielding electrode 36 is configured to shield the influence of the data voltage jump on the first transistor T1 and the second transistor T2, so as to prevent the data voltage jump from affecting the normal operation of the pixel driving circuit and improve the display effect.

[0291] In an exemplary embodiment, the second power connection line 69 and the first shielding electrode 36 may be an integral structure connected to each other.

[0292] In this embodiment, by setting the second power connection line 69 on the third conductive layer, a second power signal line extending along the first direction X on the display substrate is realized, the area of ​​the second power signal line on the display substrate is increased, and it helps to reduce the voltage drop of the second power signal during transmission.

[0293] (23) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern may include: depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer, and providing a plurality of vias in each circuit unit, as shown in FIG. 17 .

[0294] In an exemplary embodiment, the plurality of vias of each circuit unit in the display substrate includes at least a thirty-first via V31, a thirty-second via V32, a thirty-third via V33, a thirty-fourth via V34, and a thirty-fifth via V35. The positions, structures, and connection relationships of the thirty-first via V31 to the thirty-fourth via V34 are substantially the same as those in the aforementioned embodiment, and are not described in detail herein.

[0295] In an exemplary embodiment, the orthographic projection of the thirty-fifth via V35 on the substrate is within the range of the orthographic projection of the first power connection line 68 on the substrate, the fifth insulating layer in the thirty-fifth via V35 is removed to expose the surface of the first power connection line 68, and the thirty-fifth via V35 is configured to connect a subsequently formed first power connection line to the first power connection line 68 through the via.

[0296] In an exemplary embodiment, at least one circuit unit may also include a thirty-seventh via V37, the orthographic projection of the thirty-seventh via V37 on the substrate being located within the range of the orthographic projection of the third power connection block 69-1 of the second power connection line 69 on the substrate, the fifth insulating layer in the thirty-seventh via V37 being removed to expose the surface of the third power connection block 69-1, and the thirty-seventh via V37 being configured to connect the subsequently formed second power line to the third power connection block 69-1 through the via.

[0297] In exemplary embodiments, the thirty-seventh via hole V37 may be located between the first circuit unit and the second circuit unit.

[0298] (24) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the fifth insulating layer, as shown in FIGS. 18A and 18B , where FIG. 18B is a schematic diagram of the fourth conductive layer in FIG. 18A .

[0299] In an exemplary embodiment, the fourth conductive layer patterns of multiple circuit units in the display substrate may include: a first power line 51, a data signal line 53, a reference signal connection line 54 and an anode connection electrode 55. The positions, structures and connection relationships of the above patterns are basically the same as those in the previous embodiments and will not be repeated here.

[0300] In an exemplary embodiment, at least one circuit unit may further include a second power line 52. The second power line 52 may be in the shape of a straight line extending along the second direction Y in the main body, and the second power line 52 is connected to the third power connection block 69-1 through the thirty-seventh via V37, thereby realizing the mutual connection between the second power connection line 69 extending along the first direction X in the main body and the second power line 52 extending along the second direction Y in the main body, so that the second power line 52 and the second power connection line 69 form a mesh structure for transmitting the second power signal on the display substrate, which can not only effectively reduce the resistance of the second power line 52 and reduce the voltage drop of the second power signal, but also effectively improve the uniformity of the second power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality. In an exemplary embodiment, the second power line 52 may be located between the first circuit unit and the second circuit unit.

[0301] In an exemplary embodiment, the second power connection line 69 of the third conductive layer can be arranged in each unit row, and the second power line 52 of the fourth conductive layer can be arranged every two unit columns, and the plurality of second power lines 52 are respectively connected to the plurality of second power connection lines 69 to form a mesh structure for transmitting the second power signal. By adding the second power lines and the second power connection lines 69 to the display substrate, the space utilization rate of the display substrate is higher.

[0302] The subsequent preparation process may include forming a first flat layer pattern, on which a plurality of anode vias are arranged, the orthographic projections of the anode vias on the substrate are located within the range of the orthographic projections of the anode connecting electrode 55 on the substrate, the first flat layer in the anode vias being removed to expose the surface of the anode connecting electrode 55, and the anode vias being configured to connect a subsequently formed anode to the anode connecting electrode 55 through the vias.

[0303] At this point, the driving circuit layer of this embodiment is prepared on the substrate. In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer and a packaging structure layer can be sequentially prepared on the driving circuit layer, which will not be described in detail here.

[0304] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked, and the materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer may be amorphous silicon (a-si).

[0305] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer. The first insulating layer is called a buffer layer, the second insulating layer and the third insulating layer are called gate insulating (GI) layers, the fourth insulating layer is called an interlayer insulating (ILD) layer, and the fifth insulating layer is called a passivation (PVX) layer. The first planar layer can be made of an organic material, such as a resin, etc. The active layer can be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene and the like, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.

[0306] In a display substrate, the third plate of the first storage capacitor serves as the second end of the first storage capacitor, and the second plate of the second storage capacitor serves as the second end of the second storage capacitor, so that the second plate and the third plate need to be punched to achieve connection, which not only reduces the plate area of ​​the first storage capacitor and the second storage capacitor, but also has the problem of low space utilization of the display substrate. In addition, the line width of the first power connection line of the display substrate is small, resulting in a large voltage drop of the first power signal.

[0307] In the disclosed embodiment, the third electrode plate of the first storage capacitor is set as the second end of the first storage capacitor, and the fourth electrode plate of the second storage capacitor is set as the second end of the second storage capacitor. The third electrode plate in the first storage capacitor and the fourth electrode plate in the second storage capacitor are an integrated structure connected to each other, so that the second end of the first storage capacitor and the second end of the second storage capacitor can be connected without setting a via, which can effectively reduce the number of openings, not only saving via space, but also helping to simplify the process and improve the resolution of the display substrate, but also saving the spacing space between the electrodes on the same layer, helping to increase the area of ​​the first storage capacitor and the second storage capacitor, thereby improving the voltage stabilization effect on the first node N1 and the fifth node N5, and improving the yield of the display substrate.

[0308] The embodiment of the present disclosure rearranges the connection mode between the first storage capacitor and the second storage capacitor so that the first power connection line can extend along the first direction X and the line width can be set wider, thereby reducing the voltage drop of the first power signal and improving the display quality.

[0309] In the embodiment of the present disclosure, a first power connection line extending along a first direction X of the main part and a first power line extending along a second direction Y of the main part are arranged, and the first power lines are connected to each other, so that the first power lines and the first power connection lines form a mesh structure for transmitting a first power signal on a display substrate, which can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0310] The disclosed embodiment re-arranges the connection mode between the first storage capacitor and the second storage capacitor, and arranges the first power connection line above the second storage capacitor, thereby arranging the second power connection line above the first storage capacitor, thereby adding a line for transmitting the second power signal on the display substrate, so that the transmission line of the second power signal has a larger area on the display substrate, which can effectively reduce the resistance of the second power line and the voltage drop of the second power signal. Especially for a display substrate with a larger size, the power consumption of the display substrate can be greatly reduced by reducing the voltage drop of the second power signal.

[0311] In the embodiment of the present disclosure, a second power connection line extending along the first direction X of the main part and a second power line extending along the second direction Y of the main part are arranged, and the second power lines are connected to each other, so that the second power lines and the second power connection lines form a mesh structure for transmitting the second power signal on the display substrate, which can not only effectively reduce the resistance of the second power signal line and reduce the voltage drop of the second power signal, but also effectively improve the uniformity of the second power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0312] In the embodiment of the present disclosure, a first reference signal line extending along a first direction X in the main part and a reference signal connection line extending along a second direction Y in the main part are provided, and the first reference signal line and the reference signal connection line are connected to each other, so that the first reference signal line and the reference signal connection line form a mesh structure for transmitting the first reference signal on the display substrate, which can not only effectively reduce the resistance of the first reference signal line and reduce the voltage drop of the first reference signal, but also effectively improve the uniformity of the first reference signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0313] In the embodiment of the present disclosure, a second initial signal line extending in the first direction X of the main part and an initial connection line extending in the second direction Y of the main part are arranged, and the second initial signal line and the initial connection line are connected to each other, so that the second initial signal line and the initial connection line form a mesh structure for transmitting the second initial signal on the display substrate, which can not only effectively reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal, but also effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0314] The embodiment of the present disclosure can shield the influence of data voltage jump on the first transistor T1, the second transistor T2, the fourth transistor T4, the ninth transistor T9 and the fifth node N5 by setting the first shielding electrode, the second shielding electrode and the third shielding electrode, so as to prevent the data voltage jump from affecting the normal operation of the pixel driving circuit and improve the display effect.

[0315] The embodiment of the present disclosure provides a power shielding block, which can effectively shield the influence of other signals in the pixel driving circuit on the first node N1, thereby preventing other signals from affecting the potential of the first node N1 of the pixel driving circuit and improving the display effect.

[0316] The preparation process disclosed in the present invention is well compatible with the existing preparation process, and the process is simple to realize, easy to implement, has high production efficiency, low production cost and high yield rate.

[0317] The structure and preparation process shown above in the present disclosure are merely exemplary. In an exemplary embodiment, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0318] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0319] The present disclosure also provides a method for preparing a display substrate, so as to prepare the display substrate provided by the above embodiment.

[0320] In an exemplary embodiment, the display substrate includes a plurality of circuit units, at least one circuit unit includes a pixel driving circuit, the pixel driving circuit includes at least a first storage capacitor and a second storage capacitor, the first storage capacitor includes at least two first capacitor plates, the orthographic projections of the two first capacitor plates on the substrate at least partially overlap, and the second storage capacitor includes at least two second capacitor plates, the orthographic projections of the two second capacitor plates on the substrate at least partially overlap; the manufacturing method of the display substrate may include:

[0321] A plurality of conductive layers are formed on a substrate, a first capacitor plate in the first storage capacitor and a second capacitor plate in the second storage capacitor are arranged in the same conductive layer, another first capacitor plate in the first storage capacitor and another second capacitor plate in the second storage capacitor are arranged in the same conductive layer, and a first capacitor plate in the first storage capacitor and a second capacitor plate in the second storage capacitor are connected to each other.

[0322] The present disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., but the embodiments of the present invention are not limited thereto.

[0323] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present invention. Any technician in the relevant field can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the patent protection scope of the present invention shall still be subject to the scope defined by the attached claims.

Claims

A display substrate comprises a plurality of circuit units, at least one of which comprises a pixel driving circuit, wherein the pixel driving circuit comprises at least a first storage capacitor and a second storage capacitor, wherein the first storage capacitor comprises at least two first capacitor plates, and the orthographic projections of the two first capacitor plates on the substrate at least partially overlap, and the second storage capacitor comprises at least two second capacitor plates, and the orthographic projections of the two second capacitor plates on the substrate at least partially overlap; on a plane perpendicular to the display substrate, the display substrate comprises a plurality of conductive layers, wherein a first capacitor plate in the first storage capacitor and a second capacitor plate in the second storage capacitor are arranged in the same conductive layer, another first capacitor plate in the first storage capacitor and another second capacitor plate in the second storage capacitor are arranged in the same conductive layer, and a first capacitor plate in the first storage capacitor and a second capacitor plate in the second storage capacitor are connected to each other. The display substrate according to claim 1, wherein: The multiple conductive layers include at least a first conductive layer and a second conductive layer sequentially arranged on the substrate; the at least two first capacitor plates include a first plate and a third plate, the first plate is arranged in the first conductive layer, the third plate is arranged in the second conductive layer, and the orthographic projection of the first plate on the substrate at least partially overlaps with the orthographic projection of the third plate on the substrate; the at least two second capacitor plates include a second plate and a fourth plate, the second plate is arranged in the first conductive layer, the fourth plate is arranged in the second conductive layer, the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate, and the third plate is connected to the fourth plate. The display substrate according to claim 2, wherein: The third electrode plate of the first storage capacitor and the fourth electrode plate of the second storage capacitor are an integrated structure connected to each other. The display substrate according to claim 2, wherein: The pixel driving circuit also includes a first initialization transistor, a compensation transistor, a data writing transistor and a first reference transistor of a dual-gate structure, wherein the first electrode of the first initialization transistor is connected to the first initial signal line, the second electrode of the first initialization transistor is respectively connected to the first electrode and the first electrode plate of the data writing transistor, the first electrode of the data writing transistor is connected to the data signal line, the second electrode of the data writing transistor is respectively connected to the second electrode, the third electrode plate and the fourth electrode plate of the first reference transistor, and the first electrode of the first reference transistor is connected to the first reference signal line. The display substrate according to claim 4, wherein: At least one circuit unit also includes a first shielding electrode, wherein an orthographic projection of the first shielding electrode on the substrate at least partially overlaps with an orthographic projection of a node between two gate electrodes of the first initialization transistor on the substrate, and an orthographic projection of the first shielding electrode on the substrate at least partially overlaps with an orthographic projection of a node between two gate electrodes of the compensation transistor on the substrate. The display substrate according to claim 5, wherein: The display substrate also includes at least one first power connection line extending along a first direction and at least one first power line extending along a second direction, and the first direction intersects with the second direction; the first power line and the first power connection line are arranged in different conductive layers, the first power line and the first power connection line are connected with each other through a via to form a mesh structure for transmitting a first power signal, and the first shielding electrode is connected to the first power connection line. The display substrate according to claim 6, wherein: The first shielding electrode includes a first extension segment and a first shielding segment; the first extension segment is in the shape of a strip extending along the second direction, and the first shielding segment is in the shape of a strip extending along the first direction; the first end of the first extension segment is connected to the first power connection line, and the second end of the first extension segment is connected to the first shielding segment; the first shielding segment includes a first shielding end and a second shielding end, the orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first initialization transistor in the present circuit unit on the substrate, and the orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the compensation transistor in the adjacent circuit unit on the substrate. The display substrate according to claim 6, wherein: The first shielding electrode and the first power connection line are an integrated structure connected to each other. The display substrate according to claim 6, wherein: The orthographic projection of the first power connection line on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate on the substrate. The display substrate according to claim 5, wherein: The display substrate also includes at least one second power connection line extending along a first direction and at least one second power line extending along a second direction, the first direction intersects with the second direction; the second power line and the second power connection line are arranged in different conductive layers, the second power line and the second power connection line are connected with each other through a via to form a mesh structure for transmitting a second power signal, and the first shielding electrode is connected with the second power connection line. The display substrate according to claim 10, wherein: The first shielding electrode includes a first extension segment and a first shielding segment; the first extension segment is in the shape of a strip extending along the second direction, and the first shielding segment is in the shape of a strip extending along the first direction; the first end of the first extension segment is connected to the second power supply connection line, and the second end of the first extension segment is connected to the first shielding segment; the first shielding segment includes a first shielding end and a second shielding end, the orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first initialization transistor in the present circuit unit on the substrate, and the orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the compensation transistor in the adjacent circuit unit on the substrate. The display substrate according to claim 10, wherein: The first shielding electrode and the second power connection line are an integrated structure connected to each other. The display substrate according to claim 10, wherein: The orthographic projection of the second power connection line on the substrate at least partially overlaps with the orthographic projection of the third electrode plate on the substrate. The display substrate according to claim 4, wherein: At least one circuit unit further includes a second shielding electrode, an orthographic projection of the second shielding electrode on the substrate at least partially overlapping an orthographic projection of a node between two gate electrodes of the data writing transistor on the substrate. The display substrate according to claim 4, wherein: At least one circuit unit further includes a third shielding electrode, wherein an orthographic projection of the third shielding electrode on the substrate at least partially overlaps an orthographic projection of a node between two gate electrodes of the first reference transistor on the substrate. The display substrate according to any one of claims 1 to 15, wherein: The display substrate also includes at least one reference signal connection line extending along a first direction and at least one reference signal line extending along a second direction, and the first direction intersects with the second direction; the reference signal line and the reference signal connection line are arranged in different conductive layers, and the reference signal connection line is connected to the reference signal line through a via to form a mesh structure for transmitting a reference signal. The display substrate according to any one of claims 1 to 15, wherein: The display substrate also includes at least one initial signal line extending along a first direction and at least one initial connection line extending along a second direction, the first direction intersecting the second direction; the initial signal line and the initial connection line are arranged in different conductive layers, and the initial connection line is connected to the initial signal line through a via to form a mesh structure for transmitting the initial signal. A display device comprising the display substrate according to any one of claims 1 to 17. A method for preparing a display substrate, the display substrate comprising a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a first storage capacitor and a second storage capacitor, the first storage capacitor comprising at least two first capacitor plates, the orthographic projections of the two first capacitor plates on a substrate at least partially overlapping, the second storage capacitor comprising at least two second capacitor plates, the orthographic projections of the two second capacitor plates on the substrate at least partially overlapping; the preparation method comprising: A plurality of conductive layers are formed on a substrate, a first capacitor plate in the first storage capacitor and a second capacitor plate in the second storage capacitor are arranged in the same conductive layer, another first capacitor plate in the first storage capacitor and another second capacitor plate in the second storage capacitor are arranged in the same conductive layer, and a first capacitor plate in the first storage capacitor and a second capacitor plate in the second storage capacitor are connected to each other.

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