Wafer acceptance test method
By introducing global variables in wafer storage test and reusing the empty pin capacitance value, the problem of large proportion of hollow pin capacitance test time in traditional capacitor parameter test is solved, and the saving of capacitance test time and improvement of test efficiency is achieved.
Patent Information
- Application Number
- CN202510060380.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-14
- Publication Date
- 2025-05-06
AI Technical Summary
In traditional WAT capacitor parameter testing, the time spent testing empty pin capacitors accounts for a considerable proportion of the total test time, resulting in a waste of testing costs.
Introduce the global variables of the wafer to be tested in the test item, and obtain the total capacitance value and empty pin capacitance value of the first wafer to be tested in the first test. Then, under the same conditions, the empty pin capacitance needs to be tested only once, and the empty pin capacitance value is repeatedly used to obtain the actual capacitance value of the wafer to be tested.
By reducing the number of empty-pin capacitor tests, capacitance testing time is saved, testing efficiency is improved, and testing cost is reduced.
Smart Images
Figure CN119936621A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor wafer acceptance testing, and in particular to a wafer acceptance testing method. Background Art
[0002] In the WAT test (Wafer Acceptance Test), when testing the capacitance parameters of the wafer, since the probe card usually has an empty probe capacitance, the actual capacitance value of the wafer is equal to the total capacitance value measured on the wafer minus the empty probe capacitance value.
[0003] During the entire capacitance parameter test process, refer to Figure 1 , Figure 1 This is a schematic diagram of the traditional capacitance parameter test process. Before measuring the capacitance, in the initial state, the probe 30 connected to the needle card 20 is usually already stuck on the wafer 10. At this time, if you need to test the empty needle capacitance, you need to lift the needle (the time of lifting the needle is usually 0.1s) + test the empty needle capacitance (the time of testing the empty needle capacitance is usually 0.2s) + press the needle (the time of pressing the needle is usually 0.1s) + test the total capacitance (the time of testing the total capacitance is usually 0.2s), so the traditional capacitance parameter test takes about 0.6s in total. From the above-mentioned entire capacitance parameter test process, it can be found that the time spent on testing the empty needle capacitance accounts for a considerable proportion of the total test time, resulting in a waste of test costs, so a new wafer acceptance test method is urgently needed to reduce the capacitance test time. Summary of the invention
[0004] The present application provides a wafer acceptance test method, which can solve the problem that in the traditional WAT capacitor parameter test, the time spent on testing the empty needle capacitor accounts for a considerable proportion of the total test time, resulting in a waste of test costs.
[0005] The present application provides a wafer acceptance test method, including: Step 1: introducing a global variable of the wafer to be tested in the test item, and writing a default value in a specified address associated with the global variable in the memory, wherein the information of the global variable includes at least: a test batch number, a wafer number, a test probe number, and a test frequency; Step 2: Performing an electrical parameter test on the wafer to be tested to obtain a total capacitance value of the wafer to be tested and an empty pin capacitance value corresponding to the global variable; Step 3: obtaining the final actual capacitance value of the wafer to be tested according to the total capacitance value of the wafer to be tested and the empty needle capacitance value, and writing the empty needle capacitance value obtained in the step 2 into the designated address; Step 4: Obtain the information of the global variables of other wafers to be tested. If the information of the global variables of the current wafer to be tested is consistent with the information of the global variables of the wafer to be tested last time, read the empty needle capacitance value in the designated address corresponding to the global variable and obtain the total capacitance value of the wafer to be tested through electrical parameter testing; if the information of the global variables of the current wafer to be tested is inconsistent with the information of the global variables of the wafer to be tested last time, obtain the total capacitance value and the empty needle capacitance value of the wafer to be tested through electrical parameter testing, and write the empty needle capacitance value obtained by the test into the designated address; Step 5: Obtaining a final actual capacitance value of the wafer to be tested according to the total capacitance value of the wafer to be tested and the empty needle capacitance value; Step 6: Repeat step 4 to step 5 until the wafer acceptance test of all wafers to be tested is completed.
[0006] Optionally, in the wafer acceptance test method, during the first electrical parameter test, the default value written in the specified address in step one is 1E32.
[0007] Optionally, in the wafer acceptance test method, in the process of performing electrical parameter testing on the wafer to be tested to obtain the total capacitance value of the wafer to be tested and the empty needle capacitance value corresponding to the global variable, the total test time is a.
[0008] Optionally, in the wafer acceptance test method, the total test time a is 0.6s.
[0009] Optionally, in the wafer acceptance test method, if the information of the global variable of the wafer to be tested currently is consistent with the information of the global variable of the wafer to be tested last time, then in the process of reading the empty needle capacitance value in the specified address corresponding to the global variable and obtaining the total capacitance value of the wafer to be tested through electrical parameter testing, the total test time is b; If the information of the global variables of the wafer to be tested currently is inconsistent with the information of the global variables of the wafer to be tested last time, the total capacitance value and the empty needle capacitance value of the wafer to be tested are obtained by electrical parameter testing, and the empty needle capacitance value obtained by the test is written into the specified address, and the total test time is a; Among them, the total test time b is less than the total test time a.
[0010] Optionally, in the wafer acceptance test method, the total test time a is 0.6 s; the total test time b is 0.2 s.
[0011] The technical solution of this application has at least the following advantages: The present application provides a wafer acceptance test method, which introduces a global variable about the wafer to be tested in the test item, and tests and obtains the total capacitance value of the first wafer to be tested and the empty needle capacitance value corresponding to the global variable in the first test. Then, in the next test, when the test batch number, wafer number, test probe number and test frequency and other information are exactly the same, a wafer only needs to test the empty needle capacitance once. Then, while obtaining the total capacitance value of the wafer to be tested in each test, the empty needle capacitance value is repeatedly retrieved and utilized to directly obtain the final actual capacitance value of the wafer to be tested, eliminating the time of multiple empty needle capacitance tests and needle lifting and needle pressing, saving capacitance test time and improving test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0013] Figure 1 It is a schematic diagram of the traditional capacitance parameter test process; Figure 2 is a flow chart of a wafer acceptance test method according to an embodiment of the present invention; The reference numerals are described as follows: 10-wafer, 20-needle card, 30-probe. DETAILED DESCRIPTION
[0014] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0015] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0016] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0017] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0018] The present application provides a wafer acceptance test method, referring to Figure 2 , Figure 2 is a flow chart of a wafer acceptance test method according to an embodiment of the present invention, wherein the wafer acceptance test method comprises: First, execute step 1 (S1): introduce a global variable of the wafer to be tested in the test item, and write a default value in a specified address associated with the global variable in the memory, wherein the information of the global variable includes at least: test batch number, wafer number, test probe number and test frequency.
[0019] In this embodiment, during the first electrical parameter test, the default value written in the designated address in step 1 is 1E32.
[0020] Then, step 2 (S2) is executed: performing an electrical parameter test on the wafer to be tested to obtain a total capacitance value of the wafer to be tested and an empty pin capacitance value corresponding to the global variable; Preferably, in the process of performing electrical parameter testing on the wafer to be tested to obtain the total capacitance value of the wafer to be tested and the empty needle capacitance value corresponding to the global variable, the total test time is a.
[0021] In this embodiment, the total test duration a is 0.6 s.
[0022] Next, execute step three (S3): according to the total capacitance value of the wafer to be tested and the empty needle capacitance value, obtain the final actual capacitance value of the wafer to be tested, and write the empty needle capacitance value obtained in step two into the designated address, that is, modify the default value in the designated address of step one to the empty needle capacitance value obtained in step two.
[0023] Further, execute step four (S4): obtain the global variable information of other wafers to be tested; if the global variable information of the current wafer to be tested is consistent with the global variable information of the previous wafer to be tested, read the empty needle capacitance value in the designated address corresponding to the global variable and obtain the total capacitance value of the wafer to be tested through electrical parameter testing; if the global variable information of the current wafer to be tested is inconsistent with the global variable information of the previous wafer to be tested, obtain the total capacitance value and empty needle capacitance value of the wafer to be tested through electrical parameter testing, and write the empty needle capacitance value obtained by the test into the designated address.
[0024] Preferably, if the information of the global variable of the current wafer to be tested is consistent with the information of the global variable of the wafer to be tested last time, the total test time is b in the process of reading the empty needle capacitance value in the specified address corresponding to the global variable and obtaining the total capacitance value of the wafer to be tested through electrical parameter testing; Furthermore, if the information of the global variables of the current wafer to be tested is inconsistent with the information of the global variables of the previous wafer to be tested, the total capacitance value and the empty needle capacitance value of the wafer to be tested are obtained through electrical parameter testing, and the empty needle capacitance value obtained by the test is written into the specified address. The total test time is a; wherein, the total test time b is less than the total test time a.
[0025] Next, executing step five (S5): obtaining a final actual capacitance value of the wafer to be tested according to the total capacitance value of the wafer to be tested and the empty needle capacitance value; Finally, step six (S6) is performed: step four to step five are repeatedly performed until the wafer acceptance test of all wafers to be tested is completed.
[0026] In this embodiment, the total test duration a is 0.6 s; the total test duration b is 0.2 s.
[0027] Among them, in a single test, when the information of the global variables of the current wafer to be tested is consistent with the information of the global variables of the previous wafer to be tested, the empty needle capacitance test can be omitted in each capacitance test, and directly measuring the total capacitance only takes 0.2s. Under ideal conditions, the final test time of the current wafer to be tested can be reduced by about 67%.
[0028] Furthermore, in batch testing, the actual test time saved is related to the number of times the information of the global variables of consecutive tests in the test item is repeated and consistent. Taking 9 points are tested on each wafer as an example, assuming that the information of the global variables of x test items is consistent in consecutive tests, the percentage of the test time of the relevant capacitors that can be reduced in batch testing is as follows: ; Among them, p is the percentage of the test time of the relevant capacitors that can be reduced in batch testing; x is the number of items in which the information of the global variables of the test items is consistent (same) in consecutive (non-interrupted) tests. From the above formula, it can be seen that the larger the x, the closer the test time of the relevant capacitors can be reduced to 67%. It is worth noting that the information repetition and consistency of the global variables of consecutive tests in the test item means that the information of the global variables of the current test is consistent with the information of the global variables of the previous test, and the information of the global variables of the current test is consistent with the information of the global variables of the previous test without interruption.
[0029] In the present application, a global variable about the wafer to be tested is introduced in the test item, and the total capacitance value of the first wafer to be tested and the empty needle capacitance value corresponding to the global variable are tested in the first test. Then, in the next test, when the test batch number, wafer number, test probe number and test frequency and other information are exactly the same, a wafer only needs to test the empty needle capacitance once. Then, while obtaining the total capacitance value of the wafer to be tested in each test, the empty needle capacitance value is repeatedly retrieved and utilized to directly obtain the final actual capacitance value of the wafer to be tested, eliminating the time of multiple tests of the empty needle capacitance and the time of lifting and pressing the needle, saving the capacitance test time and improving the test efficiency.
[0030] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A wafer acceptance test method, characterized in that: include: Step 1: introducing a global variable of the wafer to be tested in the test item, and writing a default value in a specified address associated with the global variable in the memory, wherein the information of the global variable includes at least: a test batch number, a wafer number, a test probe number, and a test frequency; Step 2: Performing an electrical parameter test on the wafer to be tested to obtain a total capacitance value of the wafer to be tested and an empty pin capacitance value corresponding to the global variable; Step 3: obtaining the final actual capacitance value of the wafer to be tested according to the total capacitance value of the wafer to be tested and the empty needle capacitance value, and writing the empty needle capacitance value obtained in the step 2 into the designated address; Step 4: Obtain the information of the global variables of other wafers to be tested. If the information of the global variables of the current wafer to be tested is consistent with the information of the global variables of the wafer to be tested last time, read the empty needle capacitance value in the designated address corresponding to the global variable and obtain the total capacitance value of the wafer to be tested through electrical parameter testing; if the information of the global variables of the current wafer to be tested is inconsistent with the information of the global variables of the wafer to be tested last time, obtain the total capacitance value and the empty needle capacitance value of the wafer to be tested through electrical parameter testing, and write the empty needle capacitance value obtained by the test into the designated address; Step 5: Obtaining a final actual capacitance value of the wafer to be tested according to the total capacitance value of the wafer to be tested and the empty needle capacitance value; Step 6: Repeat step 4 to step 5 until the wafer acceptance test of all wafers to be tested is completed.
2. The wafer acceptance test method according to claim 1, characterized in that: During the first electrical parameter test, the default value written in the specified address in step 1 is 1E32.
3. The wafer acceptance test method according to claim 1, characterized in that: In the step 2, the electrical parameter test is performed on the wafer to be tested to obtain the total capacitance value of the wafer to be tested and the empty needle capacitance value corresponding to the global variable, and the total test time is a.
4. The wafer acceptance test method according to claim 3, characterized in that: The total test duration a is 0.6s.
5. The wafer acceptance test method according to claim 1, characterized in that: In the step 4, if the information of the global variable of the current wafer to be tested is consistent with the information of the global variable of the wafer to be tested last time, then in the process of reading the empty needle capacitance value in the specified address corresponding to the global variable and obtaining the total capacitance value of the wafer to be tested through electrical parameter testing, the total test time is b; If the information of the global variables of the wafer to be tested currently is inconsistent with the information of the global variables of the wafer to be tested last time, the total capacitance value and the empty needle capacitance value of the wafer to be tested are obtained by electrical parameter testing, and the empty needle capacitance value obtained by the test is written into the specified address, and the total test time is a; Among them, the total test time b is less than the total test time a.
6. The wafer acceptance test method according to claim 5, characterized in that: The total test duration a is 0.6s; The total test duration b is 0.2s.