Simple product-level dead zone test method

Abstract

The invention relates to a simple product-level dead zone test method. The method comprises the following steps: building a dead zone test platform; the dead zone test platform comprises a resistor R, a capacitor C and an oscilloscope, and the resistor R and the capacitor C are connected in parallel and then connect one output of the H bridge or the three-phase bridge to the ground; testing the voltage at the two ends of the resistor R by using an oscilloscope, and establishing a time-varying test oscillogram of the voltage at the two ends of the resistor R; and determining the dead time according to the test oscillogram of the voltage at the two ends of the resistor R along with the time change. The defects in the prior art can be overcome, the RC discharge principle is used, the dead zone time can be tested from the outside of a chip or a product, and effective testing of the dead zone time of the packaged product is achieved. The method can ensure the performance and reliability of the product, and has the characteristics of simple implementation method, easy judgment and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of product testing, and in particular to a simple product-level dead zone testing method. Background Art

[0002] Dead-time refers to the time interval during which the upper and lower power devices on the same bridge arm cannot be turned on at the same time in an H-bridge or three-phase bridge circuit. This time interval is to prevent the shoot-through phenomenon between power devices, thereby protecting the devices from damage. The setting of dead-time is particularly important for motor control because it affects the motor's torque fluctuation, efficiency, noise and other performance.

[0003] The existing dead zone test methods have the following shortcomings when testing the packaged H-bridge / three-phase bridge chip / product status: (1) The traditional dead zone test method is mainly aimed at the open board status. For the packaged H-bridge or three-phase bridge chip / product status, it is impossible to directly obtain the upper and lower bridge drive signals for testing, which limits the applicability and accuracy of the test and has limitations. (2) As the processing capacity of the test system expands, it will become more difficult to maintain or modify the program when using traditional modules for testing, which limits the flexibility and scalability of the test system. (3) Traditional test methods may require more external wiring and hardware resources, which not only increases the test cost, but also reduces the utilization rate of the system and instruments.

[0004] Therefore, it is necessary to develop a simple product-level dead time test method to effectively test the dead time of packaged products and ensure product performance and reliability. Summary of the invention

[0005] The purpose of the present invention is to provide a simple product-level dead time testing method, which can solve the deficiencies in the prior art, achieve effective testing of the dead time of packaged products, and ensure product performance and reliability.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] A simple product-level dead zone testing method comprises the following steps:

[0008] S1. Build a dead zone test platform; the dead zone test platform includes a resistor R, a capacitor C and an oscilloscope. After the resistor R and the capacitor C are connected in parallel, one output of an H bridge or a three-phase bridge is connected to the ground.

[0009] S2. Use an oscilloscope to test the voltage across the resistor R, and establish a test waveform diagram showing the voltage across the resistor R changing with time.

[0010] S3. Determine the dead time according to a test waveform diagram of the voltage across the resistor R varying with time.

[0011] As a further improvement of the above technical solution, the two MOS transistors on the same bridge arm of the H-bridge or three-phase bridge are transistor Q1 and transistor Q2, respectively. Transistor Q1 is an upper bridge MOS transistor, and transistor Q2 is a lower bridge MOS transistor.

[0012] As a further improvement of the above technical solution, the resistor R is an external resistor.

[0013] As a further improvement of the above technical solution, the capacitor C is an equivalent capacitance of a parasitic capacitor and an external capacitor.

[0014] As a further improvement of the above technical solution, in step S2, when the oscilloscope is used to test the voltage across the resistor R, there are two cases, case 1 and case 2; the test method tests the dead time once per switching cycle, and the switching cycle includes five time periods: time period 1, time period 2, time period 3, time period 4 and time period 5.

[0015] As a further improvement of the above technical solution, the method of using an oscilloscope to test the voltage across the resistor R and establishing a test waveform diagram of the voltage across the resistor R changing with time includes:

[0016] S21, Period 1

[0017] In period 1 and period 2, situation 1 is the same as situation 2. MOS tube Q1 and MOS tube Q2 are both turned off, and the voltage V across the resistor R is R =0.

[0018] S22, Period 2

[0019] Case 1: MOS tube Q1 is turned on, and MOS tube Q2 is turned off. At this time, the bus charges the capacitor C through MOS tube Q1. The charging resistance is very small, and the charging time is negligible. The bus voltage is equal to the voltage across the resistor R, that is, V R =V B .

[0020] Case 2: MOS tube Q1 is turned off, MOS tube Q2 is turned on, and the voltage V across the resistor R R =0.

[0021] S23, Period 3

[0022] Case 1: MOS tube Q1 is turned off, MOS tube Q2 is turned off, and it is in the dead zone state. At this time, capacitor C discharges through resistor R, and the voltage across resistor R

[0023] Case 2: MOS tube Q1 is turned off, MOS tube Q2 is turned off, and it is in the dead zone state. The voltage V across the resistor R R =0.

[0024] S24, Period 4

[0025] Case 1: MOS tube Q1 is turned off, MOS tube Q2 is turned on, capacitor C discharges through MOS tube Q2, the discharge resistance is very small, the discharge time is negligible, and the voltage V across the resistor R is R =0.

[0026] Case 2: MOS tube Q1 is turned on, MOS tube Q2 is turned off, at this time the bus charges C through MOS tube Q1, as shown in the attached figure. Figure 3 As shown, the red arrow represents the current direction. The charging resistance is very small and the charging time is negligible. Then V R =V B .

[0027] S25, Period 5

[0028] Case 1: MOS tube Q1 is turned off, MOS tube Q2 is turned off, and it is in the dead zone state. The voltage V across the resistor R R =0, regression situation is period 1, and the cycle continues.

[0029] Case 2: MOS tube Q1 is turned off, MOS tube Q2 is turned off, and it is in the dead zone state. At this time, capacitor C discharges through R, and the voltage across resistor R Return to period 3 of situation 1 and repeat it in sequence.

[0030] Among them, V B is the bus voltage, V R is the voltage across the resistor R.

[0031] As a further improvement of the above technical solution, the time t3 of the time period 3 in the case 1 and the time t5 of the time period 5 in the case 2 are dead time.

[0032] As a further improvement of the above technical solution, the resistance value of the resistor R is determined by formula (1): and the power P is determined by the following formula:

[0033]

[0034] The power P of the resistor R is determined by formula (2):

[0035]

[0036] Where R represents the resistance of resistor R, t represents the dead time, C represents the capacitance of resistor C, V B Indicates bus voltage, V Rrepresents the voltage across the resistor R, and P represents the power of the resistor R.

[0037] Compared with the prior art, the advantages of the present invention are:

[0038] (1) The present invention can solve the deficiencies in the prior art. By using the RC discharge principle, the dead time can be tested from the outside of the chip or product, thereby realizing effective testing of the dead time of packaged products. The present invention can ensure the performance and reliability of the product, and has the characteristics of simple implementation method and easy determination. The traditional dead time test method mainly tests the circuit in the open board state, while the present invention improves the test method so that it can be applied to the packaged H-bridge or three-phase bridge chip / product state. This greatly expands the application scope of the dead time test, so that effective dead time testing can also be performed on products that have been packaged, filling the gap in the existing test methods in this field.

[0039] (2) As the processing capacity of the test system expands, traditional test methods have difficulties in maintenance and program modification, which limits the flexibility and scalability of the test system. The present invention simplifies the test process by adopting a new test scheme, reduces the dependence on complex external wiring and hardware resources, and enables the test system to be more flexibly maintained and program modified when facing capacity expansion, thereby enhancing the scalability of the test system and being able to better adapt to test requirements of different scales and complexities.

[0040] (3) Traditional testing methods may require more external wiring and hardware resources, which not only increases the testing cost, but also reduces the utilization of the system and instruments. The present invention simplifies the construction of the test platform, requiring only basic equipment such as resistors, capacitors and oscilloscopes to complete the test, reducing the use of unnecessary external wiring and complex hardware, while reducing costs, improving the utilization of existing test equipment and instruments, and achieving optimal resource allocation. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 The method flow chart of the simplified product-level dead zone testing method of the present invention;

[0042] Figure 2 It is a schematic diagram of the dead zone test platform in the present invention;

[0043] Figure 3 This is the test schematic diagram of the dead zone test platform corresponding to Case 1 in Test Period 2. The red arrow represents the current direction.

[0044] Figure 4 This is the test schematic diagram of the dead zone test platform corresponding to Case 1 in Test Period 3. The red arrow represents the current direction;

[0045] Figure 5It is a test waveform diagram of the voltage across the resistor R changing with time. The horizontal axis represents time and the vertical axis represents voltage amplitude, that is, the voltage waveform tested by the oscilloscope. DETAILED DESCRIPTION

[0046] The present invention will be further described below in conjunction with the accompanying drawings:

[0047] The present invention can ensure the performance and reliability of the product in practical applications by effectively testing the dead time of the packaged product. Accurate dead time setting is crucial for application scenarios such as motor control, which directly affects the performance indicators such as torque fluctuation, efficiency and noise of the motor. The test method provided by the present invention can help manufacturers and R&D personnel to accurately measure and adjust the dead time, thereby optimizing product performance and improving product reliability and market competitiveness.

[0048] like Figure 1 A simple product-level dead zone test method is shown, the method comprising the following steps:

[0049] S1. Build a dead zone test platform, such as Figure 2 As shown, the dead zone test platform includes a resistor R, a capacitor C and an oscilloscope. The resistor R and the capacitor C are connected in parallel to connect one output of the H bridge or the three-phase bridge to the ground. The resistance and power of the resistor R and the capacitance of the capacitor C are selected according to the test requirements.

[0050] The present invention innovatively utilizes the RC discharge principle to perform dead time testing from the outside of the chip or product. By building a test platform including a resistor R and a capacitor C, and using an oscilloscope to test the voltage change across the resistor R, the internal dead time characteristics are cleverly converted into externally observable and measurable voltage waveform changes, thereby achieving effective testing of the dead time of the packaged product. This method breaks through the limitation of traditional testing methods that must obtain internal upper and lower bridge drive signals, and provides a new idea and means for testing dead time.

[0051] S2. Use an oscilloscope to test the voltage across the resistor R, and establish a test waveform diagram showing the voltage across the resistor R changing with time. In different time periods, the voltage across the resistor R presents different states according to the on and off conditions of the MOS tube.

[0052] When the voltage across the resistor R is tested using an oscilloscope, including two cases, case 1 and case 2, the switching cycle includes five time periods, namely, time period 1, time period 2, time period 3, time period 4 and time period 5.

[0053] After the dead zone test platform is built, Figure 2As shown, transistor Q1 and transistor Q2 are two MOS tubes on the same bridge arm, transistor Q1 is an upper bridge MOS tube, transistor Q2 is a lower bridge MOS tube, R is a resistor, C is the capacitance of the parasitic capacitor and the external capacitor, and the bus voltage is V B , the voltage across the resistor R is V R .

[0054] The step of using an oscilloscope to test the voltage across the resistor R and establishing a test waveform diagram showing the voltage across the resistor R changing with time includes:

[0055] S21, Period 1

[0056] In period 1 and period 2, situation 1 is the same as situation 2. MOS tube Q1 and MOS tube Q2 are both turned off, and the voltage V across the resistor R is R =0.

[0057] S22, Period 2

[0058] Case 1: MOS tube Q1 is turned on, MOS tube Q2 is turned off, at this time the bus charges the capacitor C through MOS tube Q1, such as Figure 3 As shown, the red arrow represents the current direction. The charging resistance is very small and the charging time is negligible. Then the bus voltage is equal to the voltage across the resistor R, that is, V R =V B .

[0059] Case 2: MOS tube Q1 is turned off, MOS tube Q2 is turned on, and the voltage V across the resistor R R =0.

[0060] S23, Period 3

[0061] Case 1: MOS tube Q1 is turned off, MOS tube Q2 is turned off, and it is in the dead zone state. At this time, capacitor C discharges through resistor R, such as Figure 4 As shown, the red arrow represents the direction of current and the voltage across the resistor R Here, t represents time.

[0062] Case 2: MOS tube Q1 is turned off, MOS tube Q2 is turned off, and it is in the dead zone state. The voltage V across the resistor R R =0.

[0063] S24, Period 4

[0064] Case 1: MOS tube Q1 is turned off, MOS tube Q2 is turned on, capacitor C discharges through MOS tube Q2, the discharge resistance is very small, the discharge time is negligible, and the voltage V across the resistor R is R =0.

[0065] Case 2: MOS tube Q1 is turned on, MOS tube Q2 is turned off, at this time the bus charges C through MOS tube Q1, as shown in the attached figure. Figure 3 As shown, the red arrow represents the current direction. The charging resistance is very small and the charging time is negligible. Then V R =V B .

[0066] S25, Period 5

[0067] Case 1: MOS tube Q1 is turned off, MOS tube Q2 is turned off, and it is in the dead zone state. The voltage V across the resistor R R =0, regression situation is period 1, and the cycle continues.

[0068] Case 2: MOS tube Q1 is turned off, MOS tube Q2 is turned off, and it is in the dead zone state. At this time, capacitor C discharges through R, as shown in the attached figure. Figure 4 As shown, the red arrow represents the direction of current and the voltage across the resistor R Return to period 3 of case 1, and repeat it in sequence. Where t represents time.

[0069] S3. Determine the dead time according to a test waveform diagram of the voltage across the resistor R varying with time.

[0070] The duration of period 3 in case 1 and period 5 in case 2 is the dead time. This test method can test the dead time once per switching cycle. The test waveform is as follows: Figure 5 As shown, t3 in case 1 and t5 in case 2 are the dead time.

[0071] The capacitor C can be selected to be external according to the actual test situation. Generally, the capacitor can be a few nF. The resistance value of the resistor R and the power P are selected as follows.

[0072] First, according to actual test experience, generally at the end of period 3 of case 1 or period 5 of case 2, the voltage drops by V B It is appropriate to use about 1 / 5 of the bus voltage, which is convenient for testing waveform determination. During the test process, the present invention designs the voltage drop amplitude to be about 1 / 5 of the bus voltage based on actual testing experience. Such a design makes the test waveform clearer and easier to identify, which is convenient for testers to accurately determine the dead time. This optimized design of the test waveform determination details improves the accuracy and efficiency of the test, reduces the difficulty of the test and the dependence on the experience of the tester, and has a strong practical value.

[0073] Secondly, calculate based on specific parameters. Here, taking bus voltage 24V, dead time 500ns (calculate and select according to software setting dead time), and capacitor 2nF as an example, the resistor selection is as follows:

[0074]

[0075] Use relevant circuit formulas and principles, combined with the charging and discharging characteristics of the capacitor, to calculate the appropriate resistance value of the resistor R. In general, the discharge time constant of the capacitor is τ = RC, where R is the resistor and C is the capacitor, and the discharge time is related to the time constant. The approximate range of the resistor can be inferred based on the requirement that the voltage drops to a certain level during the dead time. The resistor will have power loss during operation, and its power P needs to be calculated and selected based on the actual working current and the voltage across the resistor, etc., to ensure that the resistor can work stably during the test and will not be damaged due to excessive power.

[0076] Compared with the traditional test method, the test method of the present invention is simpler and easier to determine. It simplifies the construction of the test platform and the test process, reduces the test steps and complexity, enables testers to complete the test task faster, and improves the test efficiency. At the same time, the external test method based on the RC discharge principle and the convenient test waveform determination design adopted by the present invention also help to improve the accuracy of the test results, reduce the test errors caused by the limitations of the test method or human factors, and provide a more reliable basis for product quality control and performance evaluation.

[0077] The above-described embodiments are merely descriptions of preferred implementations of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the scope of protection determined by the claims of the present invention.

Claims

1. A simple product-level dead zone testing method, characterized in that: The method comprises the following steps: S1. Build a dead zone test platform; the dead zone test platform includes a resistor R, a capacitor C and an oscilloscope, and after the resistor R and the capacitor C are connected in parallel, one output of an H bridge or a three-phase bridge is connected to the ground; S2. Using an oscilloscope to test the voltage across the resistor R, and establishing a test waveform diagram showing the voltage across the resistor R changing with time; S3. Determine the dead time according to a test waveform diagram of the voltage across the resistor R varying with time.

2. The simplified product-level dead zone testing method according to claim 1, characterized in that: The two MOS transistors on the same bridge arm of the H-bridge or three-phase bridge are transistor Q1 and transistor Q2, respectively. Transistor Q1 is an upper bridge MOS transistor, and transistor Q2 is a lower bridge MOS transistor.

3. The simplified product-level dead zone testing method according to claim 1, characterized in that: The resistor R is an external resistor.

4. The simplified product-level dead zone testing method according to claim 1, characterized in that: The capacitor C is the equivalent capacitance of the parasitic capacitor and the external capacitor.

5. The simplified product-level dead zone testing method according to claim 2, characterized in that: In the step S2, when the voltage across the resistor R is tested using the oscilloscope, there are two cases, case 1 and case 2. The test method tests the dead time once per switching cycle, and the switching cycle includes five time periods: time period 1, time period 2, time period 3, time period 4 and time period 5.

6. The simplified product-level dead zone testing method according to claim 5, characterized in that: The step of using an oscilloscope to test the voltage across the resistor R and establishing a test waveform diagram showing the voltage across the resistor R changing with time includes: S21, Period 1 In period 1 and period 2, situation 1 is the same as situation 2. MOS tube Q1 and MOS tube Q2 are both turned off, and the voltage V across the resistor R is R =0; S22, Period 2 Case 1: MOS tube Q1 is turned on, and MOS tube Q2 is turned off. At this time, the bus charges the capacitor C through MOS tube Q1. The charging resistance is very small, and the charging time is negligible. The bus voltage is equal to the voltage across the resistor R, that is, V R =V B ; Case 2: MOS tube Q1 is turned off, MOS tube Q2 is turned on, and the voltage V across the resistor R R =0; S23, Period 3 Case 1: MOS tube Q1 is turned off, MOS tube Q2 is turned off, and it is in the dead zone state. At this time, capacitor C discharges through resistor R, and the voltage across resistor R Case 2: MOS tube Q1 is turned off, MOS tube Q2 is turned off, and it is in the dead zone state. The voltage V across the resistor R R =0; S24, Period 4 Case 1: MOS tube Q1 is turned off, MOS tube Q2 is turned on, capacitor C discharges through MOS tube Q2, the discharge resistance is very small, the discharge time is negligible, and the voltage V across the resistor R is R =0; Case 2: MOS tube Q1 is turned on, MOS tube Q2 is turned off, at this time the bus charges C through MOS tube Q1, the charging resistance is very small, and the charging time is negligible, then V R =V B ; S25, Period 5 Case 1: MOS tube Q1 is turned off, MOS tube Q2 is turned off, and it is in the dead zone state. The voltage V across the resistor R R =0, regression situation one period 1, cycle in sequence; Case 2: MOS tube Q1 is turned off, MOS tube Q2 is turned off, and it is in the dead zone state. At this time, capacitor C discharges through R, and the voltage across resistor R Period 3 of regression case 1, cycle sequentially; Among them, V B is the bus voltage, V R is the voltage across the resistor R.

7. The simplified product-level dead zone testing method according to claim 6, characterized in that: The duration t3 of the time period 3 in the case 1 and the duration t5 of the time period 5 in the case 2 are dead time.

8. The simplified product-level dead zone testing method according to claim 1, characterized in that: The resistance value of the resistor R is determined by formula (1): and the power P is determined by the following formula: The power P of the resistor R is determined by formula (2): Where R represents the resistance of resistor R, t represents the dead time, C represents the capacitance of resistor C, V B Indicates bus voltage, V R represents the voltage across the resistor R, and P represents the power of the resistor R.

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