BM-less panel manufacturing method and display panel

Abstract

The invention discloses a manufacturing method of a BM-less panel. The manufacturing method comprises the following steps: sequentially forming a metal film layer and a whole-surface barrier layer on a glass substrate; forming a buffer layer on the barrier layer; forming a polycrystalline silicon active layer pattern on the buffer layer to obtain a channel region, a first source drain electrode and a second source drain electrode of the first transistor; forming a gate insulating layer on the whole surface of the active layer; forming a gate metal pattern and a gate signal line on the gate insulating layer to form a control end of the first transistor; forming a first interlayer insulating layer on the whole surface of the gate metal pattern; forming a second metal layer, a first signal line and a second signal line on the first interlayer insulating layer; and forming an organic flat layer on the whole surface of the second metal layer, and forming a pixel electrode on the flat layer.

Description

Technical Field

[0001] The present invention relates to the technical field of display panels, and in particular to a BM-less panel manufacturing method and a display panel. Background Art

[0002] In LCD technology, there are gaps between adjacent pixel electrodes, the electric field distribution in the gap area is uneven, and the deflection angle of the liquid crystal molecules is abnormal, which will cause some light to pass through the gaps between the electrodes, resulting in light leakage and a decrease in the contrast of the display.

[0003] In order to improve the contrast ratio in the art, a black light shielding layer, called a black matrix (BM), is generally formed on the CF glass at a position corresponding to the gap between pixel electrodes.

[0004] BM is prepared on CF glass. There is a misalignment between CF glass and substrate glass, which is called box alignment accuracy. When designing BM, it is necessary to increase the external expansion amount based on the pixel electrode gap to ensure that the leakage light can be completely shielded.

[0005] The worse the cell alignment accuracy is, the wider the BM should be designed, and the lower the pixel aperture ratio is. For high PPI LCD products, the BM width severely limits the pixel aperture ratio, resulting in low display brightness.

[0006] In summary, the conventional display panel has the problem of being unable to balance shielding leakage light and light output brightness. Summary of the invention

[0007] In view of this, the present invention provides a BM-less panel manufacturing method and a display panel, which solves the problem of traditional display panels that they cannot balance the shielding of leaked light and the brightness of the light output by optimizing the layout design.

[0008] To solve the above problems, the technical solution of the present invention is to adopt a BM-less panel manufacturing method, including: forming a metal film layer and a whole-surface barrier layer on a glass substrate in sequence; forming a buffer layer on the barrier layer; forming a polysilicon active layer pattern on the buffer layer to obtain a channel region, a first source and drain, and a second source and drain of a first transistor; forming a gate insulating layer on the whole surface of the active layer; forming a gate metal pattern and a gate signal line on the gate insulating layer to constitute the control end of the first transistor; forming a first interlayer insulating layer on the whole surface of the gate metal pattern; forming a second metal layer, a first signal line, and a second signal line on the first interlayer insulating layer; forming an organic flat layer on the whole surface of the second metal layer, and forming a pixel electrode on the flat layer.

[0009] Optionally, when the metal film layer is used as a shading module, the metal film layer is made to have a length in the first direction greater than a gap between the pixel electrodes of two adjacent pixel driving circuits in the first direction, and overlaps with two adjacent pixel electrodes in the second direction.

[0010] Optionally, the edge of the metal film layer is manufactured to extend beyond the edge of the pixel electrode by a preset distance in the first direction, and the preset distance is greater than the alignment accuracy between the pixel electrode and the metal film layer.

[0011] Optionally, the method for making the channel region, the first source and drain, and the second source and drain of the first transistor is: after forming a polysilicon active layer pattern, using a mask plate, a heavy doping process is used to obtain the channel region, the first source and drain of the first transistor.

[0012] Optionally, the panel manufacturing method further includes: coupling the first signal line to the first source and drain of the first transistor through a transfer hole process, and coupling the second signal line to the second source and drain of the first transistor through a transfer hole process.

[0013] Optionally, the panel manufacturing method further includes: coupling the pixel electrode to a second metal layer coupled to a second source and drain of the first transistor through a transfer hole process.

[0014] Optionally, when the metal film layer and the first signal lines of two adjacent pixel driving circuits are used together as a shading module, the metal film layer is made to have a length in the first direction that is greater than the gap between the first signal lines of two adjacent pixel driving circuits in the first direction, and overlaps with the two adjacent first signal lines in the second direction.

[0015] Optionally, in the second direction, the shading module overlaps with two adjacent pixel electrodes.

[0016] Optionally, in the first direction, the edge of the shading module is manufactured to extend beyond the edge of the pixel electrode by a preset distance, and the preset distance is greater than the alignment accuracy between the pixel electrode and the first signal line.

[0017] Correspondingly, the present invention provides a BM-less display panel, comprising: a glass substrate; a metal film layer located on the glass substrate and a whole-surface barrier layer located on the metal film layer; a buffer layer arranged on the barrier layer; a polysilicon active layer pattern formed on the buffer layer, constituting a channel region, a first source and a drain, and a second source and a drain of a first transistor; a gate insulating layer arranged on the active layer, and a gate metal pattern and a gate signal line on the gate insulating layer, constituting a control end of the first transistor; a first interlayer insulating layer located on the gate metal pattern; a second metal layer, a first signal line, and a second signal line formed on the first interlayer insulating layer; an organic planar layer formed entirely on the second metal layer, and a pixel electrode arranged on the planar layer.

[0018] Accordingly, the present invention provides a preferred embodiment, a BM-less panel manufacturing method, comprising: forming a metal film layer and a whole-surface barrier layer on a glass substrate in sequence; forming a buffer layer on the barrier layer; forming a polysilicon active layer pattern on the buffer layer to obtain a channel region, a first source and drain, and a second source and drain of a first transistor; forming a gate insulating layer on the whole surface of the active layer; forming a gate metal pattern and a gate signal line on the gate insulating layer to constitute a control end of the first transistor; forming a first interlayer insulating layer on the whole surface of the gate metal pattern; forming a second metal layer, a first signal line, and a second signal line on the first interlayer insulating layer; forming an organic flat layer on the whole surface of the second metal layer, and forming a common electrode on the flat layer; forming a third metal layer pattern on the common electrode; forming a second interlayer insulating layer on the whole surface of the third metal layer, and forming a pixel electrode on the second interlayer insulating layer.

[0019] The primary improvement of the present invention is the BM-less panel manufacturing method provided, which prevents backlight from leaking out of the gap by covering the gap between the pixel electrodes with a metal film layer formed on the glass substrate. At the same time, since the metal film layer alignment accuracy is higher than the box alignment accuracy, the use of the metal film layer to shield light can greatly increase the aperture ratio of the LCD pixel and improve the display brightness. And because there is no BM layer, it is possible to reduce the box alignment accuracy requirements of the LCD module, reduce the cost of production line equipment, and improve the production line yield, solving the problem of traditional display panels that cannot balance the shielding of leaked light and light brightness. And because the metal film layer is connected on the entire surface, it can be used to transmit entire-surface signals, such as common electrode signals, while being used for shading, thereby further improving the pixel aperture ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a structural plan view of a BM-less display panel of the present invention; Figure 2 is a structural cross-sectional view of a BM-less display panel of the present invention; Figure 3 is a structural plan view of a pixel layout of a first preferred embodiment of the present invention; Figure 4 is a structural cross-sectional view of a pixel layout of a first preferred embodiment of the present invention; Figure 5 is a structural plan view of a pixel layout of a second preferred embodiment of the present invention; Figure 6 It is a structural cross-sectional view of a pixel layout of a second preferred embodiment of the present invention. Implementation

[0021] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0022] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0024] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0026] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0027] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0028] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0029] Specifically, Figure 1 and Figure 2 As shown, a BM-less panel manufacturing method includes: A metal film layer BSM and a full-surface barrier layer Barrier are sequentially formed on a glass substrate Glass, wherein the full-surface barrier layer is used to prevent the influence of impurities in the substrate on the TFT channel.

[0030] A buffer layer Buffer is formed on the barrier layer to ensure the flatness of the channel and prevent substrate impurities from being blocked, thereby ensuring the stability of the formed TFT.

[0031] A polysilicon active layer pattern is formed on the buffer layer to obtain a channel region, a first source and a drain electrode, and a second source and a drain electrode of the first transistor M1. It should be noted here that since the core invention of the present invention is to construct a metal film layer BSM, and forming a polysilicon active layer pattern and a gate metal pattern belongs to the conventional prior art in this field, those skilled in the art clearly know how to construct a polysilicon active layer pattern and a gate metal pattern. Therefore, in order to focus on the setting method of the metal film layer BSM, the following is selected. Figure 2 The cross-sectional view shown does not show the polysilicon active layer pattern and the gate metal pattern.

[0032] A gate insulating layer GI is formed entirely on the active layer.

[0033] A gate metal pattern and a gate signal line are formed on the gate insulating layer to constitute a control terminal of the first transistor.

[0034] A first interlayer insulating layer Insulator is formed entirely on the gate metal pattern.

[0035] A second metal layer, a first signal line data, and a second signal line are formed on the first interlayer insulating layer.

[0036] An organic planar layer is formed entirely on the second metal layer, and a pixel electrode Pixel ITO is formed on the planar layer.

[0037] The present invention prevents backlight from leaking out of the gaps by covering the gaps between pixel electrodes with a metal film layer formed on a glass substrate. At the same time, since the alignment accuracy of the metal film layer is higher than the box alignment accuracy, the use of the metal film layer to shield light can greatly increase the aperture ratio of LCD pixels and improve display brightness. And since there is no BM layer, it is possible to reduce the box alignment accuracy requirements of the LCD module, reduce the cost of production line equipment, and improve the production line yield, solving the problem of traditional display panels that cannot balance the shielding of leaked light and the brightness of light output. And since the metal film layer is connected on the entire surface, it can be used to transmit entire surface signals, such as common electrode signals, while being used for shading, thereby further improving the pixel aperture ratio.

[0038] Furthermore, when the light-blocking layer pattern metal film layer is used as a light-shielding module, the light-blocking layer pattern metal film layer is made to have a length in the first direction that is greater than the gap between the pixel electrodes of two adjacent pixel driving circuits in the first direction, and overlaps with the two adjacent pixel electrodes in the second direction. The first direction is defined as follows: Figure 2 The second direction is defined as the horizontal direction of the cross-sectional view of the pixel layout shown. Figure 2 The vertical direction of the cross-sectional view of the pixel layout is shown.

[0039] Furthermore, the edge of the metal film layer is made to extend beyond the edge of the pixel electrode by a preset distance in the first direction, and the preset distance is greater than the alignment accuracy between the pixel electrode and the metal film layer, so as to prevent the alignment deviation from causing the metal film layer to fail to completely shield the leaked light.

[0040] Furthermore, the method for manufacturing the channel region, the first source and drain, and the second source and drain of the first transistor M1 is: after forming a polysilicon active layer pattern, using a mask, the channel region, the first source and drain, and the second source and drain of the first transistor are obtained by a heavy doping process. It should be noted that the first source and drain and the second source and drain are the two ends of the first transistor M1, and because the source and drain are reversed in different working states, they are described as "the first source and drain" and "the second source and drain".

[0041] Furthermore, the panel manufacturing method further includes: coupling the first signal line to the first source and drain of the first transistor through a transfer hole process, and coupling the second signal line to the second source and drain of the first transistor through a transfer hole process.

[0042] Furthermore, the panel manufacturing method further includes: coupling the pixel electrode to a second metal layer coupled to a second source and drain of the first transistor through a transfer hole process.

[0043] The inventors consider that when designing the pixel layout, there may be a situation where the pixel electrode is mirror-symmetrical, which causes the first signal line data to overlap with the pixel electrode in the second direction. Therefore, Figure 3 and Figure 4 As shown, the present invention provides a preferred embodiment, specifically, the metal film layer and the first signal lines of two adjacent pixel driving circuits are used together as a shading module, and the metal film layer is made to have a length in the first direction that is greater than the gap between the first signal lines of two adjacent pixel driving circuits in the first direction, and overlaps with the two adjacent first signal lines in the second direction. Furthermore, in the second direction, the shading module overlaps with the two adjacent pixel electrodes. And, in the first direction, the edge of the shading module is made to exceed the edge of the pixel electrode by a preset distance, and the preset distance is greater than the alignment accuracy between the pixel electrode and the first signal line.

[0044] Correspondingly, the present invention provides a BM-less display panel, comprising: a glass substrate; a metal film layer located on the glass substrate and a whole-surface barrier layer located on the metal film layer; a buffer layer arranged on the barrier layer; a polysilicon active layer pattern formed on the buffer layer, constituting a channel region, a first source and a drain, and a second source and a drain of a first transistor; a gate insulating layer arranged on the active layer, and a gate metal pattern and a gate signal line on the gate insulating layer, constituting a control end of the first transistor; a first interlayer insulating layer located on the gate metal pattern; a second metal layer, a first signal line, and a second signal line formed on the first interlayer insulating layer; an organic planar layer formed entirely on the second metal layer, and a pixel electrode arranged on the planar layer.

[0045] Accordingly, if Figure 5 and Figure 6 As shown, the present invention provides a preferred embodiment, a BM-less panel manufacturing method, comprising: A metal film layer BSM and a full-surface barrier layer Barrier are sequentially formed on a glass substrate Glass, wherein the full-surface barrier layer is used to prevent the influence of impurities in the substrate on the TFT channel.

[0046] A buffer layer Buffer is formed on the barrier layer to ensure the flatness of the channel and prevent substrate impurities from being blocked, thereby ensuring the stability of the formed TFT.

[0047] A polysilicon active layer pattern is formed on the buffer layer to obtain a channel region, a first source and a drain electrode, and a second source and a drain electrode of the first transistor M1. It should be noted here that since the core invention of the present invention is to construct a metal film layer BSM, and forming a polysilicon active layer pattern and a gate metal pattern belongs to the conventional prior art in this field, those skilled in the art clearly know how to construct a polysilicon active layer pattern and a gate metal pattern. Therefore, in order to focus on the setting method of the metal film layer BSM, the following is selected. Figure 2 The cross-sectional view shown does not show the polysilicon active layer pattern and the gate metal pattern.

[0048] A gate insulating layer GI is formed entirely on the active layer.

[0049] A gate metal pattern and a gate signal line are formed on the gate insulating layer to constitute a control terminal of the first transistor.

[0050] A first interlayer insulating layer Insulator is formed entirely on the gate metal pattern.

[0051] A second metal layer, a first signal line data, and a second signal line are formed on the first interlayer insulating layer.

[0052] An organic planar layer is formed entirely on the second metal layer, and a common electrode Com ITO is formed on the planar layer.

[0053] A third metal layer pattern Com Mo is formed on the common electrode Com ITO.

[0054] A second interlayer insulating layer SiNx is formed on the entire surface of the third metal layer, and a pixel electrode Com ITO is formed on the second interlayer insulating layer SiNx, and the pixel electrode is coupled to the second metal layer coupled to the second end of the first transistor M1 through a transfer hole process, thereby coupling the pixel electrode to the first transistor M1.

[0055] Furthermore, the edge of the third metal layer exceeds the edge of the pixel electrode by a distance, and the distance is greater than the alignment accuracy between the pixel electrode and the third metal layer. In this preferred embodiment, the pixel light emitting area is determined by the light transmission area of ​​the third metal layer. At the same time, the third metal layer can also reduce the impedance of the common electrode Com ITO and improve the voltage stabilization capability of the Com signal.

[0056] Furthermore, the inventor proposes that in this embodiment, the third metal layer pattern Com Mo may not be set between adjacent pixels in the third direction, or when the third metal layer pattern Com Mo is set, the third metal layer pattern does not overlap with the pixel electrode in the second direction. The reason is that the electric field state of the gap between adjacent pixels in the third direction is between the electric field states of two adjacent pixel electrodes. In this case, even if the gap is not shielded, it will not affect the final light output quality, and will not cause a decrease in image contrast or uneven color mixing. Among them, the third direction is defined as follows Figure 5 In the layout plan shown, the direction is perpendicular to the slit in the pixel electrode.

[0057] The above is a BM-less panel manufacturing method and a display panel provided in an embodiment of the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

[0058] Professionals may further realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention. The steps of the method or algorithm described in conjunction with the embodiments disclosed herein can be directly implemented with a software module executed by a hardware or processor, or a combination of the two. The software module can be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the technical field.

Claims

1. A method for manufacturing a BM-less panel, characterized in that: include: forming a metal film layer and a whole-surface barrier layer on a glass substrate in sequence; forming a buffer layer on the barrier layer; Forming a polysilicon active layer pattern on the buffer layer to obtain a channel region, a first source and a drain, and a second source and a drain of the first transistor; forming a gate insulating layer entirely on the active layer; forming a gate metal pattern and a gate signal line on the gate insulating layer to constitute a control terminal of the first transistor; forming a first interlayer insulating layer entirely on the gate metal pattern; forming a second metal layer, a first signal line and a second signal line on the first interlayer insulating layer; An organic planar layer is entirely formed on the second metal layer, and a pixel electrode is formed on the planar layer.

2. The panel manufacturing method according to claim 1, characterized in that: When the metal film layer is used as a shading module, the metal film layer is made to have a length in the first direction greater than the gap between the pixel electrodes of two adjacent pixel driving circuits in the first direction, and overlaps with the two adjacent pixel electrodes in the second direction.

3. The panel manufacturing method according to claim 2, characterized in that: The edge of the metal film layer is manufactured to extend beyond the edge of the pixel electrode by a preset distance in a first direction, and the preset distance is greater than the alignment accuracy between the pixel electrode and the metal film layer.

4. The panel manufacturing method according to claim 1, characterized in that: The method for making the channel region, the first source and drain, and the second source and drain of the first transistor is: after forming a polysilicon active layer pattern, using a mask plate, and obtaining the channel region, the first source and drain, and the second source and drain of the first transistor through a heavy doping process.

5. The panel manufacturing method according to claim 1, characterized in that: The panel manufacturing method further includes: coupling the first signal line to the first source and drain of the first transistor through a via hole process, and coupling the second signal line to the second source and drain of the first transistor through a via hole process.

6. The panel manufacturing method according to claim 5, characterized in that: The panel manufacturing method further includes: coupling the pixel electrode to a second metal layer coupled to a second source and drain of the first transistor through a transfer hole process.

7. The panel manufacturing method according to claim 1, characterized in that: When the metal film layer and the first signal lines of two adjacent pixel driving circuits are used together as a shading module, the metal film layer is made to have a length in the first direction that is greater than the gap between the first signal lines of two adjacent pixel driving circuits in the first direction, and overlaps with the two adjacent first signal lines in the second direction.

8. The panel manufacturing method according to claim 7, characterized in that: In the second direction, the shading module overlaps with two adjacent pixel electrodes.

9. The panel manufacturing method according to claim 7, characterized in that: In the first direction, the edge of the light shielding module is manufactured to exceed the edge of the pixel electrode by a preset distance, and the preset distance is greater than the alignment accuracy between the pixel electrode and the first signal line.

10. A BM-less display panel, characterized in that: include: Glass substrate; A metal film layer located on the glass substrate and a full-surface barrier layer located on the metal film layer; a buffer layer disposed on the barrier layer; The polysilicon active layer pattern formed on the buffer layer constitutes the channel region, the first source and drain, and the second source and drain of the first transistor; A gate insulating layer disposed on the active layer, and a gate metal pattern and a gate signal line on the gate insulating layer, forming a control terminal of the first transistor; a first interlayer insulating layer located on the gate metal pattern; a second metal layer, a first signal line, and a second signal line formed on the first interlayer insulating layer; An organic planar layer is formed entirely on the second metal layer, and a pixel electrode is disposed on the planar layer.

11. A method for manufacturing a BM-less panel, characterized in that: include: forming a metal film layer and a whole-surface barrier layer on a glass substrate in sequence; forming a buffer layer on the barrier layer; Forming a polysilicon active layer pattern on the buffer layer to obtain a channel region, a first source and a drain, and a second source and a drain of the first transistor; forming a gate insulating layer entirely on the active layer; forming a gate metal pattern and a gate signal line on the gate insulating layer to constitute a control terminal of the first transistor; forming a first interlayer insulating layer entirely on the gate metal pattern; forming a second metal layer, a first signal line and a second signal line on the first interlayer insulating layer; forming an organic planar layer on the entire surface of the second metal layer, and forming a common electrode on the planar layer; forming a third metal layer pattern on the common electrode; A second interlayer insulating layer is entirely formed on the third metal layer, and a pixel electrode is formed on the second interlayer insulating layer.

Images