Driving substrate, driving method thereof and display panel

Abstract

The invention provides a driving substrate and a display panel, and relates to the technical field of display, and the driving substrate comprises a substrate and a plurality of sub-pixels which are located at one side of the substrate and are arranged in an array; a plurality of data lines, a plurality of first grid lines and a plurality of second grid lines; the data lines are located between two adjacent columns of sub-pixels; the data lines are electrically connected with the sub-pixels in the same column; the first grid lines are located between two adjacent rows of sub-pixels; the second grid lines are located between two adjacent rows of sub-pixels; wherein the plurality of sub-pixels comprise a plurality of first sub-pixels and a plurality of second sub-pixels, at least one column of first sub-pixels is electrically connected with the first grid line and the second grid line at the same time, and at least one column of second sub-pixels is electrically connected with one of the first grid line and the second grid line. According to the driving substrate, the aperture opening ratio of the display panel can be reduced, the number of source electrode driving chips can be reduced, and balance between the source electrode driving chips and the source electrode driving chips is achieved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving substrate and a driving method thereof, and a display panel. Background Art

[0002] With the rapid development of various display technologies, customers have higher and higher requirements for the display performance of display products. For liquid crystal display products, the relevant technology adjusts the gate driving method to reduce the number of source driver chips (SourceIC), thereby greatly reducing the cost of display products.

[0003] However, the adjustment of the gate driving mode is accompanied by a reduction in the aperture ratio, which has a great negative impact on the transmittance of the display product and reduces the display effect of the display product. Summary of the invention

[0004] The embodiments of the present application provide a driving substrate and a display panel. The driving substrate can reduce the aperture ratio of the display panel and can also reduce the number of source driver chips (Source ICs) and achieve a balance between the two.

[0005] The embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a driving substrate, the driving substrate comprising:

[0007] A substrate, and a plurality of sub-pixels arranged in an array on one side of the substrate;

[0008] A plurality of data lines, wherein the data lines are located between two adjacent columns of the sub-pixels; and the data lines are electrically connected to the sub-pixels in the same column;

[0009] A plurality of first gate lines, wherein the first gate lines are located between two adjacent rows of sub-pixels;

[0010] A plurality of second gate lines, wherein the second gate lines are located between two adjacent rows of sub-pixels;

[0011] The plurality of sub-pixels include a plurality of first sub-pixels and a plurality of second sub-pixels, at least one column of the first sub-pixels is electrically connected to both the first gate line and the second gate line, and at least one column of the second sub-pixels is electrically connected to one of the first gate line and the second gate line.

[0012] In some embodiments, the first sub-pixel includes a first transistor and a second transistor electrically connected, the first transistor being electrically connected to the first gate line and a storage capacitor of the first sub-pixel, respectively, and the second transistor being electrically connected to the second gate line and the data line, respectively.

[0013] In some embodiments, the driving substrate comprises:

[0014] A source-drain conductive layer, the source-drain conductive layer is located on one side of the substrate and includes a light shielding pattern and the data line;

[0015] A semiconductor layer, the semiconductor layer is located on a side of the source-drain conductive layer away from the substrate, and includes a source electrode, a drain electrode and a semiconductor pattern of a transistor;

[0016] A gate layer, the gate layer is located on a side of the semiconductor layer away from the substrate, and includes a plurality of lap electrodes, a gate of the transistor and a gate line; the lap electrode is used to electrically connect the source of the transistor and the data line together;

[0017] A common electrode layer, the common electrode layer is located on the first side of the gate layer away from the substrate, and includes a common electrode and a first electrode of the storage capacitor of the sub-pixel;

[0018] A pixel electrode layer is located at a side of the common electrode layer away from the substrate, and comprises a pixel electrode and a second electrode of the storage capacitor of the sub-pixel.

[0019] In some embodiments, the first gate line is configured to transmit a first gate control signal, and the second gate line is configured to transmit a second gate control signal;

[0020] The first gate control signal and the second gate control signal partially overlap in the same time period.

[0021] In some embodiments, the first sub-pixel includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, and the second sub-pixel also includes the first color sub-pixel, the second color sub-pixel and the third color sub-pixel; the sub-pixels of the same color are arranged in the same column;

[0022] The first sub-pixels each include the first transistor and the second transistor;

[0023] Each of the second sub-pixels includes a third transistor, and the third transistor is electrically connected to one of the first gate line and the second gate line, the data line, and a storage capacitor of the second sub-pixel.

[0024] In some embodiments, the first color sub-pixels in the first sub-pixels, the second color sub-pixels in the second sub-pixels, and the third color sub-pixels in the second sub-pixels are sequentially arranged cyclically along a row direction.

[0025] In some embodiments, the first color subpixel in the first subpixel, the second color subpixel in the second subpixel, the third color subpixel in the second subpixel, the first color subpixel in the second subpixel, the second color subpixel in the second subpixel, the third color subpixel in the first subpixel, the first color subpixel in the second subpixel, the second color subpixel in the first subpixel, and the third color subpixel in the second subpixel are sequentially arranged cyclically along a row direction;

[0026] The data line electrically connected to the first color sub-pixel in the nth column, the data line electrically connected to the first color sub-pixel in the n+1th column, and the data line electrically connected to the first color sub-pixel in the n+2th column are electrically connected together;

[0027] The data line electrically connected to the second color sub-pixel in the nth column, the data line electrically connected to the second color sub-pixel in the n+1th column, and the data line electrically connected to the second color sub-pixel in the n+2th column are electrically connected together;

[0028] The data line electrically connected to the third color sub-pixel in the nth column, the data line electrically connected to the third color sub-pixel in the n+1th column, and the data line electrically connected to the third color sub-pixel in the n+2th column are electrically connected together; n is a positive integer.

[0029] In some embodiments, the first gate control signal and the second gate control signal have the same period and duty cycle, and within one-third of the period, the first gate control signal and the second gate control signal are configured to simultaneously output high-level signals.

[0030] In some embodiments, the gate layer includes the first gate line and the second gate line, each transistor is located in a region between the first gate line and the second gate line, and the second gate line overlaps with an orthographic projection of the pixel electrode on the substrate;

[0031] The gate of the first transistor is electrically connected to the first gate line, the drain of the first transistor is electrically connected to the second electrode of the storage capacitor in the first sub-pixel, and the source of the first transistor is electrically connected to the drain of the second transistor;

[0032] The gate of the second transistor is electrically connected to the second gate line, the source of the second transistor is electrically connected to the data line through the bonding electrode, and the source of the first transistor and the drain of the second transistor are an integrated structure;

[0033] The gate of the third transistor is electrically connected to the first gate line or the second gate line, the source of the third transistor is electrically connected to the data line through the bonding electrode, and the drain of the third transistor is electrically connected to the second electrode of the storage capacitor in the second sub-pixel.

[0034] In some embodiments, a plurality of the bonding electrodes are disposed between two adjacent first gate lines and the second gate lines, and the plurality of bonding electrodes between two adjacent first gate lines and the second gate lines are disposed in the same row.

[0035] In some embodiments, in the second sub-pixel, the third transistor electrically connected to the first gate line is called a first switch tube, and the third transistor electrically connected to the second gate line is called a second switch tube;

[0036] Wherein, the area of ​​an overlapped region between the orthographic projection of the first switch tube on the substrate and the orthographic projection of the pixel electrode in the same sub-pixel on the substrate is smaller than the area of ​​an overlapped region between the orthographic projection of the second switch tube on the substrate and the orthographic projection of the pixel electrode in the same sub-pixel on the substrate;

[0037] Along a direction parallel to a plane where the substrate is located, a minimum distance between the semiconductor pattern of the first switch tube and the first gate line is smaller than a minimum distance between the semiconductor pattern of the second switch tube and the first gate line.

[0038] In some embodiments, the driving substrate includes a plurality of the first gate lines, a plurality of the second gate lines, and a plurality of third gate lines;

[0039] At least one row of the first sub-pixels is electrically connected to two of the first gate line, the second gate line and the third gate line at the same time.

[0040] In some embodiments, the first sub-pixel includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, and the second sub-pixel also includes the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel;

[0041] The sub-pixels of the same color are arranged in the same column, and the first color sub-pixel, the second color sub-pixel and the third color sub-pixel in the first sub-pixel, and the first color sub-pixel, the second color sub-pixel and the third color sub-pixel in the second sub-pixel are arranged cyclically in sequence along the row direction;

[0042] In the first sub-pixel, the first color sub-pixel includes the first transistor and the second transistor which are electrically connected, the first transistor is electrically connected to the first gate line and the data line respectively, and the second transistor is electrically connected to the second gate line and the storage capacitor of the first color sub-pixel respectively;

[0043] In the first sub-pixel, the second color sub-pixel includes a third transistor and a fourth transistor electrically connected, the third transistor is electrically connected to the second gate line and the data line respectively, and the fourth transistor is electrically connected to the third gate line and the storage capacitor of the second color sub-pixel respectively;

[0044] In the first subpixel, the third color subpixel includes a fifth transistor and a sixth transistor electrically connected, the fifth transistor is electrically connected to the third gate line and the data line respectively, and the sixth transistor is electrically connected to the first gate line and the storage capacitor of the third color subpixel respectively.

[0045] In some embodiments, in the second sub-pixel, the first color sub-pixel includes a seventh transistor, the second color sub-pixel includes an eighth transistor, and the third color sub-pixel includes a ninth transistor;

[0046] Among them, the seventh transistor is electrically connected to the second gate line, the data line and the storage capacitor of the first color sub-pixel respectively, the eighth transistor is electrically connected to the first gate line, the data line and the storage capacitor of the second color sub-pixel respectively, and the ninth transistor is electrically connected to the third gate line, the data line and the storage capacitor of the third color sub-pixel respectively.

[0047] In some embodiments, the third gate line is configured to transmit a third gate control signal;

[0048] The second gate control signal and the third gate control signal have the same period, the first gate control signal has a period that is one third of the period of the second gate control signal, and the first gate control signal, the second gate control signal and the third gate control signal have the same duty cycle.

[0049] In some embodiments, in a first time period, the first gate control signal and the second gate control signal are configured to simultaneously output high-level signals; in a second time period, the second gate control signal and the third gate control signal are configured to simultaneously output high-level signals; in a third time period, the first gate control signal and the third gate control signal are configured to simultaneously output high-level signals; in a fourth time period, the second gate control signal is configured to output a high-level signal; in a fifth time period, the first gate control signal is configured to output a high-level signal; in a sixth time period, the third gate control signal is configured to output a high-level signal;

[0050] The first time period, the second time period, the third time period, the fourth time period, the fifth time period and the sixth time period are all half of the period of the first gate control signal.

[0051] In some embodiments, orthographic projections of two of the first gate line, the second gate line, and the third gate line on the substrate intersect.

[0052] In some embodiments, the first gate line and the second gate line intersect with each other in their orthographic projections on the substrate.

[0053] The first transistor and the second transistor are located between the first gate line and the second gate line; the third transistor and the fourth transistor are located between the second gate line and the third gate line;

[0054] In the first sub-pixel, a bridge portion is provided between two adjacent third color sub-pixels along the column direction, the bridge portion is located in the source-drain conductive layer, and the first gate line and the second gate line are swapped through the bridge portion; the fifth transistor and the sixth transistor are located between the first gate line and the third gate line;

[0055] The seventh transistor is located between the second gate line and the first gate line, the eighth transistor is located between the second gate line and the first gate line, and the ninth transistor is located between the first gate line and the third gate line.

[0056] In some embodiments, in the second color sub-pixel and the third color sub-pixel in the first sub-pixel, and in the second color sub-pixel and the third color sub-pixel in the second sub-pixel, the strapping electrodes are arranged in the same row;

[0057] In the first color sub-pixel in the first sub-pixel and the first color sub-pixel in the second sub-pixel, the bonding electrodes are arranged in the same row.

[0058] In some embodiments, the drain of the first transistor and the source of the second transistor are an integrated structure, the drain of the third transistor and the source of the fourth transistor are an integrated structure, and the drain of the fifth transistor and the source of the sixth transistor are an integrated structure.

[0059] In a second aspect, an embodiment of the present application provides a display panel, comprising a driving substrate as described in any one of the first aspects.

[0060] In a third aspect, an embodiment of the present application provides a driving method for driving a driving substrate as described in any one of the first aspects, the method comprising:

[0061] Under the common control of the first gate control signal and the second gate control signal, the driving chip inputs a first data signal to the first sub-pixel electrically connected to the first gate line and the second gate line at the same time;

[0062] The driving chip inputs a second data signal to the second sub-pixel electrically connected to one of the first gate line and the second gate line;

[0063] The driving chip inputs a third data signal to the second sub-pixel electrically connected to the other one of the first gate line and the second gate line.

[0064] Embodiments of the present application provide a driving substrate and a driving method, and a display panel, wherein the driving substrate comprises a substrate, and a plurality of sub-pixels arranged in an array on one side of the substrate; a plurality of data lines, a plurality of first gate lines, and a plurality of second gate lines; the data lines are located between two adjacent columns of the sub-pixels; the data lines are electrically connected to the sub-pixels in the same column; the first gate line is located between two adjacent rows of the sub-pixels; the second gate line is located between two adjacent rows of the sub-pixels; wherein the plurality of sub-pixels comprise a plurality of first sub-pixels and a plurality of second sub-pixels, at least one column of the first sub-pixels is electrically connected to both the first gate line and the second gate line, and at least one column of the second sub-pixels is electrically connected to one of the first gate line and the second gate line.

[0065] In the present application, a plurality of sub-pixels are provided, including a plurality of first sub-pixels and a plurality of second sub-pixels, at least one column of first sub-pixels is electrically connected to the first gate line and the second gate line at the same time, and at least one column of second sub-pixels is electrically connected to one of the first gate line and the second gate line; in this way, the first sub-pixels can be driven simultaneously by the first gate line and the second gate line, some of the second sub-pixels can be driven by the first gate line, and some of the second sub-pixels can be driven by the second gate line; compared with the driving substrate with a small number of driving chips in a multi-gate line design in the related art, the driving substrate provided in the present application reduces the number of gate lines without increasing the number of driving chips, thereby greatly increasing the aperture ratio, improving the light transmittance of the driving substrate, and further improving the display effect of the display panel.

[0066] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments or descriptions of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0068] Figure 1A to Figure 1C A simplified schematic diagram of three display devices in the related art provided for the embodiments of the present application;

[0069] Figure 1D A schematic diagram of a driving architecture of a driving substrate in the related technology provided by an embodiment of the present application;

[0070] Figure 1E for Figure 1D Timing diagram of

[0071] Figure 2B A pixel design diagram of a single gate line drive in a related technology provided in an embodiment of the present application;

[0072] Figure 2A for Figure 2B A partial enlarged view of the ellipse area;

[0073] Figure 3A A pixel design diagram of a three-gate line drive in a related technology provided in an embodiment of the present application;

[0074] Figure 3B for Figure 3AA partial enlarged view of the ellipse area;

[0075] Figure 4A and Figure 4B Schematic diagram of the driving architecture of two driving substrates provided in the embodiments of the present application;

[0076] Figure 5 for Figure 4B Timing diagram of

[0077] Fig. 6A A pixel design diagram of two gate line drive provided in an embodiment of the present application;

[0078] Figure 6B for Fig. 6A A partial enlarged view of the area enclosed by the middle rectangular frame;

[0079] Figure 6C For Figure 6B A pixel design diagram after a black matrix layer BM is set on the basis;

[0080] Fig.6D for Figure 6B Schematic diagram of the cross-sectional structure along the M1M2 direction;

[0081] Fig. 7A A schematic diagram of a driving architecture of a driving substrate in another related technology provided for an embodiment of the present application;

[0082] Figure 7B for Fig. 7A Timing diagram of

[0083] Figure 8 A schematic diagram of a driving architecture of three-gate line driving provided in an embodiment of the present application;

[0084] Fig. 9 for Figure 8 Timing diagram of

[0085] Fig.10 A pixel design diagram of a three-gate line drive provided in an embodiment of the present application;

[0086] Fig.11 for Fig.10 A partial enlarged view of the first three sub-pixels at the gate line position;

[0087] Fig.12 for Fig.10 A partial enlarged view of the last three sub-pixels at the gate line position. Specific embodiments

[0088] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0089] In the embodiments of the present application, words such as "first", "second", "third", and "fourth" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application and shall not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0090] In the embodiments of the present application, the terms "upper", "lower", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0091] In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example" or "some examples" are intended to indicate that a specific feature, structure, material or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0092] In the embodiments of the present application, “plurality” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0093] The features such as "parallel", "perpendicular", and "same" used in the embodiments of the present application include the features such as "parallel", "perpendicular", and "same" in a strict sense, as well as the cases where "approximately parallel", "approximately perpendicular", "approximately the same", etc. include certain tolerances, taking into account the tolerances related to the measurement of specific quantities (e.g., the limitations of the measurement system), and are expressed as being within the acceptable deviation range for a specific value determined by a person of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0094] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0095] The "same layer" in the embodiments of the present application refers to the relationship between multiple film layers formed by the same material after the same step (e.g., a one-step patterning process). The "same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same. The polygons in this specification are not strictly defined, and can be approximate triangles, parallelograms, trapezoids, pentagons or hexagons, etc., and there may be some small deformations caused by tolerances.

[0096] With the development of driving methods and manufacturing processes, liquid crystal displays have greatly improved production costs and picture quality. Nowadays, various driving methods such as Dula Gate Driving, Triple Gate Driving, Quadruple-Gate Driving, and Hexa Gate Driving have been proposed by including pixel arrangements of liquid crystal displays. Among them, through the improvement of the driving method, the number of source driver ICs can be greatly reduced, thereby reducing the cost of the driving substrate.

[0097] Combination Figure 1A (Single gate line drive), Figure 1B (three-gate drive) and Figure 1C As shown in Figure 1, through the improvement of the gate driving method, the number of source driver ICs is gradually reduced to one. Table 1 provides the number of source driver chips under several different driving architectures.

[0098] Table 1: Number of source driver chips (S-ICs) in display devices with different driving modes

[0099] project Single Gate( Figure 1A ) Triple Gate( Figure 1B ) Hexa Gate( Figure 1C ) S-IC quantity 6 2 1 piece

[0100] Figure 1D A schematic diagram of a driving architecture of a driving substrate in the related art is provided, wherein the driving technology of TripleGate Driving sets three gate lines between two adjacent rows of sub-pixels, sets one data line between two adjacent columns of sub-pixels, and sets three columns of sub-pixels of the same color as a group, and the data lines electrically connected to the three columns of sub-pixels in the same group are electrically connected together in the fan-out area and share a source signal line (for example, the data lines electrically connected to the red sub-pixels from the first column to the third column are electrically connected together in the fan-out area and share the signal line Source1). The change in the gate line setting method is combined with the following: Figure 1E The driving timing shown can realize the normal operation of the driving substrate and greatly reduce the number of source driver ICs.

[0101] However, as the number of gate lines increases, the design space between two adjacent rows of sub-pixels becomes smaller and the aperture ratio decreases, resulting in increased power consumption and reduced display effect.

[0102] in, Figure 2B A pixel design diagram of a 1G1D (one gate line and one data line) driving substrate in the related art is provided. Figure 2A for Figure 2B A partial enlarged view of the middle elliptical area. Figure 3A This is a pixel design diagram of a Triple Gate (three-gate line drive) driving substrate in the related art. Figure 3B for Figure 3A A partial enlarged view of the middle elliptical area.

[0103] exist Figure 2A and Figure 3B In the figure, a is the width of the black matrix layer BM disposed on the gate line GL, b is the width of the gate line GL, c is the width between the gate line GL and the overlapping electrode DJ disposed on the same layer, d is the width of the via hole Via connecting the data line DL and the drain electrode of the transistor TFT, and e is the width of the gate electrode of the transistor TFT. The aperture ratio of the driving substrate is mainly determined by a, and the size of a is jointly determined by b, c, d, and e.

[0104] Table 2: Comparison of design parameters and aperture ratios of two types of drive substrates in related technologies

[0105] project a Opening rate 1G1D 19μm 80％ Triple Gate 31.5μm 72％

[0106] As shown in Table 2, the design benchmarks of transistors, vias and routing of the two driving substrates are consistent. However, due to the increase in the number of gate lines of the driving substrate of Triple Gate technology, the BM width is increased and the aperture ratio of the driving substrate is reduced from 80% to 72%.

[0107] Based on this, an embodiment of the present application provides a driving substrate, such as Figure 4A , Figure 4B or Figure 8 As shown, the driving substrate includes:

[0108] A substrate 100, and a plurality of sub-pixels P arranged in an array on one side of the substrate;

[0109] A plurality of data lines DL, wherein the data lines DL are located between two adjacent columns of sub-pixels P; the data lines DL are electrically connected to the sub-pixels P in the same column;

[0110] A plurality of first gate lines G1 (or GL1), wherein the first gate lines G1 are located between two adjacent rows of sub-pixels P;

[0111] A plurality of second gate lines G2 (or GL2), wherein the second gate lines G2 are located between two adjacent rows of sub-pixels P;

[0112] Among them, the multiple sub-pixels P include multiple first sub-pixels P1 and multiple second sub-pixels P2, at least one column of first sub-pixels P1 is electrically connected to the first gate line G1 and the second gate line G2 at the same time, and at least one column of second sub-pixels P2 is electrically connected to one of the first gate line G1 and the second gate line G2.

[0113] In an exemplary embodiment, the above-mentioned driving substrate can be applied to a liquid crystal display panel (Liquid Crystal Display, LCD), for example, a twisted nematic (Twisted Nematic, TN) type, a vertical alignment (Vertical Alignment, VA) type, an in-plane switching (In Plane Switching, IPS) type, and an advanced super-dimensional field switch (ADS, Advanced Super Dimension Switch) type liquid crystal display panel.

[0114] For example, the specific material of the substrate 1 of the driving substrate is not limited here. For example, the substrate can be any one of silicon, glass, quartz, PET, plastic and the like.

[0115] The arrangement of the sub-pixels is not limited here and can be specifically determined according to the design of the actual product.

[0116] Exemplarily, the sub-pixels may include sub-pixels of three colors, for example, a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0117] In some embodiments, sub-pixels of the same color are located in the same row. For example, multiple red sub-pixels are located in the same row, multiple green sub-pixels are located in the same row, and multiple blue sub-pixels are located in the same row; for another example, multiple red sub-pixels are located in the same column, multiple green sub-pixels are located in the same column, and multiple blue sub-pixels are located in the same column.

[0118] In some other embodiments, the same row of sub-pixels includes sub-pixels of at least two colors. For example, the same row of sub-pixels may include sub-pixels of two colors, or the same row of sub-pixels may include sub-pixels of three colors.

[0119] The shape of the orthographic projection of the sub-pixel on the substrate 1 is not limited here. For example, the shape of the orthographic projection of the sub-pixel on the substrate 1 is roughly a rectangle, a parallelogram, or a hexagon. The embodiment of the present application is drawn by taking the shape of the orthographic projection of the sub-pixel on the substrate 1 as a roughly rectangular shape as an example.

[0120] The specific structures of the gate lines GL and the data lines DL included in the driving substrate are not limited here.

[0121] Exemplarily, the gate line GL may include a straight line segment, or include a bending structure formed by a plurality of straight line segments; the specific structure may be determined according to actual design.

[0122] Exemplarily, the data line DL may include a straight line segment, or include a bent structure formed by a plurality of straight line segments, which may be specifically determined according to actual design.

[0123] Among them, at least one column of first sub-pixels P1 is electrically connected to the first gate line G1 and the second gate line G2 at the same time, and at least one column of second sub-pixels P2 is electrically connected to one of the first gate line G1 and the second gate line G2. It can be understood that the following situations may be included:

[0124] In the first type, at least one column of first sub-pixels P1 is driven by the first gate line G1 and the second gate line G2 at the same time, and at least one column of second sub-pixels P2 is driven by the first gate line G1.

[0125] The second type is that at least one column of first sub-pixels P1 is driven by the first gate line G1 and the second gate line G2 at the same time, and at least one column of second sub-pixels P2 is driven by the second gate line G2.

[0126] Third, there is at least one column of first sub-pixels P1 driven by the first gate line G1 and the second gate line G2 simultaneously, there is at least one column of second sub-pixels P2 driven by the first gate line G1, and there is at least one column of second sub-pixels P2 driven by the second gate line G2.

[0127] In the driving substrate provided in the embodiment of the present application, a plurality of sub-pixels P are provided, including a plurality of first sub-pixels P1 and a plurality of second sub-pixels P2, at least one column of the first sub-pixels P1 is electrically connected to the first gate line G1 and the second gate line G2 at the same time, and at least one column of the second sub-pixels P2 is electrically connected to one of the first gate line G1 and the second gate line G2; in this way, the first sub-pixel P1 can be driven simultaneously by the first gate line G1 and the second gate line G2, part of the second sub-pixels P2 can be driven by the first gate line G1, and part of the second sub-pixels P2 can be driven by the second gate line G2; compared with the driving substrate with a small number of driving chips of the multi-gate line design in the related art (for example Figure 1D The driving substrate provided in the present application reduces the number of gate lines GL without increasing the number of driving chips, thereby greatly increasing the aperture ratio and the light transmittance of the driving substrate, thereby improving the display effect of the display panel.

[0128] In some embodiments, Figure 4A , Figure 4B or Figure 8As shown, the first subpixel P1 includes a first transistor T1 and a second transistor T2 that are electrically connected. The first transistor T1 is electrically connected to the first gate line G1 and the storage capacitor Cst of the first subpixel P1, respectively. The second transistor T2 is electrically connected to the second gate line G2 and the data line DL, respectively.

[0129] In practical applications, the first transistor T1 can be turned on and off by the signal provided by the first gate line G1, so that the connection and disconnection between the storage capacitor Cst of the first sub-pixel P1 and the second transistor T2 can be controlled; the second transistor T2 can be turned on and off by the signal provided by the second gate line G2, so that the connection and connection between the data line DL and the first transistor can be controlled. In this way, with the cooperation of the first transistor T1 and the second transistor T2, the signal transmitted by the data line DL can be controlled to be written into the storage capacitor Cst of the first sub-pixel P1 to complete the charging process of the first sub-pixel P1.

[0130] In some embodiments, in combination Figure 6B , Figure 6C and Fig.6D As shown, the driving substrate includes:

[0131] A source-drain conductive layer SD, the source-drain conductive layer SD is located at one side of the substrate 100 and includes a light shielding pattern Shield and a data line DL;

[0132] A semiconductor layer (eg, IGZO), the semiconductor layer is located on a side of the source-drain conductive layer SD away from the substrate 100, and includes a source S, a drain D and a semiconductor pattern Active of the transistor;

[0133] The gate layer Gate is located on a side of the semiconductor layer (eg, IGZO) away from the substrate 100 and includes a plurality of bonding electrodes DJ, a gate Gate of the transistor, and a gate line GL; Fig.6D As shown, the bonding electrode DJ is used to electrically connect the source electrode S of the transistor and the data line DL;

[0134] A common electrode layer CITO, the common electrode layer CITO is located at a first side of the gate layer Gate away from the substrate 100, and includes a common electrode and a first electrode of a storage capacitor Cst of a sub-pixel;

[0135] The pixel electrode layer PITO is located at a side of the common electrode layer CITO away from the substrate 100 and includes a pixel electrode and a second electrode of a storage capacitor Cst of a sub-pixel.

[0136] The specific materials of the source-drain conductive layer SD and the gate layer Gate are not limited here.

[0137] For example, the material of the gate layer Gate may include copper, and may be formed into a stacked structure such as MoNb / Cu / MoNb by sputtering, wherein the material on the side close to the substrate 100 is MoNb with a thickness of about 1000 mm. The material of the middle layer of the laminated structure is Cu, which is the material of the electrical signal transmission channel. The material on the side away from the substrate 100 is MoNb, with a thickness of about It can be used to protect the middle layer and prevent the surface of the middle layer with low resistivity from being exposed and oxidized. Since the thickness of a single sputtering generally does not exceed 1μm, multiple sputterings are required to form the gate line GL with a thickness exceeding 1μm. In addition, it can also be formed by electroplating. Specifically, a seed layer can be formed using MoNiTi to increase the nucleation density of metal grains in the subsequent electroplating process, and then copper with low resistivity is produced by electroplating, and then an anti-oxidation layer is produced. The material can be MoNiTi.

[0138] Exemplarily, the material of the source-drain conductive layer SD may be the same as the material of the gate layer Gate.

[0139] Exemplarily, the material of the semiconductor layer may include silicon material or oxide semiconductor material, such as single crystal silicon, polycrystalline silicon or indium gallium zinc oxide (IGZO).

[0140] The semiconductor layer (eg IGZO) includes a source S, a drain D and a semiconductor pattern Active of the transistor, wherein the source S and the drain D of the transistor are conductor regions in the semiconductor layer, which are regions that have been conductorized, and the semiconductor pattern Active is a semiconductor region in the semiconductor layer.

[0141] It should be noted that if Fig.6D As shown, the jumper electrode DJ is used to electrically connect the source electrode S of the transistor and the data line DL together, so as to avoid the problem of large resistance of the connecting via hole when the source electrode S and the data line DL arranged in the semiconductor layer are directly electrically connected together.

[0142] In some embodiments, the first gate line GL1 (or G1) is configured to transmit a first gate control signal Gate1, and the second gate line GL2 (or G2) is configured to transmit a second gate control signal Gate2;

[0143] Among them, combined Figure 5 and Fig. 9 As shown, the first gate control signal Gate1 and the second gate control signal Gate2 partially overlap in the same time period.

[0144] In some embodiments, Figure 4A and Figure 4B As shown, the first sub-pixel P1 includes a first color sub-pixel (e.g., R), a second color sub-pixel (e.g., G), and a third color sub-pixel (e.g., B), and the second sub-pixel P2 also includes a first color sub-pixel (e.g., R), a second color sub-pixel (e.g., G), and a third color sub-pixel (e.g., B); sub-pixels of the same color are arranged in the same column;

[0145] The first sub-pixels P1 each include a first transistor T1 and a second transistor T2;

[0146] Each of the second sub-pixels P2 includes a third transistor T3 , which is electrically connected to one of the first gate line G1 and the second gate line G2 , the data line DL, and the storage capacitor Cst of the second sub-pixel P2 .

[0147] In some embodiments, Figure 4A As shown, the first color sub-pixel (eg, R) in the first sub-pixel P1, the second color sub-pixel (eg, G) in the second sub-pixel P2, and the third color sub-pixel (eg, G) in the second sub-pixel P2 are sequentially arranged cyclically along the row direction.

[0148] In the embodiment of the present application, the first color sub-pixel (for example, R) in the first sub-pixel P1, the second color sub-pixel (for example, G) in the second sub-pixel P2, and the third color sub-pixel (for example, G) in the second sub-pixel P2 are sequentially arranged in a row direction in a circular manner, compared with the driving substrate (for example, Figure 1D As shown), the number of gate lines can be reduced, thereby greatly improving the aperture ratio of the driving substrate, thereby improving the display effect of the display panel and reducing power consumption.

[0149] In some embodiments, Figure 4B As shown, the first color sub-pixel (e.g., R) in the first sub-pixel P1, the second color sub-pixel (e.g., G) in the second sub-pixel P2, the third color sub-pixel (e.g., B) in the second sub-pixel P3, the first color sub-pixel (e.g., R) in the second sub-pixel P2, the second color sub-pixel (e.g., G) in the second sub-pixel P2, the third color sub-pixel (e.g., B) in the first sub-pixel P1, the first color sub-pixel (e.g., R) in the second sub-pixel P2, the second color sub-pixel (e.g., G) in the first sub-pixel P1, and the third color sub-pixel (e.g., B) in the second sub-pixel P2 are sequentially arranged cyclically along the row direction;

[0150] Wherein, in the peripheral area of ​​the driving substrate, the data line DL electrically connected to the first color sub-pixel (e.g., R) in the nth column, the data line DL electrically connected to the first color sub-pixel (e.g., R) in the n+1th column, and the data line DL electrically connected to the first color sub-pixel (e.g., R) in the n+2th column are electrically connected together, and the three share a source signal line (e.g., D1);

[0151] The data line DL electrically connected to the second color sub-pixel (e.g., G) in the nth column, the data line DL electrically connected to the second color sub-pixel (e.g., G) in the n+1th column, and the data line DL electrically connected to the second color sub-pixel (e.g., G) in the n+2th column are electrically connected together, and the three share a source signal line (e.g., D2);

[0152] The data line DL electrically connected to the third color sub-pixel (e.g., B) in the nth column, the data line DL electrically connected to the third color sub-pixel (e.g., B) in the n+1th column, and the data line DL electrically connected to the third color sub-pixel (e.g., B) in the n+2th column are electrically connected together, and the three share a source signal line (e.g., D3); n is a positive integer.

[0153] It should be noted that the first color sub-pixel, the second color sub-pixel and the third color sub-pixel can be one of a red sub-pixel, a green sub-pixel and a blue sub-pixel respectively. In the present application, the first color sub-pixel is a red sub-pixel R, the second color sub-pixel is a green sub-pixel G, and the third color sub-pixel is a blue sub-pixel B as an example for explanation and drawing.

[0154] In addition, it should be noted that the first transistor T1 , the second transistor T2 and the third transistor T3 in the driving substrate are of the same type, for example, they are all P-type transistors; or, they are all N-type transistors.

[0155] This specification uses the example and explanation of each transistor being an N-type transistor. The timing provided in this specification is also based on the timing signal corresponding to the case where each transistor is an N-type transistor. When each transistor is a P-type transistor, it can be understood that the corresponding timing is opposite to the timing currently provided.

[0156] In some embodiments, Figure 5 As shown, the first gate control signal Gate1 (cycle marked as T1) and the second gate control signal Gate2 (cycle marked as T2) have the same period and duty cycle, and within one-third of the cycle, the first gate control signal Gate1 and the second gate control signal Gate2 are configured to output high-level signals simultaneously.

[0157] The duty cycle refers to the proportion of time that the effective signal occupies in a complete cycle.

[0158] In some embodiments, Figure 5 As shown, in the first time period, the first gate control signal Gate1 and the second gate control signal Gate2 are configured to simultaneously output high-level signals; in the second time period, the first gate control signal Gate1 outputs a high-level signal, and the second gate control signal Gate2 outputs a low-level signal; in the third time period, the first gate control signal Gate1 outputs a low-level signal, and the second gate control signal Gate2 outputs a high-level signal.

[0159] It should be noted that the writing order of the data signal Data inputted by the data line DL needs to be controlled. In each row of pixel units, the sub-pixels controlled by two TFTs in series need to be written with Data first. If data is written to the sub-pixels controlled by a single TFT first, the Data of the sub-pixels controlled by the following two TFTs will overwrite the pixels controlled by the single TFT, resulting in signal mis-shooting. The writing order of the data signal Data can be set and regulated by the source driver chip, which will not be described in detail here.

[0160] In some embodiments, in combination Fig. 6A and Figure 6B As shown, the gate layer Gate includes a first gate line GL1 and a second gate line GL2, each transistor is located in a region between the first gate line GL1 and the second gate line GL2, and the second gate line GL2 overlaps with an orthographic projection of the pixel electrode PITO on the substrate 100;

[0161] The gate of the first transistor T1 (eg, Gate R) is electrically connected to the first gate line GL1, the drain D of the first transistor T1 is electrically connected to the second electrode of the storage capacitor Cst in the first sub-pixel P1, and the source S of the first transistor T1 is electrically connected to the drain D of the second transistor T2;

[0162] The gate of the second transistor T2 (for example, another Gate R) is electrically connected to the second gate line GL2, the source S of the second transistor T2 is electrically connected to the data line DL through the bonding electrode DJ, and the source S of the first transistor T1 and the drain D of the second transistor T2 are an integrated structure (in Fig. 6A Marked as D / S in the middle);

[0163] The gate of the third transistor T3 is electrically connected to the first gate line GL1 or the second gate line GL2, the source S of the third transistor T3 is electrically connected to the data line DL through the bonding electrode DJ, and the drain D of the third transistor T3 is electrically connected to the second electrode of the storage capacitor Cst in the second sub-pixel P2.

[0164] in, Figure 6B for Fig. 6A A partial enlarged view of the area enclosed by the middle rectangular frame. Figure 6C For Figure 6B Design drawing after setting a black matrix layer BM on the basis.

[0165] In some embodiments, Fig. 6A As shown, a plurality of bonding electrodes DJ are arranged between two adjacent first gate lines GL1 and second gate lines GL2 (in Figure 6B Tagged as DJ, Fig. 6A In the example, the jumper electrode DJ is located at the position marked by the source electrode S, and the jumper electrode DJ overlaps with the source electrode S, and a plurality of jumper electrodes DJ between two adjacent first gate lines GL1 and second gate lines GL2 are arranged in the same row.

[0166] Among them, the multiple overlapping electrodes DJ between two adjacent first gate lines GL1 and second gate lines GL2 are arranged in the same row. It can be understood that the geometric centers of the multiple overlapping electrodes DJ between two adjacent first gate lines GL1 and second gate lines GL2 are roughly on a straight line. The meaning of the relevant description in the following text is similar to this and will not be repeated here.

[0167] In some embodiments, Fig. 6A As shown, in the second sub-pixel P2, the third transistor T2 electrically connected to the first gate line GL1 is called the first switch tube S1, and the third transistor T3 electrically connected to the second gate line GL2 is called the second switch tube S2;

[0168] Among them, Fig. 6A or Figure 6B As shown, the area of ​​the overlapped region between the orthographic projection of the first switch tube S1 on the substrate 100 and the orthographic projection of the pixel electrode PITO in the same sub-pixel on the substrate 100 is smaller than the area of ​​the overlapped region between the orthographic projection of the second switch tube S2 on the substrate 100 and the orthographic projection of the pixel electrode PITO in the same sub-pixel on the substrate 100;

[0169] Along a direction parallel to the plane of the substrate 100 , a minimum distance between the semiconductor pattern Active of the first switch tube S1 and the first gate line GL1 is smaller than a minimum distance between the semiconductor pattern Active of the second switch tube S2 and the first gate line GL1 .

[0170] By setting in this way, the sub-pixel provided with the first switch tube can have a larger aperture ratio than the sub-pixel provided with the second switch tube, so as to improve the design flexibility of sub-pixels of different colors. For example, the blue sub-pixel can be provided with the first switch tube so that its larger aperture ratio can compensate for the low brightness of the blue light itself.

[0171] Figure 6C Provided in Figure 6BFrom the design diagram after setting the black matrix layer BM on the basis of , it can be seen that due to the reduction in the number of gate lines, as shown in the data in Table 3, the width a of the black matrix layer BM is also greatly reduced, thereby improving the aperture ratio of the driving substrate and improving the brightness and display effect of the display panel.

[0172] Table 3: Comparison of design parameters and aperture ratios of the drive substrate of the related art and the present application

[0173] project a Opening rate New Triple Gate(2Gate) 24.5μm 76.8％ Triple Gate 31.5μm 72％

[0174] In addition, if Fig. 7A As shown in the figure, under the related art Hexa Gate pixel driving architecture, six gate lines are required in the Gate direction, and the six gate lines control six sub-pixels respectively, so that the number of source driving signal lines Source can be reduced to 960ea, and one IC drive can be realized. However, due to the large number of gate lines, the aperture ratio is as low as 62%. Figure 7B for Fig. 7A The corresponding timing signal.

[0175] Based on this, the embodiments of the present application propose the following improvements:

[0176] In some embodiments, Figure 8 As shown, the driving substrate includes a plurality of first gate lines G1, a plurality of second gate lines G2 and a plurality of third gate lines G3;

[0177] At least one row of first sub-pixels P1 is electrically connected to two of the first gate line G1 , the second gate line G2 , and the third gate line G3 at the same time.

[0178] In some embodiments, Figure 8 As shown, the first sub-pixel P1 includes a first color sub-pixel (e.g., R), a second color sub-pixel (e.g., G), and a third color sub-pixel (e.g., B), and the second sub-pixel P2 also includes a first color sub-pixel (e.g., R), a second color sub-pixel (e.g., G), and a third color sub-pixel (e.g., B); sub-pixels P of the same color are arranged in the same column, and the first color sub-pixel (e.g., R), the second color sub-pixel (e.g., G), and the third color sub-pixel (e.g., B) in the first sub-pixel P1, and the first color sub-pixel (e.g., R), the second color sub-pixel (e.g., G), and the third color sub-pixel (e.g., B) in the second sub-pixel P2 are sequentially arranged cyclically along the row direction;

[0179] The following is a specific description by taking the example that the first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.

[0180] like Fig.10 and Fig.11As shown, in the first sub-pixel P1, the first color sub-pixel P1 / R includes a first transistor T1 and a second transistor T2 that are electrically connected, the first transistor T1 is electrically connected to the first gate line GL1 and the data line DL, respectively, and the second transistor T2 is electrically connected to the second gate line GL2 and the storage capacitor of the first color sub-pixel P1 / R, respectively;

[0181] like Fig.10 and Fig.11 As shown, in the first sub-pixel P1, the second color sub-pixel P1 / G includes a third transistor T3 and a fourth transistor T4 that are electrically connected, the third transistor T3 is electrically connected to the second gate line GL2 and the data line DL, respectively, and the fourth transistor T4 is electrically connected to the third gate line GL3 and the storage capacitor of the second color sub-pixel P1 / G, respectively;

[0182] like Fig.10 and Fig.11 As shown, in the first sub-pixel P1, the third color sub-pixel P1 / B includes an electrically connected fifth transistor T5 and a sixth transistor T6, the fifth transistor T5 is electrically connected to the third gate line GL3 and the data line DL respectively, and the sixth transistor T6 is electrically connected to the first gate line GL1 and the storage capacitor of the third color sub-pixel P1 / B respectively.

[0183] In some embodiments, Fig.10 and Fig.12 As shown, in the second sub-pixel P2, the first color sub-pixel P2 / R includes a seventh transistor T7, the second color sub-pixel P2 / G includes an eighth transistor T8, and the third color sub-pixel P2 / B includes a ninth transistor T9;

[0184] Among them, the seventh transistor T7 is electrically connected to the second gate line GL2, the data line DL and the storage capacitor of the first color sub-pixel P2 / R, respectively, the eighth transistor T8 is electrically connected to the first gate line GL1, the data line DL and the storage capacitor of the second color sub-pixel P2 / G, respectively, and the ninth transistor T9 is electrically connected to the third gate line GL3, the data line DL and the storage capacitor of the third color sub-pixel P2 / B, respectively.

[0185] In some embodiments, the third gate line GL3 is configured to transmit a third gate control signal Gate3; Fig. 9 As shown, the periods of the second gate control signal Gate2 and the third gate control signal Gate3 are the same, the period of the first gate control signal Gate1 is one third of the period of the second gate control signal Gate2, and the duty ratios of the first gate control signal Gate1, the second gate control signal Gate2 and the third gate control signal Gate3 are the same.

[0186] In addition, it should be noted that the first transistor T1, the second transistor T2, the third transistor T3, ... to the ninth transistor T9 in the driving substrate are of the same type, for example, they are all P-type transistors; or, they are all N-type transistors.

[0187] This specification uses the example and description that each transistor is an N-type transistor. The timing sequence provided in this specification (such as Fig. 9 ) is also based on the timing signal corresponding to the case where all transistors are N-type transistors. When all transistors are P-type transistors, it can be understood that the corresponding timing is opposite to the timing currently provided.

[0188] In some embodiments, Fig. 9 As shown, in the first time period, the first gate control signal Gate1 and the second gate control signal Gate2 are configured to output high-level signals simultaneously; in the second time period, the second gate control signal Gate2 and the third gate control signal Gate3 are configured to output high-level signals simultaneously; in the third time period, the first gate control signal Gate1 and the third gate control signal Gate3 are configured to output high-level signals simultaneously; in the fourth time period, the second gate control signal Gate2 is configured to output a high-level signal; in the fifth time period, the first gate control signal Gate1 is configured to output a high-level signal; in the sixth time period, the third gate control signal Gate3 is configured to output a high-level signal; wherein the first time period, the second time period, the third time period, the fourth time period, the fifth time period and the sixth time period are all half of the period T1 of the first gate control signal Gate1.

[0189] In some embodiments, orthographic projections of two of the first gate line GL1 , the second gate line GL2 , and the third gate line GL3 on the substrate 100 intersect.

[0190] For example, Fig.10 As shown, the orthographic projections of the first gate line GL1 and the second gate line GL2 on the substrate 100 intersect.

[0191] In some embodiments, Fig.10 As shown, the first transistor T1 and the second transistor T2 are located between the first gate line GL1 and the second gate line GL2; the third transistor T3 and the fourth transistor T4 are located between the second gate line GL2 and the third gate line GL3;

[0192] In the first sub-pixel P1, a bridge Q is provided between two adjacent third color sub-pixels (for example, B) along the column direction, the bridge Q is located in the source-drain conductive layer SD, and the first gate line GL1 and the second gate line GL2 are swapped through the bridge Q; the fifth transistor T5 and the sixth transistor T6 are located between the first gate line GL1 and the third gate line GL3;

[0193] The seventh transistor T7 is located between the second gate line GL2 and the first gate line GL1 , the eighth transistor T8 is located between the second gate line GL2 and the first gate line GL1 , and the ninth transistor T9 is located between the first gate line GL1 and the third gate line GL3 .

[0194] in, Fig.11 and Fig.12 for Fig.10 A local enlarged view at the grid line position, where: Fig.11 for Fig.10 A partial enlarged view of the first three sub-pixels at the gate line position. Fig.12 for Fig.10 A partial enlarged view of the last three sub-pixels at the gate line position.

[0195] In some embodiments, Fig.10 At the position marked by the dotted line shown in the figure, in the second color sub-pixel (e.g., P1 / G) and the third color sub-pixel (e.g., P1 / B) in the first sub-pixel P1, and in the second color sub-pixel (e.g., P2 / G) and the third color sub-pixel (e.g., P2 / B) in the second sub-pixel, the bonding electrodes DJ are arranged in the same row;

[0196] In the first color sub-pixel (eg, P1 / R) in the first sub-pixel P1 and the first color sub-pixel (eg, P2 / R) in the second sub-pixel P1 , the bonding electrodes DJ are arranged in the same row.

[0197] In some embodiments, Fig.11 As shown, the drain D of the first transistor T1 and the source S of the second transistor T2 are integrated structures, the drain D of the third transistor T3 and the source S of the fourth transistor T4 are integrated structures, and the drain D of the fifth transistor T5 and the source S of the sixth transistor T6 are integrated structures.

[0198] Table 4: Comparison of design parameters and aperture ratios of the drive substrate of the related art and the present application

[0199] project a Opening rate New Hexa Gate(3Gate) 58.6μm 73.5％ Hexa Gate 94μm 62％

[0200] Compared with the driving substrate with a multi-gate line design in the related art with a smaller number of driving chips (e.g. Fig. 7AThe driving substrate provided by the present application reduces the number of gate lines GL without increasing the number of driving chips, as shown in Table 4, thereby greatly increasing the aperture ratio and the light transmittance of the driving substrate, thereby improving the display effect of the display panel.

[0201] exist Fig.11 and Fig.12 In the embodiment, the pixel electrode layer PITO includes a pixel electrode and a switching electrode, wherein the switching electrode is used to electrically connect the common electrode line Com disposed on the gate layer Gate with the common electrode layer CITO. Since the common electrode layer CITO is a film layer covering almost the entire surface, Fig.10 and Fig.11 It is not drawn in the figure. The design concept of the overlapping electrode DJ in the previous article is the same. By setting the transfer electrode ZJ (located on the pixel electrode layer PITO), the common electrode line Com on the gate layer Gate is electrically connected to the common electrode layer CITO. Compared with directly electrically connecting the common electrode line Com on the gate layer Gate to the common electrode layer CITO, it can largely solve the problem of large connection via resistance value, thereby improving the connection stability of the conductive structure and the signal transmission stability.

[0202] An embodiment of the present application provides a display panel, which includes a driving substrate as described in any one of the above descriptions.

[0203] The above display panel has the same advantages as the driving substrate mentioned above.

[0204] An embodiment of the present application provides a display device, which includes the display panel as described above.

[0205] The display device may be an LCD (Liquid Crystal Display) display device, for example, a twisted nematic (TN) type, a vertical alignment (VA) type, an in-plane switching (IPS) type, and an advanced super-dimensional switch (ADS) type liquid crystal display device.

[0206] The display device may include any device or product having a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, an electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0207] An embodiment of the present application provides a driving method for driving the driving substrate as described above, the method comprising:

[0208] S1, inputting a first gate control signal to the first gate line, and inputting a second gate control signal to the second gate line;

[0209] S2, under the common control of the first gate control signal and the second gate control signal, the driving chip inputs a first data signal to the first sub-pixel electrically connected to the first gate line and the second gate line at the same time;

[0210] The first gate line and the second gate line are both electrically connected to the first sub-pixel through a transistor. The specific connection method can refer to the above description, which will not be repeated here.

[0211] S3, under the common control of the first gate control signal and the second gate control signal, the driving chip inputs a second data signal to a second sub-pixel electrically connected to one of the first gate line and the second gate line;

[0212] S4. Under the common control of the first gate control signal and the second gate control signal, the driving chip inputs a third data signal to the second sub-pixel electrically connected to the other one of the first gate line and the second gate line.

[0213] Exemplarily, the first data signal may be one of a red data signal, a green data signal and a blue data signal, the second data signal may be the second of the red data signal, the green data signal and the blue data signal, and the third data signal may be the third of the red data signal, the green data signal and the blue data signal.

[0214] In the driving method provided in the embodiment of the present application, it is necessary to control the writing order of the data signal Data input by the data line DL. In each row of pixel units, it is necessary to first write Data data to the sub-pixels controlled by two gate lines. If Data data is written to the sub-pixels controlled by a single gate line first, then the Data data of the sub-pixels controlled by the following two gate lines will overwrite the pixels controlled by the single gate line, resulting in signal misshooting.

[0215] In practical applications, when the driving substrate further includes a third gate line, the driving method is similar, firstly writing Data to the sub-pixels controlled by two gate lines, and then writing Data to the sub-pixels controlled by a single gate line.

[0216] The following specifically introduces and illustrates the driving process of the two types of driving substrates described above in combination with the corresponding timings.

[0217] Figure 4B A schematic diagram of the electrical connection method of each sub-pixel under a driving repeating unit in a driving substrate is provided; Figure 5 The driving timing shown is Figure 4B The driving process of any row of pixel units in the driving substrate shown in FIG. 1 within one cycle is introduced.

[0218] like Figure 5 As shown in the area marked 1 in FIG. 1 (in the first time period), when the first gate control signal Gate1 and the second gate control signal Gate2 are both at high level, as shown in FIG. Figure 4B As shown, the first transistor T1 and the second transistor T2 in the first sub-pixel P1 (for example, the first column of red sub-pixels R) are turned on at the same time, controlling the writing of signals into the first column of red sub-pixels through the source signal line D1 and the data line DL and charging; at this time, the transistor in the second sub-pixel P2 (a sub-pixel provided with a transistor T3, for example, the second column of red sub-pixels and the third column of red sub-pixels) is turned on, and the second column of red sub-pixels and the third column of red sub-pixels can be pre-charged through the source signal line D1 and the data line DL.

[0219] like Figure 5 As shown in the area marked 1 in FIG. 1 (in the first time period), the first gate control signal Gate1 and the second gate control signal Gate2 are both at high level. Figure 4B As shown, the first transistor T1 and the second transistor T2 in the sixth column of sub-pixels (the second column of blue sub-pixels B) are both turned on, and signals are written into the sixth column of sub-pixels (the second column of blue sub-pixels B) and charged by controlling the source signal line D3 and the data line DL; at this time, the third column of blue sub-pixels controlled by the source signal line D3 are also turned on and pre-charged.

[0220] like Figure 5 As shown in the area marked 1 in FIG. 1 (in the first time period), the first gate control signal Gate1 and the second gate control signal Gate2 are both at high level. Figure 4B As shown, the first transistor T1 and the second transistor T2 in the eighth column sub-pixel (the third column green sub-pixel G) are both turned on, and signals are written into the eighth column sub-pixel (the third column green sub-pixel) and charged by controlling the source signal line D2 and the data line DL.

[0221] like Figure 5 As shown in the area marked 2 (in the second time period), when the first gate control signal Gate1 is at a high level and the second gate control signal Gate2 is at a low level, as shown in FIG. Figure 4B As shown, the third transistor T3 in the third column of sub-pixels (the first column of blue sub-pixels B) is turned on, and a signal is written into the first column of blue sub-pixels through the source signal line D3 and the data line DL and charged.

[0222] like Figure 5 As shown in the area marked 2 (in the second time period), when the first gate control signal Gate1 is at a high level and the second gate control signal Gate2 is at a low level, as shown in FIG. Figure 4B As shown, the third transistor T3 in the fifth column of sub-pixels (the second column of green sub-pixels G) is turned on, and a signal is written into the second column of green sub-pixels and charged by controlling the source signal line D2 and the data line DL.

[0223] like Figure 5 As shown in the area marked 2 (in the second time period), when the first gate control signal Gate1 is at a high level and the second gate control signal Gate2 is at a low level, as shown in FIG. Figure 4B As shown, the third transistor T3 in the seventh column of sub-pixels (the third column of red sub-pixels R) is turned on, and a signal is written into the third column of red sub-pixels and charged by controlling the source signal line D1 and the data line DL.

[0224] like Figure 5 As shown in the area marked 3 (in the third time period), when the first gate control signal Gate1 is at a low level and the second gate control signal Gate2 is at a high level, as shown in FIG. Figure 4B As shown, the third transistor T3 in the second column of sub-pixels (the first column of green sub-pixels G) is turned on, and a signal is written into the first column of green sub-pixels and charged by controlling the source signal line D2 and the data line DL.

[0225] like Figure 5 As shown in the area marked 3 (in the third time period), when the first gate control signal Gate1 is at a low level and the second gate control signal Gate2 is at a high level, as shown in FIG. Figure 4B As shown, the third transistor T3 in the fourth column of sub-pixels (the second column of red sub-pixels R) is turned on, and a signal is written into the second column of red sub-pixels and charged by controlling the source signal line D1 and the data line DL.

[0226] like Figure 5 As shown in the area marked 3 (in the third time period), when the first gate control signal Gate1 is at a low level and the second gate control signal Gate2 is at a high level, as shown in FIG. Figure 4BAs shown, the third transistor T3 in the ninth column of sub-pixels (the third column of blue sub-pixels B) is turned on, and a signal is written into the ninth column of sub-pixels (the third column of blue sub-pixels B) and charged by controlling the source signal line D3 and the data line DL.

[0227] Figure 8 Another schematic diagram of the electrical connection method of each sub-pixel under a driving repeating unit in a driving substrate is provided in the following text. Fig. 9 The driving timing shown is Figure 8 The driving process of any row of pixel units in the driving substrate shown in FIG. 1 within one cycle is introduced.

[0228] Combination Figure 8 and Fig. 9 As shown, in the first time period, the first gate control signal Gate1 and the second gate control signal Gate2 are configured to simultaneously output high level signals; the first transistor T1 and the second transistor T2 are simultaneously turned on to charge the first column of red sub-pixels through the data line DL;

[0229] In the second time period, the second gate control signal Gate2 and the third gate control signal Gate3 are configured to output high level signals simultaneously, the third transistor T3 and the fourth transistor T4 are turned on simultaneously, and the first column of green sub-pixels are charged through the data line DL;

[0230] In the third time period, the first gate control signal Gate1 and the third gate control signal Gate3 are configured to output high level signals simultaneously; the fifth transistor T5 and the sixth transistor T6 are turned on simultaneously, and the first column of blue sub-pixels are charged through the data line DL;

[0231] Among them, in the first three time periods, the Data data is first written to the sub-pixel controlled by two TFTs in series. If the data is written to the sub-pixel controlled by a single TFT first, the Data data of the sub-pixels controlled by the next two TFTs will cover the pixel controlled by the single TFT, resulting in signal misshooting.

[0232] In the fourth time period, the second gate control signal Gate2 is configured to output a high level signal; the seventh transistor T7 is turned on to charge the second column of red sub-pixels through the data line DL;

[0233] In the fifth time period, the first gate control signal Gate1 is configured to output a high level signal; the eighth transistor T8 is turned on to charge the second column of green sub-pixels through the data line DL;

[0234] In the sixth time period, the third gate control signal Gate3 is configured to output a high level signal; the ninth transistor T9 is turned on to charge the blue sub-pixels in the second column through the data line DL.

[0235] In the last three time periods, Data is written to the sub-pixels controlled by a single gate line respectively.

[0236] Each data line DL is electrically connected to a source driver chip (driver chip).

[0237] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A driving substrate, characterized in that: The driving substrate comprises: A substrate, and a plurality of sub-pixels arranged in an array on one side of the substrate; A plurality of data lines, wherein the data lines are located between two adjacent columns of the sub-pixels; and the data lines are electrically connected to the sub-pixels in the same column; A plurality of first gate lines, wherein the first gate lines are located between two adjacent rows of sub-pixels; A plurality of second gate lines, wherein the second gate lines are located between two adjacent rows of sub-pixels; The multiple sub-pixels include multiple first sub-pixels and multiple second sub-pixels, at least one column of the first sub-pixels is electrically connected to both the first gate line and the second gate line, and at least one column of the second sub-pixels is electrically connected to one of the first gate line and the second gate line.

2. The driving substrate according to claim 1, characterized in that: The first sub-pixel includes a first transistor and a second transistor which are electrically connected. The first transistor is electrically connected to the first gate line and a storage capacitor of the first sub-pixel, respectively. The second transistor is electrically connected to the second gate line and the data line, respectively.

3. The driving substrate according to claim 2, characterized in that: The driving substrate comprises: A source-drain conductive layer, the source-drain conductive layer is located on one side of the substrate and includes a light shielding pattern and the data line; A semiconductor layer, the semiconductor layer is located on a side of the source-drain conductive layer away from the substrate, and includes a source electrode, a drain electrode and a semiconductor pattern of a transistor; A gate layer, the gate layer is located on a side of the semiconductor layer away from the substrate, and includes a plurality of lap electrodes, a gate of the transistor and a gate line; the lap electrode is used to electrically connect the source of the transistor and the data line together; A common electrode layer, the common electrode layer is located on the first side of the gate layer away from the substrate, and includes a common electrode and a first electrode of the storage capacitor of the sub-pixel; A pixel electrode layer is located at a side of the common electrode layer away from the substrate, and comprises a pixel electrode and a second electrode of the storage capacitor of the sub-pixel.

4. The driving substrate according to claim 3, characterized in that: The first gate line is configured to transmit a first gate control signal, and the second gate line is configured to transmit a second gate control signal; The first gate control signal and the second gate control signal partially overlap in the same time period.

5. The driving substrate according to claim 4, characterized in that: The first sub-pixel includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, and the second sub-pixel also includes the first color sub-pixel, the second color sub-pixel and the third color sub-pixel; the sub-pixels of the same color are arranged in the same column; The first sub-pixels each include the first transistor and the second transistor; Each of the second sub-pixels includes a third transistor, and the third transistor is electrically connected to one of the first gate line and the second gate line, the data line, and a storage capacitor of the second sub-pixel.

6. The driving substrate according to claim 5, characterized in that: The first color sub-pixels in the first sub-pixels, the second color sub-pixels in the second sub-pixels, and the third color sub-pixels in the second sub-pixels are sequentially arranged in a circular pattern along a row direction.

7. The driving substrate according to claim 5, characterized in that: The first color subpixel in the first subpixel, the second color subpixel in the second subpixel, the third color subpixel in the second subpixel, the first color subpixel in the second subpixel, the second color subpixel in the second subpixel, the third color subpixel in the first subpixel, the first color subpixel in the second subpixel, the second color subpixel in the first subpixel, and the third color subpixel in the second subpixel are sequentially arranged in a circular manner along a row direction; The data line electrically connected to the first color sub-pixel in the nth column, the data line electrically connected to the first color sub-pixel in the n+1th column, and the data line electrically connected to the first color sub-pixel in the n+2th column are electrically connected together; The data line electrically connected to the second color sub-pixel in the nth column, the data line electrically connected to the second color sub-pixel in the n+1th column, and the data line electrically connected to the second color sub-pixel in the n+2th column are electrically connected together; The data line electrically connected to the third color sub-pixel in the nth column, the data line electrically connected to the third color sub-pixel in the n+1th column, and the data line electrically connected to the third color sub-pixel in the n+2th column are electrically connected together; n is a positive integer.

8. The driving substrate according to claim 7, characterized in that: The first gate control signal and the second gate control signal have the same period and the same duty cycle, and within a time period of one third of the period, the first gate control signal and the second gate control signal are configured to simultaneously output high level signals.

9. The driving substrate according to claim 6 or 7, characterized in that: The gate layer includes the first gate line and the second gate line, each transistor is located in a region between the first gate line and the second gate line, and the second gate line overlaps with an orthographic projection of the pixel electrode on the substrate; The gate of the first transistor is electrically connected to the first gate line, the drain of the first transistor is electrically connected to the second electrode of the storage capacitor in the first sub-pixel, and the source of the first transistor is electrically connected to the drain of the second transistor; The gate of the second transistor is electrically connected to the second gate line, the source of the second transistor is electrically connected to the data line through the bonding electrode, and the source of the first transistor and the drain of the second transistor are an integrated structure; The gate of the third transistor is electrically connected to the first gate line or the second gate line, the source of the third transistor is electrically connected to the data line through the bridging electrode, and the drain of the third transistor is electrically connected to the second electrode of the storage capacitor in the second sub-pixel.

10. The driving substrate according to claim 9, characterized in that: A plurality of the bridging electrodes are arranged between two adjacent first gate lines and the second gate lines, and the plurality of bridging electrodes between two adjacent first gate lines and the second gate lines are arranged in the same row.

11. The driving substrate according to claim 9, characterized in that: In the second sub-pixel, the third transistor electrically connected to the first gate line is called a first switch tube, and the third transistor electrically connected to the second gate line is called a second switch tube; Wherein, the area of ​​an overlapped region between the orthographic projection of the first switch tube on the substrate and the orthographic projection of the pixel electrode in the same sub-pixel on the substrate is smaller than the area of ​​an overlapped region between the orthographic projection of the second switch tube on the substrate and the orthographic projection of the pixel electrode in the same sub-pixel on the substrate; Along a direction parallel to a plane where the substrate is located, a minimum distance between the semiconductor pattern of the first switch tube and the first gate line is smaller than a minimum distance between the semiconductor pattern of the second switch tube and the first gate line.

12. The driving substrate according to claim 4, characterized in that: The driving substrate comprises a plurality of the first gate lines, a plurality of the second gate lines and a plurality of third gate lines; At least one row of the first sub-pixels is electrically connected to two of the first gate line, the second gate line and the third gate line at the same time.

13. The driving substrate according to claim 12, characterized in that: The first sub-pixel includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, and the second sub-pixel also includes the first color sub-pixel, the second color sub-pixel and the third color sub-pixel; The sub-pixels of the same color are arranged in the same column, and the first color sub-pixel, the second color sub-pixel and the third color sub-pixel in the first sub-pixel, and the first color sub-pixel, the second color sub-pixel and the third color sub-pixel in the second sub-pixel are arranged cyclically in sequence along the row direction; In the first sub-pixel, the first color sub-pixel includes the first transistor and the second transistor which are electrically connected, the first transistor is electrically connected to the first gate line and the data line respectively, and the second transistor is electrically connected to the second gate line and the storage capacitor of the first color sub-pixel respectively; In the first sub-pixel, the second color sub-pixel includes a third transistor and a fourth transistor electrically connected, the third transistor is electrically connected to the second gate line and the data line respectively, and the fourth transistor is electrically connected to the third gate line and the storage capacitor of the second color sub-pixel respectively; In the first subpixel, the third color subpixel includes a fifth transistor and a sixth transistor electrically connected, the fifth transistor is electrically connected to the third gate line and the data line respectively, and the sixth transistor is electrically connected to the first gate line and the storage capacitor of the third color subpixel respectively.

14. The driving substrate according to claim 13, characterized in that: In the second sub-pixel, the first color sub-pixel includes a seventh transistor, the second color sub-pixel includes an eighth transistor, and the third color sub-pixel includes a ninth transistor; Among them, the seventh transistor is electrically connected to the second gate line, the data line and the storage capacitor of the first color sub-pixel respectively, the eighth transistor is electrically connected to the first gate line, the data line and the storage capacitor of the second color sub-pixel respectively, and the ninth transistor is electrically connected to the third gate line, the data line and the storage capacitor of the third color sub-pixel respectively.

15. The driving substrate according to claim 14, characterized in that: The third gate line is configured to transmit a third gate control signal; The second gate control signal and the third gate control signal have the same period, the first gate control signal has a period that is one third of the period of the second gate control signal, and the first gate control signal, the second gate control signal and the third gate control signal have the same duty cycle.

16. The driving substrate according to claim 15, characterized in that: In a first time period, the first gate control signal and the second gate control signal are configured to output high-level signals at the same time; in a second time period, the second gate control signal and the third gate control signal are configured to output high-level signals at the same time; in a third time period, the first gate control signal and the third gate control signal are configured to output high-level signals at the same time; in a fourth time period, the second gate control signal is configured to output a high-level signal; in a fifth time period, the first gate control signal is configured to output a high-level signal; in a sixth time period, the third gate control signal is configured to output a high-level signal; The first time period, the second time period, the third time period, the fourth time period, the fifth time period and the sixth time period are all half of the period of the first gate control signal.

17. The driving substrate according to claim 16, characterized in that: Orthographic projections of two of the first gate line, the second gate line and the third gate line on the substrate intersect.

18. The driving substrate according to claim 17, characterized in that: The orthographic projections of the first gate line and the second gate line on the substrate intersect, The first transistor and the second transistor are located between the first gate line and the second gate line; the third transistor and the fourth transistor are located between the second gate line and the third gate line; In the first sub-pixel, a bridge portion is provided between two adjacent third color sub-pixels along the column direction, the bridge portion is located in the source-drain conductive layer, and the first gate line and the second gate line are swapped through the bridge portion; the fifth transistor and the sixth transistor are located between the first gate line and the third gate line; The seventh transistor is located between the second gate line and the first gate line, the eighth transistor is located between the second gate line and the first gate line, and the ninth transistor is located between the first gate line and the third gate line.

19. The driving substrate according to claim 18, characterized in that: In the second color sub-pixel and the third color sub-pixel in the first sub-pixel, and in the second color sub-pixel and the third color sub-pixel in the second sub-pixel, the bonding electrodes are arranged in the same row; In the first color sub-pixel in the first sub-pixel and the first color sub-pixel in the second sub-pixel, the bonding electrodes are arranged in the same row.

20. The driving substrate according to claim 18, characterized in that: The drain of the first transistor and the source of the second transistor are integrated structures, the drain of the third transistor and the source of the fourth transistor are integrated structures, and the drain of the fifth transistor and the source of the sixth transistor are integrated structures.

21. A display panel, characterized in that: The display panel includes the driving substrate according to any one of claims 4 to 20.

22. A driving method for a driving substrate, characterized in that: The method is applied to drive a driving substrate according to any one of claims 1 to 20, and the method comprises: Inputting a first gate control signal to the first gate line, and inputting a second gate control signal to the second gate line; Under the common control of the first gate control signal and the second gate control signal, the driving chip inputs a first data signal to the first sub-pixel electrically connected to the first gate line and the second gate line at the same time; The driving chip inputs a second data signal to the second sub-pixel electrically connected to one of the first gate line and the second gate line; The driving chip inputs a third data signal to the second sub-pixel electrically connected to the other one of the first gate line and the second gate line.

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