Driving substrate and driving method thereof, display panel

Abstract

The application provides a driving substrate and a display panel, and relates to the technical field of display. The driving substrate comprises a substrate, a plurality of sub-pixels arranged in an array on one side of the substrate, a plurality of data lines, a plurality of first gate lines and a plurality of second gate lines. The data lines are located between two adjacent columns of sub-pixels. The data lines are electrically connected with the same column of sub-pixels. The first gate lines are located between two adjacent rows of sub-pixels. The second gate lines are located between two adjacent rows of sub-pixels. The plurality of sub-pixels comprise a plurality of first sub-pixels and a plurality of second sub-pixels. At least one column of first sub-pixels is electrically connected with the first gate lines and the second gate lines simultaneously. At least one column of second sub-pixels is electrically connected with one of the first gate lines and the second gate lines. The driving substrate can reduce the aperture ratio of the display panel, and can also reduce the number of source driving chips while balancing the two.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a driving substrate and a driving method thereof, and a display panel. BACKGROUND

[0002] With the rapid development of various display technologies, customers have increasingly high requirements on the display performance of display products. For liquid crystal display products, in the related art, the number of source ICs is reduced by adjusting the gate driving mode, thereby greatly reducing the cost of display products.

[0003] However, the adjustment of the gate driving mode is accompanied by a decrease in the aperture ratio, which has a great negative impact on the transmittance of the display product, and reduces the display effect of the display product. SUMMARY

[0004] Embodiments of the present application provide a driving substrate and a display panel, which can reduce the aperture ratio of the display panel, and also can reduce the number of source ICs and balance between the two.

[0005] Embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, embodiments of the present application provide a driving substrate, which comprises:

[0007] a substrate, and a plurality of sub-pixels arranged in an array on one side of the substrate;

[0008] a plurality of data lines, the data lines being located between two adjacent columns of the sub-pixels; the data lines being electrically connected to the same column of the sub-pixels;

[0009] a plurality of first gate lines, the first gate lines being located between two adjacent rows of the sub-pixels;

[0010] a plurality of second gate lines, the second gate lines being located between two adjacent rows of the sub-pixels;

[0011] wherein the plurality of sub-pixels comprises a plurality of first sub-pixels and a plurality of second sub-pixels, at least one column of the first sub-pixels is electrically connected to the first gate lines and the second gate lines at the same time, and at least one column of the second sub-pixels is electrically connected to one of the first gate lines and the second gate lines.

[0012] In some embodiments, the first sub-pixel comprises a first transistor and a second transistor electrically connected to each other, the first transistor is electrically connected to the first gate line and a storage capacitor of the first sub-pixel respectively, and the second transistor is electrically connected to the second gate line and the data line respectively.

[0013] In some embodiments, the driving substrate comprises:

[0014] a source-drain conductive layer located on one side of the substrate, comprising a light-shielding pattern and the data line;

[0015] a semiconductor layer located on a side of the source-drain conductive layer away from the substrate, comprising a source, a drain and a semiconductor pattern of a transistor;

[0016] a gate layer located on a side of the semiconductor layer away from the substrate, comprising a plurality of overlapping electrodes, a gate of the transistor and a gate line; the overlapping electrodes are used to electrically connect the source of the transistor and the data line together;

[0017] a common electrode layer located on a side of the gate layer away from the first side of the substrate, comprising a common electrode and a first electrode of a storage capacitor of the sub-pixel;

[0018] a pixel electrode layer located on a side of the common electrode layer away from the substrate, comprising a pixel electrode and a second electrode of the storage capacitor of the sub-pixel.

[0019] In some embodiments, the first gate line is configured to transmit a first gate control signal, and the second gate line is configured to transmit a second gate control signal;

[0020] wherein the first gate control signal and the second gate control signal partially overlap in the same time period.

[0021] In some embodiments, the first sub-pixel comprises a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, and the second sub-pixel also comprises the first color sub-pixel, the second color sub-pixel and the third color sub-pixel; the sub-pixels of the same color are arranged in the same column;

[0022] the first sub-pixel comprises the first transistor and the second transistor;

[0023] the second sub-pixel comprises a third transistor, which is electrically connected to one of the first gate line and the second gate line, the data line and a storage capacitor of the second sub-pixel, respectively.

[0024] In some embodiments, the first color sub-pixel in the first sub-pixel, the second color sub-pixel in the second sub-pixel and the third color sub-pixel in the second sub-pixel are arranged in a row direction in a cyclic manner.

[0025] In some embodiments, the first color sub-pixel in the first sub-pixel, the second color sub-pixel in the second sub-pixel, the third color sub-pixel in the second sub-pixel, the first color sub-pixel in the second sub-pixel, the second color sub-pixel in the second sub-pixel, the third color sub-pixel in the first sub-pixel, the first color sub-pixel in the second sub-pixel, the second color sub-pixel in the first sub-pixel, and the third color sub-pixel in the second sub-pixel are arranged in a row direction in a cyclic manner.

[0026] The data line to which the first color sub-pixel in the nth column is electrically connected, the data line to which the first color sub-pixel in the (n+1)th column is electrically connected, and the data line to which the first color sub-pixel in the (n+2)th column is electrically connected are electrically connected together.

[0027] The data line to which the second color sub-pixel in the nth column is electrically connected, the data line to which the second color sub-pixel in the (n+1)th column is electrically connected, and the data line to which the second color sub-pixel in the (n+2)th column is electrically connected are electrically connected together.

[0028] The data line to which the third color sub-pixel in the nth column is electrically connected, the data line to which the third color sub-pixel in the (n+1)th column is electrically connected, and the data line to which the third color sub-pixel in the (n+2)th column is electrically connected are electrically connected together; n is a positive integer.

[0029] In some embodiments, the first gate control signal and the second gate control signal have the same period and the same duty cycle, and in one-third of the period, the first gate control signal and the second gate control signal are configured to output a high-level signal at the same time.

[0030] In some embodiments, the gate layer includes the first gate line and the second gate line, each transistor is located in a region between the first gate line and the second gate line, and the second gate line overlaps with the orthographic projection of the pixel electrode on the substrate.

[0031] The gate of the first transistor is electrically connected to the first gate line, the drain of the first transistor is electrically connected to the second electrode of the storage capacitor in the first sub-pixel, and the source of the first transistor is electrically connected to the drain of the second transistor.

[0032] The gate of the second transistor is electrically connected to the second gate line, the source of the second transistor is electrically connected to the data line through the overlap electrode, and the source of the first transistor and the drain of the second transistor are in an integrated structure.

[0033] The gate of the third transistor is electrically connected with the first gate line or the second gate line, the source of the third transistor is electrically connected with the data line through the overlap electrode, and the drain of the third transistor is electrically connected with the second electrode of the storage capacitor in the second sub-pixel.

[0034] In some embodiments, a plurality of overlap electrodes are arranged between two adjacent first gate lines and second gate lines, and the plurality of overlap electrodes between the two adjacent first gate lines and second gate lines are arranged in the same row.

[0035] In some embodiments, in the second sub-pixel, the third transistor electrically connected with the first gate line is referred to as a first switch transistor, and the third transistor electrically connected with the second gate line is referred to as a second switch transistor.

[0036] The area of the overlapping region of the projection of the first switch transistor on the substrate and the projection of the pixel electrode on the substrate in the same sub-pixel is less than the area of the overlapping region of the projection of the second switch transistor on the substrate and the projection of the pixel electrode on the substrate in the same sub-pixel.

[0037] In the direction parallel to the plane in which the substrate is located, the minimum distance between the semiconductor pattern of the first switch transistor and the first gate line is less than the minimum distance between the semiconductor pattern of the second switch transistor and the first gate line.

[0038] In some embodiments, the driving substrate includes a plurality of first gate lines, a plurality of second gate lines, and a plurality of third gate lines.

[0039] At least one row of the first sub-pixels is electrically connected with two of the first gate lines, the second gate lines, and the third gate lines at the same time.

[0040] In some embodiments, the first sub-pixels include first color sub-pixels, second color sub-pixels, and third color sub-pixels, and the second sub-pixels also include the first color sub-pixels, the second color sub-pixels, and the third color sub-pixels.

[0041] The same color sub-pixels are arranged in the same column, and the first color sub-pixels, the second color sub-pixels, and the third color sub-pixels in the first sub-pixels and the first color sub-pixels, the second color sub-pixels, and the third color sub-pixels in the second sub-pixels are arranged in the row direction in turn.

[0042] In the first sub-pixel, the first color sub-pixel comprises the first transistor and the second transistor which are electrically connected, the first transistor is electrically connected with the first gate line and the data line respectively, and the second transistor is electrically connected with the second gate line and the storage capacitor of the first color sub-pixel respectively.

[0043] In the first sub-pixel, the second color sub-pixel comprises the third transistor and the fourth transistor which are electrically connected, the third transistor is electrically connected with the second gate line and the data line respectively, and the fourth transistor is electrically connected with the third gate line and the storage capacitor of the second color sub-pixel respectively.

[0044] In the first sub-pixel, the third color sub-pixel comprises the fifth transistor and the sixth transistor which are electrically connected, the fifth transistor is electrically connected with the third gate line and the data line respectively, and the sixth transistor is electrically connected with the first gate line and the storage capacitor of the third color sub-pixel respectively.

[0045] In some embodiments, in the second sub-pixel, the first color sub-pixel comprises a seventh transistor, the second color sub-pixel comprises an eighth transistor, and the third color sub-pixel comprises a ninth transistor.

[0046] The seventh transistor is electrically connected with the second gate line, the data line and the storage capacitor of the first color sub-pixel respectively, the eighth transistor is electrically connected with the first gate line, the data line and the storage capacitor of the second color sub-pixel respectively, and the ninth transistor is electrically connected with the third gate line, the data line and the storage capacitor of the third color sub-pixel respectively.

[0047] In some embodiments, the third gate line is configured to transmit a third gate control signal.

[0048] The periods of the second gate control signal and the third gate control signal are the same, the period of the first gate control signal is one third of the period of the second gate control signal, and the duty cycles of the first gate control signal, the second gate control signal and the third gate control signal are the same.

[0049] In some embodiments, in a first time period, the first gate control signal and the second gate control signal are configured to output high level signals simultaneously; in a second time period, the second gate control signal and the third gate control signal are configured to output high level signals simultaneously; in a third time period, the first gate control signal and the third gate control signal are configured to output high level signals simultaneously; in a fourth time period, the second gate control signal is configured to output a high level signal; in a fifth time period, the first gate control signal is configured to output a high level signal; in a sixth time period, the third gate control signal is configured to output a high level signal.

[0050] The first time period, the second time period, the third time period, the fourth time period, the fifth time period and the sixth time period are each half of a period of the first gate control signal.

[0051] In some embodiments, the orthogonal projections of two of the first gate line, the second gate line and the third gate line on the substrate intersect.

[0052] In some embodiments, the orthogonal projections of the first gate line and the second gate line on the substrate intersect,

[0053] The first transistor and the second transistor are located between the first gate line and the second gate line; the third transistor and the fourth transistor are located between the second gate line and the third gate line.

[0054] In the first sub-pixel, a bridge portion is arranged between two adjacent third color sub-pixels in the column direction, the bridge portion is located in the source-drain conductive layer, and the first gate line and the second gate line exchange positions through the bridge portion; the fifth transistor and the sixth transistor are located between the first gate line and the third gate line.

[0055] The seventh transistor is located between the second gate line and the first gate line, the eighth transistor is located between the first gate line and the third gate line, and the ninth transistor is located between the first gate line and the third gate line.

[0056] In some embodiments, in the second color sub-pixel and the third color sub-pixel in the first sub-pixel, and the second color sub-pixel and the third color sub-pixel in the second sub-pixel, each of the overlap electrodes is arranged in the same row.

[0057] In the first color sub-pixel in the first sub-pixel and the first color sub-pixel in the second sub-pixel, each of the overlap electrodes is arranged in the same row.

[0058] In some embodiments, the drain of the first transistor and the source of the second transistor are integrated structures, the drain of the third transistor and the source of the fourth transistor are integrated structures, and the drain of the fifth transistor and the source of the sixth transistor are integrated structures.

[0059] In a second aspect, embodiments of the present application provide a display panel, comprising the driving substrate according to any one of the first aspect.

[0060] In a third aspect, embodiments of the present application provide a driving method for driving the driving substrate according to any one of the first aspect, the method comprising:

[0061] under the common control of the first gate control signal and the second gate control signal, the driving chip inputs a first data signal to the first sub-pixel electrically connected to the first gate line and the second gate line simultaneously;

[0062] the driving chip inputs a second data signal to the second sub-pixel electrically connected to one of the first gate line and the second gate line;

[0063] the driving chip inputs a third data signal to the second sub-pixel electrically connected to the other of the first gate line and the second gate line.

[0064] Embodiments of the present application provide a driving substrate and a driving method, and a display panel. The driving substrate comprises a substrate, a plurality of sub-pixels arranged in an array on one side of the substrate, a plurality of data lines, a plurality of first gate lines, and a plurality of second gate lines. The data lines are located between two adjacent columns of the sub-pixels. The data lines are electrically connected to the same column of the sub-pixels. The first gate lines are located between two adjacent rows of the sub-pixels. The second gate lines are located between two adjacent rows of the sub-pixels. The plurality of sub-pixels comprise a plurality of first sub-pixels and a plurality of second sub-pixels. At least one column of the first sub-pixels is electrically connected to the first gate line and the second gate line simultaneously. At least one column of the second sub-pixels is electrically connected to one of the first gate line and the second gate line.

[0065] In this application, by setting multiple sub-pixels including multiple first sub-pixels and multiple second sub-pixels, at least one column of first sub-pixels is electrically connected to both a first gate line and a second gate line simultaneously, and at least one column of second sub-pixels is electrically connected to one of the first gate line and the second gate line; thus, the first sub-pixels can be driven by both the first gate line and the second gate line simultaneously, some second sub-pixels can be driven by the first gate line, and some second sub-pixels can be driven by the second gate line; compared with the driving substrates of related technologies with a smaller number of driving chips in multi-gate line designs, the driving substrate provided in this application reduces the number of gate lines without increasing the number of driving chips, thereby greatly increasing the aperture ratio, improving the light transmittance of the driving substrate, and thus improving the display effect of the display panel.

[0066] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0067] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0068] Figures 1A-1C A simplified schematic diagram of three display devices in the related art provided for embodiments of this application;

[0069] Figure 1D A schematic diagram of a driving architecture for a driving substrate provided in the related art for the embodiments of this application;

[0070] Figure 1E for Figure 1D Timing diagram;

[0071] Figure 2B A pixel design diagram of single-gateline driving in a related art is provided for embodiments of this application;

[0072] Figure 2A for Figure 2B A magnified view of the elliptical region;

[0073] Figure 3A A pixel design diagram of a three-gateline driven system is provided for embodiments of this application.

[0074] Figure 3B for Figure 3AA local enlarged view of the area in the elliptical circle region;

[0075] Figure 4A And Figure 4B Two driving architecture diagrams of driving the substrate provided for the embodiments of the present application;

[0076] Figure 5 The timing diagram of Figure 4B

[0077] Figure 6A A two-gate-line-driven pixel design diagram provided for the embodiments of the present application;

[0078] Figure 6B The local enlarged view of the area in the rectangular frame in Figure 6A

[0079] The pixel design diagram after setting a black matrix layer BM on the basis of Figure 6C Figure 6B The cross-sectional structure diagram along the M1M2 direction;

[0080] Figure 6D Figure 6B Another driving architecture diagram of driving the substrate in the related art provided for the embodiments of the present application;

[0081] Figure 7A The timing diagram of

[0082] Figure 7B A three-gate-line-driven driving architecture diagram provided for the embodiments of the present application; Figure 7A

[0083] The timing diagram of Figure 8

[0084] A three-gate-line-driven pixel design diagram provided for the embodiments of the present application; Figure 9 Figure 8 The local enlarged view of the first three sub-pixels at the gate line position in

[0085] Figure 10 The local enlarged view of the last three sub-pixels at the gate line position in

[0086] Figure 11 Figure 10

[0087] Figure 12 The local enlarged view of the last three sub-pixels at the gate line position in Figure 10 DETAILED DESCRIPTION

[0089] ​​​​​​​With reference to the drawings, the technical solutions in the embodiments of the present application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0090] In the embodiments of the present application, the terms "first", "second", "third", "fourth" and the like are used to distinguish the same items or similar items with basically the same functions and effects, only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features.

[0091] In the embodiments of the present application, the terms "upper", "lower" and the like indicate the orientation or positional relationship shown in the drawings, only for the purpose of facilitating the description of the present application and simplifying the description, and are not intended to indicate or imply that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0092] In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example" or "some examples" are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0093] In the embodiments of the present application, "a plurality of" means two or more, and "at least one" means one or more, unless otherwise explicitly specified.

[0094] The features of "parallel", "vertical" and "same" used in the embodiments of the present application include the strictly "parallel", "vertical", "same" and the "approximately parallel", "approximately vertical", "approximately same" containing a certain tolerance, which is determined by the person skilled in the art within the acceptable deviation range for a specific value considering the measurement and the tolerance related to the measurement of a specific quantity. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0095] Unless otherwise required by the context, the term "comprising" is interpreted to be open, inclusive, meaning "including, but not limited to" in the entire specification and claims.

[0096] In the embodiments of the present application, "same layer" refers to the relationship between multiple film layers formed by the same material after the same step (for example, one patterning process). Here, "same layer" does not always mean that the thicknesses of the multiple film layers are the same or the heights of the multiple film layers in a cross-sectional view are the same. In the present specification, polygons are not strictly in the sense, and can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, etc. There can be some small deformations caused by tolerances.

[0097] With the development of driving methods and manufacturing processes, liquid crystal displays have greatly improved production costs and picture quality. Today, various different driving methods have been proposed for pixel arrangements including liquid crystal displays, such as Dula Gate Driving (double gate line driving), Triple Gate Driving (three gate line driving), Quadruple-Gate Driving (four gate line driving), Hexa Gate Driving (six gate line driving), etc. Through the improvement of the driving method, the number of source driving ICs can be greatly reduced, thereby reducing the cost of the driving substrate.

[0098] In combination with Figure 1A (single gate line driving), Figure 1B (three gate line driving), and Figure 1C (six gate line driving), it is shown that through the improvement of the gate driving method, the number of source driving ICs gradually decreases to one. The number of source driving chips under several different driving architectures is provided in Table 1.

[0099] Table 1: Number of source driving chips (S-IC) in display devices of different driving methods

[0100]

[0101] Figure 1D A driving architecture diagram of a driving substrate in the related art is provided, in which the Triple Gate Driving (three gate line driving) driving technology sets three gate lines between two adjacent rows of sub-pixels, sets one data line between two adjacent columns of sub-pixels, and further sets three columns of sub-pixels of the same color as a group. The data lines electrically connected to the three columns of sub-pixels in the same group are electrically connected together in the fan-out area and share one source signal line (for example, the data lines electrically connected to the first to third columns of red sub-pixels are electrically connected together in the fan-out area and share the signal line Source1). The change of the gate line setting mode in combination with the driving timing as shown in Figure 1E can realize the normal work of the driving substrate and greatly reduce the number of source driving ICs.

[0102] However, as the number of gate lines increases, the design space between two adjacent rows of sub-pixels becomes smaller, the aperture ratio decreases, leading to increased power consumption and reduced display effect.

[0103] wherein, Figure 2B A pixel design diagram of a 1G1D (one gate line and one data line) driving substrate in the related art is provided, Figure 2A For Figure 2B A local enlarged view of the area enclosed by the ellipse. Figure 3A A pixel design diagram of a Triple Gate (three gate lines driving) driving substrate in the related art is provided, Figure 3B For Figure 3A A local enlarged view of the area enclosed by the ellipse.

[0104] In Figure 2A and Figure 3B , a is the width of the black matrix layer BM provided on the gate line GL, b is the width of the gate line GL, c is the width between the gate line GL and the overlap electrode DJ provided in the same layer, d is the width of the data line DL and the drain connection via of the transistor TFT, and e is the width of the gate of the transistor TFT. The aperture ratio of the driving substrate is mainly determined by a, and the size of a is determined by b, c, d and e.

[0105] Table 2: Comparison data of design parameters and aperture ratio of two driving substrates in the related art

[0106]

[0107] As shown in Table 2, the design references of the transistors, vias and traces of the two driving substrates are consistent, but due to the increase in the number of gate lines of the Triple Gate technology, the BM width increases, and the aperture ratio of the driving substrate decreases from 80% to 72%.

[0108] Based on this, the embodiments of the present application provide a driving substrate, as shown in Figure 4A , Figure 4B or Figure 8 , the driving substrate comprises:

[0109] a substrate 100, and a plurality of sub-pixels P arranged in an array on one side of the substrate;

[0110] a plurality of data lines DL, the data lines DL being located between two adjacent columns of sub-pixels P; the data lines DL being electrically connected to the sub-pixels P in the same column;

[0111] a plurality of first gate lines G1 (or GL1), the first gate lines G1 being located between two adjacent rows of sub-pixels P;

[0112] A plurality of second gate lines G2 (or GL2), the second gate line G2 is located between two adjacent rows of sub-pixels P;

[0113] The plurality of sub-pixels P include a plurality of first sub-pixels P1 and a plurality of second sub-pixels P2, at least one column of first sub-pixels P1 is electrically connected to the first gate line G1 and the second gate line G2 at the same time, and at least one column of second sub-pixels P2 is electrically connected to one of the first gate line G1 and the second gate line G2.

[0114] In an exemplary embodiment, the above-mentioned driving substrate can be applied to a liquid crystal display panel (LCD), such as a twisted nematic (TN) type, a vertical alignment (VA) type, an in plane switching (IPS) type, and an advanced super dimension switch (ADS) type liquid crystal display panel.

[0115] Exemplarily, the specific material of the substrate 1 of the above-mentioned driving substrate is not limited here. Exemplarily, the above-mentioned substrate can be any one of silicon, glass, quartz, PET, plastic, and the like.

[0116] The arrangement mode of the above-mentioned sub-pixel is not limited here. It can be determined according to the actual product design.

[0117] Exemplarily, the above-mentioned sub-pixel can include sub-pixels of three colors, such as red sub-pixels, green sub-pixels, and blue sub-pixels.

[0118] In some embodiments, sub-pixels of the same color are located in the same row. For example, a plurality of red sub-pixels are located in the same row, a plurality of green sub-pixels are located in the same row, and a plurality of blue sub-pixels are located in the same row; for another example, a plurality of red sub-pixels are located in the same column, a plurality of green sub-pixels are located in the same column, and a plurality of blue sub-pixels are located in the same column.

[0119] In other embodiments, at least two colors of sub-pixels are included in the same row of sub-pixels. For example, two colors of sub-pixels can be included in the same row of sub-pixels, or three colors of sub-pixels can be included in the same row of sub-pixels.

[0120] The shape of the orthographic projection pattern of the above-mentioned sub-pixel on the substrate 1 is not limited here. For example, the shape of the orthographic projection pattern of the sub-pixel on the substrate 1 is approximately rectangular, parallelogram, or hexagonal. The embodiments of the present application take the shape of the orthographic projection pattern of the sub-pixel on the substrate 1 as approximately rectangular as an example for drawing.

[0121] The specific structure of the gate lines GL and the data lines DL included in the driving substrate is not limited here.

[0122] For example, the gate lines GL can include straight line segments or a bending structure formed by multiple straight line segments, which can be determined according to actual design.

[0123] For example, the data lines DL can include straight line segments or a bending structure formed by multiple straight line segments, which can be determined according to actual design.

[0124] At least one column of the first sub-pixels P1 is electrically connected to the first gate line G1 and the second gate line G2, and at least one column of the second sub-pixels P2 is electrically connected to one of the first gate line G1 and the second gate line G2. It can be understood that the following cases can be included:

[0125] First, at least one column of the first sub-pixels P1 is driven by the first gate line G1 and the second gate line G2, and at least one column of the second sub-pixels P2 is driven by the first gate line G1.

[0126] Second, at least one column of the first sub-pixels P1 is driven by the first gate line G1 and the second gate line G2, and at least one column of the second sub-pixels P2 is driven by the second gate line G2.

[0127] Third, at least one column of the first sub-pixels P1 is driven by the first gate line G1 and the second gate line G2, at least one column of the second sub-pixels P2 is driven by the first gate line G1, and at least one column of the second sub-pixels P2 is driven by the second gate line G2.

[0128] In the driving substrate provided in the embodiments of the present application, a plurality of sub-pixels P including a plurality of first sub-pixels P1 and a plurality of second sub-pixels P2 are provided, at least one column of the first sub-pixels P1 is electrically connected to the first gate line G1 and the second gate line G2, and at least one column of the second sub-pixels P2 is electrically connected to one of the first gate line G1 and the second gate line G2. In this way, the first sub-pixels P1 can be driven by the first gate line G1 and the second gate line G2, part of the second sub-pixels P2 can be driven by the first gate line G1, and part of the second sub-pixels P2 can be driven by the second gate line G2. Compared with the driving substrate with a smaller number of driving chips in the related art (for example, the driving substrate shown in FIG. 1B), the driving substrate provided in the present application reduces the number of gate lines GL without increasing the number of driving chips, thereby greatly increasing the aperture ratio and improving the light transmittance of the driving substrate, and further improving the display effect of the display panel. Figure 1D

[0129] In some embodiments, as shown in Figure 4A , Figure 4B or Figure 8 ​As shown, the first sub-pixel P1 includes electrically connected first transistor T1 and second transistor T2, the first transistor T1 is electrically connected with the first gate line G1 and the storage capacitor Cst of the first sub-pixel P1 respectively, and the second transistor T2 is electrically connected with the second gate line G2 and the data line DL respectively.

[0130] In actual application, the first transistor T1 can be controlled to be turned on and turned off by the signal provided by the first gate line G1, so that the storage capacitor Cst of the first sub-pixel P1 and the second transistor T2 can be controlled to be turned on and turned off; the second transistor T2 can be controlled to be turned on and turned off by the signal provided by the second gate line G2, so that the data line DL and the first transistor can be controlled to be turned on and connected. In this way, under the cooperation of the first transistor T1 and the second transistor T2, the signal transmitted by the data line DL can be controlled to be written into the storage capacitor Cst of the first sub-pixel P1, so as to complete the charging process of the first sub-pixel P1.

[0131] In some embodiments, in combination with Figure 6B , Figure 6C and Figure 6D As shown, the driving substrate includes:

[0132] A source-drain conductive layer SD, the source-drain conductive layer SD is located on one side of the substrate 100, and includes a light shielding pattern Shield and a data line DL;

[0133] A semiconductor layer (for example, IGZO), the semiconductor layer is located on the side of the source-drain conductive layer SD away from the substrate 100, and includes a source S, a drain D and a semiconductor pattern Active of a transistor;

[0134] A gate layer Gate, the gate layer Gate is located on the side of the semiconductor layer (for example, IGZO) away from the substrate 100, and includes a plurality of overlap electrodes DJ, a gate Gate of a transistor and a gate line GL; as Figure 6D shown, the overlap electrode DJ is used to electrically connect the source S of the transistor and the data line DL together;

[0135] A common electrode layer CITO, the common electrode layer CITO is located on the side of the gate layer Gate away from the first side of the substrate 100, and includes a common electrode and a first electrode of a storage capacitor Cst of a sub-pixel;

[0136] A pixel electrode layer PITO, the pixel electrode layer PITO is located on the side of the common electrode layer CITO away from the substrate 100, and includes a pixel electrode and a second electrode of a storage capacitor Cst of a sub-pixel.

[0137] Here, the specific materials of the above-mentioned source-drain conductive layer SD and gate layer Gate are not limited.

[0138] For example, the material of the gate layer Gate can include copper, and a stack structure such as MoNb / Cu / MoNb can be formed by sputtering, where the material on the side close to the substrate 100 is MoNb with a thickness of about 300 A, mainly used to improve the adhesion between film layers, the material in the middle layer of the stack structure is Cu, which is the material for the electrical signal transmission channel, and the material on the side away from the substrate 100 is MoNb with a thickness of about 200 A, which can be used to protect the middle layer and prevent the surface of the low-resistance middle layer from being exposed to oxidation. Since the thickness of a single sputtering is generally not more than 1 μm, when a gate line GL with a thickness of more than 1 μm is made, multiple sputtering is needed to form it. In addition, it can also be formed by electroplating. Specifically, a seed layer of MoNiTi can be first formed to improve the nucleation density of metal grains in the subsequent electroplating process, and then low-resistance copper is made by electroplating, and then an anti-oxidation layer is made, which can be made of MoNiTi.

[0139] For example, the material of the source-drain conductive layer SD can be the same as that of the gate layer Gate.

[0140] For example, the material of the semiconductor layer can include a silicon material or an oxide semiconductor material, such as monocrystalline silicon, polycrystalline silicon, or indium gallium zinc oxide (IGZO).

[0141] The semiconductor layer (e.g., IGZO) includes the source S and the drain D of the transistor and the semiconductor pattern Active, where the source S and the drain D of the transistor are conductor regions in the semiconductor layer, which are regions subjected to conductorization treatment, and the semiconductor pattern Active is a semiconductor region in the semiconductor layer.

[0142] It should be noted that, as shown in Figure 6D The bonding electrode DJ is used to electrically connect the source S of the transistor and the data line DL together to avoid the problem of a large connection via resistance when the source S provided in the semiconductor layer and the data line DL are directly electrically connected together.

[0143] In some embodiments, the first gate line GL1 (or G1) is configured to transmit a first gate control signal Gate1, and the second gate line GL2 (or G2) is configured to transmit a second gate control signal Gate2.

[0144] As shown in Figure 5 and Figure 9 The first gate control signal Gate1 and the second gate control signal Gate2 partially overlap in the same time period.

[0145] In some embodiments, as shown in Figure 4A and Figure 4BAs shown, the first sub-pixel P1 includes a first color sub-pixel (for example, R), a second color sub-pixel (for example, G), and a third color sub-pixel (for example, B), and the second sub-pixel P2 also includes a first color sub-pixel (for example, R), a second color sub-pixel (for example, G), and a third color sub-pixel (for example, B); sub-pixels of the same color are arranged in the same column;

[0146] The first sub-pixel P1 includes a first transistor T1 and a second transistor T2;

[0147] The second sub-pixel P2 includes a third transistor T3, and the third transistor T3 is electrically connected with one of the first gate line G1 and the second gate line G2, the data line DL, and the storage capacitor Cst of the second sub-pixel P2.

[0148] In some embodiments, as shown in FIG. 1A, the first color sub-pixel (for example, R) in the first sub-pixel P1, the second color sub-pixel (for example, G) in the second sub-pixel P2, and the third color sub-pixel (for example, G) in the second sub-pixel P2 are sequentially arranged in the row direction. Figure 4A

[0149] In the embodiments of the present application, by arranging the first color sub-pixel (for example, R) in the first sub-pixel P1, the second color sub-pixel (for example, G) in the second sub-pixel P2, and the third color sub-pixel (for example, G) in the second sub-pixel P2 to be sequentially arranged in the row direction in the driving substrate, compared with the driving substrate (for example, as shown in FIG. 1A) in the related art, the number of gate lines can be reduced, thereby greatly improving the aperture ratio of the driving substrate, thereby improving the display effect of the display panel and reducing power consumption. Figure 1D

[0150] In some embodiments, as shown in FIG. 1A, the first color sub-pixel (for example, R) in the first sub-pixel P1, the second color sub-pixel (for example, G) in the second sub-pixel P2, and the third color sub-pixel (for example, G) in the second sub-pixel P2 are sequentially arranged in the row direction. Figure 4B

[0151] In the peripheral area of the driving substrate, the data line DL electrically connected with the nth column first color sub-pixel (for example, R), the data line DL electrically connected with the (n+1)th column first color sub-pixel (for example, R), and the data line DL electrically connected with the (n+2)th column first color sub-pixel (for example, R) are electrically connected together, and the three share a source signal line (for example, D1).​​​

[0152] The data line DL electrically connected to the nth column second color sub-pixel (for example, G), the data line DL electrically connected to the n+1th column second color sub-pixel (for example, G), and the data line DL electrically connected to the n+2th column second color sub-pixel (for example, G) are electrically connected together, and share a source signal line (for example, D2);

[0153] The data line DL electrically connected to the nth column third color sub-pixel (for example, B), the data line DL electrically connected to the n+1th column third color sub-pixel (for example, B), and the data line DL electrically connected to the n+2th column third color sub-pixel (for example, B) are electrically connected together, and share a source signal line (for example, D3); n is a positive integer.

[0154] It should be noted that the first color sub-pixel, the second color sub-pixel and the third color sub-pixel can be one of a red sub-pixel, a green sub-pixel and a blue sub-pixel, respectively. In this application, the first color sub-pixel is taken as a red sub-pixel R, the second color sub-pixel is taken as a green sub-pixel G, and the third color sub-pixel is taken as a blue sub-pixel B as an example for illustration and drawing of the accompanying drawings.

[0155] In addition, it should be noted that the first transistor T1, the second transistor T2 and the third transistor T3 in the driving substrate are of the same type, for example, they are all P-type transistors; or they are all N-type transistors.

[0156] This specification takes each transistor as an N-type transistor for example and illustration. The timing provided in this specification is also based on the timing signal corresponding to the case where each transistor is an N-type transistor. When each transistor is a P-type transistor, it can be understood that the corresponding timing is opposite to the timing provided at present.

[0157] In some embodiments, as shown in FIG. 1A, the period of the first gate control signal Gate1 (labeled as T1) and the period of the second gate control signal Gate2 (labeled as T2) are the same, and the duty cycle is the same. In a third of the period, the first gate control signal Gate1 and the second gate control signal Gate2 are configured to output a high level signal at the same time. Figure 5 The duty cycle refers to the proportion of the effective signal in a complete period.

[0158] In some embodiments, as shown in FIG. 1B, the period of the first gate control signal Gate1 (labeled as T1) and the period of the second gate control signal Gate2 (labeled as T2) are the same, and the duty cycle is the same. In a third of the period, the first gate control signal Gate1 and the second gate control signal Gate2 are configured to output a high level signal at the same time.

[0159] Figure 5 ​As shown, in the first time period, the first gate control signal Gate1 and the second gate control signal Gate2 are configured to output high-level signals at the same time; in the second time period, the first gate control signal Gate1 outputs a high-level signal, and the second gate control signal Gate2 outputs a low-level signal; in the third time period, the first gate control signal Gate1 outputs a low-level signal, and the second gate control signal Gate2 outputs a high-level signal.

[0160] It should be noted that the write sequence of the data signal Data input by the data line DL needs to be controlled. In each row of pixel units, the Data data of the sub-pixel controlled by two TFTs in series needs to be written first. If the data of the sub-pixel controlled by a single TFT is written first, the Data data of the two TFTs controlled sub-pixels will cover the single TFT controlled pixel, and signal misfire will occur. The write sequence of the data signal Data can be set and controlled by the source driving chip, which will not be described here.

[0161] In some embodiments, in combination with Figure 6A and Figure 6B As shown, the gate layer Gate includes a first gate line GL1 and a second gate line GL2, each transistor is located in the region between the first gate line GL1 and the second gate line GL2, and the second gate line GL2 overlaps with the orthographic projection of the pixel electrode PITO on the substrate 100;

[0162] The gate (for example, Gate R) of the first transistor T1 is electrically connected with the first gate line GL1, the drain D of the first transistor T1 is electrically connected with the second electrode of the storage capacitor Cst in the first sub-pixel P1, and the source S of the first transistor T1 is electrically connected with the drain D of the second transistor T2;

[0163] The gate (for example, another Gate R) of the second transistor T2 is electrically connected with the second gate line GL2, the source S of the second transistor T2 is electrically connected with the data line DL through the overlap electrode DJ, and the source S of the first transistor T1 and the drain D of the second transistor T2 are integrated structures (marked as D / S in Figure 6A );

[0164] The gate of the third transistor T3 is electrically connected with the first gate line GL1 or the second gate line GL2, the source S of the third transistor T3 is electrically connected with the data line DL through the overlap electrode DJ, and the drain D of the third transistor T3 is electrically connected with the second electrode of the storage capacitor Cst in the second sub-pixel P2.

[0165] Among them, Figure 6B is Figure 6A a local enlarged view of the area enclosed by the rectangular frame in Figure 6C is a design diagram after setting a black matrix layer BM on the basis of Figure 6B .

[0166] In some embodiments, as shown in FIG. 1A, a plurality of overlap electrodes DJ (labeled as DJ in FIG. 1A) are arranged between two adjacent first gate lines GL1 and second gate lines GL2. Figure 6A Figure 6B In some embodiments, as shown in FIG. 1A, the overlap electrodes DJ are arranged in the same row between the two adjacent first gate lines GL1 and second gate lines GL2. Figure 6A

[0167] In some embodiments, as shown in FIG. 1A, the overlap electrodes DJ are arranged in the same row between the two adjacent first gate lines GL1 and second gate lines GL2.

[0168] In some embodiments, as shown in FIG. 1A, the third transistor T2 electrically connected with the first gate line GL1 in the second sub-pixel P2 is referred to as a first switch S1, and the third transistor T3 electrically connected with the second gate line GL2 is referred to as a second switch S2. Figure 6A

[0169] In some embodiments, as shown in FIG. 1A, the overlap electrodes DJ are arranged in the same row between the two adjacent first gate lines GL1 and second gate lines GL2. Figure 6A Figure 6B In some embodiments, as shown in FIG. 1A, the overlap electrodes DJ are arranged in the same row between the two adjacent first gate lines GL1 and second gate lines GL2.

[0170] In some embodiments, as shown in FIG. 1A, the overlap electrodes DJ are arranged in the same row between the two adjacent first gate lines GL1 and second gate lines GL2.

[0171] In some embodiments, as shown in FIG. 1A, the overlap electrodes DJ are arranged in the same row between the two adjacent first gate lines GL1 and second gate lines GL2.

[0172] Figure 6C In some embodiments, as shown in FIG. 1A, the overlap electrodes DJ are arranged in the same row between the two adjacent first gate lines GL1 and second gate lines GL2. Figure 6B ​​​​Based on the design diagram after setting the black matrix layer BM, it can be seen that due to the reduction in the number of gate lines, as shown in the data in Table 3, the width a of the black matrix layer BM is also greatly reduced, thereby increasing the aperture ratio of the driving substrate and improving the brightness and display effect of the display panel.

[0173] Table 3: Comparison of design parameters and aperture ratio of the driving substrate of related technologies and this application

[0174]

[0175] In addition, such as Figure 7A As shown, in the related Hexa Gate pixel driving architecture, six gate lines are required in the Gate direction. These six gate lines control six sub-pixels respectively, which reduces the number of source driving signal lines to 960ea, enabling one IC to drive the pixel. However, due to the large number of gate lines, the aperture ratio is as low as 62%. Figure 7B for Figure 7A The corresponding timing signals.

[0176] Based on this, the embodiments of this application propose the following improvements:

[0177] In some embodiments, such as Figure 8 As shown, the driving substrate includes multiple first gate lines G1, multiple second gate lines G2, and multiple third gate lines G3;

[0178] At least one row of first sub-pixels P1 is simultaneously electrically connected to two of the first gate lines G1, the second gate line G2, and the third gate line G3.

[0179] In some embodiments, such as Figure 8 As shown, the first sub-pixel P1 includes a first color sub-pixel (e.g., R), a second color sub-pixel (e.g., G), and a third color sub-pixel (e.g., B), and the second sub-pixel P2 also includes a first color sub-pixel (e.g., R), a second color sub-pixel (e.g., G), and a third color sub-pixel (e.g., B); sub-pixels of the same color P are arranged in the same column, and the first color sub-pixel (e.g., R), the second color sub-pixel (e.g., G), and the third color sub-pixel (e.g., B) in the first sub-pixel P1 and the first color sub-pixel (e.g., R), the second color sub-pixel (e.g., G), and the third color sub-pixel (e.g., B) in the second sub-pixel P2 are arranged sequentially and cyclically along the row direction;

[0180] The following explanation uses the example of red as the first color sub-pixel, green as the second color sub-pixel, and blue as the third color sub-pixel.

[0181] like Figure 10 and Figure 11As shown, in the first sub-pixel P1, the first color sub-pixel P1 / R includes a first transistor T1 and a second transistor T2 that are electrically connected. The first transistor T1 is electrically connected to the first gate line GL1 and the data line DL, respectively. The second transistor T2 is electrically connected to the second gate line GL2 and the storage capacitor of the first color sub-pixel P1 / R, respectively.

[0182] like Figure 10 and Figure 11 As shown, in the first sub-pixel P1, the second color sub-pixel P1 / G includes a third transistor T3 and a fourth transistor T4 that are electrically connected. The third transistor T3 is electrically connected to the second gate line GL2 and the data line DL, respectively. The fourth transistor T4 is electrically connected to the third gate line GL3 and the storage capacitor of the second color sub-pixel P1 / G, respectively.

[0183] like Figure 10 and Figure 11 As shown, in the first sub-pixel P1, the third color sub-pixel P1 / B includes a fifth transistor T5 and a sixth transistor T6 that are electrically connected. The fifth transistor T5 is electrically connected to the third gate line GL3 and the data line DL, respectively. The sixth transistor T6 is electrically connected to the first gate line GL1 and the storage capacitor of the third color sub-pixel P1 / B, respectively.

[0184] In some embodiments, such as Figure 10 and Figure 12 As shown, in the second sub-pixel P2, the first color sub-pixel P2 / R includes the seventh transistor T7, the second color sub-pixel P2 / G includes the eighth transistor T8, and the third color sub-pixel P2 / B includes the ninth transistor T9.

[0185] Among them, the seventh transistor T7 is electrically connected to the second gate line GL2, the data line DL and the storage capacitor of the first color sub-pixel P2 / R, the eighth transistor T8 is electrically connected to the first gate line GL1, the data line DL and the storage capacitor of the second color sub-pixel P2 / G, and the ninth transistor T9 is electrically connected to the third gate line GL3, the data line DL and the storage capacitor of the third color sub-pixel P2 / B.

[0186] In some embodiments, the third gate line GL3 is configured to transmit a third gate control signal Gate3; such as Figure 9 As shown, the second gate control signal Gate2 and the third gate control signal Gate3 have the same period, the period of the first gate control signal Gate1 is one-third of the period of the second gate control signal Gate2, and the duty cycles of the first gate control signal Gate1, the second gate control signal Gate2 and the third gate control signal Gate3 are the same.

[0187] In addition, it should be noted that the first transistor T1, the second transistor T2, the third transistor T3, and the ninth transistor T9 in the driving substrate are of the same type, for example, they are all P-type transistors, or they are all N-type transistors.

[0188] The present specification takes the example that each transistor is an N-type transistor, and the timing provided in the present specification (such as Figure 9 ) is also based on the timing signal corresponding to the case that each transistor is an N-type transistor, and when each transistor is a P-type transistor, it can be understood that the corresponding timing is opposite to the timing provided at present.

[0189] In some embodiments, as shown in Figure 9 , in the first time period, the first gate control signal Gate1 and the second gate control signal Gate2 are configured to output high level signals at the same time; in the second time period, the second gate control signal Gate2 and the third gate control signal Gate3 are configured to output high level signals at the same time; in the third time period, the first gate control signal Gate1 and the third gate control signal Gate3 are configured to output high level signals at the same time; in the fourth time period, the second gate control signal Gate2 is configured to output a high level signal; in the fifth time period, the first gate control signal Gate1 is configured to output a high level signal; in the sixth time period, the third gate control signal Gate3 is configured to output a high level signal; wherein the first time period, the second time period, the third time period, the fourth time period, the fifth time period and the sixth time period are each half of the period T1 of the first gate control signal Gate1.

[0190] In some embodiments, the projections of two of the first gate line GL1, the second gate line GL2 and the third gate line GL3 on the substrate 100 intersect.

[0191] For example, as shown in Figure 10 , the projections of the first gate line GL1 and the second gate line GL2 on the substrate 100 intersect.

[0192] In some embodiments, as shown in Figure 10 , the first transistor T1 and the second transistor T2 are located between the first gate line GL1 and the second gate line GL2; the third transistor T3 and the fourth transistor T4 are located between the second gate line GL2 and the third gate line GL3;

[0193] In the first sub-pixel P1, a bridging portion Q is provided between two adjacent third color sub-pixels (e.g., B) along the column direction. The bridging portion Q is located in the source-drain conductive layer SD. The first gate line GL1 and the second gate line GL2 are swapped through the bridging portion Q. The fifth transistor T5 and the sixth transistor T6 are located between the first gate line GL1 and the third gate line GL3.

[0194] The seventh transistor T7 is located between the second gate line GL2 and the first gate line GL1, the eighth transistor T8 is located between the first gate line GL1 and the third gate line GL3, and the ninth transistor T9 is located between the first gate line GL1 and the third gate line GL3.

[0195] in, Figure 11 and Figure 12 for Figure 10 A magnified view of the area at the grid line location, where... Figure 11 for Figure 10 A magnified view of the first three sub-pixels at the grid line position. Figure 12 for Figure 10 A magnified view of the three sub-pixels in the middle and rear at the grid line position.

[0196] In some embodiments, such as Figure 10 The positions marked by the dashed lines in the diagram are where the overlapping electrodes DJ are arranged in the same row in the second color sub-pixel (e.g., P1 / G) and third color sub-pixel (e.g., P1 / B) in the first sub-pixel P1, and in the second color sub-pixel (e.g., P2 / G) and third color sub-pixel (e.g., P2 / B) in the second sub-pixel.

[0197] In the first color sub-pixel (e.g., P1 / R) in the first sub-pixel P1 and the first color sub-pixel (e.g., P2 / R) in the second sub-pixel, the overlapping electrodes DJ are arranged in the same row.

[0198] In some embodiments, such as Figure 11 As shown, the drain D of the first transistor T1 and the source S of the second transistor T2 are integrated into one structure, the drain D of the third transistor T3 and the source S of the fourth transistor T4 are integrated into one structure, and the drain D of the fifth transistor T5 and the source S of the sixth transistor T6 are integrated into one structure.

[0199] Table 4: Comparison of design parameters and aperture ratio of the driving substrate of related technologies and this application

[0200]

[0201] Compared to related technologies, driver substrates with fewer driver chips using multi-gate line designs (e.g.) Figure 7AIn the Hexa Gate design shown in the prior art, the driving substrate provided in the present application reduces the number of gate lines GL without increasing the number of driving chips, as shown in Table 4, thereby greatly increasing the aperture ratio, improving the light transmittance of the driving substrate, and further improving the display effect of the display panel.

[0202] In Figure 11 and Figure 12 , the pixel electrode layer PITO includes a pixel electrode and further includes a transfer electrode, wherein the transfer electrode is used to electrically connect the common electrode line Com provided on the gate layer Gate and the common electrode layer CITO together. Since the common electrode layer CITO is almost a full-surface covering film layer, it is not drawn in Figure 10 and Figure 11 , and the design concept of the overlap electrode DJ in the foregoing is the same. The transfer electrode ZJ (on the pixel electrode layer PITO) is used to electrically connect the common electrode line Com provided on the gate layer Gate and the common electrode layer CITO together. Compared with directly electrically connecting the common electrode line Com provided on the gate layer Gate and the common electrode layer CITO together, the problem of large connection via resistance value can be greatly solved, thereby improving the connection stability of the conductive structure and the signal transmission stability.

[0203] Embodiments of the present application provide a display panel, comprising the driving substrate according to any one of the foregoing.

[0204] The display panel has the same advantages as the driving substrate described in the foregoing.

[0205] Embodiments of the present application provide a display device, comprising the display panel described in the foregoing.

[0206] The display device can be an LCD (Liquid Crystal Display) display device. For example, a twisted nematic (TN) type, a vertical alignment (VA) type, an in plane switching (IPS) type, and an advanced super dimension switch (ADS) type liquid crystal display device.

[0207] The display device can include any device or product having a display function. For example, the display device can be a smartphone, a mobile phone, an e-book reader, a desktop PC, a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (e.g., a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, electronic accessories, an electronic tattoo, or a smart watch), a television, etc.

[0208] Embodiments of the present application provide a driving method for driving the driving substrate as described in the foregoing, the method comprising:

[0209] S1, inputting a first gate control signal to the first gate line and a second gate control signal to the second gate line;

[0210] S2, under the common control of the first gate control signal and the second gate control signal, inputting a first data signal to the first sub-pixel which is electrically connected to the first gate line and the second gate line by the driving chip;

[0211] Wherein, the first gate line and the second gate line are both electrically connected to the first sub-pixel through transistors. The specific connection mode can refer to the foregoing description, which will not be repeated here.

[0212] S3, under the common control of the first gate control signal and the second gate control signal, inputting a second data signal to the second sub-pixel which is electrically connected to one of the first gate line and the second gate line by the driving chip;

[0213] S4, under the common control of the first gate control signal and the second gate control signal, inputting a third data signal to the second sub-pixel which is electrically connected to the other of the first gate line and the second gate line by the driving chip.

[0214] For example, the first data signal can be one of a red data signal, a green data signal and a blue data signal, the second data signal can be the second of the red data signal, the green data signal and the blue data signal, and the third data signal can be the third of the red data signal, the green data signal and the blue data signal.

[0215] In the driving method provided by the embodiments of the present application, the writing order of the data signal Data input by the data line DL needs to be controlled, and in each row of pixel units, the Data data of the sub-pixel controlled by two gate lines needs to be written first. If the Data data of the sub-pixel controlled by a single gate line is written first, then the Data data of the sub-pixel controlled by the two gate lines will cover the single gate line controlled pixel, and signal misfire will occur.

[0216] In practical applications, when the driving substrate also includes a third gate line, the driving method is similar: first, Data is written to the sub-pixels controlled by two gate lines, and then Data is written to the sub-pixels controlled by a single gate line.

[0217] The driving process will be described and explained in detail below, taking into account the two types of driving substrates mentioned above and their corresponding timing.

[0218] Figure 4B The diagram above illustrates the electrical connection of sub-pixels within a driving repeating unit in a driving substrate; the following text will combine... Figure 5 The driving timing shown is for Figure 4B The driving process of any row of pixel units in the driving substrate shown is described within one cycle.

[0219] like Figure 5 As shown in area 1 (within the first time period), when both the first gate control signal Gate1 and the second gate control signal Gate2 are high, as... Figure 4B As shown, the first transistor T1 and the second transistor T2 in the first sub-pixel P1 (e.g., the first column of red sub-pixels R) are simultaneously turned on, controlling the writing of signals to the first column of red sub-pixels through the source signal line D1 and the data line DL and charging them; at this time, the transistor in the second sub-pixel P2 (a sub-pixel with a transistor T3, e.g., the second column of red sub-pixels and the third column of red sub-pixels) is turned on, and the second column of red sub-pixels and the third column of red sub-pixels can be pre-charged through the source signal line D1 and the data line DL.

[0220] like Figure 5 As shown in area 1 (within the first time period), both the first gate control signal Gate1 and the second gate control signal Gate2 are at a high level. Figure 4B As shown, the first transistor T1 and the second transistor T2 in the sixth column sub-pixel (the second column blue sub-pixel B) are both turned on, and signals are written to the sixth column sub-pixel (the second column blue sub-pixel) and charged by controlling the source signal line D3 and the data line DL; at this time, the third column blue sub-pixel controlled by the source signal line D3 is also turned on and pre-charged.

[0221] like Figure 5 As shown in area 1 (within the first time period), both the first gate control signal Gate1 and the second gate control signal Gate2 are at a high level. Figure 4B As shown, the first transistor T1 and the second transistor T2 in the eighth column sub-pixel (the third column green sub-pixel G) are both turned on, and signals are written to the eighth column sub-pixel (the third column green sub-pixel) and charged by controlling the source signal line D2 and the data line DL.

[0222] As Figure 5 shown in the area marked 2 (in the second time period), when the first gate control signal Gate 1 is at a high level and the second gate control signal Gate 2 is at a low level signal, as Figure 4B shown, the third transistor T3 in the third column of sub-pixels (the first column of blue sub-pixels B) is turned on, and signals are written into and charged in the first column of blue sub-pixels through the source signal line D3 and the data line DL.

[0223] As Figure 5 shown in the area marked 2 (in the second time period), when the first gate control signal Gate 1 is at a high level and the second gate control signal Gate 2 is at a low level signal, as Figure 4B shown, the third transistor T3 in the fifth column of sub-pixels (the second column of green sub-pixels G) is turned on, and signals are written into and charged in the second column of green sub-pixels through the control source signal line D2 and the data line DL.

[0224] As Figure 5 shown in the area marked 2 (in the second time period), when the first gate control signal Gate 1 is at a high level and the second gate control signal Gate 2 is at a low level signal, as Figure 4B shown, the third transistor T3 in the seventh column of sub-pixels (the third column of red sub-pixels R) is turned on, and signals are written into and charged in the third column of red sub-pixels through the control source signal line D1 and the data line DL.

[0225] As Figure 5 shown in the area marked 3 (in the third time period), when the first gate control signal Gate 1 is at a low level and the second gate control signal Gate 2 is at a high level signal, as Figure 4B shown, the third transistor T3 in the second column of sub-pixels (the first column of green sub-pixels G) is turned on, and signals are written into and charged in the first column of green sub-pixels through the control source signal line D2 and the data line DL.

[0226] As Figure 5 shown in the area marked 3 (in the third time period), when the first gate control signal Gate 1 is at a low level and the second gate control signal Gate 2 is at a high level signal, as Figure 4B shown, the third transistor T3 in the fourth column of sub-pixels (the second column of red sub-pixels R) is turned on, and signals are written into and charged in the second column of red sub-pixels through the control source signal line D1 and the data line DL.

[0227] As Figure 5 shown in the area marked 3 (in the third time period), when the first gate control signal Gate 1 is at a low level and the second gate control signal Gate 2 is at a high level signal, as Figure 4B ​​​​​​​​​​​​​​​​​As shown, the third transistor T3 in the ninth column of sub-pixels (third column of blue sub-pixels B) is turned on, and the signal is written into the ninth column of sub-pixels (third column of blue sub-pixels) through the control of the source signal line D3 and the data line DL and charging.

[0228] Figure 5 Another schematic diagram of a driving connection mode of each sub-pixel under a driving repeating unit in a driving substrate is provided in the middle of the article; the following will be combined with Figure 4B The driving timing shown in the article is introduced. Figure 8 The driving process of any row of pixel units in the driving substrate in one period is introduced.

[0229] The article is combined with Figure 9 and Figure 8 Figure 8 Figure 9 As shown in the article, in the first time period, the first gate control signal Gate1 and the second gate control signal Gate2 are configured to output high level signals at the same time; the first transistor T1 and the second transistor T2 are turned on at the same time, and the first column of red sub-pixels is charged through the data line DL;

[0230] In the second time period, the second gate control signal Gate2 and the third gate control signal Gate3 are configured to output high level signals at the same time, the third transistor T3 and the fourth transistor T4 are turned on at the same time, and the first column of green sub-pixels is charged through the data line DL;

[0231] In the third time period, the first gate control signal Gate1 and the third gate control signal Gate3 are configured to output high level signals at the same time; the fifth transistor T5 and the sixth transistor T6 are turned on at the same time, and the first column of blue sub-pixels is charged through the data line DL;

[0232] Among them, in the first three time periods, the Data data of the sub-pixel controlled by two TFTs in series is written first, if the Data data of the sub-pixel controlled by a single TFT is written first, then the Data data of the sub-pixel controlled by the two TFTs will cover the single TFT controlled pixel, and signal error will occur.

[0233] In the fourth time period, the second gate control signal Gate2 is configured to output a high level signal; the seventh transistor T7 is turned on, and the second column of red sub-pixels is charged through the data line DL;

[0234] In the fifth time period, the first gate control signal Gate1 is configured to output a high level signal; the eighth transistor T8 is turned on, and the second column of green sub-pixels is charged through the data line DL;

[0235] In the sixth time period, the third gate control signal Gate3 is configured to output a high level signal; the ninth transistor T9 is turned on, and the second column of blue sub-pixels is charged through the data line DL.

[0236] In the last three time periods, the sub-pixels controlled by the single gate line are written with Data data respectively.

[0237] Wherein, each data line DL is electrically connected with a source driving chip (a driving chip).

[0238] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which shall be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A drive substrate, characterized by, The driving substrate comprises: a substrate, and a plurality of sub-pixels arranged in an array on one side of the substrate; a plurality of data lines, the data lines being located between two adjacent columns of the sub-pixels; the data lines being electrically connected to the same column of the sub-pixels; a plurality of first gate lines, the first gate lines being located between two adjacent rows of the sub-pixels; a plurality of second gate lines, the second gate lines being located between two adjacent rows of the sub-pixels; wherein the plurality of sub-pixels comprises a plurality of first sub-pixels and a plurality of second sub-pixels, at least one column of the first sub-pixels being electrically connected to both the first gate lines and the second gate lines, and at least one column of the second sub-pixels being electrically connected to one of the first gate lines and the second gate lines.

2. The drive substrate according to claim 1, wherein The first sub-pixel comprises a first transistor and a second transistor electrically connected, the first transistor being electrically connected to the first gate lines and a storage capacitor of the first sub-pixel respectively, and the second transistor being electrically connected to the second gate lines and the data lines respectively.

3. The drive substrate according to claim 2, wherein The driving substrate comprises: a source-drain conductive layer located on one side of the substrate, comprising a light-shielding pattern and the data lines; a semiconductor layer located on a side of the source-drain conductive layer away from the substrate, comprising a source, a drain and a semiconductor pattern of a transistor; a gate layer located on a side of the semiconductor layer away from the substrate, comprising a plurality of overlapping electrodes, a gate of the transistor and gate lines; the overlapping electrodes being used to electrically connect the source of the transistor and the data lines together; a common electrode layer located on a side of the gate layer away from the substrate, comprising a common electrode and a first electrode of a storage capacitor of the sub-pixel; a pixel electrode layer located on a side of the common electrode layer away from the substrate, comprising a pixel electrode and a second electrode of the storage capacitor of the sub-pixel.

4. The drive substrate according to claim 3, wherein The first gate lines are configured to transmit a first gate control signal, and the second gate lines are configured to transmit a second gate control signal; wherein the first gate control signal and the second gate control signal partially overlap in the same time period.

5. The drive substrate according to claim 4, wherein The first sub-pixel comprises a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, and the second sub-pixel also comprises the first color sub-pixel, the second color sub-pixel and the third color sub-pixel; the same color sub-pixels are arranged in the same column; The first sub-pixel comprises the first transistor and the second transistor; The second sub-pixel comprises a third transistor, the third transistor being electrically connected to one of the first gate lines and the second gate lines, the data lines and a storage capacitor of the second sub-pixel respectively.

6. The drive substrate according to claim 5, wherein The first color sub-pixel in the first sub-pixel, the second color sub-pixel in the second sub-pixel and the third color sub-pixel in the second sub-pixel are arranged in a row direction in a cyclic manner.

7. The drive substrate according to claim 5, wherein The first color sub-pixel in the first sub-pixel, the second color sub-pixel in the second sub-pixel, the third color sub-pixel in the second sub-pixel, the first color sub-pixel in the second sub-pixel, the second color sub-pixel in the second sub-pixel, the third color sub-pixel in the first sub-pixel, the first color sub-pixel in the second sub-pixel, the second color sub-pixel in the first sub-pixel, and the third color sub-pixel in the second sub-pixel are arranged in a row direction in a cyclic manner. The data line to which the first color sub-pixel in the nth column is electrically connected, the data line to which the first color sub-pixel in the (n+1)th column is electrically connected, and the data line to which the first color sub-pixel in the (n+2)th column is electrically connected are electrically connected together. The data line to which the second color sub-pixel in the nth column is electrically connected, the data line to which the second color sub-pixel in the (n+1)th column is electrically connected, and the data line to which the second color sub-pixel in the (n+2)th column is electrically connected are electrically connected together. The data line to which the third color sub-pixel in the nth column is electrically connected, the data line to which the third color sub-pixel in the (n+1)th column is electrically connected, and the data line to which the third color sub-pixel in the (n+2)th column is electrically connected are electrically connected together.

8. The drive substrate according to claim 7, wherein The first gate control signal and the second gate control signal have the same period and the same duty cycle, and in one third of the period, the first gate control signal and the second gate control signal are configured to output a high-level signal at the same time.

9. The drive substrate according to claim 6 or 7, characterized by, The gate layer includes the first gate line and the second gate line, each transistor is located in a region between the first gate line and the second gate line, and the second gate line overlaps with the orthographic projection of the pixel electrode on the substrate. The gate of the first transistor is electrically connected to the first gate line, the drain of the first transistor is electrically connected to the second electrode of the storage capacitor in the first sub-pixel, and the source of the first transistor is electrically connected to the drain of the second transistor. The gate of the second transistor is electrically connected to the second gate line, the source of the second transistor is electrically connected to the data line through the overlap electrode, and the source of the first transistor and the drain of the second transistor are in an integrated structure. The gate of the third transistor is electrically connected to the first gate line or the second gate line, the source of the third transistor is electrically connected to the data line through the overlap electrode, and the drain of the third transistor is electrically connected to the second electrode of the storage capacitor in the second sub-pixel.

10. The drive substrate according to claim 9, wherein A plurality of overlap electrodes are arranged between adjacent two first gate lines and second gate lines, and the plurality of overlap electrodes between the adjacent two first gate lines and second gate lines are arranged in the same row.

11. The drive substrate according to claim 9, wherein In the second sub-pixel, the third transistor electrically connected to the first gate line is referred to as a first switch tube, and the third transistor electrically connected to the second gate line is referred to as a second switch tube. The first switch tube is arranged on the substrate, and the area of the intersection of the orthogonal projection of the first switch tube on the substrate and the orthogonal projection of the pixel electrode on the substrate in the same sub-pixel is smaller than the area of the intersection of the orthogonal projection of the second switch tube on the substrate and the orthogonal projection of the pixel electrode on the substrate in the same sub-pixel. The minimum distance between the semiconductor pattern of the first switch tube and the first gate line in the direction parallel to the plane where the substrate is located is smaller than the minimum distance between the semiconductor pattern of the second switch tube and the first gate line.

12. The drive substrate according to claim 4, wherein The driving substrate comprises a plurality of first gate lines, a plurality of second gate lines and a plurality of third gate lines. At least one row of the first sub-pixels is simultaneously electrically connected to two of the first gate line, the second gate line and the third gate line.

13. The drive substrate according to claim 12, wherein The first sub-pixels comprise first color sub-pixels, second color sub-pixels and third color sub-pixels, and the second sub-pixels also comprise the first color sub-pixels, the second color sub-pixels and the third color sub-pixels. The same color sub-pixels are arranged in the same column, and the first color sub-pixels, the second color sub-pixels and the third color sub-pixels in the first sub-pixels and the first color sub-pixels, the second color sub-pixels and the third color sub-pixels in the second sub-pixels are arranged in the row direction in turn. In the first sub-pixels, the first color sub-pixels comprise the first transistor and the second transistor which are electrically connected, the first transistor is electrically connected to the first gate line and the data line respectively, and the second transistor is electrically connected to the second gate line and the storage capacitor of the first color sub-pixel respectively. In the first sub-pixels, the second color sub-pixels comprise the third transistor and the fourth transistor which are electrically connected, the third transistor is electrically connected to the second gate line and the data line respectively, and the fourth transistor is electrically connected to the third gate line and the storage capacitor of the second color sub-pixel respectively. In the first sub-pixels, the third color sub-pixels comprise the fifth transistor and the sixth transistor which are electrically connected, the fifth transistor is electrically connected to the third gate line and the data line respectively, and the sixth transistor is electrically connected to the first gate line and the storage capacitor of the third color sub-pixel respectively.

14. The driving substrate according to claim 13, wherein In the second sub-pixels, the first color sub-pixels comprise the seventh transistor, the second color sub-pixels comprise the eighth transistor, and the third color sub-pixels comprise the ninth transistor. The seventh transistor is electrically connected to the second gate line, the data line and the storage capacitor of the first color sub-pixel respectively, the eighth transistor is electrically connected to the first gate line, the data line and the storage capacitor of the second color sub-pixel respectively, and the ninth transistor is electrically connected to the third gate line, the data line and the storage capacitor of the third color sub-pixel respectively.

15. The drive substrate according to claim 14, wherein The third gate line is configured to transmit a third gate control signal. The second gate control signal and the third gate control signal have the same period, the period of the first gate control signal is one third of the period of the second gate control signal, and the duty cycles of the first gate control signal, the second gate control signal and the third gate control signal are the same.

16. The drive substrate according to claim 15, wherein In a first time period, the first gate control signal and the second gate control signal are configured to output high level signals at the same time; in a second time period, the second gate control signal and the third gate control signal are configured to output high level signals at the same time; in a third time period, the first gate control signal and the third gate control signal are configured to output high level signals at the same time; in a fourth time period, the second gate control signal is configured to output a high level signal; in a fifth time period, the first gate control signal is configured to output a high level signal; and in a sixth time period, the third gate control signal is configured to output a high level signal. The first time period, the second time period, the third time period, the fourth time period, the fifth time period and the sixth time period are each one half of the period of the first gate control signal.

17. The drive substrate according to claim 16, wherein The orthogonal projections of two of the first gate line, the second gate line and the third gate line on the substrate intersect.

18. The drive substrate according to claim 17, wherein The orthogonal projections of the first gate line and the second gate line on the substrate intersect, The first transistor and the second transistor are located between the first gate line and the second gate line; the third transistor and the fourth transistor are located between the second gate line and the third gate line. In the first sub-pixel, a bridging portion is arranged between two adjacent third color sub-pixels in the column direction, the bridging portion is located in the source-drain conductive layer, and the first gate line and the second gate line exchange positions through the bridging portion; the fifth transistor and the sixth transistor are located between the first gate line and the third gate line. The seventh transistor is located between the second gate line and the first gate line, the eighth transistor is located between the first gate line and the third gate line, and the ninth transistor is located between the first gate line and the third gate line.

19. The drive substrate according to claim 18, wherein In the second color sub-pixel and the third color sub-pixel in the first sub-pixel and the second color sub-pixel and the third color sub-pixel in the second sub-pixel, each of the overlapping electrodes is arranged in the same row. In the first color sub-pixel in the first sub-pixel and the first color sub-pixel in the second sub-pixel, each of the overlapping electrodes is arranged in the same row.

20. The drive substrate according to claim 18, wherein The drain of the first transistor and the source of the second transistor are in an integrated structure, the drain of the third transistor and the source of the fourth transistor are in an integrated structure, and the drain of the fifth transistor and the source of the sixth transistor are in an integrated structure.

21. A display panel, comprising: The display panel comprises the drive substrate according to any one of claims 4-20.

22. A driving method of driving a substrate, characterized by, The method is applied to drive the drive substrate according to any one of claims 1-20, and the method comprises: The first gate control signal is input to the first gate line, and the second gate control signal is input to the second gate line; The driving chip inputs a first data signal to the first sub-pixel which is electrically connected to the first gate line and the second gate line simultaneously under the common control of the first gate control signal and the second gate control signal; The driving chip inputs a second data signal to the second sub-pixel which is electrically connected to one of the first gate line and the second gate line; The driving chip inputs a third data signal to the second sub-pixel which is electrically connected to the other of the first gate line and the second gate line.

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