Manufacturing method of zero-layer photoetching alignment mark and semiconductor structure
By forming a first marking groove in a specific crystal direction in the semiconductor substrate and forming an epitaxial barrier layer at the bottom, the problem of the zero-layer lithography alignment marks being easily distorted after epitaxial growth is solved, and the incision accuracy in the semiconductor manufacturing process is improved.
Patent Information
- Application Number
- CN202411993929.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-05-06
AI Technical Summary
During semiconductor manufacturing, the first mark groove is easily distorted after the epitaxial growth of zero-layer lithography, affecting the alignment accuracy of the subsequent layer and the front layer.
By forming a first marking groove in the substrate with the side walls recessed in the substrate direction, and forming a crystalline direction at its side walls, epitaxial growth is prevented, thereby maintaining the morphology of the zero-layer lithography alignment mark. Optionally, an epitaxial barrier layer is formed at the bottom of the first marking groove to enhance alignment accuracy.
It effectively prevents distortion of zero-layer lithography alignment marks, ensures the accuracy of engraving between layers, and further improves the alignment accuracy and recognition ability through the use of epitaxial barrier layers.
Smart Images
Figure CN119937263A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of semiconductor manufacturing, and in particular to a manufacturing method for a zero-layer photolithography alignment mark and a semiconductor structure. Background Art
[0002] Multiple photolithography steps are required in the semiconductor manufacturing process, among which zero-layer photolithography is an extremely important one. The photolithography alignment first mark groove formed in the substrate will affect the alignment of subsequent layers with the previous layer, thus having an important impact on semiconductor manufacturing.
[0003] In some manufacturing processes, epitaxial growth will be performed after the zero-layer lithography alignment first mark groove is formed, and epitaxial growth will also be performed in the zero-layer lithography alignment first mark groove. After epitaxial growth is performed in the zero-layer lithography alignment first mark groove, the lithography alignment of the subsequent layer with the zero layer will be identified by the height difference between the epitaxial layer formed in the zero-layer lithography alignment first mark groove and the epitaxial layer on the substrate surface.
[0004] However, the high temperature environment of the epitaxial process makes it easy for the height difference structure of the top surface of the epitaxial layer grown in the zero-layer lithography alignment first mark groove to deviate from the position and shape of the zero-layer lithography alignment first mark groove, which in turn causes the zero-layer lithography alignment first mark groove pattern to be distorted, thereby affecting the overlay accuracy between subsequent layers. Summary of the invention
[0005] The invention provides a method for manufacturing a zero-layer photolithography alignment mark and a semiconductor structure, so as to solve the problem that the groove pattern of the zero-layer photolithography alignment mark is easily distorted after epitaxial growth.
[0006] According to a first aspect of the present invention, there is provided a method for manufacturing a zero-layer photolithography alignment mark, comprising:
[0007] A substrate is provided, wherein the crystal orientation of the substrate is <100> ;
[0008] forming a vertical groove in the substrate;
[0009] The vertical groove is wet-etched to form a first mark groove, wherein the sidewall of the first mark groove is recessed toward the substrate direction of the sidewall of the vertical groove, the etching rate of the wet etching on the (100) crystal plane is greater than the etching rate on the (111) crystal plane, and the crystal direction of the substrate at the sidewall of the first mark groove is <111> ;
[0010] An epitaxial process is performed to form an epitaxial layer on the top surface of the substrate.
[0011] Optionally, the manufacturing method further includes: forming an epitaxial barrier layer at the bottom of the first marking groove.
[0012] Optionally, the method of forming an epitaxial barrier layer at the bottom of the first mark groove includes:
[0013] Depositing an epitaxial barrier layer material on the surface of the substrate and at the bottom of the first mark groove;
[0014] The epitaxial barrier layer material on the surface of the substrate is removed to form an epitaxial barrier layer at the bottom of the first mark groove.
[0015] Optionally, the depth of the vertical groove ranges from 750 nanometers to 2 micrometers, the width of the vertical groove ranges from 0.1 micrometer to 30 micrometers, and the depth of the first mark groove ranges from 800 nanometers to 2.5 micrometers.
[0016] Optionally, the wet etching solution includes tetramethylammonium hydroxide solution, potassium hydroxide solution or a mixed solution of potassium hydroxide and isopropyl alcohol.
[0017] According to a second aspect of the present invention, there is provided a semiconductor structure, comprising:
[0018] substrate;
[0019] A first marking groove, wherein the first marking groove is located in the substrate, and the crystal orientation of the substrate at the sidewall of the first marking groove is <111> , the side wall of the first marking groove is recessed toward the substrate.
[0020] Optionally, an epitaxial barrier layer is further included, and the epitaxial barrier layer is located at the bottom of the first mark groove.
[0021] Optionally, the semiconductor structure further includes:
[0022] An epitaxial layer is located on the surface of the substrate and exposes the sidewall of the first mark groove and the epitaxial barrier layer.
[0023] Optionally, the semiconductor structure further includes:
[0024] An epitaxial layer is located on the surface of the substrate and at the bottom of the first mark groove, and a thickness of the epitaxial layer is less than a depth of the first mark groove.
[0025] Optionally, the semiconductor structure further includes:
[0026] The epitaxial layer is located in the upper area corresponding to the substrate surface and the bottom of the first mark groove. The epitaxial layer has a second mark groove corresponding to the first mark groove pattern. The bottom surface of the second mark groove is higher than the substrate surface. There is a gap between the epitaxial layer in the first mark groove and the side wall of the first mark groove.
[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0028] In a method for manufacturing a zero-layer photolithography alignment mark provided by an embodiment of the present invention, the crystal orientation of the substrate at the sidewall formed by wet etching is <111> The first mark groove is formed so that the sidewall of the first mark groove cannot effectively grow epitaxy when the substrate is subsequently epitaxially grown. Therefore, the zero-layer photolithography alignment mark formed by subsequent epitaxial growth will not be distorted, thereby ensuring the recognition capability of the zero-layer photolithography alignment mark during photolithography alignment and improving the alignment accuracy of zero-layer overlay.
[0029] Furthermore, by forming an epitaxial barrier layer at the bottom of the first mark groove, it is difficult to grow epitaxy in the first mark groove, so that the zero-layer lithography alignment mark pattern corresponds one-to-one with the epitaxial barrier layer. Because there is a difference in the refractive index between the epitaxial barrier layer and the epitaxial layer, the first mark groove can be more easily identified, thereby further improving the alignment accuracy of the zero-layer overlay. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1-Figure 3 It is a schematic cross-sectional diagram of a device structure corresponding to each step of a method for manufacturing a zero-layer photolithography alignment mark provided by an embodiment of the present invention;
[0031] Figure 4 is a cross-sectional view of a semiconductor structure provided by an embodiment of the present invention Figure 1 ;
[0032] Figure 5 is a cross-sectional view of a semiconductor structure provided by an embodiment of the present invention Figure 2 ;
[0033] Figure 6 is a cross-sectional view of a semiconductor structure provided by an embodiment of the present invention Figure 3 .
[0034] Reference numerals:
[0035] 1- substrate;
[0036] 2-vertical grooves;
[0037] 3- first marking groove;
[0038] 4- epitaxial barrier layer;
[0039] 5- epitaxial layer;
[0040] 6- Second marking groove. DETAILED DESCRIPTION
[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the embodiments in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present invention. The terms "first", "second", "third", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0042] As described in the background art, the zero-layer photolithography alignment mark groove is prone to distortion and even slip line defects when the substrate is epitaxially grown, which seriously affects the overlay accuracy between subsequent layers.
[0043] In view of this, the present invention creatively proposes a method for manufacturing a zero-layer photolithography alignment mark, comprising:
[0044] A substrate is provided, wherein the crystal orientation of the substrate is <100> ;
[0045] forming a vertical groove in the substrate;
[0046] The vertical groove is wet-etched to form a first mark groove whose sidewall is recessed toward the substrate, wherein the sidewall of the first mark groove is recessed toward the substrate of the sidewall of the vertical groove, wherein the etching rate of the wet etching on the (100) crystal plane is greater than the etching rate on the (111) crystal plane, and the crystal direction of the substrate at the sidewall of the first mark groove is <111> ;
[0047] An epitaxial process is performed to form an epitaxial layer on the top surface of the substrate.
[0048] Specifically, an epitaxial layer is formed on the substrate, and there is a height difference structure between the top surface of the epitaxial layer and the bottom of the first mark groove after epitaxial growth. The height difference structure is a zero-layer photolithography alignment mark. The layer after the epitaxial layer is formed is aligned with the height difference structure and thus aligned with the first mark groove. It can be seen that the first mark groove formed by wet etching the vertical groove has a crystal orientation of the substrate at its side wall. <111> , so that in the subsequent substrate <100> During epitaxial growth in the crystal direction, the side walls of the first mark groove cannot effectively grow epitaxy, so that the height difference structure pattern corresponding to the first mark groove will not be distorted, ensuring the ability of the layer after the epitaxial layer to recognize the zero-layer lithography alignment mark during the lithography process and other processes, thereby improving the alignment accuracy of the zero-layer overlay.
[0049] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0050] Figure 1-Figure 3 It is a schematic cross-sectional diagram of a device structure corresponding to each step of a method for manufacturing a zero-layer photolithography alignment mark provided by an embodiment of the present invention; Figure 4 is a cross-sectional view of a semiconductor structure provided by an embodiment of the present invention Figure 1 ; Figure 5 is a cross-sectional view of a semiconductor structure provided by an embodiment of the present invention Figure 2 ; Figure 6 is a cross-sectional view of a semiconductor structure provided by an embodiment of the present invention Figure 3 .
[0051] Please refer to Figure 1-Figure 3 The method for manufacturing a zero-layer photolithography alignment mark provided by an embodiment of the present invention includes:
[0052] S1: Please refer to Figure 1 , providing a substrate 1, wherein the crystal orientation of the substrate 1 is <100> .
[0053] In this embodiment, the substrate 1 may be any semiconductor substrate, such as a silicon substrate, an SOI substrate, a germanium substrate, a germanium silicon substrate, etc., and the present invention does not limit this.
[0054] S2: Please continue to refer to Figure 1 , a vertical groove 2 is formed in the substrate 1.
[0055] Wherein, the S2 specifically includes:
[0056] S21: forming a patterned first mask layer on the substrate 1;
[0057] S22: using the first mask layer as a mask, etching the substrate 1 to form a vertical groove 2.
[0058] As a specific implementation, step S21 may include:
[0059] S211: spin coating a photoresist layer on the substrate 1;
[0060] S212: using a photomask to expose and develop the photoresist layer to form a patterned first mask layer.
[0061] In this embodiment, after step S22 is completed, the following step may further include: removing the remaining first mask layer.
[0062] In addition, it should be appreciated that the above is an example in which the material of the first mask layer is photoresist. In actual applications, the patterned mask layer can also be made of other materials and can also be formed in other ways, and the present invention is not limited thereto.
[0063] In one embodiment, the etching method for forming the vertical groove 2 is dry etching.
[0064] In one possible implementation manner, the width of the vertical groove 2 ranges from 0.1 micrometer to 30 micrometers, and the depth of the vertical groove 2 ranges from 750 nanometers to 2 micrometers.
[0065] S3: Please refer to Figure 2 , the vertical groove 2 is wet-etched to form a first marking groove 3.
[0066] The wet etching is anisotropic wet etching, and the etching rate of the wet etching on the (100) crystal plane is greater than the etching rate on the (111) crystal plane. The crystal orientation of the substrate 1 at the side wall of the first mark groove 3 is <111> .
[0067] S4: Please refer to Figure 5 or Figure 6 , performing an epitaxial process to form an epitaxial layer 5 on the top surface of the substrate.
[0068] Specifically, since the crystal orientation of the substrate 1 at the side wall of the first mark groove 3 is <111> , and the substrate crystal orientation <100> Different, so when epitaxial growth is performed on the substrate, it is difficult to effectively grow an epitaxial layer on the side wall of the first mark groove 3. Even if the epitaxial layer can be grown on the side wall of the first mark groove 3, it will be difficult to achieve a good epitaxial effect because the epitaxial growth rate at the side wall of the first mark groove is different from the epitaxial growth rate on the surface of the substrate 1, that is, the epitaxial growth rate of the (111) crystal plane is smaller than the epitaxial growth rate of the (100) crystal plane. Therefore, the height difference structure between the top surface of the epitaxial layer 5 after epitaxial growth and the bottom of the first mark groove 3 after epitaxy can better maintain the morphology of the first mark groove 3, reduce the distortion of the zero-layer lithography alignment mark corresponding to the first mark groove pattern caused by epitaxial growth, thereby ensuring the recognition ability of the subsequent lithography process and other processes to the first mark groove 3, ensuring the recognition ability of the layer after the epitaxial layer 5 to the zero-layer lithography alignment mark, and improving the alignment accuracy of the zero-layer overlay.
[0069] In addition, since the sidewalls of the first mark groove 3 are recessed toward the substrate 1 , no material will adhere to the sidewalls during the subsequent deposition process, so that the first mark groove pattern is complete.
[0070] Furthermore, the side wall of the first marking groove 3 is composed of two inclined planes inclined in the concave direction thereof, and an angle is formed between the two inclined planes. Specifically, the side wall structure of the first marking groove 3 is a structure approximately in the shape of "∑".
[0071] In one embodiment, the depth of the first mark groove 3 ranges from 800 nanometers to 2.5 micrometers, and the depth of the concave apex of the sidewall of the first mark groove ranges from 300 nanometers to 0.9 micrometers. If the first mark groove 3 is too deep, it will cause damage to the first mark groove 3 during the subsequent epitaxial growth process. If the first mark groove 3 is too shallow, it will make it difficult for the first mark groove 3 to provide sufficient contrast, making the first mark groove 3 difficult to identify, thereby affecting the alignment accuracy of subsequent layers. Therefore, by adopting a first mark groove 3 of appropriate depth, it is possible to provide sufficient contrast while ensuring that the first mark groove 3 is not damaged, thereby ensuring the alignment accuracy of subsequent layers.
[0072] In one embodiment, the wet etching solution includes tetramethylammonium hydroxide solution, potassium hydroxide solution or a mixed solution of potassium hydroxide and isopropyl alcohol. Of course, there are many other types of wet etching solutions, and any solution that can perform anisotropic etching on the substrate 1 is within the protection scope of the present invention.
[0073] Preferably, please refer to Figure 3After step S3 and before step S4 , the method further includes: forming an epitaxial barrier layer 4 at the bottom of the first marking groove 3 .
[0074] Since the epitaxial barrier layer 4 is formed at the bottom of the first mark groove 3, the epitaxial growth cannot be achieved at the bottom of the first mark groove 3, and the sidewall of the first mark groove 3 is recessed toward the substrate 1, so that the epitaxial barrier layer material will not adhere to the sidewall of the first mark groove 3, so that the pattern of the first mark groove 3 corresponds to the epitaxial barrier layer 4, thereby effectively improving the accuracy of zero-layer alignment. In addition, the epitaxial barrier layer 4 has a different refractive index from the epitaxial layer grown on the surface of the substrate 1, so that the photolithography zero-layer alignment mark can be obtained by detecting the refractive index of the epitaxial barrier layer 4 in the first mark groove. Since the epitaxial barrier layer 4 is formed in the first mark groove 3, the photolithography zero-layer alignment mark corresponds to the position of the first mark groove 3, and the deviation is small, so the alignment accuracy of the layer after the epitaxial layer is formed and the zero-layer alignment mark and the set pattern accuracy can be improved.
[0075] Wherein, forming the epitaxial barrier layer 4 at the bottom of the first marking groove 3 includes:
[0076] Depositing an epitaxial barrier layer material on the surface of the substrate 1 and at the bottom of the first marking groove 3;
[0077] The epitaxial barrier layer material on the surface of the substrate 1 is removed to form an epitaxial barrier layer 4 at the bottom of the first mark groove 3 .
[0078] The method for removing the epitaxial barrier layer material on the surface of the substrate 1 may be, for example, chemical mechanical polishing. Of course, there are many methods for removing the epitaxial barrier layer material on the surface of the substrate 1, and the present invention does not limit this.
[0079] In this embodiment, the material of the epitaxial barrier layer 4 includes silicon dioxide. Of course, there are many other choices for the material of the epitaxial barrier layer 4, and the present invention does not limit this.
[0080] In this embodiment, the thickness of the epitaxial barrier layer 4 is 10 nanometers to 100 nanometers.
[0081] In summary, in a method for manufacturing a zero-layer photolithography alignment mark provided by an embodiment of the present invention, the crystal orientation of the substrate at the sidewall formed by wet etching is <111> The first mark groove makes it impossible for the side wall of the first mark groove to effectively grow epitaxy when the subsequent substrate is subjected to epitaxial growth. Therefore, when the subsequent epitaxial growth is carried out, the zero-layer lithography alignment mark corresponding to the first mark groove pattern will not be distorted, thereby ensuring the recognition ability of the layer after the epitaxial layer to the zero-layer lithography alignment mark and improving the alignment accuracy of the zero-layer overlay.
[0082] Furthermore, by forming an epitaxial barrier layer at the bottom of the first mark groove, it is difficult to grow epitaxy in the first mark groove, and the side wall of the first mark groove is recessed toward the substrate so that the epitaxial barrier layer material will not adhere to the side wall of the first mark groove, thereby making the first mark groove 3 pattern correspond one-to-one to the epitaxial barrier layer, and because there is a difference in the refractive index between the epitaxial barrier layer and the epitaxial layer, the first mark groove can be more easily identified, thereby further improving the alignment accuracy of the zero-layer overlay.
[0083] An embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 2 , the semiconductor structure comprises:
[0084] Substrate 1;
[0085] The first marking groove 3 is located in the substrate 1, and the crystal orientation of the substrate 1 at the side wall of the first marking groove 3 is <111> , the side wall of the first marking groove 3 is recessed toward the substrate 1 .
[0086] As a specific example, please refer to Figure 5 The semiconductor structure further includes: an epitaxial layer 5 , the epitaxial layer 5 is located on the surface of the substrate 1 and at the bottom of the first marking groove 3 , and the thickness of the epitaxial layer 5 is less than the depth of the first marking groove 3 .
[0087] As another specific embodiment, please refer to Figure 6 The semiconductor structure also includes: an epitaxial layer 5, the epitaxial layer 5 is located in the upper area corresponding to the surface of the substrate 1 and the bottom of the first mark groove 3, the epitaxial layer 5 has a second mark groove 6 corresponding to the first mark groove pattern, the bottom surface of the second mark groove 6 is higher than the surface of the substrate 1, and there is a gap between the epitaxial layer 5 in the first mark groove 3 and the side wall of the first mark groove 3.
[0088] Preferably, please refer to Figure 3 The semiconductor structure further includes an epitaxial barrier layer 4 , and the epitaxial barrier layer 4 is located at the bottom of the first marking groove 3 .
[0089] Accordingly, as a specific embodiment, please refer to Figure 4 The semiconductor structure further includes: an epitaxial layer 5 , which is located on the surface of the substrate 1 and exposes the sidewall of the first marking groove 3 and the epitaxial barrier layer 4 .
[0090] Since the semiconductor structure of the above embodiment is formed based on the above method for manufacturing the zero-layer photolithography alignment mark, for a detailed description of the various features of the semiconductor structure of the above embodiment, please refer to the relevant explanations and descriptions in the above method for manufacturing the zero-layer photolithography alignment mark, which will not be repeated here.
[0091] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for manufacturing a zero-layer photolithography alignment mark, characterized in that: include: A substrate is provided, wherein the crystal orientation of the substrate is <100> ; forming a vertical groove in the substrate; The vertical groove is wet-etched to form a first mark groove, wherein the sidewall of the first mark groove is recessed toward the substrate direction of the sidewall of the vertical groove, the etching rate of the wet etching on the (100) crystal plane is greater than the etching rate on the (111) crystal plane, and the crystal direction of the substrate at the sidewall of the first mark groove is <111> ; An epitaxial process is performed to form an epitaxial layer on the top surface of the substrate.
2. The method for manufacturing a zero-layer photolithography alignment mark according to claim 1, characterized in that: The manufacturing method further includes: forming an epitaxial barrier layer at the bottom of the first mark groove.
3. The zero-layer photolithography alignment mark according to claim 2, characterized in that: The method of forming an epitaxial barrier layer at the bottom of the first mark groove comprises: Depositing an epitaxial barrier layer material on the surface of the substrate and at the bottom of the first mark groove; The epitaxial barrier layer material on the surface of the substrate is removed.
4. The method for manufacturing a zero-layer photolithography alignment mark according to claim 1, characterized in that: The depth of the vertical groove ranges from 750 nanometers to 2 micrometers, the width of the vertical groove ranges from 0.1 micrometers to 30 micrometers, and the depth of the first mark groove ranges from 800 nanometers to 2.5 micrometers.
5. The method for manufacturing a zero-layer photolithography alignment mark according to claim 1, characterized in that: The wet etching solution includes tetramethylammonium hydroxide solution, potassium hydroxide solution or a mixed solution of potassium hydroxide and isopropyl alcohol.
6. A semiconductor structure, characterized in that: include: substrate; A first marking groove, wherein the first marking groove is located in the substrate, and the crystal orientation of the substrate at the sidewall of the first marking groove is <111> , the side wall of the first marking groove is recessed toward the substrate.
7. The semiconductor structure according to claim 6, characterized in that: Also includes: An epitaxial barrier layer is located at the bottom of the first mark groove.
8. The semiconductor structure according to claim 7, characterized in that: The semiconductor structure further comprises: An epitaxial layer is located on the surface of the substrate and exposes the sidewall of the first mark groove and the epitaxial barrier layer.
9. The semiconductor structure according to claim 6, characterized in that: The semiconductor structure further comprises: An epitaxial layer is located on the surface of the substrate and at the bottom of the first mark groove, and a thickness of the epitaxial layer is less than a depth of the first mark groove.
10. The semiconductor structure according to claim 6, characterized in that: The semiconductor structure further comprises: The epitaxial layer is located in the upper area corresponding to the substrate surface and the bottom of the first mark groove. The epitaxial layer has a second mark groove corresponding to the first mark groove pattern. The bottom surface of the second mark groove is higher than the substrate surface. There is a gap between the epitaxial layer in the first mark groove and the side wall of the first mark groove.