Multi-core dynamic balance test card

Abstract

The invention relates to the technical field of balance test cards, in particular to a multi-core dynamic balance test card which comprises a circuit board A and a circuit board B. The circuit board A is provided with at least two sets of signal processing modules and A / D converters, and each set of signal processing module comprises a pre-amplifier, a variable gain amplifier, a low-pass filter and a biasing circuit. A CPU, an FPGA programmable logic chip and a network port interface chip are arranged on the circuit board B, the CPU, the FPGA programmable logic chip and the network port interface chip are electrically connected, and a pre-amplifier, a variable gain amplifier, a low-pass filter and a biasing circuit in the signal processing module are further connected with the FPGA programmable logic chip. The same signal passes through a plurality of paths of amplifying circuits with different amplification factors and then passes through a plurality of paths of A / D converters, so that a gain switch does not need to be switched according to the size of the signal, and only the most suitable signal needs to be directly selected, so that on one hand, the dynamic range is expanded, on the other hand, the test rhythm is saved, the production efficiency is improved, and the test cost is reduced. The problem of low signal-to-noise ratio is solved, and the problem of overlong test rhythm is also solved.

Description

Technical Field

[0001] The present invention relates to the technical field of balance test cards, and in particular to a multi-core dynamic balance test card. Background Art

[0002] In order to improve the signal-to-noise ratio, the conventional dynamic balancing test system needs to automatically adjust different magnifications according to the signal size. Since the adjustment of different magnifications requires switching electronic switches, which causes signal mutations, it requires stabilization time, resulting in a long test cycle of the fully automatic dynamic balancing machine, which cannot meet the actual production requirements. In view of this, it is necessary to improve the current balance test card to solve the above problems.

[0003] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute prior art. Summary of the invention

[0004] The purpose of the present invention is to provide a multi-core dynamic balance test card to solve the problems raised in the above background technology.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] A multi-core dynamic balancing test card, comprising a circuit board A and a circuit board B, wherein the circuit board A is provided with at least two groups of signal processing modules and an A / D converter, and each group of the signal processing modules respectively comprises a preamplifier, a variable gain amplifier, a low-pass filter and a bias circuit;

[0007] The circuit board B is respectively provided with a CPU, an FPGA programmable logic chip and a network port interface chip, and the CPU, the FPGA programmable logic chip and the network port interface chip are electrically connected;

[0008] The preamplifier, variable gain amplifier, low-pass filter and bias circuit in the signal processing module are also connected to the FPGA programmable logic chip;

[0009] In addition, a preferred structure is that the preamplifier includes a resonant circuit, a diode, a vibration sensor, a comparison amplifier and a plurality of resistors electrically connected to each other, the preamplifier is externally connected to a PGND power ground and a ground terminal, and the vibration sensor is externally connected to a ground terminal and a power common terminal.

[0010] In addition, a preferred structure is that the low-pass filter includes a capacitor, a comparison amplifier and a plurality of resistors which are electrically connected to each other, wherein the low-pass filter is also externally connected to an analog ground and a signal ground.

[0011] In addition, a preferred structure is that the bias circuit includes a transistor, a capacitor and a plurality of resistors that are electrically connected to each other, and the bias circuit is externally connected to a ground terminal.

[0012] In addition, a preferred structure is that the A / D converter is externally connected to a ground terminal, and the A / D converter includes an input terminal input, VCC, a data signal DATA and a clock signal CLK.

[0013] In addition, a preferred structure is that the model of the FPGA programmable logic chip is AG10KL144H.

[0014] The beneficial effects of the present invention are:

[0015] In the present invention, by using the same signal to pass through multiple amplifier circuits with different amplification factors and then pass through multiple A / D converters, there is no need to switch the gain switch according to the signal size, and it is only necessary to directly select the most suitable signal. On the one hand, the dynamic range is improved, and on the other hand, the test cycle is saved, the production efficiency is improved, the problem of low signal-to-noise ratio is solved, and the problem of too long test cycle is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of the structure of a circuit board A and a circuit board B in a multi-core dynamic balancing test card proposed by the present invention;

[0017] Figure 2 A schematic diagram of a multi-core dynamic balancing test card proposed by the present invention;

[0018] Figure 3 A schematic diagram of a preamplifier in a multi-core dynamic balancing test card proposed by the present invention;

[0019] Figure 4 A schematic diagram of a variable gain amplifier in a multi-core dynamic balancing test card proposed by the present invention;

[0020] Figure 5 A schematic diagram of a low-pass filter in a multi-core dynamic balancing test card proposed by the present invention;

[0021] Figure 6 A schematic diagram of a bias circuit in a multi-core dynamic balancing test card proposed by the present invention;

[0022] Figure 7 A schematic diagram of an A / D converter in a multi-core dynamic balancing test card proposed by the present invention;

[0023] Figure 8 The present invention provides a schematic diagram of an FPGA programmable logic chip in a multi-core dynamic balancing test card.

[0024] In the figure: 101 circuit board A, 102 circuit board B, 2 signal processing module, 21 preamplifier, 22 variable gain amplifier, 23 low pass filter, 24 bias circuit, 3 A / D converter, 4 CPU, 5 FPGA programmable logic chip, 6 network port interface chip. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0026] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0027] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0028] Reference Figure 1-8 , a multi-core dynamic balancing test card, comprising a circuit board A101 and a circuit board B102, wherein the circuit board A101 is provided with at least two groups of signal processing modules 2 and an A / D converter 3;

[0029] The signal processing module 2 includes a preamplifier 21, a variable gain amplifier 22, a low-pass filter 23 and a bias circuit 24;

[0030] In other embodiments, the preamplifier 21 includes a resonant circuit, a diode, a vibration sensor, a comparison amplifier and a plurality of resistors electrically connected to each other, the preamplifier 21 is externally connected to a PGND power ground and a ground terminal, wherein the vibration sensor is externally connected to a ground terminal and a power common terminal;

[0031] With this design, connecting the external ground terminal of the vibration sensor to the common terminal of the power supply not only helps to reduce interference and improve signal quality, but also enhances the safety and stability of the system;

[0032] The circuit board B102 is provided with a CPU 4, an FPGA programmable logic chip 5 and an Internet port interface chip 6, respectively, and the CPU 4, the FPGA programmable logic chip 5 and the Internet port interface chip 6 are electrically connected;

[0033] Through this design, by electrically connecting the FPGA programmable logic chip 5 with the network port interface chip 6, not only the flexibility and adaptability of the system are improved, but also the data transmission efficiency and system integration are improved, while the development cost and power consumption are reduced, so that the FPGA programmable logic chip 5 can further realize an efficient and flexible network port interface;

[0034] In other embodiments, the model of the FPGA programmable logic chip 5 is AG10KL144H;

[0035] Through this design, by using AG10KL144H as FPGA programmable logic chip 5, it has high programmability and reconfigurability. Users can implement different logic functions through programming according to their needs to adapt to rapidly changing application scenarios;

[0036] Furthermore, the FPGA chip supports parallel computing, can handle multiple tasks simultaneously, improve data processing efficiency, and the AG10KL144H supports multiple interfaces to facilitate system integration and maintenance;

[0037] The preamplifier 21, variable gain amplifier 22, low pass filter 23 and bias circuit 24 in the signal processing module 2 are also connected to the FPGA programmable logic chip 5;

[0038] In other embodiments, the low-pass filter 23 includes a capacitor, a comparison amplifier, and a plurality of resistors electrically connected to each other, wherein the low-pass filter is also externally connected to an analog ground and a signal ground;

[0039] Through this design, the low-pass filter 23 can effectively suppress high-frequency signals, thereby reducing the impact of noise on the system. At the same time, the low-pass filter 23 is externally connected to the analog ground and the signal ground, which can further improve the filtering effect and circuit stability.

[0040] In other embodiments, the bias circuit 24 includes a transistor, a capacitor, and a plurality of resistors electrically connected to each other, and the bias circuit 24 is externally connected to a ground terminal;

[0041] Through this design, the bias circuit 24 can provide a stable bias voltage or current for devices such as transistors and diodes, thereby ensuring that these devices operate at the optimal operating point and improving the performance and stability of the circuit. By using the bias circuit 24, the design of the circuit can be simplified. The bias circuit 24 can also achieve current and voltage stability through feedback control.

[0042] Furthermore, the design of the bias circuit 24 being externally connected to the ground terminal can effectively suppress the influence of high-frequency noise and parasitic parameters, thereby improving the stability of the circuit;

[0043] In other embodiments, the A / D converter 3 is externally connected to a ground terminal, and the A / D converter 3 includes an input terminal input, a VCC, a data signal DATA, and a clock signal CLK;

[0044] Through this design, the input terminal input in the A / D converter 3 is used to receive analog signals, VCC is the power input terminal, the data signal DATA is used to transmit the digital data converted by the A / D converter 3, and the clock signal CLK is used to control the working timing of the A / D converter. The clock signal CLK provides a stable timing reference to ensure the correct sampling and transmission of data;

[0045] In this embodiment, by using the same signal to pass through multiple amplifier circuits with different amplification factors and then pass through multiple A / D converters, there is no need to switch the gain switch according to the signal size, and it is only necessary to directly select the most suitable signal. On the one hand, the dynamic range is improved, and on the other hand, the test cycle is saved, the production efficiency is improved, the problem of low signal-to-noise ratio is solved, and the problem of too long test cycle is solved.

[0046] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A multi-core dynamic balancing test card, comprising a circuit board A and a circuit board B, characterized in that: At least two groups of signal processing modules and A / D converters are arranged on the circuit board A, and each group of the signal processing modules includes a preamplifier, a variable gain amplifier, a low-pass filter and a bias circuit; The circuit board B is respectively provided with a CPU, an FPGA programmable logic chip and a network port interface chip, and the CPU, the FPGA programmable logic chip and the network port interface chip are electrically connected; The preamplifier, variable gain amplifier, low-pass filter and bias circuit in the signal processing module are also connected to the FPGA programmable logic chip.

2. A multi-core dynamic balance test card according to claim 1, characterized in that: The preamplifier comprises a resonant circuit, a diode, a vibration sensor, a comparison amplifier and a plurality of resistors which are electrically connected to each other. The preamplifier is externally connected to a PGND power ground and a ground terminal, wherein the vibration sensor is externally connected to a ground terminal and a power common terminal.

3. A multi-core dynamic balance test card according to claim 1, characterized in that: The low-pass filter comprises a capacitor, a comparison amplifier and a plurality of resistors which are electrically connected to each other, wherein the low-pass filter is also externally connected to an analog ground and a signal ground.

4. A multi-core dynamic balance test card according to claim 1, characterized in that: The bias circuit includes a transistor, a capacitor and a plurality of resistors which are electrically connected to each other, and the bias circuit is externally connected to a ground terminal.

5. The multi-core dynamic balance test card according to claim 1, characterized in that: The A / D converter is externally connected to a ground terminal, and includes an input terminal input, VCC, a data signal DATA and a clock signal CLK.

6. The multi-core dynamic balance test card according to claim 1, characterized in that: The model of the FPGA programmable logic chip is AG10KL144H.

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