Rapid ca train method for lpddr5

Abstract

The invention aims to provide a rapid ca train method for lpddr5, and the method comprises the following steps: sending three groups of data to CA (Certain Authority) in a Command Bus train Mode particle, and respectively receiving a return result of a DQ (Digital Quantitative) signal line; judging the relationship between each bit in the CA signal and the clock signal according to the received result; and adjusting the delay of the CA signal according to the relationship between each bit in the CA signal and the clock signal. According to the method, the three groups are continuously sent, and the position relation between the CA signal and the clock signal is judged through the return value, so that left shift or right shift is needed when the left and right boundaries of each bit of the CA signal are searched, and the time is reduced. Different position relations are classified into the same kind through a left shift control signal or a right shift control signal, and the process is simplified.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a fast ca train method for lpddr5. Background Art

[0002] When the control signal (ca), chip select signal (cs), and clock signal (ck) are transmitted between the physical layer (phy) and the storage particles, due to the existence of delay errors and the different delays between them, the clock signal (ck) cannot sample the correct control signal (ca), thus affecting normal operation. The impact of delay is more obvious when working at high speed. Ideally, the position relationship of the control signal (ca), chip select signal (cs), and clock signal (ck) received by the particle is as follows: Figure 2 As shown in the figure, the rising and falling edges of the clock signal (ck) are aligned with the middle of the control signal (ca) edge, which ensures that the clock signal (ck) samples the correct and stable control signal (ca). However, in practical applications, the transmission of signals in the line will inevitably cause delays. When there is a delay, when the clock signal (ck) is transmitted to the particle, the position relationship between the clock signal (ck) and the control signal (ca) may be as follows: Figure 3 As shown in the figure, the edge of the clock signal (ck) corresponds to the edge of the control signal (ca), which will cause the clock signal (ck) to sample unstable data. In addition, since the control signal (ca) has 7 bits, these bits have their own lines and the delays between them are also different. The edge of the clock signal (ck) will sample incorrect data. In high-speed situations, the edge width of the control signal (ca) and the period of the clock signal (ck) are shorter, and the impact of these different delays is also greater. The delays caused by these lines and other external factors are inevitable and unpredictable. In order to eliminate the impact of these delays, additional controllable delays ca_delay[i] (i ranges from 0 to 6) and ck_delay are added before the signal reaches the particle. The process of finding the optimal values ​​of ca_delay[i] and ck_delay is called ca training. Without ca training, it is impossible to ensure that the particle receives the correct command.

[0003] The current technology for finding the left and right boundaries of the control signal (ca) relies on traversing the value combination of ca_delay[i] and ck_delay. The positional relationship between the control signal (ca) and the clock signal (ck) is in an unaware state, and it is difficult to determine whether the control signal (ca) needs to be shifted left or right relative to the clock signal (ck), which takes a long time. In addition, the control signal (ca) has 7 bits, and the positions of different bits of the control signal (ca) are also different. Each bit of the control signal (ca) may need to be shifted left or right. The adjustable range between ca_delay and ck_delay is limited. Once the boundary cannot be found, it will be difficult to handle. In addition, ck_delay is also closely related to the chip select signal (cs) and cannot be adjusted at will, which also increases the difficulty of training. Summary of the invention

[0004] The purpose of the present invention is to provide a method for fast ca train of lpddr5. The method sends three sets of commands to the particles. The rising edge or falling edge of the clock signal will sample the CA and feedback the result through DQ. The position relationship between the control signal and the clock signal is judged by the return value, so as to find out whether the left or right shift is needed when finding the left and right boundaries of each bit of the control signal, thereby reducing the time spent. After determining the position relationship, different position relationships can be classified into the same type (the left or right shift control signal) by shifting the control signal left or right. Figure 6 , Figure 7 The location of Figure 5 ), thereby simplifying the process. When the position relationship between the control signal and the clock signal is poor and cannot meet the conditions of finding both the left boundary and the right boundary, it is also possible to determine which boundary can be found based on the position relationship and abandon the other one, thus reducing unnecessary work.

[0005] A method for fast ca train for lpddr5, comprising: Send three sets of data to the CA of the Command Bus Training Mode particle and receive the return results of the DQ signal line respectively; Determine the relationship between each bit in the CA signal and the clock signal based on the received results; The delay of the CA signal is adjusted according to the relationship between each bit in the CA signal and the clock signal.

[0006] Preferably, the sending of three sets of data to the CA of the Command Bus Training Mode particle and receiving the return results of the DQ signal lines respectively include: After the first data: 0, 7f, 0, 7f, is sent out and the data receiving end receives the corresponding result, the second data: 0, 0, 7f, 0 is sent; After the second data is sent out and the data receiving end receives the corresponding result, the third data is sent: 7f, 0, 7f, 7f.

[0007] Preferably, determining the relationship between each bit in the CA signal and the clock signal according to the received result includes: If the received result is 0, 1, 1, it means that the rising edge of the clock signal is in the middle of the control signal; If the received result is 1, 0, 0, it means that the rising edge of the clock signal is to the left of the left boundary of the control signal; If the received result is 1, 0, 1, it means that the rising edge of the clock signal is to the right of the right boundary of the control signal.

[0008] Preferably, adjusting the delay of the CA signal according to the relationship between each bit in the CA signal and the clock signal comprises: The delay of the control signal is pre-adjusted so that the rising edge of the clock signal is in the middle of the control signal; Coarsely adjust the delay of the control signal to quickly find the approximate position of the control signal boundary Fine-tune the delay of the control signal to find the precise position boundary of the control signal Preferably, the delay of the pre-adjusted control signal so that the rising edge of the clock signal is exactly in the middle of the control signal comprises: When it is detected that the rising edge of the clock signal is to the right of the right boundary of the control signal, the control signal is shifted right by half a clock cycle; When it is detected that the rising edge of the clock signal is to the left of the left boundary of the control signal, the control signal is shifted left by half a clock cycle.

[0009] Preferably, the delay of the control signal to find the left boundary of the control signal comprises: Increase the value of the control signal delay to shift the control signal to the right and find the left boundary; Each time the value of the control signal delay is changed, data is sent once until the value at the data receiving end changes from 1 to 0; When the value of a bit at the data receiving end changes from 1 to 0, it means that the left boundary of the control signal of this bit has been found; Stop increasing the delay value of the corresponding control signal, and continue to increase the delay value of the control signal for the bit that has not jumped until the control signals of all bits find the left boundary.

[0010] Preferably, the delay of the control signal to find the right boundary of the control signal comprises: Increase the value of the control signal delay to shift the control signal to the left and find the right boundary; Each time the value of the control signal delay is changed, it is sent once until the value at the data receiving end changes from 1 to 0; When the value of a bit at the data receiving end changes from 1 to 0, it means that the right boundary of the control signal of this bit has been found; Reduce the value of the control signal delay until all bits transition.

[0011] Preferably, it also includes: First, use a larger step size a to roughly adjust the control signal delay, and then use a smaller step size b to fine-tune the control signal delay; If a jump occurs after n*a is added, the control signal is delayed back to (dly_init+(n-1)*a); Use a step size b that is smaller than a for adjustment. If a jump occurs after adding m*b, the control signal delay of the left boundary is finally found to be (initial delay + (n-1)*a + m*b).

[0012] A system for fast ca train for lpddr5, comprising: The data sending module is used to send three sets of data to the CA of the Command Bus Training Mode particle and receive the return results of the DQ signal line respectively; A data receiving module is used to determine the relationship between each bit in the CA signal and the clock signal according to the received result; The data processing module is used to adjust the delay of the CA signal according to the relationship between each bit in the CA signal and the clock signal.

[0013] An electronic device comprises: a chip, a processor and a memory, wherein the memory is used to store computer program code, the computer program code comprises computer instructions, and when the chip executes the computer instructions, the electronic device executes a method for fast ca train of lpddr5.

[0014] The beneficial effects of the present invention are: 1. The present invention determines the positional relationship between the control signal and the clock signal through the return value, so as to determine whether left shift or right shift is required when finding the left and right boundaries of each bit of ca, thereby reducing the time spent, clarifying the adjustment direction, saving simulation time, and improving work efficiency; 2. The present invention combines coarse adjustment and fine adjustment, which can not only reduce the number of adjustments and save time, but also ensure the adjustment accuracy and improve accuracy; 3. The present invention adjusts the control signal bit by bit to ensure that the control signal has the largest edge width and improves stability; 4. The present invention has strong flexibility, and various positional relationships between the bits of the control signal and various positional relationships between the control signal and the clock signal can be flexibly handled. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0017] Figure 1 A flow chart of a method for fast ca train of lpddr5 of the present invention; Figure 2 This is a schematic diagram of a clock signal sampling control signal in an ideal situation of the present invention; Figure 3 A schematic diagram of a clock signal sampling control signal in a practical situation of the present invention; Figure 4 This is a schematic diagram of sending three sets of data to particles according to the present invention; Figure 5 This is a schematic diagram of a rising edge of a clock signal in the middle of a control signal of the present invention; Figure 6 It is a schematic diagram of the rising edge of the clock signal of the present invention being close to the right boundary of the control signal; Figure 7 It is a schematic diagram of the rising edge of the clock signal of the present invention being close to the left boundary of the control signal; Figure 8 A schematic diagram of the positional relationship among the clock signal, chip selection signal and control signal of the present invention; Fig. 9 The figure is a schematic diagram of the hardware structure of an electronic device of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0020] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0021] The current technology for finding the left and right boundaries of the control signal (ca) relies on traversing the value combination of ca_delay[i] and ck_delay. The positional relationship between the control signal (ca) and the clock signal (ck) is in an unaware state, and it is difficult to determine whether the control signal (ca) needs to be shifted left or right relative to the clock signal (ck), which takes a long time. In addition, the control signal (ca) has 7 bits, and the positions of different bits of the control signal (ca) are also different. Each bit of the control signal (ca) may need to be shifted left or right. The adjustable range between ca_delay and ck_delay is limited. Once the boundary cannot be found, it will be difficult to handle. In addition, ck_delay is also closely related to the chip select signal (cs) and cannot be adjusted at will, which also increases the difficulty of training.

[0022] The present invention determines the positional relationship between the control signal and the clock signal through the return value, thereby obtaining whether left shift or right shift is required when finding the left and right boundaries of each bit of ca, reducing the time spent, clarifying the adjustment direction, saving simulation time, and improving work efficiency; the present invention combines coarse adjustment and fine adjustment, which can reduce the number of adjustments and save time, and can also ensure the adjustment precision and improve the accuracy; the present invention adjusts the control signal bit by bit to ensure that the control signal has the maximum edge width and improves the stability; the present invention has strong flexibility, and various positional relationships between the bits of the control signal and various positional relationships between the control signal and the clock signal can be flexibly processed.

[0023] Example 1 A method for fast ca train for lpddr5, reference Figure 1 ,include: S100, sends three sets of data to the CA of the Command Bus Training Mode particle, and receives the return results of the DQ signal line respectively; The physical layer (Phy) is the lowest layer in the OSI model of computer networks, and is mainly responsible for providing physical connections and transmission media for data transmission. The physical layer specifies the mechanical, electronic, functional, and normative characteristics required to create, maintain, and dismantle physical links, ensuring that original data can be transmitted on various physical media. The physical layer provides a reliable transmission environment for data communication between devices, shielding the differences between different physical devices and transmission media, so that the upper data link layer only needs to focus on the protocols and services of this layer without having to consider the specific transmission media.

[0024] Storage particles usually refer to memory particles, which are mainly used in dynamic random access memory (DRAM). Memory particles are composed of millions of capacitors and transistors and are used to store data. These particles are packaged to become memory particles, which are an important component of computer memory.

[0025] In the embodiment of the present invention, the physical layer sends three different groups of data to the storage particles, and then the data receiving end receives the feedback results to determine the positional relationship between the control signal and the clock signal.

[0026] S200, determining the relationship between each bit in the CA signal and the clock signal according to the received result; There are generally three situations of the received results, which correspond to the positional relationships between the three control signals and the clock signal respectively. The present invention can quickly and accurately determine the positional relationship between the control signal and the clock signal based on the received results.

[0027] S300, adjusting the delay of the CA signal according to the relationship between each bit in the CA signal and the clock signal.

[0028] With the positional relationship between the control signal and the clock signal, we can proceed to the next step, which is to adjust the control signal delay so that the middle of the control signal edge is aligned with the rising edge or falling edge of the clock signal.

[0029] Preferably, S100, sending three sets of data to the CA of the Command Bus Training Mode particle, and receiving the return results of the DQ signal lines respectively include: After the first data: 0, 7f, 0, 7f, is sent out and the data receiving end receives the corresponding result, the second data: 0, 0, 7f, 0 is sent; After the second data is sent out and the data receiving end receives the corresponding result, the third data is sent: 7f, 0, 7f, 7f.

[0030] In the embodiment of the present invention, specifically, a first set of data is sent to the particle CA, and the data receiving end receives the corresponding result after the data is sent out; sending a second line pattern; After the second line pattern is sent out and the data receiving end receives the corresponding result, the third line pattern is sent.

[0031] A total of 3 data are sent to the storage particles, and the control signal of each data is four consecutive 7f or 0. The first data is 0, 7f, 0, 7f; the second data is 0, 0, 7f, 0; the third data is 7f, 0, 7f, 7f. After the current data is sent out and the data receiving end receives the corresponding result, the next data is sent. After the three data are completed, the position relationship between each bit of the control signal and the clock signal can be determined by combining the data from the three data receiving ends.

[0032] Preferably, reference Figure 5 , Figure 6 and Figure 7 , S200, judging the relationship between each bit in the CA signal and the clock signal according to the received result includes: If the received result is 0, 1, 1, it means that the rising edge of the clock signal is in the middle of the control signal; If the received result is 0, 1, 1, it means that the rising edge of the clock signal is in the middle of the left and right boundaries of the control signal, and each bit of the data receiving end corresponds to the control signal one by one. If the result of dq[i] three times is 0, 1, 1, then finding the two boundaries of the control signal only requires shifting the control signal left and right.

[0033] If the received result is 1, 0, 0, it means that the rising edge of the clock signal is to the left of the left boundary of the control signal; If the received result is 1, 0, 0, it means that the rising edge of the clock signal corresponds to the left side of the left boundary of the control signal. If the three results of dq[i] are 1, 0, 0 respectively, then the control signal needs to be shifted left to find both boundaries of the control signal.

[0034] If the received result is 1, 0, 1, it means that the rising edge of the clock signal is close to the right side of the right boundary of the control signal.

[0035] If the received results are 1, 0, 1, it means that the rising edge of the clock signal corresponds to the right side of the right boundary of the control signal. If the three results of dq[i] are 1, 0, 1 respectively, then the control signal needs to be shifted right to find both boundaries of the control signal.

[0036] In an embodiment of the present invention, the result received by the data receiving end can be used to determine the approximate positional relationship between the boundary of the control signal and the rising edge of the clock signal, and then the control signal delay can be changed according to the determined positional relationship to achieve the purpose of aligning the middle of the control signal with the rising edge of the clock signal. This overcomes the technical problem in the prior art of relying on traversing the difference between ca_delay and ck_delay, being in an unaware state of the positional relationship between the control signal and the clock signal, and being difficult to determine whether the control signal needs to be shifted left or right relative to the clock signal, and taking a long time. The present invention can accurately determine the positional relationship between the control signal and the clock signal, and then make corresponding improvements to the positional relationship between the control signal and the clock signal, which can save adjustment time and does not require traversing the entire signal, thereby greatly improving work efficiency.

[0037] Preferably, S300, adjusting the delay of the CA signal according to the relationship between each bit in the CA signal and the clock signal includes: S310, pre-adjusting the delay of the control signal so that the rising edge of the clock signal is in the middle of the control signal; In order to reduce the amount of code, in the latter two cases, the control signal will first be shifted left or right by two ui (half a clock signal cycle) to change the control signal edge to the middle close to the rising edge or falling edge of the clock signal.

[0038] S320, coarsely adjusting the delay of the control signal to quickly find the approximate position of the control signal boundary; S330, coarsely adjusting and finely adjusting the delay of the control signal to find the boundary of the control signal.

[0039] When the delay of the control signal is adjusted to be close to the rising edge or falling edge of the clock signal, fine adjustment should be started so that the middle of the control signal is exactly aligned with the rising edge or falling edge of the clock signal.

[0040] The delay of the coarse control signal can find the approximate location of the CA boundary more quickly; The delay of the fine-tuning control signal can ensure accuracy based on the coarse-tuning control signal.

[0041] Combining coarse adjustment and fine adjustment can both increase speed and ensure accuracy.

[0042] Preferably, S310, pre-adjusting the delay of the control signal so that the rising edge of the clock signal is exactly in the middle of the control signal includes: S311, when it is detected that the rising edge of the clock signal is to the right of the right boundary of the control signal, the control signal is shifted rightward by half a clock cycle; The clock cycle is also called the oscillation period, which is defined as the inverse of the clock frequency. It is the most basic and smallest unit of time in a computer. In one clock cycle, the CPU only completes one basic action. The clock cycle represents the highest frequency at which the SDRAM can operate. A smaller clock cycle means a higher operating frequency.

[0043] S312, when it is detected that the rising edge of the clock signal is close to the left side of the left boundary of the control signal, the control signal is shifted left by half a clock cycle.

[0044] Preferably, reference Figure 8 , S320, the delay of the control signal to find the left boundary of the control signal includes: S321, increasing the delay value of the control signal so that the control signal moves rightward to find the left boundary; Increasing the control signal delay moves the control signal to the right, making the left boundary of the control signal closer to the rising edge of the clock signal. When the left boundary of the control signal is close to the rising edge of the clock signal, reduce the delay value until the return value jumps, indicating that the left boundary of the control signal has been found.

[0045] S322, each time the value of the control signal delay is changed, data is sent once until the value at the data receiving end changes from 1 to 0; The value of each change in the control signal delay can be set relatively large first, and then coarse adjustment is performed, and then check whether the data receiving end has a jump. If it has a jump, return to the result of the previous coarse adjustment, and then reduce the value of each change in the control signal delay, perform fine adjustment, and then check whether the data receiving end has a jump, and so on, until the data receiving end jumps, it means that the current control signal delay value represents the distance between the left boundary of the control signal and the rising edge of the clock signal. The present invention first searches for a larger range, and then slowly narrows the range until the accurate delay value is found, so as to determine how far the left boundary of the control signal is from the clock signal.

[0046] S323, when the value of a bit at the data receiving end changes from 1 to 0, it indicates that the left boundary of the control signal of this bit has been found; The number of bits of the control signal depends on the number of states it needs to represent. In a communication system, the control signal is usually represented by different symbols (code elements), and the number of states that each symbol can represent determines the number of bits required. In the embodiment of the present invention, the control signal has a total of seven bits, which come from different lines. Since the routes of each line are different, the delay of each line is also different, which can easily lead to inaccurate sampling of the clock signal. Therefore, the boundary of each bit of the control signal must be found and then aligned.

[0047] S324, stop increasing the delay value of the corresponding control signal, and continue to increase the delay value of the control signal for the bit where no jump occurs, until the control signals of all bits find the left boundary.

[0048] After determining the positional relationship between each bit of ca and ck and classifying it as the first case, start adjusting the value of ca_delay[i] and send a new pattern. First increase the value of ca_delay[i] to shift ca to the right to find the left boundary. Each time the value of ca_delay[i] is changed, send a pattern until the value of dq[i] changes from 1 to 0. When the dq value of a bit changes from 1 to 0, it means that the left boundary of ca of this bit has been found. Then stop increasing the corresponding ca_delay[i]. Continue for other bits that have not jumped until the left boundary of ca of all bits has been found.

[0049] Preferably, S320, delaying the control signal to find the right boundary of the control signal includes: S325, increasing the delay value of the control signal so that the control signal moves leftward and finds the right boundary; Before finding the right boundary of the control signal, the control signal is first shifted left as a whole by (3 / 4)*half a clock cycle, and then the right boundary is found according to the method of finding the left boundary.

[0050] S326, each time the value of the control signal delay is changed, it is sent once until the value at the data receiving end changes from 1 to 0; The data receiving end DQ is used for data transmission and is bidirectional. It can be used as both data input and data output. The DQ pin is used for data read and write operations. In the read operation, the memory chip transmits the stored data to the motherboard or other processing units through the DQ pin. In the write operation, the processing unit writes the data to the memory chip through the DQ pin. In order to ensure accurate data transmission, there are usually one or more DQS (Data Strobe) pins used to synchronize the data on the DQ pin. The DQS pin provides a clock signal during data transmission to ensure that the data is read or written at the right time.

[0051] S327, when the value of a bit at the data receiving end changes from 1 to 0, it indicates that the right boundary of the control signal of this bit has been found; S328, reducing the value of the control signal delay until all bits are switched.

[0052] Then start looking for the right boundary. First, shift ca to the left as a whole by (3 / 4)*half the ck period, and then follow the method of finding the left boundary and start reducing the value of ca_delay[i] until all bits are changed.

[0053] Record the ca_delay[i] value of each bit when the left and right boundaries are found, and take the average of the corresponding bits to get the final result.

[0054] Preferably, it also includes: First, use a larger step size a to roughly adjust the control signal delay, and then use a smaller step size b to fine-tune the control signal delay; In an embodiment of the present invention, the delay of the control signal can be adjusted by a calibration delay circuit. The transmission time of the signal can be extended by using a calibration delay circuit. The calibration delay circuit is a circuit with a specific delay time, which can delay the input signal for a period of time before outputting it. By adjusting the delay time of the delay circuit, the delay of the signal can be controlled. The delay circuit usually uses a signal such as a clock to control the delay time.

[0055] If a jump occurs after n*a is added, the control signal is delayed back to (dly_init+(n-1)*a); Use a step size b that is smaller than a for adjustment. If a jump occurs after adding m*b, the control signal delay of the left boundary is finally found to be (initial delay + (n-1)*a + m*b).

[0056] With this method, you can make a rough adjustment first and then a fine adjustment when finding the boundary, further saving simulation time. Taking the search for the left boundary as an example, assuming that the initial ca_delay is dly_init, first use a larger step size a to adjust ca_delay. If a jump occurs after increasing n*a, first roll back ca_delay to (dly_init+(n-1)*a), and then use a smaller step size b to adjust. If a jump occurs after increasing m*b, the final ca_delay for the left boundary is: (dly_init+(n-1)*a+m*b).

[0057] Example 2 A system for fast ca train for lpddr5, comprising: The data sending module is used to send three sets of data to the CA of the Command Bus Training Mode particle and receive the return results of the DQ signal line respectively; A data receiving module is used to determine the relationship between each bit in the CA signal and the clock signal according to the received result; The data processing module is used to adjust the delay of the CA signal according to the relationship between each bit in the CA signal and the clock signal.

[0058] Example 3 An electronic device comprises: a chip, a processor and a memory, wherein the memory is used to store computer program codes, and the computer program codes comprise computer instructions. When the chip executes the computer instructions, the electronic device executes a method for fast ca train of lpddr5.

[0059] refer to Fig. 9 , the electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled via a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0060] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0061] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or portable read only memory (CD-ROM), which is used for related instructions and data.

[0062] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 may be independent devices or an integrated device.

[0063] The present invention judges the positional relationship between the control signal and the clock signal through the return value, so as to obtain whether the left or right shift is required when finding the left and right boundaries of each bit of ca, thereby reducing the time spent, clarifying the adjustment direction, saving simulation time, and improving work efficiency; the present invention combines coarse adjustment and fine adjustment, which can reduce the number of adjustments and save time, and can also ensure the adjustment precision and improve the accuracy; the present invention adjusts the control signal bit by bit, ensures that the control signal has the maximum edge width, and improves the stability; the present invention has strong flexibility, and various positional relationships between the bits of the control signal and various positional relationships between the control signal and the clock signal can be flexibly processed.

[0064] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for fast ca train of lpddr5, characterized in that, include: Send three sets of data to the CA of the Command Bus Training Mode particle and receive the return results of the DQ signal line respectively; Determine the relationship between each bit in the CA signal and the clock signal based on the received results; The delay of the CA signal is adjusted according to the relationship between each bit in the CA signal and the clock signal.

2. A method for fast ca train for lpddr5 according to claim 1, characterized in that, The sending of three sets of data to the CA of the Command Bus Training Mode particle and receiving the return results of the DQ signal lines respectively include: After the first data: 0, 7f, 0, 7f, is sent out and the data receiving end receives the corresponding result, the second data: 0, 0, 7f, 0 is sent; After the second data is sent out and the data receiving end receives the corresponding result, the third data is sent: 7f, 0, 7f, 7f.

3. A method for fast ca train for lpddr5 according to claim 1, characterized in that, Determining the relationship between each bit in the CA signal and the clock signal according to the received result includes: If the received result is 0, 1, 1, it means that the rising edge of the clock signal is in the middle of the control signal; If the received result is 1, 0, 0, it means that the rising edge of the clock signal is to the left of the left boundary of the control signal; If the received result is 1, 0, 1, it means that the rising edge of the clock signal is to the right of the right boundary of the control signal.

4. A method for fast ca train for lpddr5 according to claim 1, characterized in that, The step of adjusting the delay of the CA signal according to the relationship between each bit in the CA signal and the clock signal includes: The delay of the control signal is pre-adjusted so that the rising edge of the clock signal is in the middle of the control signal; Coarsely adjust the delay of the control signal to quickly find the approximate position of the control signal boundary The delay of the control signal is fine-tuned to find the precise position boundary of the control signal.

5. A method for fast ca train for lpddr5 according to claim 4, characterized in that, The delay of the coarse control signal makes the rising edge of the clock signal exactly in the middle of the control signal, including: When it is detected that the rising edge of the clock signal is to the right of the right boundary of the control signal, the control signal is shifted right by half a clock cycle; When it is detected that the rising edge of the clock signal is close to the left side of the left boundary of the control signal, the control signal is shifted left by half a clock cycle.

6. A method for fast ca train for lpddr5 according to claim 4, characterized in that, The delay of the control signal to find the left boundary of the control signal includes: Increase the value of the control signal delay to shift the control signal to the right and find the left boundary; Each time the value of the control signal delay is changed, data is sent once until the value at the data receiving end changes from 1 to 0; When the value of a bit at the data receiving end changes from 1 to 0, it means that the left boundary of the control signal of this bit has been found; Stop increasing the delay value of the corresponding control signal, and continue to increase the delay value of the control signal for the bit that has not jumped until the control signals of all bits find the left boundary.

7. A method for fast ca train for lpddr5 according to claim 4, characterized in that, The delay of the fine-tuning control signal to find the right boundary of the control signal comprises: Increase the value of the control signal delay to shift the control signal to the left and find the right boundary; Each time the value of the control signal delay is changed, it is sent once until the value at the data receiving end changes from 1 to 0; When the value of a bit at the data receiving end changes from 1 to 0, it means that the right boundary of the control signal of this bit has been found; Reduce the value of the control signal delay until all bits transition.

8. A method for fast ca train of lpddr5 according to claim 6 or 7, characterized in that: Also includes: First, use a larger step size a to roughly adjust the control signal delay, and then use a smaller step size b to fine-tune the control signal delay; If a jump occurs after adding n*a, the control signal is delayed back to: dly_init+(n-1)*a; Use a step size b that is smaller than a for adjustment. If a jump occurs after adding m*b, the control signal delay of the left boundary is finally found to be: initial delay + (n-1)*a + m*b.

9. A system for fast ca train of lpddr5, characterized in that, include: The data sending module is used to send three sets of data to the CA of the Command Bus Training Mode particle and receive the return results of the DQ signal line respectively; A data receiving module is used to determine the relationship between each bit in the CA signal and the clock signal according to the received result; The data processing module is used to adjust the delay of the CA signal according to the relationship between each bit in the CA signal and the clock signal.

10. An electronic device, characterized in that: include: A chip, a processor and a memory, wherein the memory is used to store computer program codes, wherein the computer program codes include computer instructions, and when the chip executes the computer instructions, the electronic device executes a method for fast CATrain of LPDDR5 as described in any one of claims 1 to 8.

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