Multi-domain storage device performing domain balancing operation and operating method thereof

Abstract

A storage device configured to perform address mapping in a multi-domain manner includes: a non-volatile memory device including a plurality of dies associated with a first domain or a second domain; and a storage controller configured to map a logical address of the write request to a first physical address mapped to the first domain. In response to detecting that the workload or resource corresponding to the write request is concentrated in the first domain at a reference ratio or higher ratio, the storage controller is configured to redirect a first physical address mapped to the first domain to a second physical address allocated to the second domain.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0148806 filed in the Korean Intellectual Property Office on November 1, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of the present disclosure described herein relate to a storage device, and more particularly, to a multi-domain storage device that performs a domain balancing operation and an operating method thereof. Background Art

[0003] As storage capacity increases, multi-domain address mapping is being applied to storage, such as solid-state drives (hereinafter referred to as SSDs). As the storage capacity of SSDs increases, the size of the mapping table used for address mapping also increases. As the size of the mapping table increases, the capacity of the DRAM storing the mapping table must also increase. When multi-domain address mapping is used, a mapping table can be independently assigned to each of a plurality of domains. Applying this method can have the effect of reducing the maximum capacity of physical addresses to be managed, thereby reducing the size of the entire mapping table.

[0004] However, depending on the workload of the host system, input / output I / O requests may be concentrated in a specific domain of the SSD. The overall performance of the SSD may be limited according to the performance limitations of the domain where the I / O requests are concentrated. Summary of the invention

[0005] The embodiments of the present disclosure may be directed to the situation where I / O requests are concentrated in one domain during multi-domain address mapping. The embodiments of the present disclosure provide a multi-domain storage device that performs domain balancing operations and an operation method thereof.

[0006] According to an embodiment of the present invention, a storage device configured to perform address mapping in a multi-domain manner includes: a non-volatile memory device including multiple dies, wherein the dies or storage blocks of the dies are associated with a first domain or a second domain; and a storage controller configured to map a logical address of a write request to a first physical address mapped to the first domain, and in response to detecting that a workload or resource corresponding to the write request is concentrated in the first domain at a reference ratio or a higher ratio, redirect a portion of the first physical address mapped to the first domain to a second physical address assigned to the second domain.

[0007] According to an embodiment of the present invention, a method for operating a storage device to perform address mapping according to a multi-domain method includes: receiving a write request; detecting a load imbalance between multiple domains according to the write request, wherein the multiple domains are associated with a storage die or a corresponding subset of storage blocks of the storage die; generating a new flow in addition to an existing flow in which the load among the multiple domains is higher than that of a first domain in a reference value set; and redirecting a target physical address of the new flow to a storage block included in a second domain among the multiple domains.

[0008] According to an embodiment of the present invention, a storage device configured to perform address mapping in a multi-domain manner includes: a non-volatile memory device including multiple dies, wherein the dies or storage blocks of the dies are associated with a first domain or a second domain; a storage controller configured to map a logical address of a write request to a first physical address mapped to the first domain, and in response to detecting that a load corresponding to the write request is concentrated in the first domain at a reference ratio or a higher ratio, redirect a portion of the first physical address mapped to the first domain to a second physical address assigned to the second domain; and a buffer memory configured to store a mapping table mapping logical addresses to physical addresses, wherein the storage controller includes: a domain allocator configured to allocate physical addresses of dies in multiple dies by referring to specific bits of the logical address to write data requested to be written by the write request to the first domain or the second domain; an input / output monitor configured to monitor whether the workload or resources corresponding to the write request are concentrated in the first domain at a ratio greater than the reference ratio; and a domain redirection unit configured to redirect a portion of the first physical address mapped to the first domain to the second physical address assigned to the second domain. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0010] Figure 1 is a block diagram showing a storage system including the storage device of the present invention.

[0011] Figure 2 It is shown exemplarily Figure 1 Block diagram of a storage device.

[0012] Figure 3 It is shown Figure 2 A block diagram of the configuration of a nonvolatile memory device shown in FIG.

[0013] Figure 4 is a block diagram showing the structure of a nonvolatile memory device of the present invention.

[0014] Figure 5 It is a diagram schematically showing a domain redirection method in multi-domain mapping according to the present invention.

[0015] Figure 6 4 is a diagram briefly showing the entry size of the mapping table added for domain redirection according to the present invention.

[0016] Figure 7 is a diagram illustrating the effect of domain redirection according to an embodiment of the present invention.

[0017] Figure 8 is a flow chart illustrating a domain redirection method activated when a domain imbalance is detected according to an embodiment of the present invention.

[0018] Fig. 9 It is shown Figure 1 A block diagram of another configuration method of a storage controller.

[0019] Fig.10 is a flow chart illustrating a domain redirection operation according to another embodiment of the present invention.

[0020] Fig.11 is a table showing an example of a write allocation method according to the imbalance rate of each domain.

[0021] Fig.12 is a table showing another example of a write allocation method according to the imbalance rate of each domain.

[0022] Fig.13 is a block diagram illustrating a storage system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] It should be understood that the above overview and the detailed description below are exemplary and should be considered as providing additional descriptions for the claimed invention. In the preferred embodiment of the present invention, the reference numerals are marked in detail, and examples thereof are marked in the drawings. Where possible, the same reference numerals are used in the description and the drawings to refer to the same or similar parts. The terms "first", "second", etc. can be used only to distinguish one component, layer, direction, etc. from another component, layer, direction, etc. in this article. When used in this article, the terms "include", "comprise", "have", and / or "contain in" specify the existence of the stated elements, but do not exclude the existence of other elements. The term "and / or" includes any and all combinations of one or more items listed in association. The term "connection" can be used to refer to physical and / or electrical connections in this article. When a component or layer is referred to as "directly" on it, or "directly in contact" or "directly connected" in this article, there is no intermediate component or layer. Similarly, when components are "directly" adjacent to each other, there may be no intermediate component.

[0024] Figure 11 is a block diagram showing a storage system including a storage device of the present invention. The storage system 1000 may include a host 1100 and a storage device 1200. And the storage device 1200 includes a storage controller 1210, a nonvolatile memory device 1230, and a buffer memory 1250.

[0025] The host 1100 can manage and process the overall operation of the storage system 1000. The host 1100 can send a read or write request to the storage device 1200. That is, the host 1100 sends an I / O request. To this end, the host 1100 can generate a write command or a read command. The host 1100 can perform various arithmetic / logical operations to access the storage device 1200. For example, the host 1100 may include one or more processor cores. The host 1100 can be implemented using a dedicated circuit (e.g., a field programmable gate array FPGA or an application-specific integrated circuit ASIC), or can be implemented as a system-on-chip SoC. The host 1100 may include a general-purpose processor, a dedicated processor, or an application processor. The host 1100 may be the processor itself, or an electronic device or system including a processor.

[0026] The storage device 1200 may include a storage controller 1210, a nonvolatile memory device 1230, and a buffer memory 1250. The storage controller 1210 may program data in the nonvolatile memory device 1230 according to a write request from the host 1100. Alternatively, the storage controller 1210 may read data stored in the nonvolatile memory device 1230 according to a read request from the host 1100. To this end, the storage controller 1210 manages a mapping table that defines a correspondence between a logical address and a physical address of data stored (or to be stored) in the nonvolatile memory device 1230. For example, the storage controller 1210 may manage a logical block address (LBA) to physical block address mapping table to record a mapping relationship between a logical address (managed by the host 1100) and a physical address (managed by the storage controller 1210). The mapping table may be a table or other data structure that includes a logical address associated with each memory location where data is stored in the nonvolatile memory device 1230. The mapping table is mainly stored and managed in the buffer memory 1250 provided as a DRAM.

[0027] The storage controller 1210 may perform the function of a flash translation layer FTL. By using the flash translation layer FTL, the shortcomings of the non-volatile memory device 1230, such as erasing before writing and the mismatch between the erase unit and the write unit, may be compensated. Specifically, the flash translation layer FTL maps the logical address generated by the file system of the host 1100 to the physical address of the non-volatile memory device 1230. In addition, the flash translation layer FTL performs wear leveling to manage the service life of the non-volatile memory device 1230, and performs garbage collection to manage data capacity.

[0028] Specifically, the storage controller 1210 uses a multi-domain method when mapping addresses. As used herein, a "domain" may refer to a group of storage areas, such as a group of storage blocks or a group of storage chips. For example, a first subset of storage blocks or chips may be associated with a first domain, and a second subset of storage blocks or chips may be associated with a second domain. As the capacity of the non-volatile memory device 1230 increases, the size of the mapping table for mapping logical addresses to physical addresses also increases. Therefore, the capacity of the buffer memory 1250 storing the mapping table must also increase. In order to reduce or minimize the cost increase caused by the size of the mapping table, one of the techniques for reducing the size of the mapping table is a multi-domain mapping technique.

[0029] According to the multi-domain mapping, the first mapping table and the second mapping table may be configured according to a specific bit of a logical address (e.g., LBA) sent from the host 1100. A different processor is assigned to each of the first mapping table and the second mapping table to process the mapping operation. Here, the first mapping table maps the logical address to the first die group of the nonvolatile memory device 1230 (i.e., mapped to a physical address corresponding to the first die group). On the other hand, the second mapping table maps the logical address to a second die group physically separated from the first die group (i.e., mapped to a physical address corresponding to the second die group). Through this multi-domain address mapping, the mapping table of each domain can be reduced by at least 1 bit.

[0030] In the above-mentioned multi-domain method, the logical addresses of the input / output requests provided by the host 1100 can be concentrated in one domain. This phenomenon of input / output requests being concentrated in a specific domain is called domain imbalance or domain skew. When domain imbalance occurs, write operations only occur or are concentrated in one domain, and thus the performance of the storage device 1200 is limited to the operational performance of the domain in which the input / output requests are concentrated. In addition, the utilization of the domain with a lower workload will decrease, and thus the wear leveling characteristics will deteriorate.

[0031] When such a domain imbalance occurs, the storage controller 1210 of the present invention can access the storage blocks or chips managed by one or more idle domains by creating a new stream for the input / output request. Using the new stream, the domain redirection unit 1216 can redirect the logical address of the input / output request from the physical address of the busy domain to the physical address of the idle domain (for example, from the first physical address of the first domain to the second physical address of the second domain) in the case of domain imbalance. The domain balancing function of the storage controller 1210 will be described in more detail through the drawings described later.

[0032] The non-volatile memory device 1230 may store data received from the memory controller 1210 or send the stored data to the memory controller 1210 under the control of the memory controller 1210. The non-volatile memory device 1230 may include a plurality of dies, and each die may include a plurality of memory blocks. In the non-volatile memory device 1230, only one memory block is selected from one die during a write operation. Therefore, selecting a die during a write operation may have the same meaning as selecting a memory block. Here, each of the plurality of memory blocks may have a three-dimensional memory structure in which word line layers are stacked in a vertical direction on a substrate. The memory controller 1210 may manage each of the plurality of memory blocks through information for wear leveling, such as an erase count (hereinafter referred to as EC).

[0033] The buffer memory 1250 provides a buffer function or a metadata loading function of the storage device 1200. In addition, the buffer memory 1250 may support a direct memory access (DMA) function for data exchanged between the nonvolatile memory device 1230 and the host 1100. That is, the buffer memory 1250 provides a buffer function to temporarily store data programmed in the nonvolatile memory device 1230 or data output from the nonvolatile memory device 1230. Specifically, the buffer memory 1250 may store a mapping table or various metadata generated by the storage controller 1210. The buffer memory 1250 of the present invention may load a multi-domain mapping table.

[0034] According to the above configuration, when the input / output request from the host 1100 is concentrated in the first domain, the storage device 1200 of the present invention can perform a load balancing function between the first domain and the second domain in the storage device. Therefore, it is possible to prevent the performance degradation caused by the load concentration on a specific domain in the storage device 1200 having a multi-domain structure and the reduction in the utilization and life of the non-volatile memory device 1230.

[0035] Figure 2 It is shown exemplarily Figure 1 Block diagram of a storage device. Figure 2, the storage device 1200 may include a storage controller 1210, a non-volatile memory device 1230, and a buffer memory 1250. For example, the storage controller 1210, the non-volatile memory device 1230, and the buffer memory 1250 may each be provided as a chip, a package, or a module or circuit. Alternatively, the storage controller 1210, the non-volatile memory device 1230, and the buffer memory 1250 may be included in one chip, one package, or one module or circuit. That is, the storage controller 1210, the non-volatile memory device 1230, and the buffer memory 1250 may be composed of storage devices such as embedded memory, memory card, memory stick, and solid state drive SSD.

[0036] The storage controller 1210 may be configured to control the nonvolatile memory device 1230 and the buffer memory 1250. For example, the storage controller 1210 may be configured to control the nonvolatile memory device 1230 and the buffer memory 1250 according to the host 1100 (see Figure 1 ) to write data to the nonvolatile memory device 1230 or read data stored in the nonvolatile memory device 1230. In order to access the nonvolatile memory device 1230, the storage controller 1210 may receive an I / O request, such as a read command or a write command. Then, the I / O request from the host 1100 may include a logical address (LBA or LPN (Logical Page Number)).

[0037] Specifically, the storage controller 1210 performs multi-domain address mapping on the logical address from the host 1100. At this time, the input / output request can be concentrated in one domain based on the logical address. In this case, the storage controller 1210 can detect the situation where the input / output request to a specific domain is concentrated (hereinafter referred to as domain tilt or domain imbalance). When the domain tilt is detected, the storage controller 1210 redirects the mapping of the physical blocks (or tube cores) concentrated in one domain to the physical blocks in another idle domain. Hereinafter, when such input / output requests are concentrated in a specific domain, the operation of generating additional streams and allocating them to the idle domain will be referred to as a domain balancing operation. For this domain balancing operation, the storage controller 1210 may include a domain allocator 1212, an input / output monitor 1214, and a domain redirection unit 1216.

[0038] The domain allocator 1212 allocates domains according to the logical address accompanying the I / O request. For example, when operating two domains (Domain_0, Domain_1), the domain allocator 1212 can configure the first mapping table (MT_0, 1251) and the second mapping table (MT_1, 1253) according to the specific bit (e.g., LSB) of the logical address LBA included in the input / output request (I / O request). The first mapping table MT_0 maps the logical address to the physical address of the storage block (or die) corresponding to the first domain Domain_0. And the second mapping table MT_1 maps the logical address to the physical address of the storage block (or die) corresponding to the second domain Domain_1. That is, when the specific bit of the logical address LBA is logical '0' (or an even number), the domain allocator 1212 maps the input logical address LBA to the first domain Domain_0. And when a specific bit of the logical address LBA is logic '1' (or an odd number), the domain allocator 1212 maps the input logical address LBA to the second domain Domain_1. However, the input logical address (LBA or LPN) is not provided in a domain-balanced manner. Therefore, domain imbalance may occur according to the logical address (LBA or LPN).

[0039] The input / output monitor 1214 detects domain imbalance (or skew) generated by the domain allocator 1212. The input / output monitor 1214 may monitor the input / output performance of each domain. For example, the input / output monitor 1214 may monitor the workload or resources of each domain (Domain_0 and Domain_1). If it is observed that the workload or resources are concentrated in one domain, the input / output monitor 1214 may provide the monitoring result to the domain redirection unit 1216.

[0040] The domain redirection unit 1216 may redirect the logical address of the input / output request from the busy domain to the idle domain according to the monitoring result of the input / output monitor 1214. For example, the input / output monitor 1214 may detect that the write request is concentrated in the first domain Domain_0. Then, the domain redirection unit 1216 may reallocate the mapping of the logical address of the specified first domain Domain_0 to the storage block (or die) of the second domain Domain_1. For this operation, the domain redirection unit 1216 may open a new flow and map the physical address of the new flow to the storage block (or die) of the second domain Domain_1. For the address mapping of the new flow, the domain redirection unit 1216 may create an additional mapping table.

[0041] The non-volatile memory device 1230 includes a plurality of dies Die_0 to Die_7 implemented as flash memories. The plurality of dies Die_0 to Die_7 may each be divided into domain units. Dies Die_0 to Die_3 may correspond to a first domain Domain_0, and dies Die_4 to Die_7 may constitute a second domain Domain_1. Dies Die_0 to Die_3 constituting the first domain Domain_0 are connected to a first channel, allowing simultaneous or pipeline write operations. In addition, dies Die_4 to Die_7 constituting the second domain Domain_1 are connected to a second channel, allowing simultaneous or pipeline write operations. That is, each domain may be assigned to a stream capable of simultaneous write operations.

[0042] The buffer memory 1250 may include a first mapping table MT_0 and a second mapping table MT_1. The first mapping table MT_0 may map a logical address to a physical address region corresponding to the first domain Domain_0. And the second mapping table MT_1 may map a logical address to a physical address region corresponding to the second domain Domain_1. Specifically, when a domain imbalance is detected and domain redirection occurs, an additional mapping table may be created in addition to the first mapping table MT_0 or the second mapping table MT_1. The additional mapping table serves to remap or redirect the physical block mapping of the domain where the input / output request is concentrated to the idle domain.

[0043] Therefore, even when input / output requests from the host 1100 are concentrated in one domain through the above-mentioned storage device 1200, load balancing between domains can be achieved. Therefore, in the storage device 1200 having a multi-domain structure, performance degradation and reduction in the utilization rate or life of the die due to the concentration of load on a specific domain can be reduced or prevented.

[0044] Figure 3 It is shown Figure 2 A block diagram of the configuration of a nonvolatile memory device shown in FIG. Figure 3 , the nonvolatile memory device 1230 may include a plurality of dies Die_0 to Die_7 .

[0045] A plurality of dies Die_0 to Die_7 may be arranged in a multi-channel structure. In the present invention, for ease of explanation, it is assumed that a plurality of dies Die_0 to Die_7 are arranged in a 2-channel structure. For example, dies Die_0 to Die_3 are connected to a first channel CH0, and dies Die_4 to Die_7 are connected to a second channel CH1. Dies Die_0 to Die_3 connected to the first channel CH0 constitute a first domain Domain_0, and dies Die_4 to Die_7 connected to the second channel CH1 constitute a second domain Domain_1. The write speed of each die Die_0 to Die_7 implemented as a flash memory device is relatively slow. However, the write performance can be improved by providing write commands and write data to a chip connected to one channel in a pipeline. In other words, when write commands and data are provided to each die Die_0 to Die_3 in sequence, the time required for the write operation of each die is the same, but the write speed of all four dies can be improved.

[0046] When a stream is opened according to these channel attributes, the data of the opened stream is allocated on a domain basis, thereby ensuring high write performance. That is, when address mapping is performed for a write request in a multi-domain manner, the storage controller 1210 can open the first stream Stream_0 allocated to the first domain Domain_0. Then, the data of the first stream Stream_0 is mapped to the physical address of the first domain Domain_0, thereby achieving a high-speed write operation.

[0047] Specifically, when the domain redirection method of the present invention is used, even if a domain imbalance occurs or when a domain imbalance occurs, the physical address of the busy domain or the physical address corresponding to the busy domain can be redirected to the idle domain. Therefore, the overhead caused by the domain imbalance of the present invention can be prevented. Here, the non-volatile memory device 1230 constituting two channels has been described as an example, but the present invention is not limited to the number of channels specifically described herein. It can be understood that in various embodiments, various numbers of dies can be connected to three or more channels.

[0048] Figure 4 1 is a block diagram schematically showing the structure of a nonvolatile memory device of the present invention. Figure 4 , shows the structure of a non-volatile memory die Die_i implemented as a flash memory device. The non-volatile memory die Die_i may include a cell array 1231, a row decoder 1232, a page buffer circuit 1233, a control logic circuit 1234, and a voltage generator 1235. Figure 4Although not shown, the nonvolatile memory device 1230 may further include a data input / output circuit or an input / output interface. In addition, the nonvolatile memory device 1230 may further include components such as column logic, a pre-decoder, a temperature sensor, a command decoder, and an address decoder.

[0049] The cell array 1231 may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of memory cells. A plurality of memory blocks may be included in one memory plane, but the present invention is not limited thereto. The cell array 1231 may be connected to the row decoder 1232 via a page buffer circuit 1233, a bit line BL, a word line WL, a string selection line SSL, and a ground selection line GSL. In an example embodiment, the cell array 1231 may include a three-dimensional memory cell array.

[0050] The row decoder 1232 may select one of the memory blocks of the cell array 1231 in response to the address ADDR. The row decoder 1232 may select one of the word lines of the selected memory block in response to the address ADDR. The row decoder 1232 transmits a voltage VWL corresponding to the operation mode to the word line of the selected memory block. During a programming operation, the row decoder 1232 provides a program voltage and a verification voltage to the selected word line, and provides a pass voltage to an unselected word line. During a read operation, the row decoder 1232 provides a read voltage to the selected word line, and provides a read pass voltage to an unselected word line.

[0051] The page buffer circuit 1233 may include a plurality of page buffers PB0 to PBn-1. The plurality of page buffers PB0 to PBn-1 may be connected to the memory cells through a plurality of bit lines BL, respectively. The page buffer circuit 1233 may select at least one bit line among the bit lines BL in response to the column address. The page buffer circuit 1233 may operate as a write driver or a sense amplifier according to the operation mode. For example, during a programming operation, the page buffer circuit 1233 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, the page buffer circuit 1233 may detect the data stored in the memory cell by detecting the current or voltage of the selected bit line.

[0052] The control logic circuit 1234 may generally control various operations within the nonvolatile memory device 1230. The control logic circuit 1234 programs data into the cell array 1231 or reads data from the cell array 1231 in response to a control signal CTRL, a command CMD, and / or an address ADDR. Alternatively, various control signals for erasing data stored in the cell array 1231 may be output. For example, the control logic circuit 1234 may output a voltage control signal VTG_C, an address ADDR, etc. In an exemplary embodiment, the control logic circuit 1234 may output a control signal for programming multi-bit data according to the received control signal CTRL, the command CMD, and / or the address ADDR.

[0053] The voltage generator 1235 can generate various types of voltages based on the voltage control signal VTG_C to perform programming, reading and erasing operations. For example, the voltage generator 1235 can generate a programming voltage, a reading voltage and a programming verification voltage as a word line voltage VWL. For example, the programming voltage can be generated using an incremental step pulse programming ISPP method.

[0054] Figure 5 FIG. 2 is a diagram schematically showing a domain redirection method in a multi-domain mapping of the present invention. Figure 5 , shows a method for solving imbalance through domain redirection according to the present invention when input / output requests are concentrated in the first domain Domain_0.

[0055] The logical address corresponding to the input / output request can be mapped in a multi-domain manner. At this time, the logical address corresponding to the input / output request can be concentrated in the first domain Domain_0 in the domains Domain_0 and Domain_1. In the illustrated example, 100% of the input / output requests are concentrated in the first domain Domain_0. The domain allocator 1212 opens the first stream Stream_0 in the first domain Domain_0 for programming the data requested to be written in the input / output request. In addition, the domain allocator 1212 opens the second stream (Stream_1, 1224) in the second domain Domain_1 for programming the data requested to be written in the input / output request. And the domain allocator 1212 will allocate a storage block to each of the dies Die_0 to Die_3, where the write data of the first stream (Stream_0, 1222) will be written into the storage block. Dies Die_0 to Die_3 correspond to the block addresses mapped to the first domain Domain_0.

[0056] However, the domain imbalance will be detected by the input / output monitor 1214. The input / output monitor 1214 transmits the detection of the domain imbalance to the global block manager 1218 (e.g., by generating and sending a detection signal indicating the domain imbalance). Then, the global block manager 1218 opens the third stream Stream_2 in the first domain Domain_0 to resolve the detected domain imbalance. The third stream Stream_2 can be mapped to share the size of the write load (e.g., half) with the first stream Stream_0. And the input / output monitor 1214 redirects the physical address of the third stream Stream_2 to the second domain Domain_1. Then, the physical address of the data written to the third stream Stream_2 is mapped to the die Die_4 to Die_7 of the second domain Domain_1.

[0057] In summary, by generating the third stream mapped to the second domain Domain_1 , the write load can be more evenly distributed to the dies Die_0 to Die_7 of the nonvolatile memory device 1230 .

[0058] Figure 6 1 is a diagram briefly showing the entry size of the mapping table added for domain redirection of the present invention. Figure 6 , when domain imbalance occurs, the additional mapping table 1256 of the present invention can be used for domain redirection.

[0059] Mapping table entry 1252 shows the mapping size in the single-domain structure mapping method. For example, when the logical address is directly mapped to the physical address, the page mapping requires 13 bits, the block mapping requires 11 bits, the bank mapping requires 5 bits, and the channel mapping requires 4 bits. Therefore, the size of the mapping table must be set to 33 bits.

[0060] On the other hand, the mapping table entry 1254 of the multi-domain structure does not include the bit 1253 for selecting a domain. Therefore, since only a mapping table for one domain needs to be configured, the size of the mapping table can be reduced.

[0061] Mapping table entry 1256 represents a mapping table added for domain redirection from one domain (e.g., the first domain) to another domain (e.g., the second domain). The size of the added mapping table may be, for example, 20 bits. This indicates that even with a 20-bit size, the number of entries for selecting a storage block of another domain within a domain can be achieved.

[0062] Mapping table entry 1258 shows the size of the entry specifying the physical page address. The entry of the physical page address may also be provided in 33 bits like mapping table entry 1252.

[0063] Figure 72 is a diagram showing the effect of domain redirection according to an embodiment of the present invention. Figure 7 , even if the logical address LPN corresponds to the first domain Domain_0, when domain redirection is activated, the memory dies Die_4 to Die_7 of the second domain Domain_1 may be mapped to the physical block.

[0064] In this example, the logical address LPN of the input / output request passed to the storage controller 1210 using multi-domain address mapping corresponds to the first domain Domain_0. Then, the domain allocator 1212 allocates the provided logical address LPN to the logical address DLPN of the first domain Domain_0. The virtual block address VBN can select the dies Die_0 to Die_3 included in the first domain Domain_0 according to the logical address DLPN allocated to the first domain Domain_0. However, when domain imbalance is detected and the domain redirection of the present invention is activated, even if the logical address LPN corresponds to the first domain Domain_0, the physical address PBN can actually be mapped to the dies Die_4 to Die_7 of the second domain Domain_1.

[0065] Figure 8 is a flow chart illustrating a domain redirection method activated when a domain imbalance is detected according to an embodiment of the present invention. Figure 8 , the storage device 1200 uses multi-domain address mapping for input / output requests provided from the host 1100. And when domain imbalance is detected, the storage controller 1210 can use domain redirection technology to solve the domain imbalance situation.

[0066] In step S110, the storage controller 1210 receives an input / output request from the host 1100. For example, the storage controller 1210 may receive a write request sent with a logical address (LBA or LPN) from the host 1100. Then, the domain allocator 1212 (see Figure 2 ) allocates domains according to specific bits of the logical address. In other words, in a multi-domain type mapping that manages mapping to two domains Domain_0 and Domain_1, the domain allocator 1212 sends a write request to the first domain Domain_0 and the second domain Domain_0 to allocate to one of the domains according to specific bits of the logical address. For example, the first stream Stream_0 will be opened to process the write request allocated to the first domain Domain_0. And the second stream Stream_1 will be opened to process the write request allocated to the second domain Domain_1.

[0067] In step S120, the input / output monitor 1214 (see Figure 2) detects domain imbalance (or domain skew) of domains assigned by domain allocator 1212. Input / output monitor 1214 may monitor input / output performance of each domain. For example, input / output monitor 1214 may monitor workload or resources of each of domains Domain_0 and Domain_1.

[0068] In step S130, the input / output monitor 1214 determines whether the workload or resources are concentrated in one domain among the two or more domains. If a domain imbalance in which the input / output requests are concentrated in one domain is detected (the "yes" direction), the process goes to step S140. On the other hand, if it is determined that the input / output requests allocated by the domain allocator 1212 are evenly distributed among the domains (the "no" direction), the process returns to step S120 to continue monitoring the domain imbalance.

[0069] In step S140 , the global block manager 1218 opens a new stream to share the load of the current stream according to the monitoring result provided from the input / output monitor 1214 .

[0070] In step S150, the domain redirection unit 1216 creates a remapping table for mapping the newly opened stream. The domain redirection unit 1216 may redirect the mapping of the logical addresses of the input / output requests determined to be domain imbalance from the busy domain to the idle domain through the remapping table. For example, it may be detected that the write requests are concentrated to the first domain Domain_0. Then, the domain redirection unit 1216 may reallocate a portion (e.g., 50%) of the logical addresses specifying the first domain Domain_0 to the storage blocks (or chips) of the second domain Domain_1.

[0071] In step S160, the domain redirection unit 1216 transfers the load corresponding to the write request of the new flow mapped by the remapping table to the die of the second domain Domain_1. In other words, the write operation to the second domain Domain_1 occurs according to the physical address to which the input / output request is redirected.

[0072] As described above, according to the domain allocation method of the present invention, even if the input / output request from the host 1100 is concentrated in one domain, load balancing between domains can be achieved. Therefore, in the storage device 1200 having a multi-domain structure, performance degradation and reduction in chip usage or life due to load concentration on a specific domain can be prevented.

[0073] Fig. 9 It is shown Figure 1 A block diagram of another configuration method of the storage controller. Fig. 9, the storage controller 1210' includes a processing unit 1211, a working memory 1213, a host interface 1215, a buffer manager 1217 and a flash memory interface 1219. However, it is well understood that the components of the storage controller 1210' are not limited to the above components. For example, the storage controller 1210' may also include a read-only memory ROM or an error correction code ECC unit.

[0074] The processing unit 1211 may include a central processing unit or a microprocessor. The processing unit 1211 may run software or firmware for driving the storage controller 1210'. Specifically, the processing unit 1211 may drive or execute software instructions loaded into the working memory 1213. For example, the processing unit 1211 may execute software instructions such as the domain allocator 1212, the input / output monitor 1214, and the domain redirection unit 1216 loaded into the working memory 1213. In addition, the processing unit 1211 may execute core functions of the storage device 1200, such as a flash translation layer FTL.

[0075] The processing unit 1211 may be provided in a multi-core form including multiple CPUs. Each core may create and update a mapping table for each domain allocated according to a multi-domain method. That is, the processing unit 1211 may include multiple cores capable of driving a multi-domain mapping table.

[0076] Software (or firmware) or data for controlling the storage controller 1210' is loaded into the working memory 1213. The software and data loaded into the working memory 1213 are driven or processed by the processing unit 1211. Specifically, according to an embodiment of the present invention, the domain allocator 1212, the input / output monitor 1214, and the domain redirection unit 1216 may be loaded into the working memory 1213. Alternatively, firmware such as a host interface layer (HIL) or a flash translation layer FTL including the functions of the domain allocator 1212, the input / output monitor 1214, and the domain redirection unit 1216 may be loaded into the working memory 1213. The working memory 1213 may be implemented with, for example, SRAM or other non-transitory storage media.

[0077] The domain allocator 1212 driven by the processing unit 1211 allocates I / O requests in a multi-domain manner according to specific bits of the logical address. However, in the multi-domain address mapping, domain imbalance may occur according to the logical address (LBA or LPN). The input / output monitor 1214 driven by the processing unit 1211 detects the domain imbalance. The input / output monitor 1214 may monitor the input / output performance of each domain. For example, the input / output monitor 1214 may monitor the workload or resources of each domain. If it is detected that the workload or resources are concentrated in one domain (e.g., the first domain), the input / output monitor 1214 may activate the domain redirection unit 1216 according to the monitoring result. The domain redirection unit 1216 driven by the processing unit 1211 redirects the logical address of the input / output request from the busy domain (e.g., the first domain) to the idle domain (e.g., the second domain) according to the monitoring result of the input / output monitor 1214. For this operation, the domain redirection unit 1216 or the global block manager 1218 (see Figure 5 ) opens a new flow and stores the physical address of the new flow in a memory block (or die) of the second domain Domain_1. For address mapping of the new flow, the domain redirection unit 1216 may create an additional mapping table or remapping table. The domain allocator 1212, the input / output monitor 1214, and the domain redirection unit 1216 perform the same operations as described above. Figure 2 Therefore, further description thereof will be omitted.

[0078] The host interface 1215 provides an interface between the host 1100 and the storage controller 1210'. The host and the storage controller 1210' may be connected through one of various standard interfaces. Here, the standard interface may include, but is not limited to, ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (External SATA), SCSI (Small Computer Mini Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnect), PCIe (PCI Express), USB (Universal Serial Bus), IEEE 1394, UFS (Universal Flash Storage), eMMC (Embedded Multimedia Card), NVMe, NVMe-of, NVMe-MI, etc.

[0079] The buffer manager 1217 provides a buffer function for read data or write data moved between the host interface 1215 and the flash memory interface 1219. The buffer manager 1217 controls the buffer memory 1250 implemented with a high-capacity dynamic random access memory DRAM, and can provide a DMA function or a buffer function between the nonvolatile memory device 1230 and the host 1100.

[0080] The flash memory interface 1219 provides an interface between the storage controller 1210′ and the non-volatile memory device 1230. For example, data processed by the processing unit 1211 is stored in the non-volatile memory device 1230 through the flash memory interface 1219. As another example, data stored in the non-volatile memory device 1230 may be exchanged with the storage controller 1210′ through the flash memory interface 1219.

[0081] The configuration of the storage controller 1210' is described above in an exemplary manner. According to the functions of the storage controller 1210' of the present invention, the domain allocator 1212, the input / output monitor 1214, and the domain redirection unit 1216 can be implemented as software stored in a non-temporary storage medium and executed by a processor. In some embodiments, the domain allocator 1212 can be implemented in the storage controller 1210' in the form of hardware logic and distinguish domains by referencing logical addresses. However, the domain allocator 1212 is not limited to hardware logic and can be configured as software or a combination of software and hardware. In addition, it can be well understood that, like the domain allocator 1212, the input / output monitor 1214 and the domain redirection unit 1216 can be composed of a combination of hardware and software.

[0082] Fig.10 is a flow chart showing a domain redirection operation according to another embodiment of the present invention. Fig.10 When a domain imbalance is detected, the storage controller 1210 may determine a domain redirection ratio according to the degree of the domain imbalance.

[0083] In step S210, the storage controller 1210 receives an input / output request from the host 1100. For example, the storage controller 1210 receives a write request sent with a logical address (LBA or LPN) from the host 1100. The domain allocator 1212 of the storage controller 1210 (see Figure 2 ) Allocate domains according to specific bits of the logical address. For example, when managing a multi-domain mapping with two domains Domain_0 and Domain_1, the domain allocator 1212 allocates a write request to one of the first domain Domain_0 and the second domain Domain_1 according to specific bits of the logical address. For example, the first stream Stream_0 will be opened to process the write request allocated to the first domain Domain_0. And the second stream Stream_1 will be opened to process the write request allocated to the second domain Domain_1.

[0084] In step S220, the input / output monitor 1214 (see Figure 2) detects an imbalance of domains assigned by the domain allocator 1212. The input / output monitor 1214 can monitor the input / output performance of each domain. For example, the input / output monitor 1214 can determine domain imbalance by monitoring the workload or resources of each domain Domain_0 and Domain_1.

[0085] In step S230, the input / output monitor 1214 determines whether the workload or resources are concentrated in one domain among the two or more domains. If a domain imbalance in which the input / output requests are concentrated in one domain is detected (the "yes" direction), the process goes to step S240. On the other hand, if it is determined that the input / output requests allocated by the domain allocator 1212 are evenly distributed among the domains (the "no" direction), the process returns to step S220 to continue monitoring the domain imbalance.

[0086] In step S240 , the global block manager 1218 opens a new stream to share the load of the current stream according to the monitoring result provided from the input / output monitor 1214 .

[0087] In step S250, the domain redirection unit 1216 creates a remapping table for mapping the newly opened stream. At this time, the domain redirection unit 1216 can create a remapping table according to the detected domain tilt ratio. The domain redirection unit 1216 allocates write requests to the domains at a predetermined or optimal allocation ratio for the imbalance rate through the remapping table. For example, the tilt ratio between the first domain Domain_0 and the second domain Domain_1 can be 3:1. This means that 75% of the write requests are allocated to the first stream Stream_0 opened in the first domain Domain_0, and 25% of the write requests are allocated to the second stream Stream_1 opened in the second domain Domain_1. At this time, the domain redirection unit 1216 can split 75% of the write requests of the first stream Stream_0 by 2:1, and redirect 25% of the write requests to the newly created third stream Stream_2. Then, the third stream Stream_2 is redirected to the second domain Domain_1. Finally, through domain redirection, 50% of the write requests can be redistributed to the first domain Domain_0 and the second domain Domain_1.

[0088] In step S260, the domain redirection unit 1216 sends the write request of the new stream Stream_2 mapped by the remapping table to the die in the second domain Domain_1. Then, according to the redirected physical addresses, the write requests are reallocated to the first domain Domain_0 and the second domain Domain_1 by 50% each. Finally, the write request can be restored from the unbalanced state (75%:25%) to the balanced state (50%:50%).

[0089] As described above, according to the domain allocation method of the present invention, the ratio of domain redirection can be adjusted according to the imbalance degree of input / output requests from the host 1100. Therefore, even in various imbalance situations, load balancing between domains can be achieved.

[0090] Fig.11 is a table showing an example of a write allocation method according to an imbalance rate of each domain. Fig.11 , domain redirection unit 1216 (see Figure 2 ) can be based on the input / output monitor 1214 (see Figure 2 ) determines the write allocation ratio of the newly created stream based on the imbalance rate of input / output requests detected by the multi-domain method. In this example, the multi-domain method is managed by two domains.

[0091] If the domain allocator 1212 allocates the write request to each of the first domain Domain_0 and the second domain Domain_1 at 50%, no domain imbalance is detected. That is, the input / output monitor 1214 will determine that the write request is allocated to each domain in a domain-balanced state. Then, it will be determined that domain redirection of the write request is not required.

[0092] If the domain allocator 1212 allocates write requests to the first domain Domain_0 and the second domain Domain_1 at 75% and 25% respectively, the input / output monitor 1214 will determine that the domains are unbalanced. Then, the domain redirection unit 1216 creates a new flow in the first domain Domain_0 to redirect to the second domain Domain_1. And the allocation ratio (e.g., weighted round-robin: WRR) of the write requests between the existing flow and the new flow in the first domain Domain_0 is allocated to 2:1. The new flow is mapped to the die in the second domain Domain_1. Here, the weighted round-robin WRR can be implemented with a scheduling algorithm such as Token Control.

[0093] If the domain allocator 1212 allocates write requests to the first domain Domain_0 and the second domain Domain_1 at 100% and 0%, respectively, the input / output monitor 1214 will determine that the domains are unbalanced. Then, the domain redirection unit 1216 creates a new flow within the first domain Domain_0 to redirect to the second domain Domain_1. And the allocation ratio (weighted round-robin: WRR) of the write request between the existing flow and the new flow within the first domain Domain_0 is allocated to 1:1. The new flow will be mapped to the die in the second domain Domain_1. By redirecting the new flow to the second domain Domain_1, the allocation ratio of the write request between the domains can be adjusted to 1:1.

[0094] Fig.12is a table showing another example of a write allocation method according to an imbalance rate of each domain. Fig.12 , shows a domain redirection method according to a domain imbalance rate in a storage controller 1210 to which a multi-domain method managed by four domains is applied.

[0095] If the domain allocator 1212 allocates the write request to each of the four domains Domain_0, Domain_1, Domain_2, and Domain_3 at 25%, no domain imbalance will be detected. That is, the input / output monitor 1214 will determine that the write request is allocated to each domain in a domain-balanced state. Then, it will be determined that domain redirection of the write request is not required.

[0096] When the domain allocator 1212 allocates write requests to the four domains Domain_0, Domain_1, Domain_2, and Domain_3 at 50%, 50%, 0%, and 0%, respectively, the input / output monitor 1214 determines that the domains are unbalanced. New internal flows must be created in the first domain Domain_0 and the second domain Domain_1, respectively, to redirect to the third domain Domain_2 and the fourth domain Domain_3. The domain redirection unit 1216 creates a new flow New Stream 1 in the first domain Domain_0 to redirect to the third domain Domain_2. In addition, the domain redirection unit 1216 creates another new flow New Stream 2 in the second domain Domain_1 to redirect to the fourth domain Domain_3. The domain redirection unit 1216 allocates the allocation ratio (weighted round-robin: WRR) of the write request between the existing flow in the first domain Domain_0 and the new flow New Stream 1 at 1:1. The new flow New Stream 1 is mapped to the die in the third domain Domain_2. The domain redirection unit 1216 allocates the write request at a 1:1 allocation ratio (e.g., weighted round-robin: WRR) between the existing streams in the second domain Domain_1 and another new stream New Stream 2. Another new stream NewStream 2 is mapped to the die in the fourth domain Domain_3. Here, weighted round-robin (WRR) can be implemented with a scheduling algorithm such as Token Control.

[0097] When the domain allocator 1212 allocates write requests to each of the four domains Domain_0, Domain_1, Domain_2, and Domain_3 at 100%, 0%, 0%, and 0%, respectively, the input / output monitor 1214 determines that the domain is unbalanced. Within the first domain Domain_0, a new internal flow must be created to redirect to the second domain Domain_1, the third domain Domain_2, and the fourth domain Domain_3. The domain redirection unit 1216 will create three new flows NS_1, NS_2, and NS_3 within the first domain Domain_0. The domain redirection unit 1216 sets the allocation ratio (weighted round-robin: WRR) of the write requests between the existing flows within the first domain Domain_0 and the new flows NS_1, NS_2, and NS_3 to 1:1:1:1. The new flows NS_1, NS_2, and NS_3 are mapped to the dies in the second domain Domain_1, the third domain Domain_2, and the fourth domain Domain_3, respectively. According to the domain redirection, write requests may be reallocated to the first domain Domain_0, the second domain Domain_1, the third domain Domain_2, and the fourth domain Domain_3 at 25% each.

[0098] The above description takes the method of performing domain reallocation on write requests according to various domain imbalance ratios as an example. However, the value of the domain imbalance ratio is an illustrative value used to illustrate the advantages of the present invention, and various changes or modifications may be made.

[0099] Fig.13 is a block diagram showing a storage system according to an embodiment of the present invention. Fig.13 , the storage system 2000 includes a host 2100 and a storage device 2200 implemented as a solid state drive. In an example embodiment, the host 2100 and the storage device 2200 may be (or may be similar to) the host 2100 and the storage device 2200 of the reference Figures 1 to 12 Alternatively, the host 2100 and the storage device 2200 may be based on the reference Figures 1 to 12 Operate according to the described operation method.

[0100] The storage device 2200 exchanges a signal SIG with the host 2100 through a signal connector 2201 and receives power PWR through a power connector 2202. The storage device 2200 includes an SSD controller 2210, a plurality of nonvolatile memories 2230, a buffer memory 2250, and an auxiliary power supply device 2270.

[0101] The SSD controller 2210 may control the plurality of nonvolatile memories 2230 in response to a signal SIG received from the host 2100. The plurality of nonvolatile memories 2230 may operate under the control of the SSD controller 2210. The auxiliary power supply device 2270 is connected to the host 2100 through the power connector 2202. The auxiliary power supply device 2270 may receive power PWR from the host 2100 and be charged. When the power supply of the host 2100 is not smooth, the auxiliary power supply device 2270 may provide power to the storage device 2200. The buffer memory 2250 may be used as a buffer memory of the storage device 2200.

[0102] In an example embodiment, the storage device 2200 may include a domain allocator 2220. When the workload of the input / output request from the host 2100 is concentrated in one domain, the domain allocator 2220 may perform a load balancing operation between domains within the storage device. The domain allocator 2220 may be provided in a software form and loaded into a memory of the SSD controller 2210, and / or may be provided in a hardware form as a part of the SSD controller 2210. In addition, the nonvolatile memory 2230 stores data or outputs stored data under the control of the SSD controller 2210.

[0103] The storage system 2000 of the present invention described above can achieve load balancing between domains even when input / output requests from the host 2100 are concentrated in one domain. Therefore, in the storage device 2200 having a multi-domain structure, performance degradation, reduced die utilization, and reduced lifespan due to load concentration on a specific domain can be reduced or prevented.

[0104] Embodiments of the present invention have been described herein with reference to the flowchart and / or block diagram illustration of the method, system and device according to exemplary embodiments of the present invention. It will be understood that each block in the flowchart and / or block diagram illustration and the combination of blocks in the flowchart and / or block diagram illustration can be implemented by computer program instructions and / or hardware operations. For example, each block in the flowchart or block diagram can represent a section or a portion of code, which includes one or more executable instructions for implementing a specified logical function. The functions indicated in the block may not occur in the order shown. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device, so that the instructions executed by the processor of the computer or other programmable data processing device produce a machine for implementing the functions specified in one or more blocks in the flowchart and / or block diagram.

[0105] These computer program instructions may also be stored in a non-transitory computer-usable memory or a computer-readable memory, where the computer-usable memory or the computer-readable memory can direct a computer or other programmable data processing device to work in a specific manner so that the instructions stored in the computer-usable memory or the computer-readable memory produce a product including instructions for implementing the functions specified in one or more blocks in the flowchart blocks and / or the block diagrams.

[0106] The computer program instructions may also be loaded into a computer or other programmable data processing device to cause a series of operable steps to be executed on the computer or other programmable device to generate a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the flowchart and / or block diagram. Figure 1 Steps to specify a function in one or more boxes.

[0107] The above is a specific embodiment of the present invention. In addition to the above embodiments, the present invention may also include design changes or modifications of the embodiments described herein. In addition, the present invention includes techniques that can be modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above embodiments, but should be limited by the following claims of the present invention and the equivalents of the claims.

Claims

1. A storage device configured to perform address mapping in a multi-domain manner, comprising: A non-volatile memory device comprising a plurality of dies, wherein the dies or memory blocks of the dies are associated with a first domain or a second domain; as well as A storage controller configured to map a logical address of a write request to a first physical address mapped to the first domain, and in response to detecting that a workload or resources corresponding to the write request is concentrated in the first domain at a reference ratio or higher, redirect the first physical address mapped to the first domain to a second physical address allocated to the second domain.

2. The storage device according to claim 1, wherein: The memory controller is configured to generate additional flows associated with the first domain and map the additional flows to a second subset of dies corresponding to the second domain.

3. The storage device according to claim 2, wherein: The memory controller is configured to generate an additional mapping table for mapping the additional streams to the second subset of dies.

4. The storage device according to claim 3, further comprising: The buffer memory is configured to store the additional mapping table.

5. The storage device according to claim 1, wherein: The write request includes data requested to be written, and wherein the storage controller includes: a domain allocator configured to allocate a physical address of a die among the plurality of dies to write the write-requested data into the first domain or the second domain by referring to a specific bit of the logical address; an input / output monitor configured to monitor whether a workload or a resource corresponding to the write request is concentrated in the first domain at a ratio greater than the reference ratio; and A domain redirection unit is configured to redirect the first physical address mapped to the first domain to the second physical address allocated to the second domain.

6. The storage device according to claim 5, wherein: The domain redirection unit is configured to generate an additional flow to redirect the first physical address to the second domain.

7. The storage device according to claim 6, wherein: The domain redirection unit is configured to determine a size of the additional stream to be redirected according to a distribution ratio of the write request to the first domain and the second domain.

8. The storage device according to claim 1, wherein: The first domain corresponds to a first subset of dies connected to a first channel, and the second domain corresponds to a second subset of chips connected to a second channel.

9. A method of operating a storage device to perform address mapping according to a multi-domain method, the method comprising: receiving a write request; detecting a load imbalance between a plurality of domains based on the write request, wherein the plurality of domains are associated with respective subsets of memory dies or memory blocks of the memory die; generating a new flow in addition to the existing flows for a first domain among the plurality of domains having a load higher than that of the reference value set; and A target physical address of the new stream is redirected to a storage block included in a second domain among the plurality of domains.

10. The method according to claim 9, wherein: A first mapping table and a second mapping table are created according to specific bits of a logical address included in the write request, the first mapping table corresponding to the first domain, and the second mapping table corresponding to the second domain.

11. The method according to claim 9, wherein: Detecting the load imbalance includes: A workload or resource allocated to each of the plurality of domains is monitored.

12. The method according to claim 9, further comprising: A remapping table is generated for redirecting the target physical address of the existing flow to the target physical address of the new flow.

13. The method according to claim 12, wherein: Detecting the load imbalance includes: A load distribution ratio between the first domain and the second domain is detected, wherein the load distribution ratio indicates distribution of write requests to the first domain compared to the second domain.

14. The method according to claim 13, wherein: The size of the new flow is determined according to the load distribution ratio.

15. The method according to claim 9, wherein: A second channel connected to a second subset of storage die mapped to the new stream is different from a first channel connected to a first subset of storage die mapped to the existing stream.

16. A storage device configured to perform address mapping in a multi-domain manner, the storage device comprising: A non-volatile memory device comprising a plurality of dies, wherein the dies or memory blocks of the dies are associated with a first domain or a second domain; a storage controller configured to map a logical address of a write request to a first physical address mapped to the first domain, and in response to detecting that a workload or resources corresponding to the write request is concentrated in the first domain at a reference ratio or higher, redirect the first physical address mapped to the first domain to a second physical address allocated to the second domain; as well as a buffer memory configured to store a mapping table mapping logical addresses to physical addresses, Wherein, the write request includes data requested to be written, and wherein the storage controller includes: a domain allocator configured to allocate a physical address of a die among the plurality of dies to write the write-requested data into the first domain or the second domain by referring to a specific bit of the logical address; an input / output monitor configured to monitor whether a workload or a resource corresponding to the write request is concentrated in the first domain at a ratio greater than the reference ratio; and A domain redirection unit is configured to redirect the first physical address mapped to the first domain to the second physical address allocated to the second domain.

17. The storage device according to claim 16, wherein: The domain redirection unit is configured to generate an additional flow to redirect the first physical address to the second domain.

18. The storage device according to claim 17, wherein: The domain redirection unit is configured to determine a size of the additional flow to be redirected according to a load distribution ratio of the first domain and the second domain, wherein the load distribution ratio indicates distribution of write requests to the first domain compared to the second domain.

19. The storage device according to claim 18, wherein: The first domain and the second domain are mapped to different first and second die groups of the plurality of dies, respectively.

20. The storage device according to claim 17, wherein: The storage controller is configured to generate an additional mapping table for mapping the additional stream.

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