Binary translation method, translator, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a binary translation method, a translator, electronic equipment and a readable storage medium, and the method comprises the steps: when a direct jump instruction in a first basic block is translated, identifying whether a second basic block to which the direct jump instruction is to jump crosses pages or not; if it is determined that the second basic block crosses pages, a target instruction sequence is inserted in front of an unoptimized instruction sequence translated by the direct jump instruction, the target instruction sequence is used for detecting whether the direct jump instruction meets an optimization condition or not, and jumping is conducted through the link instruction sequence under the condition that the direct jump instruction is detected to meet the optimization condition; the optimization condition comprises that the virtual and real address mapping relation of the second basic block is not changed; the link instruction sequence is used for skipping to an initial address of the translated basic block corresponding to the second basic block in the code cache. According to the embodiment of the invention, the execution of the direct jump instruction is optimized under the condition that the optimization condition is satisfied, so that the program running efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a binary translation method, a translator, an electronic device and a readable storage medium. Background Art

[0002] Binary translation can convert the binary code of one ISA (Instruction Set Architecture) into the binary code of another instruction set architecture. Through binary translation technology, an application of one ISA (source architecture) can run on another ISA (target architecture).

[0003] Binary translation is performed in units of basic blocks (TB). A basic block is a set of instruction sequences executed sequentially in a program, with a single entry point and a single exit point. Once a program enters a basic block, all instructions in it will be executed sequentially until the exit of the basic block is reached. There will be no branching of control flow within the basic block (except for the sequential execution to the last instruction). The entry point is the first instruction of the basic block; the exit point is the last instruction of the basic block. The last instruction can be a jump instruction, a function call instruction, or a program termination instruction.

[0004] When a basic block ends with a jump instruction and the program executes to the jump instruction, the control flow needs to jump from the current basic block to another basic block, which involves a basic block search operation. This process usually requires a relatively high cost and affects the program execution efficiency. Summary of the invention

[0005] In view of the above problems, an embodiment of the present invention is proposed to provide a binary translation method that overcomes the above problems or at least partially solves the above problems. When it is determined that the optimization conditions are met, the execution of direct jump instructions can be optimized to improve the program running efficiency.

[0006] Correspondingly, the embodiment of the present invention also provides a binary translator, an electronic device, and a computer program product to ensure the implementation and application of the above method.

[0007] In a first aspect, an embodiment of the present invention discloses a binary translation method, which is applied to a system-level binary translator. The method includes: When translating to a direct jump instruction in a first basic block, identifying whether a second basic block to which the direct jump instruction is to jump spans pages; If it is determined that the second basic block crosses pages, a target instruction sequence is inserted before the unoptimized instruction sequence after the translation of the direct jump instruction, and the target instruction sequence is used to detect whether the direct jump instruction meets the optimization conditions, and if it is detected that the direct jump instruction meets the optimization conditions, the jump is performed through a link instruction sequence; the optimization conditions include: the virtual-to-real address mapping relationship of the second basic block has not changed; the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the second basic block in the code cache.

[0008] In a second aspect, an embodiment of the present invention discloses a system-level binary translator, the system-level binary translator comprising: A translation identification module, used for identifying whether a second basic block to which the direct jump instruction is to be jumped spans pages when translating to a direct jump instruction in the first basic block; A translation optimization module is used for inserting a target instruction sequence before the unoptimized instruction sequence after the translation of the direct jump instruction if it is determined that the second basic block crosses pages, the target instruction sequence is used to detect whether the direct jump instruction meets the optimization condition, and when it is detected that the direct jump instruction meets the optimization condition, jumping through a link instruction sequence; the optimization condition includes: the virtual-real address mapping relationship of the second basic block has not changed; the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the second basic block in the code cache.

[0009] In the third aspect, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method as described in any of the above.

[0010] In a fourth aspect, an embodiment of the present invention discloses a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the binary translation method as described in any of the above can be implemented.

[0011] In a fifth aspect, an embodiment of the present invention discloses a computer program product, including a computer program, which, when executed by a processor, performs the steps of any of the aforementioned binary translation methods.

[0012] The embodiments of the present invention include the following advantages: In the dynamic binary translation process of the embodiment of the present invention, when translating to the direct jump instruction in the first basic block, it is identified whether the second basic block to which the direct jump instruction is to jump crosses pages, and the optimization operation executed by the direct jump instruction is refined according to whether the second basic block crosses pages and whether the virtual-to-real address mapping relationship of the second basic block changes when the second basic block crosses pages. In the case where the second basic block does not cross pages, or in the case where the second basic block crosses pages but the virtual-to-real address mapping relationship of the second basic block does not change, the execution of the direct jump instruction in the first basic block can be optimized, and the jump is performed by linking the instruction sequence to directly jump to the starting address of the translated basic block corresponding to the second basic block in the code cache, thereby avoiding the basic block search operation performed by the unoptimized instruction sequence, thereby improving the jump efficiency and thus improving the program running efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of a binary translation architecture of the present invention; Figure 2 is a flowchart of a binary translation method embodiment of the present invention; Figure 3 is a schematic flow chart of an exemplary binary translation method of the present invention; Figure 4 is a structural block diagram of an embodiment of a system-level binary translator of the present invention; Figure 5 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0014] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0015] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0016] Binary translation technology can solve the problem of binary-level applications running across instruction set architectures. Specifically, binary translation technology can convert instruction sequences in one instruction set architecture into instruction sequences in another instruction set architecture.

[0017] Reference Figure 1 , shows a schematic diagram of the architecture of dynamic binary translation. Figure 1 As shown in the figure, dynamic binary translation adopts the "translate while running" method to translate the instructions of the client architecture into the instructions of the host architecture at runtime and run them on the host. After the translator reads the binary file of the target program (client program), it translates and executes it according to the granularity of basic blocks (TranslationBlock, TB). A basic block usually ends with a control flow change instruction (such as an indirect jump instruction, a function call instruction, etc.). Before executing a basic block, it first searches in the code cache. If a translated basic block is found, it executes the basic block. If a translated basic block is not found in the code cache, it translates the basic block and puts the translated basic block into the code cache, and then executes the translated basic block. After executing a basic block, it searches for the next basic block in the code cache, and repeats this cycle until the program execution ends.

[0018] Dynamic binary translators can be divided into user-level binary translators and system-level binary translators, and their application scopes are different. The application scope of user-level binary translators is mainly limited to the operation of a single user-mode program. They are suitable for executing target programs on different architectures without running the entire operating system. They are often used in software compatibility solutions that are cross-architecture but not cross-operating systems. System-level binary translators cover the operation of the entire system, including the operating system kernel and user-mode programs. They can simulate a complete computer system on different architectures and are usually used in software compatibility solutions that are both cross-architecture and cross-operating systems. System-level binary translators can also be used in scenarios such as virtualization, embedded development, and operating system migration.

[0019] The present invention provides a binary translation method, which is applied to a system-level binary translator and can be used to optimize the translation and execution of direct jump instructions.

[0020] Some concepts involved in the embodiments of the present invention are explained below.

[0021] The guest virtual address (GVA) is the virtual address space allocated by the guest operating system to its process or application.

[0022] The guest physical address (GPA) is the address obtained by the client operating system after converting the GVA through its memory management unit (MMU). It is the "physical address" considered by the client operating system or runtime environment. The client operating system maps the GVA to the GPA, but these addresses are not real physical addresses, but are further mapped to the address space of the host by the binary translator or virtualization layer.

[0023] The host virtual address (HVA) is the virtual address used by the host operating system for its own processes and the client.

[0024] GVA can be used to uniquely identify a basic block in user-level binary translation. Specifically, the user-level binary translator mainly translates the binary code of a single user process. In the context of a single process, the client virtual address GVA provides an independent and continuous virtual address space for the process. The GVA used by each process is unique, and the code and data within the process are organized and accessed according to the GVA. Therefore, in this relatively independent process environment, a basic block can be uniquely identified using GVA.

[0025] In system-level binary translation, both GVA and GPA need to be used to uniquely identify a basic block. Specifically, system-level binary translation involves the entire operating system and multiple processes it manages. Different processes may have the same GVA, but their actual locations in physical memory are different. The client physical address GPA represents the physical memory address from the perspective of the client operating system, which can reflect the actual location of the basic block in physical memory. Therefore, GVA alone cannot uniquely identify a basic block, and GPA needs to be combined to distinguish different basic blocks corresponding to the same GVA in different processes. Therefore, in system-level binary translation, both GVA and GPA need to be relied upon to uniquely identify a basic block.

[0026] Since the client program runs in the host environment, the physical memory of the client program is actually simulated by the virtual memory of the host. Therefore, it is necessary to establish a mapping relationship between GPA and HVA. This mapping relationship is maintained by the binary translation system to ensure that the physical memory accessed by the client can correctly correspond to the virtual memory space of the host. The relationship between GVA and HVA is indirect, and GPA is needed as an intermediate bridge. First, GVA is converted to GPA, and then GPA is mapped to HVA. Although GPA and HVA belong to different address spaces of the client and host respectively, they actually point to the same physical memory resource. For example, when the client program accesses the memory corresponding to a GPA, the binary translation system will map it to an HVA, and these two addresses correspond to the same actual memory data.

[0027] Since there is a one-to-one mapping relationship between the client physical address GPA and the host virtual address HVA in the system-level binary translation, the same purpose can be achieved by using GPA or HVA in the present invention. For the convenience of description, the client physical address GPA and the host virtual address HVA are uniformly described as actual addresses in the embodiments of the present invention. That is, in the embodiments of the present invention, the actual address corresponding to the client virtual address GVA can be the client physical address GPA or the host virtual address HVA. In the embodiments of the present invention, the actual address is mainly described as the client physical address GPA. It can be understood that the client physical address GPA in the description can be replaced by the host virtual address HVA, which can also achieve the purpose of the present invention.

[0028] Reference Figure 2 , shows a flowchart of a binary translation method embodiment of the present invention, the method is applied to a system-level binary translator, and the method may include the following steps: Step 101: when translating a direct jump instruction in a first basic block, identifying whether a second basic block to which the direct jump instruction is to be jumped spans pages; Step 102: If it is determined that the second basic block crosses pages, a target instruction sequence is inserted before the non-optimized instruction sequence after the translation of the direct jump instruction, and the target instruction sequence is used to detect whether the direct jump instruction meets the optimization condition, and when it is detected that the direct jump instruction meets the optimization condition, the jump is performed through a link instruction sequence; the optimization condition includes: the virtual-to-real address mapping relationship of the second basic block has not changed; the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the second basic block in the code cache.

[0029] In system-level binary translation, both the guest virtual address GVA and the actual address (guest physical address GPA or host virtual address HVA) are needed to uniquely identify a basic block.

[0030] In the memory management of the operating system, in order to manage the memory efficiently, the memory is divided into pages of fixed size. The page is the basic unit of memory management.

[0031] For ease of description, the system-level binary translator is also referred to as a translator in the embodiments of the present invention. Before executing the first basic block in a page, the translator checks whether the virtual-to-real address mapping relationship of the page is correct. The virtual-to-real address mapping relationship refers to the mapping relationship between the client virtual address GVA and the actual address. This is because the operating system may perform various operations on the memory, such as page replacement, memory allocation adjustment, etc., which may cause the virtual-to-real address mapping relationship to change. If the virtual-to-real address mapping relationship is correct (no change), it means that all address accesses in the page are predictable and safe. When executing subsequent basic blocks in the page, there is no need to repeatedly check the virtual-to-real address mapping relationship of the page.

[0032] In the embodiment of the present invention, the first basic block refers to a basic block ending with a direct jump instruction. The second basic block refers to a basic block to which the direct jump instruction in the first basic block jumps.

[0033] The direct jump instruction explicitly specifies the jump target address. During the program compilation or assembly stage, the jump target address of the direct jump instruction has been determined, and the jump target will not change unless the program code is modified. The direct jump instruction carries the jump target address, which points to the first instruction of the basic block to be jumped to. It can be understood that the address of a basic block described in the embodiment of the present invention refers to the address of the first instruction in the basic block. For example, the client virtual address GVA of basic block B refers to the client virtual address GVA of the first instruction in basic block B.

[0034] Since the jump target address of the direct jump instruction is fixed, unlike the jump target address of the indirect jump instruction which can only be determined during execution, the embodiment of the present invention optimizes the translation of the direct jump instruction and inserts a target instruction sequence when translating the direct jump instruction. The target instruction sequence is used to optimize the execution of the direct jump instruction when executing the direct jump instruction, and directly jump through the link instruction sequence, thereby reducing the search operation of the basic block during the program running process and improving the program running efficiency under the premise of ensuring the correct jump.

[0035] Furthermore, the target instruction sequence is also used to not optimize the execution of the direct jump instruction when it is detected that the direct jump instruction does not meet the optimization conditions, jump to the non-optimized instruction sequence, perform basic block search according to the original process, and then jump to ensure the correct jump.

[0036] In one example, the first basic block is recorded as basic block A, the last instruction of basic block A is a direct jump instruction, and the second basic block to which the direct jump instruction jumps is recorded as basic block B.

[0037] In the translation stage, when a direct jump instruction in the first basic block (such as basic block A) is translated, it can be translated into an unoptimized instruction sequence, which is used to jump to the target search code, and the target search code is used to perform the following operations: The translated basic block corresponding to the second basic block is searched in the code cache. If found, the starting address of the translated basic block corresponding to the second basic block in the code cache is obtained, and execution is jumped to the starting address; if not found, the second basic block is translated, and after the translation is completed, the translated basic block corresponding to the second basic block is saved in the code cache.

[0038] The target search code is used to execute the slow search logic, that is, to search the host virtual address HVA of the translated basic block corresponding to the second basic block according to the client virtual address GVA of the second basic block (basic block B). The host virtual address HVA of the translated basic block corresponding to the second basic block refers to the starting address of the translated basic block corresponding to the second basic block in the code cache.

[0039] Specifically, first search for the translated basic block corresponding to the second basic block in the code cache; if found, obtain the starting address of the translated basic block corresponding to the second basic block in the code cache, and jump to the starting address for execution; if not found, exit the execution process, enter the translation context, translate the second basic block, and after the translation is completed, save the translated basic block corresponding to the second basic block to the code cache, and jump to the starting address of the translated basic block corresponding to the second basic block in the code cache for execution.

[0040] During the execution phase, when the direct jump instruction (client instruction) in basic block A is executed, the translated unoptimized instruction sequence (host instruction) will be executed, that is, the above-mentioned target search code will be executed to complete the search for the starting address of the translated basic block corresponding to basic block B in the code cache and jump to basic block B.

[0041] During program execution, a basic block may be executed multiple times. If the above target search code is executed each time a direct jump instruction of basic block A is executed, the program execution efficiency will be affected.

[0042] Basic block linking is performed on the first basic block and the second basic block, so that the execution of the direct jump instruction can be optimized. Specifically, for the first basic block ending with the direct jump instruction, when the first basic block is executed for the first time, the first basic block is in an unlinked state. When the direct jump instruction is executed, the translation context is exited, and the second basic block to be jumped to is translated. After the translation is completed, the first basic block and the second basic block are basic block linked.

[0043] The process of basic block linking the first basic block and the second basic block may be as follows: In the translation stage, when translating to the direct jump instruction in the first basic block, it can be translated into an unoptimized instruction sequence, and a placeholder instruction sequence is inserted before the unoptimized instruction sequence. The placeholder instruction sequence may include at least one empty instruction (such as the NOP instruction of the host architecture). The placeholder instruction sequence is used to reserve a position for the subsequent execution of the basic block link. The NOP instruction (No Operation) is an instruction widely used in computer architecture, and its function is "no operation". When the CPU executes the NOP instruction, it will not have any substantial impact on the registers, memory or program status, but simply consumes one or more clock cycles and then continues to execute the next instruction.

[0044] When the direct jump instruction in the first basic block is executed for the first time, the basic block linking operation has not been performed on the first basic block, and the first basic block is in an unlinked state. At this time, the placeholder instruction sequence is still a NOP instruction, so the unoptimized instruction sequence will be executed in sequence, and then the target search code will be executed. After the target search code is executed, since the starting address of the translated basic block corresponding to the second basic block in the code cache has been known, the placeholder instruction sequence can be replaced with a link instruction sequence, and the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the second basic block in the code cache. Thus, the basic block linking operation of the first basic block and the second basic block is completed. At this time, the first basic block is in a linked state. Among them, the starting address of the translated basic block corresponding to the second basic block in the code cache is the host virtual address HVA of the translated basic block corresponding to the second basic block.

[0045] When the direct jump instruction in the first basic block is executed for the Nth time (N≥2), the first basic block is in a linked state, and the placeholder instruction sequence has been replaced by the link instruction sequence. Therefore, the link instruction sequence will be executed, and then directly jump to the starting address (HVA) of the translated basic block corresponding to the second basic block in the code cache, and the subsequent target search code will not be executed again. This can avoid the process of searching the starting address (HVA) of the translated basic block corresponding to the second basic block in the code cache according to the GVA of the second basic block each time the target search code is executed, and the program running efficiency can be improved.

[0046] However, during program execution, there may be two situations: one is that the second basic block and the first basic block are in the same page, which is called the second basic block does not cross pages; the other is that the second basic block and the first basic block are not in the same page, which is called the second basic block crosses pages.

[0047] Before executing the first basic block in a page, the translator will check whether the virtual-to-real address mapping relationship of the page is correct. In the above example, regardless of whether the first basic block (such as basic block A) is the first basic block in the page where it is located, when executing the direct jump instruction in the first basic block, the virtual-to-real address mapping relationship of the page where the first basic block is located has been checked for correctness, that is, the virtual-to-real address mapping relationship of the page has not changed. However, for the second basic block (such as basic block B) to which the direct jump instruction is to jump, the virtual-to-real address mapping relationship of the page where the second basic block is located has not been checked for changes.

[0048] When the second basic block does not cross pages, that is, jumps within the same page, since the virtual-to-real address mapping relationship of the page has been checked before executing the first basic block, directly jumping from the first basic block to the second basic block can ensure correct execution.

[0049] For the case where the second basic block crosses pages, that is, the first basic block and the second basic block are located in different pages, since the virtual-to-real address mapping relationship of the page where the second basic block is located has not been checked for correctness, directly jumping from the first basic block to the second basic block may cause execution errors.

[0050] In a specific implementation, for the case where the second basic block does not cross pages, the basic block linking can be used to optimize the execution of the direct jump instruction in the first basic block. For the case where the second basic block crosses pages, in order to ensure the correctness of the basic block jump behavior, the basic block linking operation of the first basic block and the second basic block can be abandoned, and the non-optimized instruction sequence is still executed.

[0051] Specifically, when translating to a direct jump instruction in a first basic block, it can be identified whether a second basic block to which the direct jump instruction is to be jumped spans pages; if it is determined that the second basic block does not span pages, the execution of the direct jump instruction is optimized, and the jump is performed through the link instruction sequence. If it is determined that the second basic block spans pages, the execution of the direct jump instruction is not optimized, and the jump is still performed through the non-optimized instruction sequence.

[0052] In the translation stage, the GVA address of the first basic block and the GVA address of the second basic block are known, so the GVA address of the page where the first basic block is located and the GVA address of the page where the second basic block is located are also known. By judging whether the GVA address of the page where the first basic block is located and the GVA address of the page where the second basic block is located are consistent, it can be determined whether the second basic block crosses pages. If the GVA address of the page where the first basic block is located and the GVA address of the page where the second basic block is located are inconsistent, it is determined that the second basic block crosses pages.

[0053] Furthermore, the embodiment of the present invention has found through research that the virtual-to-real address mapping relationship of the page where the second basic block is located is in a stable state without change most of the time, and the optimization operation performed by the basic block link when the second basic block crosses pages is completely abandoned, resulting in the sacrifice of part of the translator's performance. In order to further improve the performance of the translator and further improve the program running efficiency, the embodiment of the present invention further optimizes the jump when the second basic block crosses pages.

[0054] Specifically, when translating to a direct jump instruction in a first basic block, it is identified whether the second basic block to which the direct jump instruction is to jump crosses pages; if it is determined that the second basic block crosses pages, a target instruction sequence is inserted before the unoptimized instruction sequence after the translation of the direct jump instruction, and the target instruction sequence is used to detect whether the direct jump instruction meets the optimization condition, and when it is detected that the direct jump instruction meets the optimization condition, the execution of the direct jump instruction can still be optimized, and the jump is performed by linking the instruction sequence. The optimization condition includes: the virtual-to-real address mapping relationship of the second basic block has not changed, that is, the actual address corresponding to the client virtual address of the second basic block remains consistent before and after the basic block is linked.

[0055] In the embodiment of the present invention, when the second basic block crosses pages, it is further determined whether the virtual-to-real address mapping relationship of the second basic block has changed. If it has not changed, directly jumping from the first basic block to the second basic block can ensure correct execution. In this case, it is considered that the direct jump instruction in the first basic block still meets the optimization conditions, and the jump can be performed by linking the instruction sequence, thereby further improving the translator performance while ensuring the correctness of the cross-page jump.

[0056] Further, inserting the target instruction sequence before the non-optimized instruction sequence after the direct jump instruction is translated may include: A placeholder instruction sequence is inserted before the non-optimized instruction sequence, and the target instruction sequence is inserted before the placeholder instruction sequence.

[0057] The embodiment of the present invention inserts a target instruction sequence before a placeholder instruction sequence. The target instruction sequence is used to detect whether the direct jump instruction meets the optimization condition when executing the direct jump instruction in the first basic block, and in the case where it is detected that the direct jump instruction meets the optimization condition, jump through the link instruction sequence, thereby directly jumping to the starting address of the translated basic block corresponding to the second basic block in the code cache, and no longer executing the non-optimized instruction sequence, which can avoid executing the slow search logic of the target search code. If it is detected that the direct jump instruction does not meet the optimization condition, the non-optimized instruction sequence is still executed to ensure the correct jump.

[0058] In an optional embodiment of the present invention, the target instruction sequence may include: A first instruction sequence is used to read the client virtual address of the second basic block recorded when the basic block is linked; and continue to execute sequentially; A second instruction sequence, for jumping to the non-optimized instruction sequence when it is determined that the value pointed to by the client virtual address of the second basic block read is empty; if it is not empty, continuing to execute sequentially; A third instruction sequence is used to read the actual address corresponding to the client virtual address of the second basic block recorded when the basic block is linked; and continue to execute sequentially; A fourth instruction sequence is used to query the actual address corresponding to the client virtual address of the second basic block during the current execution based on the read client virtual address of the second basic block; and continue sequential execution; The fifth instruction sequence is used to jump to the unoptimized instruction sequence when it is determined that the actual address queried during this execution is inconsistent with the actual address read during the basic block link; if they are consistent, it is determined that the optimization conditions are met and sequential execution continues.

[0059] It should be noted that the inserted target instruction sequence is an instruction sequence under the host machine architecture. The embodiment of the present invention does not limit the form of the target instruction sequence, and different host machine architectures may have different forms of expression. For example, any one of the first to fifth instruction sequences inserted above may include a single or multiple instructions under the host machine architecture in different host machine architectures.

[0060] In the translation stage, when translating to a direct jump instruction in a first basic block, an embodiment of the present invention identifies that the second basic block to be jumped to crosses pages, then a target instruction sequence is inserted before an unoptimized instruction sequence after the translation of the direct jump instruction. Specifically, the target instruction sequence is inserted before a placeholder instruction sequence before the unoptimized instruction sequence.

[0061] After the target instruction sequence is inserted, when the direct jump instruction in the first basic block is executed for the first time, the target instruction sequence will be executed first. Specifically, the first instruction sequence is executed first, and the client virtual address of the second basic block recorded when the basic block is linked is read. Then the second instruction sequence is executed, and it is determined whether the value pointed to by the client virtual address of the second basic block recorded when the basic block is linked is empty. Since this is the first execution, the value is empty, and then jump to the unoptimized instruction sequence, and then execute the target search code. The target search code searches for the translated basic block corresponding to the second basic block in the code cache, and therefore translates the second basic block. After the translation is completed, the translated basic block corresponding to the second basic block is saved in the code cache, and jumps to the translated basic block corresponding to the second basic block at the starting address in the code cache for execution, and replaces the placeholder instruction sequence with the link instruction sequence, and records the client virtual address of the second basic block (such as GVA1) and the actual address corresponding to the client virtual address (such as GPA1).

[0062] It should be noted that, since the target instruction sequence inserted in the embodiment of the present invention is before the placeholder instruction sequence, and the placeholder instruction sequence is before the non-optimized instruction sequence, the embodiment of the present invention can perform basic block linking on the first basic block and the second basic block when the direct jump instruction is executed for the first time, and replace the placeholder instruction sequence with the link instruction sequence. When the direct jump instruction in the first basic block is executed again, it can be controlled in the target instruction sequence whether to execute the link instruction sequence or the non-optimized instruction sequence by judging whether the direct jump instruction meets the optimization condition.

[0063] When the direct jump instruction in the first basic block is executed for the Nth time (N≥2), the target instruction sequence is still executed first. Taking the second execution as an example, specifically, the first instruction sequence is executed first, and the client virtual address (such as GVA1) of the second basic block recorded when the basic block is linked is read. Then the second instruction sequence is executed. Since the value pointed to by GVA1 recorded when the basic block is linked is not empty, the sequential execution continues. Next, the third instruction sequence is executed, and the actual address (such as GPA1) corresponding to the client virtual address (GVA1) of the second basic block recorded when the basic block is linked is read. Next, the fourth instruction sequence is executed, and based on the read client virtual address (GVA1) of the second basic block, the actual address corresponding to the client virtual address (GVA1) of the second basic block during this execution is queried (such as GPA2 obtained by querying). Finally, the fifth instruction sequence is executed. If it is determined that the actual address (GPA2) queried during this execution is inconsistent with the actual address (GPA1) when the basic block is linked, jump to the unoptimized instruction sequence. If it is determined that GPA2 is consistent with GPA1 and the optimization condition is satisfied, the sequential execution will continue, and the link instruction sequence after the placeholder instruction sequence is replaced will be executed, and then a direct jump will be performed.

[0064] The fourth instruction sequence queries the actual address corresponding to the client virtual address of the second basic block during the current execution based on the client virtual address of the second basic block read, which can be queried through the address translation lookaside buffer; illustratively, the query is performed through the software address translation lookaside buffer; the software address translation lookaside buffer is used to store the mapping relationship between the most recently used GVA and GPA to speed up the address translation process. Therefore, by querying the software address translation lookaside buffer based on the GVA, the GPA corresponding to the GVA can be obtained.

[0065] In the translation stage of the embodiment of the present invention, when translating to a direct jump instruction in the first basic block, if it is identified that the second basic block to which the direct jump instruction is to jump crosses pages, a target instruction sequence is inserted before the unoptimized instruction sequence after the translation of the direct jump instruction. When the direct jump instruction is executed for the first time, the unoptimized instruction sequence is executed, and the first basic block and the second basic block are linked to each other, and the client virtual address and the corresponding actual address of the second basic block are recorded. Therefore, when the direct jump instruction is executed again in the future, the execution process can be controlled by the target instruction sequence, such as controlling whether to adopt the optimization strategy of basic block linking. Specifically, when the direct jump instruction meets the optimization condition (the virtual-real address mapping relationship of the second basic block has not changed), the jump is performed by the link instruction sequence. When the direct jump instruction does not meet the optimization condition (the virtual-real address mapping relationship of the second basic block has changed), the jump is performed by the unoptimized instruction sequence to ensure the correctness of the execution.

[0066] In an optional embodiment of the present invention, the method may further include: In a translation phase of a target basic block, an actual address corresponding to a client virtual address of the target basic block is recorded in a structure of the target basic block; the target basic block includes the first basic block or the second basic block; When basic block linking is performed between the first basic block and the second basic block, the client virtual address and the corresponding actual address of the second basic block are read from the structure of the second basic block and recorded in the structure of the first basic block.

[0067] In a specific implementation, the structure of each basic block contains the client virtual address (GVA) of the basic block to identify the basic block. When translating each basic block, the embodiment of the present invention additionally records the actual address (such as GPA) corresponding to the client virtual address (GVA) of the basic block in the structure of the basic block. Therefore, when the first basic block and the second basic block are linked to each other, the client virtual address (GVA) and the corresponding actual address (such as GPA) of the second basic block recorded therein can be obtained by querying the structure of the second basic block. Furthermore, the client virtual address (GVA) and the corresponding actual address (such as GPA) of the second basic block when the basic blocks are linked can be recorded for use in querying the target instruction sequence during the next execution.

[0068] In the embodiment of the present invention, when basic block linking is performed on the first basic block and the second basic block, the client virtual address (GVA) and the corresponding actual address (GPA) of the second basic block are recorded. Furthermore, in the embodiment of the present invention, the client virtual address (GVA) and the corresponding actual address (GPA) of the second basic block are recorded in the structure of the first basic block. Thus, when a direct jump instruction in the first basic block is executed next time, the client virtual address (GVA) and the corresponding actual address (GPA) of the second basic block recorded during basic block linking can be directly read from the structure of the first basic block, which can improve the reading speed.

[0069] Of course, the embodiment of the present invention does not limit the location of recording the client virtual address (GVA) and the corresponding actual address (GPA) of the second basic block. For example, it can also be recorded in the structure of the second basic block.

[0070] When translating each basic block, the embodiment of the present invention records the client virtual address (GVA) and the corresponding actual address (GPA) of the basic block in the structure of the basic block. Furthermore, when basic block linking is performed on the first basic block and the second basic block, the client virtual address (GVA) and the corresponding actual address (GPA) of the second basic block when the basic block is linked can be additionally recorded in the structure of the first basic block. Thus, when the direct jump instruction in the first basic block is executed next time, the target instruction sequence can directly read the client virtual address (GVA) and the corresponding actual address (GPA) of the second basic block recorded when the basic block is linked from the structure of the first basic block, which can speed up the data reading speed.

[0071] If when basic block linking is performed on the first basic block and the second basic block, the client virtual address (GVA) and the corresponding actual address (GPA) of the second basic block are recorded in the structure of the second basic block. When the direct jump instruction in the first basic block is executed next time, the target instruction sequence needs to first obtain the structure pointer of the second basic block, and then find the structure of the second basic block according to the structure pointer of the second basic block, and then read the client virtual address (GVA) and the corresponding actual address (GPA) of the second basic block recorded when the basic block is linked from the structure of the second basic block. It can be understood that the embodiment of the present invention does not limit the location of recording the client virtual address (GVA) and the corresponding actual address (GPA) of the second basic block when the basic block is linked, as long as it can be obtained when the target instruction sequence is executed.

[0072] In a specific implementation, direct jump instructions may include unconditional jump instructions and conditional jump instructions. An unconditional jump instruction is an instruction that causes the program to immediately jump to a specified target address to continue execution regardless of any conditions. Once an unconditional jump instruction is executed, the program will directly jump to the address specified in the instruction. A conditional jump instruction is an instruction that determines whether to jump to a specified target address based on specific conditions.

[0073] The conditional jump instruction has two jump branches: the branch is taken or not taken. When the condition of the conditional jump instruction is met, the program will jump to the specified target address to continue execution. This situation is called the branch is taken, that is, the jump operation is executed. When the condition of the conditional jump instruction is not met, the program will not jump, but continue to execute the next instruction sequentially. This situation is called the branch is not taken, that is, the jump operation is not executed.

[0074] Therefore, a direct jump instruction may have one jump target or two jump targets. For an unconditional jump instruction, there is only one jump target. For a conditional jump instruction, there are two jump targets.

[0075] In an optional embodiment of the present invention, the unoptimized instruction sequence may include a first jump instruction sequence and / or a second jump instruction sequence; the first jump instruction sequence is used to jump to the jump target of an unconditional jump instruction, or the first jump instruction sequence is used to jump to the jump target of a conditional jump instruction when the condition is met; the second jump instruction sequence is used to jump to the jump target of a conditional jump instruction when the condition is not met.

[0076] For ease of description, in the embodiment of the present invention, the first jump instruction sequence is recorded as I_link0, the second jump instruction sequence is recorded as I_link1, and the unoptimized instruction sequence is recorded as I_exit. It should be noted that the first jump instruction sequence, the second jump instruction sequence and the unoptimized instruction sequence are all translated host machine instruction sequences.

[0077] When linking the first basic block and the second basic block, the placeholder instruction sequence in the first basic block is replaced with the link instruction sequence. When the direct jump instruction in the first basic block is an unconditional jump instruction, the link instruction sequence is a first jump instruction sequence. When the direct jump instruction in the first basic block is a conditional jump instruction, if the condition is met, the link instruction sequence is the first jump instruction sequence; if the condition is not met, the link instruction sequence is the second jump instruction sequence. The first jump instruction sequence and the second jump instruction sequence are used to jump to the corresponding second basic block.

[0078] Furthermore, the unoptimized instruction sequence may only include a single instruction (e.g., denoted as I_exit), which is used to jump to the target search code. Since the target search code needs to perform multiple steps of operations and contains a large number of instructions, the target search code can be used as a common code and stored in a common basic block. I_exit is used to jump to the common basic block to execute the common code.

[0079] It should be noted that, in the embodiment of the present invention, in the execution phase, the first basic block and the second basic block refer to the basic blocks under the host machine instruction architecture after translation. In the translation phase, the first basic block and the second basic block refer to the basic blocks under the client machine instruction architecture before translation. The unoptimized instruction sequence, link instruction sequence, target instruction sequence, placeholder instruction sequence, and target search code are all instruction sequences under the host machine instruction architecture.

[0080] Reference Figure 3 , shows a schematic flow chart of an exemplary binary translation method of the present invention, which may specifically include the following steps: Step A1: when translating a target basic block, recording an actual address (GPA or HVA) corresponding to a client virtual address (GVA) of the target basic block in a structure of the target basic block; the target basic block includes a first basic block or a second basic block.

[0081] Step A2: when translating to the direct jump instruction in the first basic block, determine whether the second basic block to which the first jump instruction sequence I_link0 is to jump crosses pages. If not, execute step A4; if so, insert the following target instruction sequence before the first jump instruction sequence I_link0: A first instruction sequence is used to read the client virtual address of the second basic block recorded when the basic block is linked; and continue to execute sequentially; A second instruction sequence, for jumping to the non-optimized instruction sequence when it is determined that the value pointed to by the client virtual address of the second basic block read is empty; if it is not empty, continuing to execute sequentially; A third instruction sequence is used to read the actual address corresponding to the client virtual address of the second basic block recorded when the basic block is linked; and continue to execute sequentially; A fourth instruction sequence is used to query the actual address corresponding to the client virtual address of the second basic block during the current execution based on the read client virtual address of the second basic block; and continue sequential execution; The fifth instruction sequence is used to jump to the unoptimized instruction sequence when it is determined that the actual address queried during this execution is inconsistent with the actual address read during the basic block link; if they are consistent, it is determined that the optimization conditions are met and sequential execution continues.

[0082] Step A3: When basic block linking is performed on the first basic block and the second basic block, a client virtual address (GVA) and a corresponding actual address (GPA) of the second basic block are recorded.

[0083] Step A4, determine whether there is a second jump instruction sequence I_link1. If so, determine whether the second basic block to which the second jump instruction sequence I_link1 is to jump crosses pages. If so, insert the above target instruction sequence before the second jump instruction sequence I_link1. If not, continue to execute sequentially.

[0084] In summary, in the dynamic binary translation process, when translating to the direct jump instruction in the first basic block, the embodiment of the present invention identifies whether the second basic block to which the direct jump instruction is to jump crosses pages, and refines the optimization operation executed by the direct jump instruction according to whether the second basic block crosses pages and whether the virtual-to-real address mapping relationship of the second basic block changes when the second basic block crosses pages. In the case where the second basic block does not cross pages, or in the case where the second basic block crosses pages but the virtual-to-real address mapping relationship of the second basic block does not change, the execution of the direct jump instruction in the first basic block can be optimized, and the jump is performed by linking the instruction sequence to directly jump to the starting address of the translated basic block corresponding to the second basic block in the code cache, thereby avoiding the basic block search operation performed by the unoptimized instruction sequence, which can improve the jump efficiency and thus improve the program running efficiency.

[0085] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0086] Reference Figure 4 , shows a structural block diagram of an embodiment of a system-level binary translator of the present invention, and the system-level binary translator may include: A translation identification module 401 is used to identify whether a second basic block to which the direct jump instruction is to be jumped spans pages when translating to a direct jump instruction in a first basic block; The translation optimization module 402 is used to insert a target instruction sequence before the unoptimized instruction sequence after the translation of the direct jump instruction if it is determined that the second basic block crosses pages, and the target instruction sequence is used to detect whether the direct jump instruction meets the optimization conditions, and when it is detected that the direct jump instruction meets the optimization conditions, jump through a link instruction sequence; the optimization conditions include: the virtual-to-real address mapping relationship of the second basic block has not changed; the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the second basic block in the code cache.

[0087] Optionally, the target instruction sequence includes: A first instruction sequence is used to read the client virtual address of the second basic block recorded when the basic block is linked; and continue to execute sequentially; A second instruction sequence, for jumping to the non-optimized instruction sequence when it is determined that the value pointed to by the client virtual address of the second basic block read is empty; if it is not empty, continuing to execute sequentially; A third instruction sequence is used to read the actual address corresponding to the client virtual address of the second basic block recorded when the basic block is linked; and continue to execute sequentially; A fourth instruction sequence is used to query the actual address corresponding to the client virtual address of the second basic block during the current execution based on the read client virtual address of the second basic block; and continue sequential execution; The fifth instruction sequence is used to jump to the unoptimized instruction sequence when it is determined that the actual address queried during this execution is inconsistent with the actual address read during the basic block link; if they are consistent, it is determined that the optimization conditions are met and sequential execution continues.

[0088] Optionally, the target instruction sequence is further used to jump to the non-optimized instruction sequence when it is detected that the direct jump instruction does not meet the optimization condition.

[0089] Optionally, the unoptimized instruction sequence is used to jump to a target lookup code, and the target lookup code performs the following operations: The translated basic block corresponding to the second basic block is searched in the code cache. If found, the starting address of the translated basic block corresponding to the second basic block in the code cache is obtained, and execution is jumped to the starting address; if not found, the second basic block is translated, and after the translation is completed, the translated basic block corresponding to the second basic block is saved in the code cache.

[0090] Optionally, the translation optimization module is specifically used to: Inserting a placeholder instruction sequence before the non-optimized instruction sequence, and inserting the target instruction sequence before the placeholder instruction sequence; The system-level binary translator also includes: A basic block linking module is used to replace the placeholder instruction sequence with the linking instruction sequence after obtaining the starting address of the translated basic block corresponding to the second basic block in the code cache during the first execution of the direct jump instruction in the first basic block.

[0091] Optionally, the unoptimized instruction sequence includes a first jump instruction sequence and / or a second jump instruction sequence; the first jump instruction sequence is used to jump to the jump target of an unconditional jump instruction, or the first jump instruction sequence is used to jump to the jump target of a conditional jump instruction when a condition is met; the second jump instruction sequence is used to jump to the jump target of a conditional jump instruction when the condition is not met.

[0092] Optionally, the system-level binary translator further includes: A first recording module is used to record, in a translation phase of a target basic block, an actual address corresponding to a client virtual address of the target basic block in a structure of the target basic block; the target basic block includes the first basic block or the second basic block; The second recording module is used to read the client virtual address and the corresponding actual address of the second basic block from the structure of the second basic block when basic block linking is performed on the first basic block and the second basic block, and record them in the structure of the first basic block.

[0093] Optionally, the system-level binary translator further includes: The non-cross-page jump module is used to jump through the link instruction sequence if it is determined that the second basic block does not cross pages.

[0094] The system-level binary translator provided by the embodiment of the present invention, during the dynamic binary translation process, identifies whether the second basic block to which the direct jump instruction is to be jumped crosses pages when translating to the direct jump instruction in the first basic block, and refines the optimization operation executed by the direct jump instruction according to whether the second basic block crosses pages and whether the virtual-to-real address mapping relationship of the second basic block changes when the second basic block crosses pages. In the case where the second basic block does not cross pages, or in the case where the second basic block crosses pages but the virtual-to-real address mapping relationship of the second basic block does not change, the execution of the direct jump instruction in the first basic block can be optimized, and the jump is performed by linking the instruction sequence to directly jump to the starting address of the translated basic block corresponding to the second basic block in the code cache, thereby avoiding the basic block search operation performed by the unoptimized instruction sequence, thereby improving the jump efficiency and thus improving the program running efficiency.

[0095] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0096] Reference Figure 5 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 5 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method of the above-mentioned embodiment.

[0097] An embodiment of the present invention provides a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a program or a processor of a terminal, the terminal is enabled to perform the steps of the binary translation method of the aforementioned embodiment.

[0098] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0099] Those skilled in the art will appreciate that the embodiments of the embodiments of the present invention may be provided as methods, binary translators, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0100] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0101] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0102] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1The steps for the functions specified in one or more boxes.

[0103] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0104] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A binary translation method, characterized in that: Applied to a system-level binary translator, the method comprises: When translating to a direct jump instruction in a first basic block, identifying whether a second basic block to which the direct jump instruction is to jump spans pages; If it is determined that the second basic block crosses pages, a target instruction sequence is inserted before the unoptimized instruction sequence after the translation of the direct jump instruction, and the target instruction sequence is used to detect whether the direct jump instruction meets the optimization conditions, and if it is detected that the direct jump instruction meets the optimization conditions, the jump is performed through a link instruction sequence; the optimization conditions include: the virtual-to-real address mapping relationship of the second basic block has not changed; the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the second basic block in the code cache.

2. The method according to claim 1, characterized in that The target instruction sequence includes: A first instruction sequence is used to read the client virtual address of the second basic block recorded when the basic block is linked; and continue to execute sequentially; A second instruction sequence, for jumping to the non-optimized instruction sequence when it is determined that the value pointed to by the client virtual address of the second basic block read is empty; if it is not empty, continuing to execute sequentially; A third instruction sequence is used to read the actual address corresponding to the client virtual address of the second basic block recorded when the basic block is linked; and continue to execute sequentially; A fourth instruction sequence is used to query the actual address corresponding to the client virtual address of the second basic block during the current execution based on the read client virtual address of the second basic block; and continue sequential execution; The fifth instruction sequence is used to jump to the unoptimized instruction sequence when it is determined that the actual address queried during this execution is inconsistent with the actual address read during the basic block link; if they are consistent, it is determined that the optimization conditions are met and sequential execution continues.

3. The method according to claim 1, characterized in that The target instruction sequence is also used to jump to the non-optimized instruction sequence when it is detected that the direct jump instruction does not meet the optimization condition.

4. The method according to claim 1, characterized in that: The unoptimized instruction sequence is used to jump to the target lookup code, and the target lookup code performs the following operations: Searching for a translated basic block corresponding to the second basic block in the code cache, and if found, obtaining a starting address of the translated basic block corresponding to the second basic block in the code cache, and jumping to the starting address for execution; If not found, the second basic block is translated, and after the translation is completed, the translated basic block corresponding to the second basic block is saved in the code cache.

5. The method according to claim 1, characterized in that The inserting the target instruction sequence before the unoptimized instruction sequence after the direct jump instruction is translated comprises: Inserting a placeholder instruction sequence before the non-optimized instruction sequence, and inserting the target instruction sequence before the placeholder instruction sequence; The method further comprises: During the first execution of the direct jump instruction in the first basic block, after obtaining the starting address of the translated basic block corresponding to the second basic block in the code cache, the placeholder instruction sequence is replaced with the link instruction sequence.

6. The method according to claim 1, characterized in that The unoptimized instruction sequence includes a first jump instruction sequence and / or a second jump instruction sequence; the first jump instruction sequence is used to jump to a jump target of an unconditional jump instruction, or the first jump instruction sequence is used to jump to a jump target of a conditional jump instruction when a condition is met; The second jump instruction sequence is used to jump to a jump target of the conditional jump instruction when a condition is not satisfied.

7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: In a translation phase of a target basic block, an actual address corresponding to a client virtual address of the target basic block is recorded in a structure of the target basic block; the target basic block includes the first basic block or the second basic block; When basic block linking is performed between the first basic block and the second basic block, the client virtual address and the corresponding actual address of the second basic block are read from the structure of the second basic block and recorded in the structure of the first basic block.

8. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: If it is determined that the second basic block does not cross pages, a jump is performed through the link instruction sequence.

9. A system-level binary translator, characterized in that: The system-level binary translator comprises: A translation identification module, used for identifying whether a second basic block to which the direct jump instruction is to be jumped spans pages when translating to a direct jump instruction in the first basic block; A translation optimization module is used for inserting a target instruction sequence before the unoptimized instruction sequence after the translation of the direct jump instruction if it is determined that the second basic block crosses pages, the target instruction sequence is used to detect whether the direct jump instruction meets the optimization condition, and when it is detected that the direct jump instruction meets the optimization condition, jumping through a link instruction sequence; the optimization condition includes: the virtual-real address mapping relationship of the second basic block has not changed; the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the second basic block in the code cache.

10. The system-level binary translator according to claim 9, characterized in that: The target instruction sequence includes: A first instruction sequence is used to read the client virtual address of the second basic block recorded when the basic block is linked; and continue to execute sequentially; A second instruction sequence, for jumping to the non-optimized instruction sequence when it is determined that the value pointed to by the client virtual address of the second basic block read is empty; if it is not empty, continuing to execute sequentially; A third instruction sequence is used to read the actual address corresponding to the client virtual address of the second basic block recorded when the basic block is linked; and continue to execute sequentially; A fourth instruction sequence is used to query the actual address corresponding to the client virtual address of the second basic block during the current execution based on the read client virtual address of the second basic block; and continue sequential execution; The fifth instruction sequence is used to jump to the unoptimized instruction sequence when it is determined that the actual address queried during this execution is inconsistent with the actual address read during the basic block link; if they are consistent, it is determined that the optimization conditions are met and sequential execution continues.

11. The system-level binary translator according to claim 9, characterized in that: The target instruction sequence is also used to jump to the non-optimized instruction sequence when it is detected that the direct jump instruction does not meet the optimization condition.

12. The system-level binary translator according to claim 9, characterized in that: The unoptimized instruction sequence is used to jump to the target lookup code, and the target lookup code performs the following operations: Searching for a translated basic block corresponding to the second basic block in the code cache, and if found, obtaining a starting address of the translated basic block corresponding to the second basic block in the code cache, and jumping to the starting address for execution; If not found, the second basic block is translated, and after the translation is completed, the translated basic block corresponding to the second basic block is saved in the code cache.

13. The system-level binary translator according to claim 9, characterized in that: The translation optimization module is specifically used for: Inserting a placeholder instruction sequence before the non-optimized instruction sequence, and inserting the target instruction sequence before the placeholder instruction sequence; The system-level binary translator also includes: A basic block linking module is used to replace the placeholder instruction sequence with the linking instruction sequence after obtaining the starting address of the translated basic block corresponding to the second basic block in the code cache during the first execution of the direct jump instruction in the first basic block.

14. The system-level binary translator according to claim 9, characterized in that: The unoptimized instruction sequence includes a first jump instruction sequence and / or a second jump instruction sequence; the first jump instruction sequence is used to jump to a jump target of an unconditional jump instruction, or the first jump instruction sequence is used to jump to a jump target of a conditional jump instruction when a condition is met; The second jump instruction sequence is used to jump to a jump target of the conditional jump instruction when a condition is not satisfied.

15. The system-level binary translator according to any one of claims 9 to 14, characterized in that: The system-level binary translator also includes: A first recording module is used to record, in a translation phase of a target basic block, an actual address corresponding to a client virtual address of the target basic block in a structure of the target basic block; the target basic block includes the first basic block or the second basic block; The second recording module is used to read the client virtual address and the corresponding actual address of the second basic block from the structure of the second basic block when basic block linking is performed on the first basic block and the second basic block, and record them in the structure of the first basic block.

16. The system-level binary translator according to any one of claims 9 to 14, characterized in that: The system-level binary translator also includes: The non-cross-page jump module is used to jump through the link instruction sequence if it is determined that the second basic block does not cross pages.

17. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method according to any one of claims 1 to 8.

18. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the binary translation method according to any one of claims 1 to 8 are implemented.

19. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the binary translation method according to any one of claims 1 to 8 are implemented.

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