Method based on multi-core communication
By setting the sender, shared memory and receiver in the multi-core MCU system, and using timing tasks and interrupt mechanisms to achieve synchronous data transmission, the bandwidth and hardware resource limitations in traditional inter-core communication methods are solved, and the system performance and stability are improved.
Patent Information
- Application Number
- CN202411847921.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-16
- Publication Date
- 2025-05-06
AI Technical Summary
Traditional multi-core MCU inter-core communication methods have bandwidth limitations and hardware resource limitations, making it difficult to achieve efficient and reliable inter-core communication, especially when multiple cores transmit large amounts of data at the same time.
Using a multi-core communication method, by setting the sender, shared memory and receiver, the sender writes the data into its data cache area and periodically updates it to the shared memory through a timing task. The receiver obtains data through an interrupt mechanism to realize the synchronous transmission of data.
This method improves the performance and stability of multi-core MCU systems, avoids the load rate bottleneck of transmission channels, reduces the overhead caused by frequent system interruptions and calls, and achieves efficient and reliable inter-core communication.
Smart Images
Figure CN119938351A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of electronic information technology, and in particular relates to a method based on multi-core communication. Background Art
[0002] In the current field of electronic information technology, multi-core MCU has become the preferred solution for embedded system design with its powerful computing power and parallel processing capabilities. With the continuous advancement of technology and the increasing complexity of application requirements, multi-core MCUs are increasingly widely used in various fields, including automotive electronics, industrial control, smart home, etc. However, the efficient operation of multi-core systems cannot be separated from the support of inter-core communication. The efficiency and reliability of inter-core communication are directly related to the performance and stability of the entire system. Traditional multi-core MCU inter-core communication methods mainly rely on inter-core communication channels provided by hardware, such as shared buses, cross switches, or dedicated inter-core communication interfaces. Although these methods meet the basic needs of inter-core communication to a certain extent, they expose a series of problems in practical applications. For example, traditional inter-core communication channels often have bandwidth limitations. When multiple cores need to transmit a large amount of data at the same time, the communication channel easily becomes a bottleneck, resulting in low data transmission efficiency. In addition, due to the limitation of hardware resources, traditional inter-core communication methods often find it difficult to implement complex communication protocols and flexible communication mechanisms, thereby limiting the performance of multi-core systems.
[0003] In order to solve the above problems, the industry has begun to explore new methods for inter-core communication in multi-core MCUs. Some methods attempt to improve data transmission efficiency by optimizing communication protocols and communication mechanisms, but they often require a lot of modifications and customizations at the hardware level, which not only increases the complexity and cost of the system, but also limits the versatility and scalability of the methods. Other methods attempt to achieve efficient inter-core communication through software-level optimization, such as using message passing libraries or middleware, but these methods often rely on specific operating systems or platforms and are difficult to promote and apply in different multi-core MCU systems.
[0004] Therefore, it is particularly important to develop an inter-core communication method for multi-core MCUs that is both efficient, reliable, general, and scalable. Summary of the invention
[0005] In view of this, the object of the present invention is to provide a method based on multi-core communication. The present invention aims to solve the problems existing in the traditional inter-core communication method and improve the performance and stability of the multi-core MCU system.
[0006] The present invention provides a method based on multi-core communication, comprising the following steps:
[0007] S1. Set up sender, shared memory and receiver;
[0008] The sender and the receiver each maintain their own data cache area, and the data cache area is used to store data to be sent or received;
[0009] Shared memory is used as a data transfer station to store the updated data of the sender and allow the receiver to access it;
[0010] S2. The sender writes the data into its data cache area and periodically scans the data cache area through a two-millisecond timer task. After obtaining channel control, the sender writes the updated data into the shared memory.
[0011] S3. After the sender updates the data to the shared memory, it calls on the receiver to take the data through an interrupt. After the receiver takes the data, the channel is released so that the sender can continue to use it next time.
[0012] Furthermore, the data cache area includes a plurality of data cache regions, each of which matches a different data structure type.
[0013] Furthermore, the data structure types include data queue A, data queue B and signal table.
[0014] Furthermore, when the sender has large-capacity data to transmit, the data is not sent directly through the inter-core transmission channel, but is first written into the sender's data cache area and then updated to the shared memory by a two-millisecond timer task.
[0015] Furthermore, the receiver can also send data as a sender to achieve two-way communication. At this time, the receiver's data cache area and two-millisecond timing task start working, write the data into the shared memory, and notify the original sender through an interrupt to take away the data.
[0016] Furthermore, during the two-way communication process, the data buffer areas and two-millisecond timing tasks of the sender and the receiver work independently without affecting each other, thereby achieving full-duplex transmission.
[0017] Furthermore, during the data transmission process between the sender and the receiver, the data in the shared memory is not fully copied, but it is first determined whether the data is updated. When there is no data update, the shared memory is in an idle state.
[0018] Furthermore, during the data transmission process between the sender and the receiver, the traditional inter-core data transmission channel is no longer used to transmit specific data, but is used as an interlocking mechanism. When the data is ready, the sender notifies the receiver through the traditional inter-core data transmission channel.
[0019] Furthermore, during the data transmission process between the sender and the receiver, the size of the data cache area and the period of the two-millisecond timing task can be flexibly adjusted according to different application scenarios and real-time requirements to adapt to different business scenarios and functional requirements.
[0020] Beneficial effects:
[0021] The present invention discloses a method based on multi-core communication, which consists of three parts: a sender, a shared memory and a receiver, and each part maintains its own data cache area. The data cache area is flexibly designed and can support a variety of data structures including data queues, signal tables, etc., which provides great convenience for future expansion. During the data transmission process, the sender is responsible for writing data into its data cache area, and periodically scanning and updating it to the shared memory through a two-millisecond timing task. The shared memory serves as a data transfer station to ensure the synchronization of data between two processor cores. The receiver is awakened by an interrupt mechanism. When an interrupt occurs, the data is read from the shared memory and updated to its data cache area, thereby completing a typical data transmission process. The model has several significant features. First, when there is a large-capacity data transmission, the data is not sent directly through the inter-core transmission channel, but is first written into the sender's data cache area, and then periodically updated to the shared memory by the timing task, thereby avoiding the load rate bottleneck of the transmission channel. Secondly, the sender does not immediately notify the receiver each time it sends data, but instead uses a two-millisecond timing task to process it regularly, which avoids frequent interrupt wake-ups of the receiver and saves the overhead caused by the frequent system interrupt call process. In addition, there is no conflict between the sender's data storage and the two-millisecond timing acquisition task, because the data cache area adopts a queue structure, so that the data sender does not need to worry about the specific process and timing of data synchronization. In summary, this method achieves efficient and reliable communication between multi-core MCU cores by optimizing the data transmission mechanism and the design of the data cache area, providing strong support for the design of multi-core MCU systems in the fields of Internet of Things, automotive electronics, and industrial automation.
[0022] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 It is the data flow diagram of inter-core communication;
[0024] Figure 2 It is a flow chart of data sending / receiving;
[0025] Figure 3 To initialize the flow chart;
[0026] Figure 4 Flowchart for periodically transferring data to shared memory for the sender;
[0027] Figure 5 Flowchart for receiving interrupt to get data;
[0028] Figure 6 It is a schematic diagram of data flow (data queue);
[0029] Figure 7 A schematic diagram of the data flow (signal table). DETAILED DESCRIPTION
[0030] In order to make the technical solutions, advantages and purposes of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the protection scope of this application.
[0031] like Figure 1 and Figure 2 As shown, the present invention provides a method based on multi-core communication, comprising the following steps:
[0032] S1. Set up sender, shared memory and receiver;
[0033] The sender and receiver each maintain their own data cache area, which is used to store data to be sent or received; these data cache areas not only have sufficient capacity, but also can support a variety of data structures, including multiple data queues and signal tables, etc. This design enables the sender and receiver to flexibly process different types of data to meet various communication needs.
[0034] Shared memory serves as a data transfer station to store the updated data of the sender and allows the receiver to access it.
[0035] S2. The sender writes the data into its data cache area and periodically scans the data cache area through a two-millisecond timer task. After obtaining channel control (locking), the updated data is written into the shared memory.
[0036] This timing task mechanism ensures timely data transmission, while avoiding frequent interrupt wake-ups and reducing system power consumption.
[0037] S3. After the sender updates the data to the shared memory, it calls on the receiver to take the data through an interrupt. After the receiver takes the data, it releases the channel (releases the lock) so that the sender can continue to use it next time.
[0038] The interrupt wake-up mechanism enables the receiver to respond promptly when data arrives, improving the real-time performance of data transmission.
[0039] When the sender needs to send data, it only needs to write the data into its data cache area without notifying the receiver immediately. Subsequently, a two-millisecond timer task updates the data to the shared memory and notifies the receiver to take the data away through an interrupt. This asynchronous data transmission mechanism avoids frequent interrupt wake-ups of the receiver and saves the overhead caused by frequent system interrupt calls.
[0040] As a preferred embodiment of the present invention, the data cache area includes a plurality of data cache areas, each of which matches a different data structure type. This design enables the sender to select a suitable cache area for data storage according to the data type, thereby improving the efficiency and accuracy of data transmission. The design of the data cache area supports a variety of data structures and facilitates future expansion. By adjusting the size of the data cache area and the cycle of the two-millisecond timing task, the present invention can adapt to different application scenarios and real-time requirements, thereby improving the flexibility and adaptability of the system.
[0041] As a preferred embodiment of this embodiment, when the sender has large-capacity data transmission, the data is not sent directly through the inter-core transmission channel, but is first written into the sender's data cache area, and then updated to the shared memory by a two-millisecond timer task. This method avoids the load rate bottleneck of the transmission channel and improves the data transmission efficiency. At the same time, by optimizing the management strategy of the data cache area, the present invention also realizes the rapid processing and transmission of large-capacity data.
[0042] As a preferred embodiment of the present invention, the receiver can also send data as the sender at a certain moment to realize two-way communication. At this time, the data cache area and the two-millisecond timing task of the receiver start working, write the data into the shared memory, and notify the original sender to take the data away through an interrupt. In this way, the data cache area and the two-millisecond timing task of the sender and the receiver work independently during the two-way communication process without affecting each other, thereby realizing full-duplex transmission. This design improves the flexibility and reliability of communication and meets the needs of complex application scenarios.
[0043] As a preferred embodiment of the present invention, during the data transmission process between the sender and the receiver, the present invention avoids full copying of the data in the shared memory by judging whether the data is updated. When there is no data update, the shared memory is idle, thereby saving system overhead. At the same time, by optimizing the data processing and storage strategy during the data transmission process, the present invention further improves the efficiency and accuracy of data transmission.
[0044] As a preferred embodiment of this embodiment, during the data transmission process between the sender and the receiver, the traditional inter-core data transmission channel is no longer used to transmit specific data, but is used as an interlocking mechanism. When the data is ready, the sender notifies the receiver through the inter-core transmission channel. This design simplifies the data transmission process, reduces the load rate of the transmission channel, and improves the reliability and real-time performance of data transmission.
[0045] Example 1
[0046] This embodiment describes in detail the specific operation steps of the sender and receiver in multi-core MCU inter-core communication:
[0047] Data writing and queue management:
[0048] 1.1 The sender and receiver complete the initialization process (such as Figure 3 shown).
[0049] 1.2 For different data types, the sender has corresponding tasks responsible for data writing. These tasks classify the data according to the data type and write it into the corresponding queue (or signal table) to be sent.
[0050] 1.3 When there is a need to send data, the sender task only needs to focus on the data writing operation, without worrying about when the data is actually transmitted. When the sender writes data to the queue to be sent, it updates the queue header information to mark the arrival of new data.
[0051] Scheduled scanning and data update:
[0052] 2.1 As Figure 4 As shown, the sender is configured with a two-millisecond timing task, which periodically scans the sender's to-be-sent area and determines whether the data is updated.
[0053] 2.2 As Figure 4 , Figure 6 As shown, if the data in the waiting area is a sending data queue, the scheduled task starts judging from the end of the queue to ensure that the newly arrived data can be processed first. When it is detected that any of the sending queues is not empty, it means that there is new data to be transmitted.
[0054] 2.3 As Figure 4 , Figure 7As shown, if the regional data to be sent is a signal table, the timing task judges each signal in turn and synchronizes it to the shared memory signal table.
[0055] 3. Channel request and data transmission:
[0056] 3.1 As Figure 4 As shown, the sender requests channel control through the traditional inter-core communication channel and locks the channel to ensure the exclusivity and security of data transmission.
[0057] 3.2 After obtaining control of the channel, the sender takes the data from the tail of the queue to be sent and adds the data to the head of the shared memory queue. In this way, the receiver can see the latest data first when accessing the shared memory. If the sender has multiple data queues to be transmitted, they will be processed one by one according to this step.
[0058] 3.3 As Figure 4 , Figure 7 As shown, if the sender has a signal table to transmit, the signal table is synchronized to the shared memory area
[0059] 4. Notification Recipient:
[0060] like Figure 4 As shown, after the data is transferred to the shared memory, the sender sends a notification to the receiver through the inter-core communication channel, requesting an interrupt to wake up the receiver to process the newly arrived data.
[0061] After the sender task completes all the above steps, it is considered to have completed a data transmission task, the sender task is completed, and is ready to enter the next interrupt processing process.
[0062] 5. Receiver interrupt processing:
[0063] 5.1 As Figure 5 As shown, after the receiver is awakened by the interrupt, it enters the interrupt processing service flow. First, the receiver determines in turn whether there is data to be processed in the data queue and signal table in the shared memory.
[0064] 5.2 As Figure 5 , Figure 6 As shown in the figure, when the data queue is detected to be not empty, the receiver takes the data from the tail of the queue and adds it to the head of the receiver's receiving data queue. In this way, the application layer can process the data in the order in which it arrives. If there are multiple data queues or signal tables in the shared memory that need to be processed, the receiver will refer to the process in this step and process them one by one.
[0065] 5.3 As Figure 5 , Figure 7 As shown, if the signal table in the shared memory needs to be processed, the shared memory data is synchronized to the receiver signal table.
[0066] 5.4 As Figure 5 As shown, when all data queues and signal tables are processed, the receiver task is executed and ready to enter the next interrupt processing flow.
[0067] 6. Full-duplex transmission implementation:
[0068] 6.1 The receiver can also send data as the sender at a certain moment to achieve two-way communication. At this time, the receiver's data writing, scanning, transmission and notification process is exactly the same as the sender's.
[0069] 6.2 Through this design, the sender and receiver can perform their respective tasks and processes independently during the two-way communication process without affecting each other, thus achieving full-duplex transmission. This design improves the flexibility and reliability of communication and meets the needs of complex application scenarios.
[0070] Through the above specific implementation methods, the present invention realizes efficient, reliable and flexible multi-core MCU inter-core communication. The method not only improves the efficiency of data transmission, but also reduces system overhead and power consumption, providing strong support for the design and application of embedded systems.
[0071] It is hereby declared that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention is described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions, which should be included in the scope of the claims of the present invention.
Claims
1. A method based on multi-core communication, characterized in that: The following steps are involved: S1. Set up sender, shared memory and receiver; The sender and the receiver each maintain their own data cache area, and the data cache area is used to store data to be sent or received; Shared memory is used as a data transfer station to store the updated data of the sender and allow the receiver to access it; S2. The sender writes the data into its data cache area and periodically scans the data cache area through a two-millisecond timer task. After obtaining channel control, the sender writes the updated data into the shared memory. S3. After the sender updates the data to the shared memory, it calls on the receiver to take the data through an interrupt. After the receiver takes the data, the channel is released so that the sender can continue to use it next time.
2. The method based on multi-core communication according to claim 1, characterized in that: The data cache area includes a plurality of data cache areas, each of which matches a different data structure type.
3. The method based on multi-core communication according to claim 2, characterized in that: The data structure types include data queue A, data queue B and signal table.
4. The method based on multi-core communication according to claim 1, characterized in that: When the sender has large-capacity data to transmit, the data is not sent directly through the inter-core transmission channel, but is first written into the sender's data cache area and then updated to the shared memory by a two-millisecond timer task.
5. The method based on multi-core communication according to claim 1, characterized in that: The receiver can also send data as a sender to achieve two-way communication. At this time, the receiver's data cache area and two-millisecond timing task start working, write the data into the shared memory, and notify the original sender through an interrupt to take the data away.
6. The method based on multi-core communication according to claim 5, characterized in that: During the two-way communication process, the data buffer area and the two-millisecond timing task of the sender and the receiver work independently without affecting each other, thereby achieving full-duplex transmission.
7. The method based on multi-core communication according to claim 6, characterized in that: During the data transmission process between the sender and the receiver, the data in the shared memory is not fully copied, but it is first determined whether the data is updated. When there is no data update, the shared memory is in an idle state.
8. The method based on multi-core communication according to claim 7, characterized in that: During the data transmission process between the sender and the receiver, the traditional inter-core data transmission channel is no longer used to transmit specific data, but is used as an interlocking mechanism. When the data is ready, the sender notifies the receiver through the traditional inter-core data transmission channel.
9. The method based on multi-core communication according to claim 8, characterized in that: During the data transmission process between the sender and the receiver, the size of the data cache area and the period of the two-millisecond timing task can be flexibly adjusted according to different application scenarios and real-time requirements to adapt to different business scenarios and functional requirements.