Ordering Retrode Blocks For Non-Volatile Memory Cells

Abstract

The invention relates to ordering of retrofit blocks of non-volatile memory cells. The memory system may recover the blocks that have been marked as "bad" using a re-authentication process. For example, after operating in an error protection mode for the block, the memory system may monitor the block to determine whether a status flag indicating an access error is set. If the status flag is set, the memory system may store information indicating that the block is unrecoverable, and the block may then be refused. Alternatively, if a state flag is not set, the memory system may store information indicating that the block may be recoverable. If one or more additional access operations on the block are successful, the memory system may store information indicating that the block may be used for a subsequent access operation.

Description

[0001] Related Applications

[0002] This patent application claims priority to U.S. patent application No. 18 / 776,211, entitled “SORTING RETIRED BLOCKS OF NON-VOLATILEMEMORY CELLS,” filed by Redaelli et al. on July 17, 2024, and claims priority to and the benefit of U.S. patent application No. 63 / 595,691, entitled “SORTING RETIRED BLOCKS OF NON-VOLATILE MEMORY CELLS,” filed by Redaelli et al. on November 2, 2023, each of which is assigned to the present assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to ordering retirement blocks of non-volatile memory cells. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, etc., including devices with higher reliability uses, such as automotive applications. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, often represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, either of which can be stored. To access the stored information, the memory device can read (e.g., sense, detect, retrieve, determine) a state from the memory cell. To store information, the memory device can write (e.g., program, set, assign) a state to the memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selection memory, chalcogenide memory technology, "NOR" and "NAND" memory devices, etc. Memory cells can be described according to volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration can maintain a stored logic state for a long period of time even in the absence of external power. Memory cells configured in a volatile configuration may lose the stored state when disconnected from the external power supply. Summary of the invention

[0006] A method is described. The method may include: operating in an error correction mode for one or more memory cell blocks of a memory system; monitoring, for a memory cell block in the one or more memory cell blocks and based on the error correction mode, a state associated with the memory cell block, wherein the state indicates whether an access operation to the memory cell block is successful; and storing information indicating whether the memory cell block is available for one or more subsequent access operations, the information being based on the state associated with the memory cell block.

[0007] A non-transitory computer-readable medium storing code, the code comprising instructions. The instructions may be executable by one or more processors to perform the following operations: operate in an error correction mode for one or more memory cell blocks of a memory system; monitor a state associated with a memory cell block in the one or more memory cell blocks and based on the error correction mode, wherein the state indicates whether an access operation to the memory cell block is successful; and store information indicating whether the memory cell block is available for one or more subsequent access operations, the information being based on the state associated with the memory cell block.

[0008] An apparatus is described. The apparatus may include: a controller associated with a memory device, wherein the controller is configured to cause the apparatus to: operate in an error correction mode for one or more memory cell blocks of a memory system; monitor a state associated with a memory cell block in the one or more memory cell blocks and based on the error correction mode, wherein the state indicates whether an access operation to the memory cell block is successful; and store information indicating whether the memory cell block is available for one or more subsequent access operations, the information being based on the state associated with the memory cell block. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system that supports ordering retirement blocks of non-volatile memory cells according to examples disclosed herein is shown.

[0010] Figure 2 An example of a system that supports ordering retirement blocks of non-volatile memory cells according to examples disclosed herein is shown.

[0011] Figure 3 An example of a process flow supporting ordering of retirement blocks of non-volatile memory cells according to examples disclosed herein is shown.

[0012] Figure 4A and 4B An example of a set of metadata that supports ordering retirement blocks of non-volatile memory cells according to examples disclosed herein is shown.

[0013] Figure 5 A block diagram of a memory system supporting ordering of retirement blocks of non-volatile memory cells according to examples disclosed herein is shown.

[0014] Figure 6 A flow chart illustrating one or more methods of supporting ordering of retirement blocks of non-volatile memory cells according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0015] The memory system may perform an error correction mode on a valid memory cell block within one or more memory arrays of the memory system to recover the damaged data within the valid block. For example, if the memory system detects an error in the data stored in the valid block (e.g., as part of a read operation), the memory system may perform one or more error correction operations to attempt to correct the error. If the error correction operation is unsuccessful, the host system may trigger an error correction mode, which may be associated with enhanced correction and protection of the data by adjusting the ratio of data bits to parity bits and storing the data at various locations within the memory system. In some cases, the memory system may retire a valid block with an invalid bit (e.g., the block may be marked as unavailable or "bad") after performing an error correction mode on the valid block, such as by placing the block in a retired block pool.

[0016] The error protection mode can be triggered by identifying one or more errors within a valid block. Such errors may be caused by external defects associated with the valid block, such as excessive wear or manufacturing defects, or by intrinsic operating conditions, such as errors caused by long-term data retention, read interference caused by expansion stress, cross temperature, or some combination of the two. In some cases, a valid block containing errors caused by intrinsic operating conditions may be recoverable (for example, after a requalification process, it can still be used to reliably store data). Therefore, retiring such a valid block may remove the valid block from use prematurely. In some instances, if the spare block pool of the memory system is empty, the memory system can be restored to a "write protection" state, in which the memory system may not perform write operations. The write protection state may include interventions, such as replacing the memory system or components of the memory system (for example, in an automotive environment or a personal computing environment), or may cause the device using the memory system to become inoperable, as well as other aspects.

[0017] As described herein, a memory system can use a requalification process to recover a valid block that has been marked as "bad". For example, after operating in an error protection mode for a valid block, the memory system can monitor the valid block to determine whether a status flag indicating an access error (e.g., programming state failure, erase state failure) is set. If the status flag is set, the memory system can store information indicating that the valid block is unrecoverable, and the valid block can then be retired (e.g., kept unused in subsequent access operations). Alternatively, if the status flag is not set, the memory system can store information indicating that the valid block may be recoverable. When in idle mode, the memory system can perform a requalification process on the valid block, such as by performing one or more additional access operations. If one or more additional access operations are successful, the memory system can store information indicating that the valid memory block can be used for subsequent access operations (e.g., the valid block can be added to the spare block pool). This method of requalifying a valid block can improve the reliability of the memory system and extend the service life of the memory system, reduce manufacturing costs (e.g., by increasing yield), and allow a more robust manufacturing process (e.g., an improved welding process), as well as other benefits.

[0018] In addition to applicability in the memory systems described herein, the techniques for sorting the retirement blocks of non-volatile memory cells may be implemented generally to support virtual reality or augmented reality applications. As the presence and use of virtual, augmented, extended, and / or other reality devices increase, electronic devices that support unique aspects of these technologies may be needed. For example, virtual reality and augmented reality devices and applications may benefit from faster processing to enhance user immersion, and wearable electronic devices that support virtual reality or augmented reality may be subject to various size, weight, or other constraints. Implementation of the techniques described herein may support virtual, augmented, extended, and / or other reality devices or technologies by improving the reliability and life of the memory system, which may allow for a reduction in device size and thus may produce a smaller wearable device, as well as other benefits.

[0019] In addition to applicability in the memory systems described herein, the techniques for sorting retirement blocks of non-volatile memory cells may be implemented generally to support enhanced connectivity of electronic systems. As the use of systems that rely on interconnected electronic devices increases, the connectivity of these electronic devices becomes an increasingly important factor in the operation of the systems. For example, as critical systems become increasingly dependent on connectivity, as systems use larger numbers of interconnected devices, or if the number and complexity of signals transmitted between devices increases, delays associated with signals transmitted between devices may become increasingly important. Implementation of the techniques described herein may support techniques for enhanced connectivity in electronic systems by improving the reliability of the electronic devices, which may support improved data transmission techniques between devices, as well as other benefits.

[0020] In addition to its applicability in the memory systems described herein, the techniques for sorting retired blocks of non-volatile memory cells can be implemented generally to support cloud computing and storage applications. With the increase in the use of cloud computing to provide processing, storage, and network services for multiple devices, many devices and systems can benefit from improved remote processing and storage capabilities. For example, improving reliability or other capabilities can bring larger and more accessible storage options to users, while increasing memory access time can bring faster processing for computing or database applications. Implementation of the techniques described herein can support cloud computing and storage technologies by increasing the storage capacity of cloud servers, thereby increasing response time and reducing processing time, as well as other benefits.

[0021] In addition to its applicability in the memory systems described herein, the techniques for sorting retired blocks of non-volatile memory cells can generally be implemented to support edge computing applications. Edge computing is a distributed computing paradigm that brings computing and data storage closer to the data source than traditional cloud services. With the increase in the use of edge computing to provide computing, storage, and network services at locations geographically closer to end users, many devices and systems can benefit from the improved processing, performance, and storage of edge devices. For example, improving the memory density, reliability, and processing power of edge devices can reduce reliance on remote computing or devices, which otherwise may increase the latency of operations performed at the device. Implementation of the techniques described herein can support edge computing technology by improving the reliability associated with edge computing devices, which can improve response time and other functions associated with edge computing devices, as well as other benefits.

[0022] Features of the present disclosure are illustrated and described in the context of systems, devices, and circuits. Features of the present disclosure are further illustrated and described in the context of process flows, metadata tables, and flowcharts.

[0023] Figure 1An example of a system 100 that supports ordering of retired blocks of non-volatile memory cells according to examples disclosed herein is shown. The system 100 includes a host system 105 coupled to a memory system 110. The system 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, an industrial device, or a networked commercial device), or any other computing device that includes a memory and a processing device.

[0024] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other devices.

[0025] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a peripheral component interconnect express (PCIe) controller, a serial advanced technology attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to the memory system 110 and read data from the memory system 110. Although Figure 1 One memory system 110 is shown, but the host system 105 may be coupled to any number of memory systems 110 .

[0026] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise communicate control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces may include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DIMM socket interface supporting DDR), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in or otherwise supported between a host system controller 106 of the host system 105 and a memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110, or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0027] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory devices 130 may include one or more memory arrays of any type of memory cells (eg, non-volatile memory cells, volatile memory cells, or any combination thereof). Figure 1 Although two memory devices 130-a and 130-b are shown in the example of FIG, the memory system 110 may include any number of memory devices 130. Furthermore, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0028] The memory system controller 115 may be coupled and communicate with the host system 105 (e.g., via a physical host interface), and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled and communicate with the memory device 130 to perform operations that may generally be referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or updating data, as well as other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to perform such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may convert responses (e.g., data packets or other signals) associated with the memory devices 130 into corresponding signals for the host system 105.

[0029] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refreshes, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0030] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0031] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that may store operating codes (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed to the memory system controller 115 herein. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that may be used by the memory system controller 115 for internal storage or computation, e.g., internal storage or computation related to the functions attributed to the memory system controller 115 herein. Additionally or alternatively, the local memory 120 may be used as a cache for the memory system controller 115. For example, if the data is read from or written to the memory device 130, the data may be stored in the local memory 120, and the data may be available within the local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 (e.g., with reduced latency relative to the memory device 130) according to the cache policy.

[0032] although Figure 1 The example of the memory system 110 in FIG. 1 has been shown as including a memory system controller 115, but in some cases the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135 that may be respectively internal to the memory device 130 to perform the functions attributed herein to the memory system controller 115. In general, one or more functions attributed herein to the memory system controller 115 may in some cases be alternatively performed by the host system 105, the local controller 135, or any combination thereof. In some cases, a memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0033] The memory device 130 may include one or more arrays of non-volatile memory cells. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory device 130 may include one or more arrays of volatile memory cells. For example, the memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0034] In some examples, the memory devices 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115, or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 As shown, memory device 130 - a may include a local controller 135 - a and memory device 130 - b may include a local controller 135 - b .

[0035] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, memory device 130 may be a package including one or more die 160. In some examples, die 160 may be a piece of electronic grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0036] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as a single-level cell (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as a multi-level cell (MLC) if configured to store two bits of information each, a triple-level cell (TLC) if configured to store three bits of information each, a quad-level cell (QLC) if configured to store four bits of information each, or more generally, a multi-level memory cell. A multi-level memory cell may provide greater storage density relative to an SLC memory cell, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0037] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed on different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and a virtual block 180 may refer to a group of blocks 170 within which parallel operations may occur. For example, parallel operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as a virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, etc.). In some cases, concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0038] In some cases, block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share (e.g., be coupled to) a common word line, and memory cells in the same string may share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0039] For some NAND architectures, memory cells may be read and programmed (e.g., written) at a first level of granularity (e.g., at a page granularity level, or portions thereof), but may be erased at a second level of granularity (e.g., at a block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a set of memory cells) that may be independently programmed or read (e.g., programmed or read simultaneously as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a set of memory cells) that may be independently erased (e.g., erased simultaneously as part of a single erasing operation). Furthermore, in some cases, a NAND memory cell may be erased before it may be rewritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0040] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and related circuitry in combination with a local (e.g., on-die or in-package) controller, such as local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0041] The system 100 may include any number of non-transitory computer-readable media that support ordering of retired blocks of non-volatile memory cells. For example, the host system 105 (e.g., host system controller 106), the memory system 110 (e.g., memory system controller 115), or the memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware, logic, code) for performing the functions attributed to the host system 105, the memory system 110, or the memory device 130 herein. For example, such instructions, when executed by the host system 105 (e.g., host system controller 106), the memory system 110 (e.g., memory system controller 115), or the memory device 130 (e.g., local controller 135), may cause the host system 105, the memory system 110, or the memory device 130 to perform the associated functions described herein.

[0042] In some cases, the memory system 110 can use a requalification process to recover a block 170 that has been marked as "bad". For example, after operating in an error protection mode for a block 170, the memory system 110 can monitor the block 170 to determine whether a status flag indicating an access error (e.g., a programming state failure, an erase state failure) is set. If the status flag is set, the memory system 110 can store information indicating that the block 170 is unrecoverable, and the block 170 can then be retired (e.g., kept unused in subsequent access operations). Alternatively, if the status flag is not set, the memory system can store information indicating that the block 170 can be recovered. When in an idle mode, the memory system 110 can perform a requalification process on the block 170, for example, by performing one or more additional access operations. If the one or more additional access operations are successful, the memory system 110 can store information indicating that the block 170 can be used for subsequent access operations. The memory system 110 can thereby reduce the number of retired blocks 170 by performing the requalification process described herein. This method of requalifying block 170 may improve memory system reliability and increase the useful life of the memory system, among other benefits.

[0043] Figure 2 An example of a system 200 that supports ordering retirement blocks of non-volatile memory cells according to examples disclosed herein is shown. The system 200 may be a reference Figure 1 The system 200 may include a memory system 210 configured to store data received from a host system 205 and to send data to the host system 205 if requested by the host system 205 using an access command (e.g., a read command or a write command). The system 200 may implement reference Figure 1 Aspects of system 100 are described. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0044] The memory system 210 may include one or more memory devices 240 to store data transferred between the memory system 210 and the host system 205 (eg, in response to receiving an access command from the host system 205). The memory device 240 may include a reference Figure 1 For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D crosspoint or other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM, among other examples.

[0045] The memory system 210 may include a storage controller 230 for controlling the transfer of data directly into and out of the memory devices 240 (e.g., for storing data, retrieving data, and determining memory locations to store and retrieve data from). The storage controller 230 may communicate with the memory devices 240 directly or via a bus (not shown) (which may include using a protocol specific to each type of memory device 240). In some cases, a single storage controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, the memory system 210 may include multiple storage controllers 230 (e.g., a different storage controller 230 for each type of memory device 240). In some cases, the storage controller 230 may implement reference Figure 1 Aspects of the local controller 135 are described.

[0046] The memory system 210 may include an interface 220 for communicating with the host system 205 and a buffer 225 for temporary storage of data transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 may support the conversion of data between the host system 205 and the memory device 240 (e.g., as shown by data path 250), and may be collectively referred to as data path components.

[0047] Using buffer 225 to temporarily store data during transfers may allow data to be buffered while commands are being processed, which may reduce latency between commands and may support arbitrary data sizes associated with commands. This may also allow command bursts to be handled, and the buffered data may be stored or transmitted, or both (e.g., after the burst has ceased). Buffer 225 may include relatively fast memory (e.g., some type of volatile memory, such as SRAM or DRAM) or a hardware accelerator, or both, to allow fast storage and retrieval of data in and out of buffer 225. Buffer 225 may include a data path switching component for bidirectional data transfer between buffer 225 and other components.

[0048] Temporary storage of data within buffer 225 may refer to storage of data in buffer 225 during execution of an access command. For example, after completion of an access command, the associated data may no longer be maintained in buffer 225 (e.g., may be overwritten with data from additional access commands). In some examples, buffer 225 may be a non-cacheable buffer. For example, host system 205 may not read data directly from buffer 225. In some examples, a read command may be added to a queue without requiring an operation to match an address with an address already in buffer 225 (e.g., without requiring a cache address match or lookup operation).

[0049] The memory system 210 may also include a memory system controller 215 for executing commands received from the host system 205 (which may include controlling data path components for data movement). The memory system controller 215 may be a reference Figure 1 An example of a memory system controller 115 is depicted. Bus 235 may be used to communicate between system components.

[0050] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) may be used to control the processing of access commands and the movement of corresponding data. For example, this may be beneficial if the memory system 210 processes more than one access command from the host system 205 in parallel. As an example of a possible implementation, the command queue 260, buffer queue 265, and storage queue 270 are depicted at the interface 220, the memory system controller 215, and the storage controller 230, respectively. However, if implemented, the queues may be located anywhere within the memory system 210.

[0051] Data transferred between the host system 205 and the memory device 240 may be transferred along a different path than non-data information (e.g., commands, status information) in the memory system 210. For example, system components in the memory system 210 may communicate with each other using the bus 235, while data may be transferred through data path components using the data path 250 instead of the bus 235. The memory system controller 215 may control how and whether data is transferred between the host system 205 and the memory device 240 by communicating with the data path components via the bus 235 (e.g., using a protocol specific to the memory system 210).

[0052] If the host system 205 transmits an access command to the memory system 210, the interface 220 may receive the command (e.g., according to a protocol such as the UFS protocol or the eMMC protocol). Therefore, the interface 220 may be considered as the front end of the memory system 210. After receiving each access command, the interface 220 may transmit the command to the memory system controller 215 (e.g., via the bus 235). In some cases, each command may be added to the command queue 260 by the interface 220 to transmit the command to the memory system controller 215.

[0053] The memory system controller 215 may determine that an access command has been received based on the communication from the interface 220. In some cases, the memory system controller 215 may determine that an access command has been received by retrieving the command from the command queue 260. After the command has been retrieved (e.g., by the memory system controller 215), the command may be removed from the command queue 260. In some cases, the memory system controller 215 may cause the interface 220 (e.g., via the bus 235) to remove the command from the command queue 260.

[0054] After determining that an access command has been received, the memory system controller 215 may execute the access command. For a read command, this may include obtaining data from one or more memory devices 240 and transferring the data to the host system 205. For a write command, this may include receiving data from the host system 205 and moving the data to the one or more memory devices 240. In either case, the memory system controller 215 may use the buffer 225, among other things, for temporary storage of data received from or sent to the host system 205. The buffer 225 may be considered as the middle of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations in the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0055] To process a write command received from the host system 205, the memory system controller 215 may determine whether the buffer 225 has sufficient available space to store the data associated with the command. For example, the memory system controller 215 may determine (e.g., via firmware, via controller firmware) the amount of space available within the buffer 225 to store the data associated with the write command.

[0056] In some cases, the buffer queue 265 may be used to control the flow of commands associated with data stored in the buffer 225, including write commands. The buffer queue 265 may include access commands associated with data currently stored in the buffer 225. In some cases, commands in the command queue 260 may be moved to the buffer queue 265 by the memory system controller 215 and may remain in the buffer queue 265 while the associated data is stored in the buffer 225. In some cases, each command in the buffer queue 265 may be associated with an address at the buffer 225. For example, a pointer may be maintained indicating where the data associated with each command is stored in the buffer 225. Using the buffer queue 265, multiple access commands may be received sequentially from the host system 205 and at least portions of the access commands may be processed in parallel.

[0057] If the buffer 225 has sufficient space to store the write data, the memory system controller 215 may cause the interface 220 to transmit an indication of availability (e.g., a "ready to transfer" indication) to the host system 205, which may be performed according to a protocol (e.g., a UFS protocol, an eMMC protocol). When the interface 220 subsequently receives data associated with a write command from the host system 205, the interface 220 may use the data path 250 to transfer the data to the buffer 225 for temporary storage. In some cases, the interface 220 may obtain the location of the data stored in the buffer 225 (e.g., from the buffer 225, the buffer queue 265). The interface 220 may indicate to the memory system controller 215 (e.g., via the bus 235) whether the data transfer to the buffer 225 has been completed.

[0058] After the write data has been stored in the buffer 225 through the interface 220, the data may be transferred out of the buffer 225 and stored in the memory device 240, which may involve the operation of the storage controller 230. For example, the memory system controller 215 may cause the storage controller 230 to retrieve the data from the buffer 225 using the data path 250 and transfer the data to the memory device 240. The storage controller 230 may be considered the back end of the memory system 210. The storage controller 230 may indicate to the memory system controller 215 (e.g., via the bus 235) that the data transfer to one or more memory devices 240 has been completed.

[0059] In some cases, the storage queue 270 may support the transfer of write data. For example, the memory system controller 215 may push (e.g., via the bus 235) a write command from the buffer queue 265 to the storage queue 270 for processing. The storage queue 270 may include an entry for each access command. In some examples, the storage queue 270 may additionally include: a buffer pointer (e.g., an address) that may indicate where in the buffer 225 the data associated with the command is stored; and a storage pointer (e.g., an address) that may indicate a location associated with the data in the memory device 240. In some cases, the storage controller 230 may obtain (e.g., from the buffer 225, the buffer queue 265, or the storage queue 270) a location within the buffer 225 from which the data is to be obtained. The storage controller 230 may manage the location within the memory device 240 for storing data (e.g., performing wear leveling, performing garbage collection). Entries may be added to the storage queue 270 (e.g., by the memory system controller 215). After the data transfer is complete, the entry may be removed from the storage queue 270 (eg, by the storage controller 230 , by the memory system controller 215 ).

[0060] To process a read command received from the host system 205, the memory system controller 215 may determine whether the buffer 225 has sufficient available space to store data associated with the command. For example, the memory system controller 215 may determine (e.g., via firmware, via controller firmware) the amount of space available within the buffer 225 to store data associated with the read command.

[0061] In some cases, the buffer queue 265 may support buffer storage of data associated with a read command in a similar manner as discussed with respect to a write command. For example, if the buffer 225 has sufficient space to store the read data, the memory system controller 215 may cause the memory controller 230 to retrieve the data associated with the read command from the memory device 240 and store the data in the buffer 225 for temporary storage using the data path 250. The memory controller 230 may indicate to the memory system controller 215 (e.g., via the bus 235) when the data transfer to the buffer 225 has been completed.

[0062] In some cases, the storage queue 270 may be used to assist in the transfer of read data. For example, the memory system controller 215 may push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 may obtain (e.g., from the buffer 225, from the storage queue 270) a location within the one or more memory devices 240 from which to retrieve data. In some cases, the storage controller 230 may obtain (e.g., from the buffer queue 265) a location within the buffer 225 to store data. In some cases, the storage controller 230 may obtain (e.g., from the storage queue 270) a location within the buffer 225 to store data. In some cases, the memory system controller 215 may move the command processed by the storage queue 270 back to the command queue 260.

[0063] After the data has been stored in buffer 225 by memory controller 230, the data may be transferred from buffer 225 and sent to host system 205. For example, memory system controller 215 may cause interface 220 to retrieve the data from buffer 225 using data path 250 and transfer the data (e.g., according to a protocol such as a UFS protocol or an eMMC protocol) to host system 205. For example, interface 220 may process commands from command queue 260 and may indicate to memory system controller 215 (e.g., via bus 235) that the data transfer to host system 205 has been completed.

[0064] The memory system controller 215 may execute the received commands according to an order (e.g., a first-in, first-out order according to the order of the command queue 260). For each command, the memory system controller 215 may cause data corresponding to the command to be moved into and out of the buffer 225, as discussed herein. The command may remain in the buffer queue 265 while the data is moved into and stored within the buffer 225. If processing of the command has been completed (e.g., if data corresponding to an access command has been transferred out of the buffer 225), the command may be removed from the buffer queue 265 (e.g., by the memory system controller 215). If a command is removed from the buffer queue 265, the address that previously stored data associated with the command may be used to store data associated with a new command.

[0065] In some examples, the memory system controller 215 may be configured for operations associated with one or more memory devices 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refreshes, health monitoring, and address conversion between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. For example, the host system 205 may issue a command indicating one or more LBAs, and the memory system controller 215 may identify the one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, the storage controller 230 may be configured to perform one or more of the described operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the storage controller 230, and the storage controller 230 may be omitted.

[0066] The memory system 210 may implement one or more categories or “pools” for each block 170 within the memory device 240. For example, the memory system 210 may maintain a retired block pool 275 containing one or more unreliable blocks 170 (e.g., bad blocks) that are not used by the memory system 210 for access operations, and a spare block pool 280 containing one or more valid blocks 170 that may be used for access operations (e.g., programming operations, subsequent read operations, subsequent erase operations). Additionally or alternatively, the memory system 210 may maintain one or more pools associated with blocks that may have become defective (e.g., one or more growing bad block (GBB) pools), such as a hard pool 290 corresponding to blocks 170 that the memory system 210 may subsequently retire (e.g., placed in the retired block pool 275), and a soft pool 285 corresponding to blocks 170 that are eligible for a requalification process.

[0067] In some cases, the memory system may use metadata associated with the blocks 170 to maintain (e.g., track, store) one or more categories or pools of blocks 170. For example, the memory system 210 may store metadata within each block indicating whether the block is in the retired block pool 275, the spare block pool 280, the soft pool 285, or the hard pool 290. Additionally or alternatively, the memory system 210 may maintain one or more lists or tables (or both) of metadata indicating which blocks 170 are included in each pool. For example, the memory system 210 may maintain a list indicating an index to one or more blocks 170 included in the retired block pool 275, a list indicating an index to one or more blocks 170 included in the spare block pool 280, a list indicating an index to one or more blocks 170 included in the soft pool 285, a list indicating an index to one or more blocks 170 included in the hard pool 290, or a combination thereof. The lists may be stored as a single list or separate lists and may represent an instance of a metadata collection. The memory system 210 may store a set of metadata indicating the type of the block in the available block 170. For example, the memory system 210 may store the set of metadata in a block 170 within the spare block pool 280, or in some other block 170 available for access operations, so that the memory system 210 can access the metadata. Examples of metadata for indicating the type of the block 170 are described in further detail elsewhere herein, including reference to Figure 4A and 4B .

[0068] As described herein, to improve reliability and reduce overhead, the memory system 210 (eg, using the memory system controller 215) may use a requalification process to recover valid blocks that have been marked as "bad", such as reference Figure 1The block 170 described above. For example, after operating in the error protection mode for the valid block 170, the memory system 210 can monitor the valid block 170 to determine whether a status flag indicating an access error (e.g., a program state failure, an erase state failure) is set. If the status flag is set, the memory system 210 can store information indicating that the valid block 170 is unrecoverable (e.g., by sorting the block 170 to the hard pool 290), and the block 170 can be subsequently retired (e.g., sorting the block 170 to the retired block pool 275). Alternatively, if the status flag is not set, the memory system 210 can store information indicating that the valid block 170 may be recoverable (e.g., by sorting the block 170 to the soft pool 285). When in the idle mode, the memory system 210 can perform a requalification process on the block 170, such as by performing one or more additional access operations. If one or more additional access operations are successful, the memory system 210 can store information indicating that the block 170 is available for subsequent access operations (e.g., by ordering the block 170 to the spare block pool 280). This method of requalifying blocks can improve the reliability of the memory system and extend the useful life of the memory system 210, among other benefits.

[0069] Figure 3 300 is shown to support ordering of retirement blocks of non-volatile memory cells according to examples disclosed herein. In some examples, a memory system (which may be as described in reference Figure 1 and 2 300. In some embodiments, the memory system 110 or the memory system 210 (or both) described herein may use a memory system controller (e.g., memory system controller 115, memory system controller 215) to implement aspects of the process flow 300. For example, the memory system controller may utilize a flash translation layer (FTL) that may perform or support aspects of the process flow 300. The FTL may include software, firmware, hardware, or a combination thereof that may manage aspects of one or more memory cell blocks of a memory system. In the following description of the process flow 300, operations may be performed in an order different from that shown. For example, certain operations may also be omitted from the process 300, or other operations may be added to the process 300.

[0070] Process flow 300 may illustrate a method of supporting and executing a requalification operation that determines whether to transfer a block from a soft pool (e.g., soft pool 285) to a spare block pool (e.g., spare block pool 280) or to a retired block pool (e.g., retired block pool 275), or to a retired block pool from a hard pool (e.g., hard pool 290). In some cases, the ordering of blocks into such pools may include storage metadata or other indications that each block is contained in a corresponding pool, such as reference Figure 4A and4B Described in more detail.

[0071] The memory system may operate in an error correction mode for one or more blocks of memory cells of the memory system at 305. For example, if the memory system detects an error in data stored to a block (e.g., as part of a read operation), the memory system may perform one or more error correction operations, such as by using one or more error correction codes (ECCs) that can detect and in some cases correct errors in the one or more blocks to attempt to correct the errors.

[0072] If the error correction operation is unsuccessful, the host system may trigger an error correction mode, which may be associated with enhanced correction and protection of data by adjusting the ratio of data bits to parity bits and storing the data in various locations within the memory system. Additionally or alternatively, the error correction mode may be triggered due to one or more defects in the memory system. The error correction mode may include one or more higher-level error correction operations to retrieve or recover data, such as a redundant array of independent NAND (RAIN) operation or a turbo RAIN operation. Such operations may include recovering data stored in a particular block using error correction information corresponding to or stored across multiple blocks.

[0073] At 310, the memory system may monitor access status of one or more blocks associated with an error correction mode (e.g., blocks that have undergone a RAIN operation). In some cases, monitoring the status of a given block may include performing or monitoring one or more access operations, such as a program operation, an erase operation, or both, for the block. The access operation may be performed as part of or in accordance with the error correction mode. In this case, the status may include or may be an indication of whether the access operation was successful or unsuccessful, such as a program state failure (PSF), an erase state failure (ESF), or both, and if the status is set, the status may indicate that the program operation or the erase operation was unsuccessful, respectively.

[0074] In some instances, an unsuccessful access operation (e.g., PSF, ESF) to a block may indicate one or more physical defects (e.g., external defects) in the block. Therefore, if the memory system detects that the access status includes a failure indication, the memory system may determine that the access operation is unsuccessful. At 315, if the memory system determines that the access operation is unsuccessful, the memory system may store information (e.g., indication, metadata) indicating that the memory unit block is unavailable for subsequent access operations. For example, the memory system may sort (e.g., classify) the block into a hard pool, and may subsequently retire the block (e.g., may sort the block into a retired block pool). That is, if a failure indication is set after an access operation, the memory system may determine that the block is defective and may not be recoverable for subsequent use.

[0075] Additionally or alternatively, a successful access operation to a block may indicate or suggest that the cause of the block's error correction pattern is related to an intrinsic operating mode, such as long-term data retention, read disturbance due to extended stress, cross temperature, or both. In some cases, errors due to such intrinsic operating conditions may indicate that the block is available for subsequent access operations (e.g., after accounting for the operating conditions). Therefore, if the memory system does not detect a failure indication at 310, the memory system may determine that the access operation is successful. At 320, if the memory system determines that the access operation is successful, the memory system may store information (e.g., an indication, metadata) indicating that the block of memory cells is available for subsequent access operations. For example, the memory system may sort (e.g., classify) the blocks into a soft pool, and may subsequently perform a requalification operation on the blocks. The hard pool and the soft pool may represent reference Figure 2 Examples of hard pool 290 and soft pool 285 are described.

[0076] When the memory system is operating in idle mode, the memory system may trigger a requalification process for blocks in the soft pool, which may correspond to an operating period (e.g., idle period, idle mode) in which the memory system may receive relatively few commands from the host system or may otherwise be occupied by executing host commands. At 325, the memory system may determine whether the memory system is operating in idle mode. The memory system may check the idle mode periodically, semi-statically, or based on the number of blocks in the soft pool, or any combination thereof. If the memory system is not operating in idle mode, the memory system may continue to sort blocks into hard pools and soft pools, or may perform other operations. At 330, if the memory system transitions to operating in idle mode, the memory system may initiate a block requalification operation for each block in the soft pool by performing one or more requalification operations on the memory cell blocks.

[0077] At 335, as part of the block requalification operation for the block, the memory system may perform one or more additional access operations on the block. For example, the memory system may perform one or more erase operations on the block, may perform one or more program operations on the block, may perform one or more read operations on the block, or a combination thereof.

[0078] At 340, the memory system may monitor errors associated with the access operation. If the number of errors is greater than a threshold (e.g., at least one or some other threshold), the memory system may determine that the operation was unsuccessful. The memory system may sort the block into a hard pool, and may subsequently retire the block (e.g., sort the block into a retired block pool). Alternatively, if the number of errors is less than a threshold, the memory system may determine that the block can be requalified. The memory system may place the block in a spare block pool, and the memory system may use the block for subsequent access operations. The hard pool and spare pool may represent references. Figure 2 Examples of hard pool 290 and spare block pool 280 are depicted.

[0079] At 345, the memory system may additionally or alternatively determine whether an error rate associated with one or more additional access operations satisfies a threshold. For example, the memory system may determine a bit rate error (BER) associated with the access operation, which may indicate the number or fraction of bits stored in the block that contain incorrect data. In some examples, the threshold may be a fixed threshold (e.g., the same threshold applied to each block). Additionally or alternatively, the threshold may depend on the block for which the error correction operation is performed. For example, the threshold may depend on the age of the block, the number of access operations (e.g., the number of read operations, the number of program operations, the number of erase operations) that have been performed on the block, or both.

[0080] In some examples, the BER may be an example of a raw BER (RBER), which may correspond to the number or fraction of bits containing incorrect data stored in the block before one or more errors are corrected using an error correction operation. Additionally or alternatively, the BER may be an example of an uncorrectable BER (UBER), which may correspond to the number or fraction of bits containing incorrect data stored in the block after one or more errors are corrected using an error correction operation. If the error rate meets a threshold (e.g., exceeds a threshold), the memory system may sort the block to a hard pool at 315, which may signal that the block is to be retired.

[0081] At 350, the memory system may store information indicating that the block is available for one or more subsequent access operations. For example, if the access operation is successful at 340, or if the error rate is less than a threshold at 345, or both, the memory system may determine that the block can be requalified. The memory system may place the block in a spare block pool, and the memory system may use the block for subsequent access operations. Requalifying the blocks that are sorted into the soft pool may improve the reliability of the memory system, extend the useful life of the memory system, reduce manufacturing costs (e.g., by increasing yields), and allow for a more robust manufacturing process (e.g., an improved soldering process), among other benefits.

[0082] Figure 4A and 4B 1 shows an example of metadata set 400-a and metadata set 400-b that respectively support ordering of retired blocks of non-volatile memory cells according to examples disclosed herein. Metadata sets 400-a and 400-b may be stored in one or more blocks of a memory system (e.g., reference Figure 1-3 A conceptual example of metadata associated with each of the blocks 170 of the memory system 110, the memory system 210, or both is described.

[0083] In some instances, metadata sets 400-a and 400-b may be stored across various portions of a memory system, such as in one or more blocks dedicated to storing metadata, stored with user data within a block, or a combination thereof. In some instances, metadata may be stored across blocks that may be used for subsequent access operations (e.g., blocks in a spare pool). In order to sort blocks into particular categories (e.g., retired block pool 275, spare block pool 280, soft pool 285, or hard pool 290), the memory system may store metadata that includes information associated with the corresponding category as well as a block identifier. In some cases, a block identifier may be an instance of a number or bit string that identifies an associated block. For example, a block identifier may be an address (e.g., a physical address, a logical address) corresponding to an associated block, or otherwise include a bit sequence that is unique to the associated block. Metadata may be stored in one or more different formats, such as Figure 4A and 4B shown.

[0084] Figure 4AA first example of a metadata set 400-a is shown, which can include one or more different metadata lists or metadata sets. For example, the metadata set 400-a can be stored as or can include one or more lists associated with different categories, such as a retired (e.g., bad block) list 405 associated with the retired block pool 275, a spare list 415 associated with the spare block pool 280, a soft list 425 associated with the soft pool 285, and a hard list 435 associated with the hard pool 290. In some examples, the list can include one or more block identifiers corresponding to the ordered blocks in the list.

[0085] The retirement list 405 may include block identifiers 410-a through 410-m that may correspond to blocks that have been retired (e.g., unavailable for access operations), the spare list 415 may include block identifiers 420-a through 420-m that may correspond to blocks that may be available for access operations, and the soft list 425 may include block identifiers 420-a through 420-m that may correspond to blocks that may be eligible for requalification operations (see Figure 3 4 ), and hard list 435 may contain block identifiers 430-a through 430-m that may correspond to blocks that are about to be retired (e.g., subsequently sorted into retirement list 405). Although four separate lists are shown in FIG. 4 , it should be understood that the memory system may store any number of lists indicating any type of blocks, including the four types shown in FIG. 4 or any other combination of block types.

[0086] In some cases, in order to sort the blocks into the list, a block identifier of the block can be added to the list. As a non-limiting example, the memory system can sort blocks that have undergone an error correction mode (e.g., a RAIN operation) and have successfully performed subsequent access operations to the soft list 425 (e.g., blocks with no ongoing PSF, ESF, or both) by storing the block identifiers to the soft list 425. In some cases, the memory system can store additional metadata, such as an indication that the subsequent access operation was successful. Subsequently, as part of the requalification process (e.g., reference Figure 3 ), the memory system may perform one or more additional access operations on the block. If the additional access operation is successful, the memory system may sort the block to the standby list 415 by removing the block identifier from the soft list 425 and storing the block identifier in the standby list 415.

[0087] Figure 4BA second example of a metadata set 400-b that may be stored as a metadata table 445 is shown. The metadata table 445 may store a mapping between blocks and categories corresponding to the blocks. For example, the metadata table 445 may store one or more indications associated with different categories, such as a retired block indication 455 associated with the retired block pool 275, a spare block indication 460 associated with the spare block pool 280, a soft indication 465 associated with the soft pool 285, and a hard indication 470 associated with the hard pool 290. The one or more indications may represent instances of metadata or other information indicating or pointing to a corresponding type of block. The metadata table 445 may be indexed by a unique block identifier 450 (e.g., a block address or other unique identifier).

[0088] As an example, metadata table 445 may include one or more entries that map block identifiers 450 to categories, such as mapping block identifier 450-a to a first entry of retired block pool 275 using retired block indication 455, mapping block identifier 450-b to a second entry of spare block pool 280 using spare block indication 460, mapping block identifier 450-c to a third entry of soft pool 285 using soft indication 465, and mapping block identifier 450-d to a fourth entry of hard pool 290 using hard indication 470. In some cases, to sort blocks into categories, the memory system may add an entry containing the block identifier 450 of the block and an indication corresponding to the category to metadata table 445. Additionally or alternatively, the memory system may update an existing entry containing the block identifier 450 to change the existing indication to a current indication corresponding to a current category associated with the block.

[0089] The memory system can thereby sort blocks into various categories based on one or more conditions associated with the blocks by storing metadata or other information indicating the category of each block. The memory system can utilize the classification information to improve block retention and reliability of the memory system.

[0090] Figure 5 A block diagram 500 is shown of a memory system 520 that supports ordering of retired blocks of non-volatile memory cells according to examples disclosed herein. The memory system 520 may be a reference Figure 1 4. The memory system 520 or its various components may be examples of means for performing various aspects of ordering retired blocks of non-volatile memory cells described herein. For example, the memory system 520 may include an error correction mode operation component 525, a status monitoring component 530, a metadata storage component 535, an idle mode operation component 540, a requalification operation component 545, or any combination thereof. Each of these components or their components or subcomponents (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0091] The error correction mode operation component 525 may be configured as or otherwise support means for operating in an error correction mode for one or more memory cell blocks of a memory system. The state monitoring component 530 may be configured as or otherwise support means for monitoring, for a memory cell block in the one or more memory cell blocks and based on the error correction mode, a state associated with the memory cell block, wherein the state indicates whether an access operation to the memory cell block is successful. The metadata storage component 535 may be configured as or otherwise support means for storing information indicating whether the memory cell block is available for one or more subsequent access operations, the information being based on the state associated with the memory cell block.

[0092] In some examples, the information includes an indication that the access operation was unsuccessful and thus the block of memory cells is unavailable based on the status.

[0093] In some examples, the information includes an indication that the access operation was successful based on the status and thus the block of memory cells is available.

[0094] In some examples, the idle mode operation component 540 may be configured or otherwise support means for operating the memory system in an idle mode. In some examples, the requalification operation component 545 may be configured or otherwise support means for performing one or more requalification operations on the memory cell block based on the memory cell block being included in a first group of blocks while operating in the idle mode, wherein the memory cell block is included in the first group of blocks based on the status indicating that the access operation to the memory cell block is successful, and wherein storing the information is further based on the one or more requalification operations.

[0095] In some examples, the information indicates that the block of memory cells is available for the one or more subsequent access operations based on an error rate associated with the one or more re-qualification operations being less than or equal to a threshold error rate.

[0096] In some examples, based on the one or more re-qualification operations being unsuccessful, the information indicates that the block of memory cells is unavailable for the one or more subsequent access operations.

[0097] In some examples, the information indicates that the block of memory cells is unusable for the one or more subsequent access operations based on an error rate associated with the one or more re-qualification operations being greater than a threshold error rate.

[0098] In some examples, the metadata storage component 535 may be configured to or otherwise support means for storing first information indicating that the block of memory cells can recover from an error condition based on the status indicating that the access operation was successful, wherein the first information further indicates that the block is included in the first group of blocks.

[0099] In some examples, the one or more re-qualification operations include one or more erase operations, one or more program operations, one or more read operations, or any combination thereof to refresh the block of memory cells for the one or more subsequent access operations.

[0100] In some instances, to support storing the information, the metadata storage component 535 may be configured to or otherwise support components for the following operations: storing first metadata and second metadata in a metadata set, the first metadata including the information and a first identifier of the memory unit block, the second metadata including a second identifier of one or more second memory unit blocks from the one or more memory unit blocks of the memory system and second information indicating whether the one or more second memory unit blocks are available for subsequent access operations.

[0101] In some examples, the first identifier includes an address associated with the block of memory cells.

[0102] In some examples, the error correction mode is based on failed read operations on the one or more blocks of memory cells.

[0103] In some examples, the error correction mode includes RAIN operation.

[0104] In some examples, the access operation includes a program operation or an erase operation. In some examples, the status includes an erase state failure indication or a program state failure indication.

[0105] In some examples, the described functionality of the memory system 520 or its various components may be supported by or may involve at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the described functionality of the memory system 520 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) that may be executed by such at least one processor.

[0106] Figure 6A flowchart illustrating a method 600 for supporting the ordering of retirement blocks of non-volatile memory cells according to examples disclosed herein is shown. The operations of the method 600 may be implemented by the memory system or components thereof described herein. For example, the operations of the method 600 may be implemented by reference to Figures 1 to 5 The memory system described herein can be used to perform. In some examples, the memory system can execute instruction sets to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory system can use dedicated hardware to perform various aspects of the described functions.

[0107] At 605, the method may include operating in an error correction mode for one or more memory cell blocks of a memory system. In some examples, aspects of the operation of 605 may be described with reference to Figure 5 The error correction mode operation component 525 described herein performs. For example, a memory system may include a controller (e.g., memory system controller 115, memory system controller 215) that implements aspects of the error correction mode operation component 525 to perform (e.g., at step 305 of process flow 300) one or more error correction operations, such as a RAIN operation, on one or more blocks.

[0108] At 610, the method may include monitoring a status associated with a memory cell block in the one or more memory cell blocks and based on an error correction mode, wherein the status indicates whether an access operation to the memory cell block is successful. In some examples, aspects of the operation of 610 may be described with reference to Figure 5 The described status monitoring component 530 performs. For example, the memory system may include a controller (eg, memory system controller 115, memory system controller 215) that implements aspects of the status monitoring component 530 to determine (eg, at step 310 of process flow 300) whether an access operation was successful.

[0109] At 615, the method may include storing information indicating whether the memory cell block is available for one or more subsequent access operations, the information being based on the state associated with the memory cell block. In some examples, aspects of the operation of 615 may be described by reference to Figure 5 The metadata storage component 535 described performs. For example, the memory system may include a controller (e.g., memory system controller 115, memory system controller 215) that implements aspects of the metadata storage component to store (e.g., at step 350 of process flow 300, at step 315 of process flow 300) metadata indicating information.

[0110] In some examples, an apparatus described herein may perform one or more methods, such as method 600. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0111] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for performing the following operations: operating in an error correction mode for one or more memory cell blocks of a memory system; monitoring a state associated with a memory cell block in the one or more memory cell blocks and based on the error correction mode, wherein the state indicates whether an access operation to the memory cell block is successful; and storing information indicating whether the memory cell block is available for one or more subsequent access operations, the information being based on the state associated with the memory cell block.

[0112] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1, wherein the information includes an indication that the access operation was unsuccessful and thus the block of memory cells is unavailable based on the status.

[0113] Aspect 3: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 2, wherein the information includes an indication that the access operation is successful based on the status and thus the memory cell block is available.

[0114] Aspect 4: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 3, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for performing the following operations: operating the memory system in an idle mode; and when operating in the idle mode, performing one or more re-qualification operations on the memory cell block based on the memory cell block being included in a first group of blocks, wherein the memory cell block is included in the first group of blocks based on the status indicating that the access operation to the memory cell block is successful, and wherein storing the information is further based on the one or more re-qualification operations.

[0115] Aspect 5: The method, apparatus, or non-transitory computer-readable medium of aspect 4, wherein the information indicates that the block of memory cells is available for the one or more subsequent access operations based on an error rate associated with the one or more requalification operations being less than or equal to a threshold error rate.

[0116] Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 4 to 5, wherein based on the one or more re-qualification operations being unsuccessful, the information indicates that the memory cell block is unavailable for the one or more subsequent access operations.

[0117] Aspect 7: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 4 to 6, wherein the information indicates that the memory cell block is unavailable for the one or more subsequent access operations based on an error rate associated with the one or more re-qualification operations being greater than a threshold error rate.

[0118] Aspect 8: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 4 to 7, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for performing the following operations: storing first information indicating that the memory cell block can recover from an error condition based on the status indicating that the access operation is successful, wherein the first information further indicates that the block is included in the first group of blocks.

[0119] Aspect 9: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 4 to 8, wherein the one or more re-qualification operations include one or more erase operations, one or more program operations, one or more read operations, or any combination thereof, to refresh the memory cell block for the one or more subsequent access operations.

[0120] Aspect 10: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 9, wherein storing the information includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for performing the following operations: storing first metadata and second metadata in a metadata set, the first metadata including the information and a first identifier of the memory unit block, the second metadata including a second identifier of one or more second memory unit blocks from the one or more memory unit blocks of the memory system and second information indicating whether the one or more second memory unit blocks can be used for subsequent access operations.

[0121] Aspect 11: The method, apparatus, or non-transitory computer-readable medium of Aspect 10, wherein the first identifier comprises an address associated with the block of memory cells.

[0122] Aspect 12: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 11, wherein the error correction mode is based on failed read operations on the one or more blocks of memory cells.

[0123] Aspect 13: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 12, wherein the error correction mode comprises a RAIN operation.

[0124] Aspect 14: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 13, wherein the access operation comprises a program operation or an erase operation, and the status comprises an erase status fail indication or a program status fail indication.

[0125] It should be noted that the described techniques include possible implementations, and that operations and steps may be rearranged or otherwise modified, and that other implementations are possible. Additionally, portions from two or more of the described methods may be combined.

[0126] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or symbols of the signaling that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate signaling as a single signal; however, a signal may represent a bus of signals, where the bus may have a variety of bit widths.

[0127] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of electrons between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device containing the connected components, the conductive path between the components that are electronically connected (or in conductive contact or connected or coupled) to each other may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component such as a switch, transistor, or other component. In some instances, the signal flow between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as a switch or transistor.

[0128] The term "coupled" (e.g., "electrically coupled") may refer to a condition of moving from an open circuit relationship between components, in which signals are currently unable to be transmitted between components via conductive paths, to a closed circuit relationship between components, in which signals are able to be transmitted between components via conductive paths. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that previously did not permit signal flow.

[0129] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between the components. For example, components separated by a switch positioned between two components are isolated from one another when the switch is open. If a controller isolates two components, the controller implements a change that blocks a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0130] The terms "if", "when", "based on", or "based at least in part on" are used interchangeably. In some instances, the terms "if", "when", "based on", or "based at least in part on" are interchangeable if they are used to describe a conditional action, a conditional process, or a connection between parts of a process.

[0131] The devices discussed herein, including memory arrays, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In some other instances, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0132] The switch assembly or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain and a gate. The terminals may be connected to other electronic components by a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, such as degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0133] The descriptions set forth herein in conjunction with the accompanying drawings describe example configurations and do not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," rather than "preferably" or "better than other examples." The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid confusing the concepts of the described examples.

[0134] In the drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0135] The functions described herein may be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions (e.g., code). Due to the nature of software, the functions described herein may be implemented using software executed by a processing system, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may be physically located at various locations, including distributed such that portions of the functions are implemented at different physical locations.

[0136] The illustrative blocks and modules described herein may be implemented or executed with one or more processors, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof designed to perform the functions described herein. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or other type of processor. A processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0137] As used herein, "or," as used in a list of items (e.g., a list of items followed by a phrase such as "at least one of" or "one or more of"), as included in the claims, indicates a list that includes endpoints, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted similarly to the phrase "based at least in part on."

[0138] As used herein, the article "a" or "an" preceding a noun, including in the claims, is open-ended and should be understood to refer to "at least one" of those nouns or "one or more" of those nouns. Therefore, the terms "a", "at least one", "one or more", "at least one of one or more..." may be interchangeable. For example, if a claim recites a "component" that performs one or more functions, each of the individual functions may be performed by a single component or by any combination of multiple components. Therefore, the term "component" having a characteristic or performing a function may refer to "at least one of one or more components" that has a specific characteristic or performs a specific function. Subsequent references to components introduced with the article "a" using the term "the" or "said" may relate to any or all of the one or more components. For example, a component introduced with the article "a" may be understood to mean "one or more components", and subsequent references to "the component" in the claims may be understood to be equivalent to references to "at least one of the one or more components". Similarly, subsequent reference to a component introduced as "one or more components" using the term "the" or "said" may refer to any or all of the one or more components. For example, a subsequent reference to "the one or more components" in a claim may be understood to be equivalent to a reference to "at least one of the one or more components."

[0139] Computer-readable media include both non-transitory computer-readable storage media and communication media, and communication media include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory EEPROM, compact disc (CD) ROM or other optical disc storage device, magnetic disk storage device or other magnetic storage device, or can be used to carry or store the desired program code components in the form of instructions or data structures and can be accessed by a general or special-purpose computer or a general or special-purpose processor. Any other non-transitory media. And, any connection is appropriately referred to as computer-readable media. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are used to transmit software from a website, server or other remote source, the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwaves are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs use lasers to reproduce data optically. Combinations of the above are also included within the scope of computer-readable media.

[0140] The description herein is provided to enable a person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: operating in an error correction mode for one or more memory cell blocks of a memory system; monitoring, for a memory cell block of the one or more memory cell blocks and based on the error correction mode, a status associated with the memory cell block, wherein the status indicates whether an access operation to the memory cell block is successful; as well as Information indicating whether the block of memory cells is available for one or more subsequent access operations is stored, the information being based on the status associated with the block of memory cells. 2 . The method of claim 1 , wherein the information includes an indication that the access operation was unsuccessful and thus the memory cell block is unavailable based on the status. 3 . The method of claim 1 , wherein the information includes an indication that the access operation is successful and thus the block of memory cells is available based on the status.

4. The method according to claim 1, further comprising: operating the memory system in an idle mode; as well as When operating in the idle mode, one or more requalification operations are performed on the memory cell block based on the memory cell block being included in a first group of blocks, wherein the memory cell block is included in the first group of blocks based on the status indicating that the access operation to the memory cell block is successful, and wherein storing the information is further based on the one or more requalification operations.

5. The method of claim 4, wherein the information indicates that the block of memory cells is available for the one or more subsequent access operations based on an error rate associated with the one or more re-qualification operations being less than or equal to a threshold error rate.

6. The method of claim 4, wherein the information indicates that the block of memory cells is unavailable for the one or more subsequent access operations based on the one or more re-qualification operations being unsuccessful.

7. The method of claim 4, wherein the information indicates that the block of memory cells is unavailable for the one or more subsequent access operations based on an error rate associated with the one or more re-qualification operations being greater than a threshold error rate.

8. The method according to claim 4, further comprising: First information indicating that the block of memory cells is recoverable from an error condition based on the status indicating that the access operation was successful is stored, wherein the first information further indicates that the block is included in the first group of blocks.

9. The method of claim 4, wherein the one or more re-qualification operations include one or more erase operations, one or more program operations, one or more read operations, or any combination thereof to refresh the block of memory cells for the one or more subsequent access operations.

10. The method of claim 1, wherein storing the information comprises: First metadata and second metadata are stored in a metadata set, the first metadata including the information and a first identifier of the memory unit block, the second metadata including a second identifier of one or more second memory unit blocks from the one or more memory unit blocks of the memory system and second information indicating whether the one or more second memory unit blocks are available for subsequent access operations. The method of claim 10 , wherein the first identifier comprises an address associated with the block of memory cells.

12. The method of claim 1, wherein the error correction mode is based on failed read operations on the one or more blocks of memory cells.

13. The method of claim 1, wherein the error correction mode comprises independent and non-redundant array (RAIN) operation.

14. The method of claim 1, wherein the access operation comprises a program operation or an erase operation, and the status comprises an erase status fail indication or a program status fail indication.

15. A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to: operating in an error correction mode for one or more memory cell blocks of a memory system; monitoring, for a memory cell block of the one or more memory cell blocks and based on the error correction mode, a status associated with the memory cell block, wherein the status indicates whether an access operation to the memory cell block is successful; and Information indicating whether the block of memory cells is available for one or more subsequent access operations is stored, the information being based on the status associated with the block of memory cells.

16. The non-transitory computer-readable medium of claim 15, wherein the information includes an indication that the access operation was unsuccessful and thus the block of memory cells is unavailable based on the status.

17. The non-transitory computer-readable medium of claim 15, wherein the information includes an indication that the access operation was successful and thus the block of memory cells is available based on the status.

18. The non-transitory computer-readable medium of claim 15, wherein the instructions are further executable by the one or more processors to: operating the memory system in an idle mode; and When operating in the idle mode, one or more requalification operations are performed on the memory cell block based on the memory cell block being included in a first group of blocks, wherein the memory cell block is included in the first group of blocks based on the status indicating that the access operation to the memory cell block is successful, and wherein storing the information is further based on the one or more requalification operations.

19. The non-transitory computer-readable medium of claim 18, wherein the information indicates that the block of memory cells is available for the one or more subsequent access operations based on an error rate associated with the one or more re-qualification operations being less than or equal to a threshold error rate.

20. An apparatus comprising: A controller associated with the memory device, wherein the controller is configured to cause the apparatus to: operating in an error correction mode for one or more memory cell blocks of a memory system; monitoring, for a memory cell block of the one or more memory cell blocks and based on the error correction mode, a status associated with the memory cell block, wherein the status indicates whether an access operation to the memory cell block is successful; as well as Information indicating whether the block of memory cells is available for one or more subsequent access operations is stored, the information being based on the status associated with the block of memory cells.

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