Bus data detection module and detection method

Abstract

The invention discloses a bus data detection module and a detection method, which are used for performing write-in mode processing or read mode processing on bus data. When the target slave ID and the M.ECC check code generated by the M.ECC generation module are respectively consistent with the slave ID and the S.ECC check code obtained by the S.ECC generation module, the bus data information sent by the host M can be written into the corresponding slave S; and when the M.ECC generation module generates a target slave ID, the M.ECC check code and the M.data ECC check code are respectively consistent with the slave ID, the S.ECC check code and the S.data ECC check code generated by the S.ECC generation module, the bus data in the slave S can be transmitted to the host M and read by the client. According to the method, the bus data information, the check code and the address information are transmitted in a branching way, a judgment and detection step is added in the transmission process, and if any error occurs in the transmission process, the error is identified and reported in different judgment steps, so that the problem of missing detection in the traditional ECC technology is effectively solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of data transmission, and in particular relates to a bus data detection module and a detection method. Background Art

[0002] In the design of automotive microcontrollers (MCUs), the address width of the bus in the computer system will be shortened during the transmission process. This is because different modules require different address widths during digital data processing. For example, the CPU requires a larger address space, while the memory controller and device may only need to process a limited address range. In addition, a wider address bus requires more signal lines, which may cause signal integrity issues such as interference and delay. Therefore, there is usually an address decoder inside the bus bridge module, which generates a control signal based on the complete address input by the host to determine the effective address, thereby generating a selection signal for the specified slave and intercepting the effective address width required by the slave to send to the corresponding slave. The address width received by the slave will only retain its own effective address space, and there will be no high-order address information.

[0003] Bus data transmission mainly relies on ECC technology (Error Correcting Code) to detect and correct errors in data transmission. ECC technology is derived from parity check technology and has more powerful automatic identification and correction capabilities. It can identify and correct error bits that parity check technology cannot detect. In bus transmission, there are multiple bus protocol signals such as data signals, address signals, and control signals. These signals may have errors during transmission. Therefore, bus bridges usually check these signals through ECC methods. The flowchart of the traditional ECC verification method can be found in the attached Figures 1 to 3 .

[0004] However, when the MCU's host accesses the slave device through the bus bridge, if the address decoder is interfered by electromagnetic or noise, an erroneous slave select signal may be generated, causing the data to be mistakenly sent to an unintended slave or host. In this case, since the bus data itself is correct, the ECC check will still consider the data correct because the ECC cannot detect this erroneous slave selection. This poses a potential safety hazard because the system cannot identify this error, which may cause data to be sent to the wrong component, causing unpredictable behavior.

[0005] In addition, current ECC implementations do not support AXI (Advanced eXtenS1ble Interface) out-of-order mode. The AXI protocol allows transactions to arrive in a non-linear order, thereby improving the efficiency of the system. However, in out-of-order mode, ECC's error detection and correction capabilities may be limited because ECC generally assumes that data is transmitted in a specific order. This mismatch may make it impossible to use traditional ECC technology in out-of-order transmission, thereby reducing the overall reliability of the system.

[0006] In summary, although ECC plays an important role in detecting and correcting errors in bus transmission, its limitations in AXI out-of-order mode and the inability to detect slave selection errors when the address decoder is disturbed indicate that the existing technology is still insufficient in ensuring system security and reliability.

[0007] The existing patent CN119149446A "A method for generating a memory address, a storage control method and a generating device" proposes a method for generating a memory address, a storage control method and a generating device. The generating method includes using a storage controller in a SOC system to obtain a data storage address based on an address signal from a bus of the SOC system, and storing the data from the bus in a data storage unit in an access order from the lowest bit to the highest bit of the data storage address; based on the mode in which the storage controller is located, obtaining an ECC memory address, and storing the obtained ECC check code in an ECC storage unit in an access order from the highest bit to the lowest bit of the ECC memory address. However, this technical solution focuses on static address generation prevention, and bus data errors can only be discovered when they are read, that is, errors can only be detected after the bus data has been transmitted; and this technical solution requires a storage unit for each address ECC, and the number of storage units required is large, occupying a large storage space. In addition, this technical solution only has the bus data ECC check code, and the bus address does not have an ECC check code. It is only checked indirectly by taking the address inverse check code, and the bus data ECC check code and the bus data physical address are bound and transmitted simultaneously. This transmission method will have the risk of storing the bus data ECC check code in the wrong bus data physical address, and cannot solve the problem of address decoding errors. Therefore, these limitations need to be solved through further technical improvements and innovations. Summary of the invention

[0008] The purpose of the present invention is to solve the above problems existing in the prior art and to provide a bus data detection module and a detection method.

[0009] The purpose of the present invention is achieved through the following technical solutions: A bus data detection module is used to detect bus data transmitted between a host M and a slave S. When the host M sends an access request to the slave S, bus information and corresponding host transaction ID and slave transaction ID are generated; the bus information includes a bus address, a bus control signal and bus data; the bus data detection module includes an address decoder, an M.ECC generation module, an M.ECC check module and an S.ECC generation module; The M.ECC generation module obtains the host transaction ID, and generates a target slave ID and an M.ECC check code according to the bus information; The S.ECC generation module obtains the slave transaction ID, and obtains the host address M.ID of the host currently initiating the access and the slave ID currently to be accessed according to the bus information compiled by the address decoder, and calculates the S.ECC check code of the corresponding slave using the ECC algorithm; The M.ECC check module is provided with a FIFO memory, and by comparing the target slave ID and the slave ID, as well as the M.ECC check code and the S.ECC check code, a comprehensive detection of data transmission and slave selection in bus information transmission is achieved, thereby blocking the transmission of erroneous data.

[0010] Preferably, it also includes a transmission sequence processing module, which determines whether the host transaction IDs corresponding to two or more of the bus information are consistent; when the host transaction IDs corresponding to two or more of the bus information are the same, the transmission sequence processing module controls the order in which the slave S writes or returns data to be consistent with the order in which the access requests are issued; when the host transaction IDs corresponding to two or more of the bus information are not the same, the transmission sequence processing module controls the order in which the slave S writes or returns data to be arbitrary.

[0011] When the detection method of the bus data detection module is in the bus data writing mode, the specific steps include: S1, receiving an access request from a client to write bus data from a host M to a slave S, the host M generates a host transaction ID, a slave transaction ID and corresponding bus information; and transmits the host transaction ID and the bus information to an M.ECC generation module corresponding to the host M; the bus information includes a bus address, a bus control signal and bus data; S2, the M.ECC generation module transmits the bus information to the address decoder, and generates the M.ECC check code of the corresponding host and the target slave ID according to the bus information; S3, the M.ECC generation module transmits the M.ECC check code, the target slave ID and the host transaction ID to the M.ECC check module corresponding to the host M; selects a corresponding FIFO memory according to the target slave ID and the host transaction ID, and stores the M.ECC check code in the FIFO memory; S4, the address decoder compiles the bus information and transmits the compiled bus information to the S.ECC generation module of the corresponding slave; S5, the S.ECC generation module obtains the slave transaction ID, and obtains the host address M.ID of the host currently initiating the access and the slave ID currently to be accessed according to the compiled bus information, and simultaneously uses the ECC algorithm to calculate the S.ECC check code of the corresponding slave; S6, the S.ECC generation module transmits the slave ID, the S.ECC check code and the slave transaction ID to the M.ECC check module corresponding to the host address M.ID; S7, selecting a corresponding FIFO memory according to the slave ID and the slave transaction ID, first determining whether the slave ID and the target slave ID are consistent, and reporting an error when they are inconsistent; and retrieving the M.ECC check code stored therein from the target slave ID; reporting an error when the M.ECC check code does not exist in the FIFO memory; and determining whether the M.ECC check code is consistent with the S.ECC check code when the M.ECC check code exists in the FIFO memory, and reporting an error when they are inconsistent; and outputting a "transmission correct" signal when they are consistent; S8, feeding back the signal generated in step S7 to the S.ECC generation module; S9, writing the compiled bus data in the bus information into the corresponding slave S.

[0012] Preferably, in step S2, the M.ECC check code includes a bus address check code, a bus control signal check code and a bus data ECC check code.

[0013] Preferably, in step S4, after the bus information is compiled by the address decoder, the address decoder first selects a slave S, and then transmits the compiled bus information to the S.ECC generation module of the corresponding slave S.

[0014] Preferably, in step S5, the S.ECC check code includes a slave address check code, a slave control signal check code and a slave data ECC check code.

[0015] Preferably, in step S6, the S.ECC check code, the slave ID and the slave transaction ID need to determine the address of the host that currently initiates the access request according to the host address M.ID before reaching the M.ECC check module, and send the S.ECC check code, the slave ID and the slave transaction ID to the M.ECC check module of the corresponding host according to the host address M.ID.

[0016] Preferably, if it is determined based on the host address M.ID that the access request is not initiated by the designated host M, the S.ECC check code will be sent to the M'.ECC check module corresponding to other hosts except the designated M.ECC check module; at this time, when continuing to step S7, it will be determined that the M.ECC check code does not exist in the FIFO memory, and an error will be reported.

[0017] As for the detection method of the bus data detection module mentioned above, when in the bus data reading mode, the specific steps include: S1', receiving an access request from a client to read bus data from a host M to a slave S, the host M generates a host transaction ID, a slave transaction ID and bus information corresponding thereto; and transmits the host transaction ID and the bus information to an M.ECC generation module corresponding to the host M; the bus information includes a bus address and a bus control signal; S2', the M.ECC generation module transmits the bus information to the address decoder, and generates the M.ECC check code of the corresponding host and the target slave ID according to the bus information; S3', the M.ECC generation module transmits the M.ECC check code, the target slave ID and the host transaction ID to the M.ECC check module of the host, selects a corresponding FIFO memory according to the target slave ID and the host transaction ID, and stores the M.ECC check code in the FIFO memory; S4', the address decoder compiles the bus address and transmits the compiled bus information to the S.ECC generation module of the corresponding slave; S5', the S.ECC generation module obtains the slave transaction ID, and obtains the host address M.ID of the host currently initiating the access and the slave ID currently to be accessed according to the compiled bus information, and simultaneously calculates the S.ECC check code of the corresponding slave using the ECC algorithm; S6', the S.ECC generation module transmits the slave ID, the S.ECC check code and the slave transaction ID to the M.ECC check module corresponding to the host address M.ID; S7', select the corresponding FIFO memory according to the slave ID and the slave transaction ID, first determine whether the slave ID and the target slave ID are consistent, if not, an error is reported, if consistent, retrieve the M.ECC check code stored therein; if the M.ECC check code does not exist in the FIFO memory, an error is reported; if the M.ECC check code exists in the FIFO memory, determine whether the M.ECC check code is consistent with the S.ECC check code, if inconsistent, an error is reported; if consistent, output a "transmission correct" signal; S8', feeding back the signal generated in step S7 to the S.ECC generation module; S9', the S.ECC generation module obtains the bus data to be read from the corresponding slave, and on the one hand, uses the ECC algorithm to calculate the S.Data ECC check code of the bus data, and transmits the S.Data ECC check code together with the slave ID and the slave transaction ID to the M.ECC check module corresponding to the host address M.ID; the M.ECC check module selects the corresponding FIFO memory according to the slave ID and the slave transaction ID, and stores the S.Data ECC check code in the FIFO memory; On the other hand, the bus data is transmitted to the M.ECC generation module after passing through the address decoder, and the M.ECC generation module generates an M.data ECC check code according to the bus data; S10', the M.ECC generation module transmits the target slave ID, the M.data ECC check code and the acquired host transaction ID to the M.ECC check module corresponding to the host address M.ID; selects the corresponding FIFO memory according to the target slave ID and the host transaction ID, and retrieves the S.data ECC check code stored therein; reports an error when the S.data ECC check code does not exist in the FIFO memory corresponding to the target slave ID and the host transaction ID; if the S.data ECC check code exists in the FIFO memory, determines whether the M.data ECC check code is consistent with the S.data ECC check code, and reports an error when they are inconsistent; outputs a "transmission correct" signal when they are consistent; S11' feeds back the signal generated in step S10' to the M.ECC generation module; and feeds back the bus data in the bus information to the host M, which is finally read out by the client.

[0018] Preferably, in step S2', the M.ECC check code includes a bus address check code and a bus control signal check code.

[0019] Preferably, in the step S4', after the bus information is compiled by the address decoder, the address decoder selects a slave S and transmits the compiled bus information to the S.ECC generation module of the corresponding slave S.

[0020] Preferably, in step S5', the S.ECC check code includes a slave address check code and a slave control signal check code.

[0021] Preferably, in step S6', the S.ECC check code, the slave ID and the slave transaction ID need to determine the address of the host that currently initiates the access request according to the host address M.ID before reaching the M.ECC check module, and send the S.ECC check code, the slave ID and the slave transaction ID to the M.ECC check module of the corresponding host according to the host address M.ID.

[0022] Preferably, if it is determined based on the host address M.ID that the access request is not initiated by the designated host M, the S.ECC check code will be sent to the M'.ECC check module corresponding to other hosts except the designated M.ECC check module; at this time, when continuing to step S7', it will be determined that there is no ECC check code in the FIFO memory, and an error will be reported.

[0023] Preferably, the S. data ECC check code in step S9' includes a slave data ECC check code; and the M. data ECC check code in step S9' includes a bus data ECC check code.

[0024] Preferably, in step S9', the S.data ECC check code, the slave ID and the slave transaction ID need to determine the address of the host that currently initiates the access request according to the host address M.ID before reaching the M.ECC check module, and send the S.data ECC check code, the slave ID and the slave transaction ID to the M.ECC check module of the corresponding host according to the host address M.ID.

[0025] Preferably, if the address decoder makes an error during the compilation process, an erroneous S. data ECC check code will be generated in step S9'; and when continuing to step S10', it will be determined that the M. data ECC check code is inconsistent with the S. data ECC check code, and an error will be reported.

[0026] The advantages of the technical solution of the present invention are mainly reflected in: (1) The present invention adds a host transaction ID and a slave transaction ID, so that the traditional ECC technology adds support for the AXI out-of-order mode. In the ECC technology, the target slave ID and the host transaction ID and the slave ID and the slave transaction ID are used to effectively detect the problem that the data generated during the transmission process is mistakenly sent to an unexpected slave or host, thereby improving the efficiency, security and reliability of data transmission; (2) The present invention transmits bus information through an address decoder, and the M.ECC check code and the target slave ID other than the data information are generated by the M.ECC generation module, and the host transaction ID is generated by the host. The three are then directly transmitted to the M.ECC check module, that is, the data information, the check information and the ID information are transmitted separately, and a judgment program is added during the transmission process. If any error occurs during the transmission process, it will be identified and reported in different judgment programs, which effectively makes up for the problem of missed detection in traditional ECC technology; (3) The present invention focuses on dynamic transmission error detection. During the read transmission process, the first step is to detect whether the transmission address is wrong; the second step is to compare the consistency of the M.ECC check code and the Sn.ECC check code, the M.data ECC check code and the S.ECC check code to determine whether there is an error in the bus information transmission process. The two check procedures enhance the detection reliability. At the same time, the present invention requires fewer storage units and is more efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 : Overall schematic diagram of bus data detection in the background technology of the present invention; Figure 2 : Overall flow chart of bus data write transmission in the background technology of the present invention; Figure 3 : Overall flow chart of bus data read transmission in the background technology of the present invention; Figure 4 : Schematic diagram of the overall framework structure of bus data detection of the present invention; Figure 5 : A specific flow chart of bus data write transmission according to a preferred embodiment of the present invention; Figure 6 : Specific flow chart of bus data read transmission according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0028] The purpose, advantages and features of the present invention will be illustrated and explained by the non-limiting description of the following preferred embodiments. These embodiments are only typical examples of the application of the technical solution of the present invention, and any technical solution formed by equivalent replacement or equivalent transformation falls within the scope of protection claimed by the present invention.

[0029] like Figures 4 to 6As shown, the present invention discloses a bus data detection module for detecting bus data transmitted between a host M and a slave S. The bus data detection module can write the bus data in the host M into the slave S through a write mode, or feed back the bus data in the slave S to the host M through a read mode. At the same time, the number of hosts in the bus data detection module can be determined according to usage requirements, and its number is not specifically limited here; that is, the host can be composed of a host M1, a host M2, a host M3 to a host Mn, where n represents a natural number. Similarly, the number of slaves is also determined according to usage requirements, and is not limited here.

[0030] The present invention comprises a host M, a slave S, an address decoder, an M.ECC generating module, an M.ECC checking module and an S.ECC generating module.

[0031] When the host M sends an access request to the slave S, bus information, and corresponding host transaction ID and slave transaction ID are generated; the bus information includes a bus address, a bus control signal, and bus data.

[0032] The M.ECC generation module is located at the position where each host bus data enters the bus bridge module. The M.ECC generation module generates an M.ECC check code and a target slave ID according to the bus information generated by the host M; at the same time, the M.ECC generation module transmits the M.ECC check code, the target slave ID and the acquired host transaction ID to the M.ECC check module. That is, the M.ECC generation module has the functions of 1. calculating the check code of the bus data according to the ECC algorithm; 2. calculating the check code of the bus address according to the ECC algorithm; 3. calculating the check code of the bus control signal according to the ECC algorithm; 4. decoding the address to clarify the target slave ID; 5. obtaining the current host transaction ID from the bus information; 6. transmitting all the aforementioned check codes, the target slave ID and the host transaction ID to the M.ECC check module.

[0033] The S.ECC generation module is located at the position where the bus information is sent to the corresponding slave after passing through the address decoder. The S.ECC generation module obtains the host address M.ID of the current host and the slave ID to be accessed currently according to the bus information compiled by the address decoder, and uses the ECC algorithm to calculate the S.ECC check code of the corresponding slave; at the same time, the S.ECC generation module transmits the slave ID, the S.ECC check code and the obtained slave transaction ID to the M.ECC check module corresponding to the host address M.ID. That is, the S.ECC generation module has 1. Calculate the check code of the bus data according to the ECC algorithm; 2. Calculate the check code of the address according to the ECC algorithm; 3. Calculate the check code of the bus control signal according to the ECC algorithm; 4. Obtain the host address M.ID of the host that currently initiates the access from the bus information; 5. Obtain the current slave transaction ID; 6. Transmit the aforementioned check code, the slave transaction ID and the slave ID to the corresponding M.ECC check module according to the host address M.ID.

[0034] The M.ECC check module is provided with a FIFO memory, and by comparing the target slave ID and the slave ID, as well as the M.ECC check code and the S.ECC check code, a comprehensive detection of data errors and slave address selection errors in bus information transmission is achieved, thereby blocking the transmission of erroneous data.

[0035] Specifically, the number of FIFO memories in the M.ECC check module is determined by the number of slaves and the maximum number of out-of-order transactions supported by the bus. Each FIFO memory is bound to a unique transaction ID and slave ID to ensure the independence of the check code timing. The M.ECC check module has 1. receiving and storing the M.ECC check code and the target slave ID and host transaction ID corresponding to the M.ECC generation module; 2. receiving and storing the check code and slave ID and transaction ID of all S.ECC generation modules; 3. checking and error handling of the check code according to the slave ID and slave transaction ID.

[0036] like Figure 2 or Figure 3 In the traditional bus data detection module using ECC technology shown in the figure, after the data is transmitted to the address decoder, if the address decoder is interfered by external signals or an error occurs, the bus data that should have been written by the host M1 to the slave S1 is transmitted to the slave S2 or the slave Sn. At this time, since the bus data itself is not wrong, the corresponding ECC check module will not find any error when recalculating and comparing the data. Therefore, the traditional method cannot effectively detect the error. However, this error will cause the system to behave unexpectedly and affect functional safety.

[0037] like Figures 5 and 6 As shown, the present invention also has the advantage of comprehensively detecting bus data. Specifically, the M.ECC check code and the S.ECC check code both cover the bus address, bus control signal and bus data; and the M.ECC check code module compares the host transaction ID and the slave transaction ID, the target slave ID and the slave ID, and the M.ECC check code and the S.ECC check code through three-layer verification, thereby achieving comprehensive detection of the bus information and full coverage of the bus signal, thereby improving the accuracy and reliability of bus data transmission.

[0038] like Figures 4 to 6 The figure shows the detection method of the bus data detection module disclosed by the present invention. Through this method, the bus information written by the host M to the slave S can be detected, and the bus data fed back from the slave S to the host M can also be detected. The present invention strengthens the inspection of the data distribution logic. Specifically, in addition to verifying the data, the present invention also adds the detection of the address decoding logic. The M.ECC check code and the target slave ID are generated on the host side according to the bus information, and the S.ECC check code and the slave ID are also generated on the slave side. The host ID of the transmission is sent to the detection module of the corresponding host for comparison. This can ensure the correctness of the transmission between the host and the slave, cover more abnormal scenarios in the bus transmission process, and improve the security and reliability of the system.

[0039] The present invention also adopts the AXI protocol to support out-of-order transmission. Specifically, each bus information sent by the host M corresponds to a host transaction ID and a slave transaction ID. All bus information is classified and distinguished by the host transaction ID and the slave transaction ID, and the bus information in the FIFO memory corresponding to the same host transaction ID or the slave transaction ID must be output in sequence; the bus information in the FIFO memory corresponding to different transaction IDs or the slave transaction IDs can be output in any order. That is, in the present invention, after sending a request to the slave S through the host transaction ID and the slave transaction ID, the slave S can identify whether the host transaction ID and the slave transaction ID of all bus information are consistent and select whether the bus data is written to the corresponding slave or returned to the corresponding host in sequence or out of order.

[0040] Specifically, the technical solution of the present invention includes a transmission sequence processing module, which is located in the host M and determines whether the host transaction IDs corresponding to two or more bus information are consistent. When the host transaction IDs corresponding to two or more bus information are the same, the transmission sequence processing module controls the order in which the slave S writes or returns data to be consistent with the order in which the access request is issued. When the host transaction IDs corresponding to two or more bus information are not the same, the transmission sequence processing module controls the order in which the slave S writes or returns data to be arbitrary.

[0041] like Figure 5 The detection method of the bus data detection module shown in the figure performs detection when in the bus data writing mode, and the specific steps include: S1, the host M receives an access request from the client to write bus data to the slave S, and the host M generates a host transaction ID, a slave transaction ID and corresponding bus information. At the same time, the host M transmits the host transaction ID and the bus information to the M.ECC generation module corresponding to the host M. In this mode, the bus information includes a bus address, a bus control signal and bus data. Furthermore, the bus address includes address data, the bus control signal includes at least a write signal and the size information of the data transmission, and the bus data includes the data information to be written.

[0042] S2, the M.ECC generation module transmits the bus information to the address decoder, and generates the M.ECC check code of the corresponding host and the target slave ID according to the bus information. At the same time, the M.ECC check code in this mode includes the bus address check code, the bus control signal check code and the bus data ECC check code.

[0043] S3, the M.ECC generation module transmits the M.ECC check code, the target slave ID and the acquired host transaction ID to the M.ECC check module corresponding to the host M. At the same time, the M.ECC generation module selects a corresponding FIFO memory according to the target slave ID and the host transaction ID, and stores the M.ECC check code in the FIFO memory.

[0044] S4, the address decoder compiles the bus information and transmits the compiled bus information to the S.ECC generation module of the corresponding slave.

[0045] S5, the S.ECC generation module obtains the host address M.ID of the host that currently initiates the access request and the ID of the slave to be accessed according to the bus information, and uses the ECC algorithm to calculate the S.ECC check code of the corresponding slave. At this time, the S.ECC check code includes the slave address check code, the slave control signal check code and the slave data ECC check code.

[0046] S6, the S.ECC generation module transmits the slave ID, the S.ECC check code and the obtained slave transaction ID to the M.ECC check module corresponding to the host address M.ID. In this process, the S.ECC check code, the slave ID and the slave transaction ID need to determine the address of the host that currently initiates the access request according to the host address M.ID before reaching the M.ECC check module, and send the S.ECC check code, the slave ID and the slave transaction ID to the M.ECC check module of the corresponding host according to the host address M.ID.

[0047] In this step, if it is determined according to the host address M.ID that the access request is not initiated by the designated host M, the S.ECC check code will be sent to the M'.ECC check module corresponding to other hosts except the designated M.ECC check module. At this time, when the execution continues to step S7, it will be determined that there is no ECC check code in the FIFO memory, and an error will be reported.

[0048] Specifically, take the example of the client sending a write signal from the host M1 to the slave S1. If an error occurs when obtaining the address of the host that currently issues the access request (i.e., the host address M.ID) when executing step S5, the host address of M1.ID that should have been obtained is mistakenly considered to be the host address of M2.ID or Mn.ID. Then the S1.ECC check code generated by step S5, the S1.ID of the slave, and the S1.transaction ID of the slave will all be sent to the M2.ECC check module or the Mn.ECC check module. Furthermore, when executing step S7, it may be found that there is no ECC check code in the FIFO memory corresponding to the S1.ID and the S1.transaction ID, and an error is reported.

[0049] S7, select the corresponding FIFO memory according to the slave ID and the slave transaction ID, first determine the slave ID and the target slave ID, and when the two are consistent, retrieve the M.ECC check code stored therein; when the ECC check code does not exist in the FIFO memory, report an error; when the ECC check code exists in the FIFO memory, determine whether the M.ECC check code is consistent with the S.ECC check code, and report an error when they are inconsistent; when they are consistent, output a "transmission correct" signal.

[0050] Furthermore, when executing this step, if the M.ECC check module reports an error to the controller, the reasons are as follows: 1. The slave ID is incorrect; 2. The corresponding FIFO memory cannot be found; 3. The M.ECC check code does not exist in the FIFO memory. The root cause of the error is that the address decoder in step S4 selects the wrong slave S.

[0051] If the address decoder makes an error during the compilation process or is interfered by an external signal, resulting in the selection of slave S2 or other slave Sn instead of slave S1, the bus information will be transmitted to the S2.ECC generation module or the Sn.ECC generation module in the above step S4. Then, the S2.ECC check code, the address of slave S2 (i.e., S2.ID) and the transaction address of slave S2 (i.e., S2.Transaction ID) are generated in step S5. In step S6, the S2.ECC check code is sent to the M2.ECC check code module, or the Sn.ECC check code is sent to the Mn.ECC check code. When executing step S7, the M1.ECC check code will be retrieved from the FIFO memory corresponding to S2.ID and S2.Transaction ID in the M1.ECC check module. At this time, it will be found that the slave ID (i.e., S2.ID) or the slave transaction ID (i.e., S2.Transaction ID) does not exist, or the corresponding FIFO memory cannot be found, or the ECC check code does not exist in the FIFO memory. Therefore, when the address decoder selects an incorrect slave, the detection method of the bus data detection module disclosed in the present invention will detect it, and the M1.ECC check module will report the error to the MCU controller.

[0052] In addition, the reason why the M.ECC check module reports an error to the controller when executing this step may also be because the M.ECC check code is determined to be inconsistent with the S.ECC check code. The fundamental reason for the inconsistency between the M.ECC check code and the S.ECC check code is that the bus information generates erroneous bus data during the process, causing the S.ECC generation module to generate an erroneous S.ECC check code.

[0053] Specifically, take the client sending a write signal from the host M1 to the slave S1 as an example. If the address decoder is disturbed by external interference during the compilation process of step S4 and an error occurs, resulting in an error or omission of bus data in the bus information, then an erroneous S1.ECC check code will be generated in step S5, and the S1.ECC check code may be inconsistent when compared with the M1.ECC check code in step S7.

[0054] In addition, if after the above error is generated, it is found through investigation that the address decoder is correct during the compilation process, it means that the host address M.ID address obtained when executing step S5 is wrong.

[0055] S8, feeding back the signal generated in step S7 to the S.ECC generation module.

[0056] S9, write the bus data in the compiled bus information into the corresponding slave S. Before writing the bus data into the slave S, the transmission sequence processing module first determines whether the host transaction IDs corresponding to two or more of the bus information are consistent. When the host transaction IDs corresponding to two or more of the bus information are the same, the transmission sequence processing module controls the order in which the slave S writes data to be consistent with the order in which the access request is issued. When the host transaction IDs corresponding to two or more of the bus information are not the same, the transmission sequence processing module controls the order in which the slave S writes data to be arbitrary.

[0057] When the host M sends an access request to the slave S, it determines whether to perform write mode processing or read mode processing according to the bus control signal in the bus information. At the same time, the host M will generate the host transaction ID and the slave transaction ID.

[0058] Take the bus control signal as a write mode processing as an example: if the same slave S receives write signal requests from multiple hosts M in succession, and the transmission order processing module determines that the host transaction IDs issued by each host M are different, then the order of data written to the slave S by the out-of-order transmission processing module can be different from the order of the host transaction IDs received by the slave S. That is, when the slave S1 receives access requests from the hosts M1, M2, and M3 simultaneously or successively, the host transaction ID of the host M1 is 0, the corresponding bus information is X, bus data x, the host transaction ID of the host M2 is 1, the corresponding bus information is Y, bus data y, the host transaction ID of the host M3 is 2, the corresponding bus information is Z, bus data z. The transmission sequence processing module determines that the host transaction IDs corresponding to the three bus information are all different, and the response speed of the slave S1 to the bus data y is faster than that to the bus data x. Then, the transmission sequence processing module controls the slave S1 to write in the order of bus data y, bus data x, and bus data z, or in the order of bus data y, bus data z, bus data x or other orders.

[0059] If the same slave S receives write signal requests from multiple hosts M in succession, and the transmission sequence processing module determines that the host transaction IDs issued by some of the hosts M are the same, then the transmission sequence processing module controls the order of data written to the slave S to be different from the order of host transaction IDs received by the slave S. That is, when the slave S1 receives access requests from hosts M1, M2, and M3 simultaneously or continuously, the host transaction ID of host M1 is 0, the corresponding bus information is X, bus data x, the host transaction ID of host M2 is 1, the corresponding bus information is Y, bus data y, and the host transaction ID of host M3 is 0, the corresponding bus information is Z, bus data z. At this time, the out-of-order transmission processing module determines that some of the host transaction IDs are the same, and classifies and distinguishes them according to the host transaction ID, and divides them into two types of host transaction IDs. The transmission sequence processing module controls the slave S1 to write in the order of bus data y, bus data x, bus data z, or in the order of bus data x, bus data y, bus data z, or in the order of bus data x, bus data z, bus data y. The bus data x and bus data z must be written in the order in which they are input.

[0060] If the same slave S receives write signal requests from multiple hosts M in succession, and the out-of-order transmission processing module determines that the host transaction IDs issued by each host M are the same, then the out-of-order transmission processing module controls the order of data written to the slave S to be exactly the same as the order of host transaction IDs received by the slave S. That is, when slave S1 receives access requests from hosts M1, M2, and M3 simultaneously or in succession, the host transaction ID of host M1 is 0, the corresponding bus information is X, bus data x, the host transaction ID of host M2 is 0, the corresponding bus information is Y, bus data y, and the host transaction ID of host M3 is 0, the corresponding bus information is Z, bus data z. Because the out-of-order transmission processing module determines that all the host transaction IDs are the same, at this time the transmission sequence processing module controls the slave S1 to write only in the order in which it is received, and the write order is bus data x, bus data y, and bus data z.

[0061] In addition, the same host M may also continuously send multiple access requests to the same slave S; that is, the same host M continuously sends multiple bus information to one of the slaves S in a write mode process, and simultaneously sends the host transaction ID and slave transaction ID corresponding to each bus information to the corresponding slave S. The out-of-order transmission processing module controls the slave S to write the bus data in order or out of order based on whether the host transaction ID or the slave transaction ID is consistent. Figures 1 to 3The ECC technology used in the traditional bus data detection module shown cannot support the processing of AXI bus protocol out-of-order transmission because the host cannot generate the host transaction ID and the slave transaction ID during transmission, so the data transmission and writing sequence must be transmitted in the input sequence, which leads to a long data transmission time and low system efficiency. If the AXI out-of-order mode is used in the traditional bus data detection module, false errors will occur.

[0062] The present invention solves the problem that traditional ECC technology does not support out-of-order transmission of AXI bus protocol by adding host transaction ID and slave transaction ID to support AXI processing, so that traditional ECC technology supports out-of-order transmission of AXI bus protocol, data can be reliably verified and corrected, and system performance is improved.

[0063] like Figure 5 As shown, taking the client sending a write signal from host M1 to slave S1 as an example, in the specific steps, all the host M refers to host M1, M.ECC generation module refers to M1.ECC generation module, M.ECC check module refers to M1.ECC check module, M.ECC check code refers to M1.ECC check code, and M.data ECC check code refers to M1.data ECC check code. All the slaves S refer to slave S1, S.ECC generation module refers to S1.ECC generation module, S.ECC check module refers to S1.ECC check module, S.ECC check code refers to S1.ECC check code, and S.data ECC check code refers to S1.data ECC check code.

[0064] Similarly, if the client sends a write signal from host M1 to slave S2 as an example, then all the host M in the above specific steps refers to host M1, M.ECC generation module refers to M1.ECC generation module, M.ECC check module refers to M1.ECC check module, M.ECC check code refers to M1.ECC check code, and M.data ECC check code refers to M1.data ECC check code. All the slaves S refer to slave S2, S.ECC generation module refers to S2.ECC generation module, S.ECC check module refers to S2.ECC check module, S.ECC check code refers to S2.ECC check code, and S.data ECC check code refers to S2.data ECC check code.

[0065] By analogy, if the client sends a write signal from host M2 to slave S1 as an example, then all the host M in the above specific steps refers to host M2, M.ECC generation module refers to M2.ECC generation module, M.ECC check module refers to M2.ECC check module, M.ECC check code refers to M2.ECC check code, and M.data ECC check code refers to M2.data ECC check code. All the slaves S refer to slave 1, S.ECC generation module refers to S1.ECC generation module, S.ECC check module refers to S1.ECC check module, S.ECC check code refers to S1.ECC check code, and S.data ECC check code refers to S1.data ECC check code. Other embodiments can be inferred based on the above embodiments, which will not be repeated here.

[0066] Specific as Figure 6 The detection method of the bus data detection module shown in the figure performs detection when in the bus data writing mode, and the specific steps include: S1', the host M receives an access request from the client to read bus data from the slave S, and the host M generates a host transaction ID, a slave transaction ID and the corresponding bus information. At the same time, the host M transmits the host transaction ID and the bus information to the M.ECC generation module corresponding to the host M. In this mode, the bus information includes a bus address and a bus control signal. Furthermore, the bus address includes address data, and the bus control signal includes a read signal and size information of data transmission.

[0067] S2', the M.ECC generation module transmits the bus information to the address decoder, and generates the M.ECC check code of the corresponding host and the target slave ID according to the bus information. Meanwhile, the M.ECC check code in this mode includes the bus address check code and the bus control signal check code.

[0068] S3', the M.ECC generation module transmits the M.ECC check code, the target slave ID and the acquired host transaction ID to the M.ECC check module of the host. Then the M.ECC generation module selects a corresponding FIFO memory according to the target slave ID and the host transaction ID, and stores the M.ECC check code in the FIFO memory.

[0069] S4', the address decoder compiles the bus information and transmits the compiled bus information to the S.ECC generation module of the corresponding slave.

[0070] S5', the S.ECC generation module obtains the host address M.ID of the host that currently initiates the access request and the ID of the slave to be accessed according to the bus information, and uses the ECC algorithm to calculate the S.ECC check code of the corresponding slave. At this time, the S.ECC check code includes the bus address check code and the bus control signal check code.

[0071] S6', the S.ECC generation module transmits the slave ID, the S.ECC check code and the obtained slave transaction ID to the M.ECC check module corresponding to the host address M.ID. In this process, the S.ECC check code, the slave ID and the slave transaction ID need to determine the host that currently initiates the access request according to the host address M.ID before reaching the M.ECC check module, and send the S.ECC check code, the slave ID and the slave transaction ID to the M.ECC check module of the corresponding host according to the host address M.ID.

[0072] In this step, if it is determined according to the host address M.ID that the access request is not initiated by the designated host M, the S.ECC check code will be sent to the M'.ECC check module corresponding to other hosts except the designated M.ECC check module. At this time, when the execution continues to step S7', it will be determined that there is no ECC check code in the FIFO memory, and an error will be reported.

[0073] Specifically, take the client sending a read signal from the host M1 to the slave S1 as an example. If the address of the host that currently sends the access request (i.e., the host address M.ID) is obtained incorrectly when executing step S5', the host address of M1.ID that should have been obtained is mistakenly considered to be the host address of M2.ID or Mn.ID. Then the S1.ECC check code generated by step S5', the S1.ID of the slave and the S1.transaction ID of the slave will all be sent to the M2.ECC check module or the Mn.ECC check module. Then, when executing step S7', it may be found that there is no ECC check code in the FIFO memory corresponding to the S1.ID and the S1.transaction ID, and an error is reported; or when continuing to execute step S7', it will be determined that the M1.ECC check code is inconsistent with the S.ECC check code, and an error is reported. At this time, it can be inferred from the error information that the cause of the error is that the address of the wrong host is obtained (i.e., the host address M.ID is obtained incorrectly).

[0074] S7', select the corresponding FIFO memory according to the slave ID and the slave transaction ID, first determine whether the slave ID and the target slave ID are consistent, and then retrieve the M.ECC check code stored therein when the two are consistent; when the ECC check code does not exist in the FIFO memory, an error is reported; when the ECC check code exists in the FIFO memory, determine whether the M.ECC check code is consistent with the S.ECC check code, and report an error when they are inconsistent; when they are consistent, output a "transmission correct" signal.

[0075] The reasons why the M.ECC check module reports an error to the controller when executing this step are as follows: 1. The slave ID is incorrect. 2. The corresponding FIFO memory cannot be found. 3. The M.ECC check code does not exist in the FIFO memory. The root cause of the error is that the address decoder selects the wrong slave S in step S4'.

[0076] Specifically, take the client sending a signal from the host M1 to the slave S1 as an example. If the address decoder makes an error during the compilation process or is interfered by an external signal, resulting in the selection of the slave S2 or other slave Sn when the slave S1 should have been selected, then in the above step S4', the bus information will be transmitted to the S2.ECC generation module or the Sn.ECC generation module. Then, in step S5', the S2.ECC check code, the address of the slave S2 (ie, S2.ID) and the transaction address of the slave S2 (ie, S2.Transaction ID) are generated. In step S6', the S2.ECC check code is sent to the M2.ECC check module, or the Sn.ECC check code is sent to the Mn.ECC check code. When executing step S7', the M1.ECC check code will be retrieved from the FIFO memory corresponding to S2.ID and S2.transaction ID in the M1.ECC check module. At this time, it will be found that the slave ID (i.e. S2.ID) or the slave transaction ID (i.e. S2.transaction ID) does not exist, or the FIFO memory corresponding to the slave ID and the slave transaction ID cannot be found, or the ECC check code does not exist in the FIFO memory. Therefore, when the address decoder selects the wrong slave, a bus data detection module and detection method disclosed in the present invention will detect it, and the M1.ECC check module will report an error to the MCU controller.

[0077] In addition, the reason why the M.ECC check module reports an error to the controller when executing this step may also be because the M.ECC check code is determined to be inconsistent with the S.ECC check code. The fundamental reason for the inconsistency between the M.ECC check code and the S.ECC check code is that the bus information generates erroneous bus data during the transmission process, causing the S.ECC generation module to generate an erroneous S.ECC check code.

[0078] Specifically, take the client sending a read signal from the host M1 to the slave S1 as an example. If the address decoder is disturbed by external interference during the compilation process of step S4 and an error occurs, resulting in an error or omission of the bus data in the bus information, then an erroneous S1.ECC check code will be generated in step S5. When the S1.ECC check code is compared with the M1.ECC check code in step S7, there may be inconsistency, and then an error is reported.

[0079] In addition, if after the above error is generated, it is found through investigation that the address decoder is correct during the compilation process, it means that the host address M.ID address obtained when executing step S5' is wrong.

[0080] S8', feeding back the signal generated in step S7 to the S.ECC generation module.

[0081] S9', the S.ECC generation module obtains the bus data to be read in the corresponding slave, the bus data is the information in the bus information except the ECC check code, data ECC check code, ID and transaction ID, that is, the information only contains the bus data to be transmitted and read. Further, the bus data belongs to the bus information, so it can be directly obtained by extracting from the bus information in the corresponding slave.

[0082] On the one hand, the S.Data ECC check code of the bus data is calculated by using an ECC algorithm, and the S.Data ECC check code is transmitted together with the slave ID and the slave transaction ID to the M.ECC check module corresponding to the host address M.ID. Then the M.ECC check module selects the corresponding FIFO memory according to the slave ID and the slave transaction ID, and stores the S.Data ECC check code in the FIFO memory. The S.Data ECC check code is a check code generated according to the bus data in the slave S; and the S.Data ECC check code includes the slave data ECC check code.

[0083] Furthermore, in this process, the S.data ECC check code, the slave ID and the slave transaction ID need to determine the address of the host that currently initiates the access request based on the host address M.ID before reaching the M.ECC check module, and send the S.data ECC check code, the slave ID and the slave transaction ID to the corresponding M.ECC check module based on the host address M.ID.

[0084] If the address decoder makes an error during the compilation process, an erroneous S. data ECC check code will be generated in this step; and when continuing to execute step S10', it will be determined that the M. data ECC check code is inconsistent with the S. data ECC check code, and an error will be reported.

[0085] On the other hand, the bus data is transmitted to the M.ECC generation module after passing through the address decoder, and the M.ECC generation module generates an M.Data ECC check code according to the bus data. The M.Data ECC check code is a check code generated according to the data information in the host M; the M.Data ECC check code includes a bus data ECC check code.

[0086] S10', the M.ECC generation module transmits the target slave ID, the M.Data ECC check code and the acquired host transaction ID to the M.ECC check module corresponding to the host address M.ID. Select the corresponding FIFO memory according to the target slave ID and the host transaction ID, and retrieve the S.Data ECC check code stored therein; when the S.Data ECC check code does not exist in the FIFO memory, an error is reported; if the S.Data ECC check code exists in the FIFO memory, determine whether the M.Data ECC check code is consistent with the S.Data ECC check code, and report an error if they are inconsistent; if they are consistent, output a "transmission correct" signal.

[0087] The reason why the M.ECC check module reports an error to the controller when executing this step is that the S.data ECC check code does not exist in the FIFO memory corresponding to the target slave ID and the host transaction ID. The fundamental reason for the error is that the address decoder selects the wrong slave S.

[0088] Specifically, take the client sending a signal from the host M1 to the slave S1 as an example. If the address decoder makes an error during the compilation process or is interfered by an external signal, resulting in the selection of slave S2 or other slave Sn when the slave S1 should have been selected, the bus data obtained in the above step S9' will be transmitted to the S2.ECC generation module or the Sn.ECC generation module. When executing step S10', the S1.data ECC check code will be retrieved from the FIFO memory corresponding to S2.ID and S2.transaction ID in the M1.ECC check module. At this time, it will be found that the slave ID (ie S2.ID) or the slave transaction ID (ie S2.transaction ID) does not exist, or the FIFO memory corresponding to the slave ID and the slave transaction ID cannot be found, or the ECC check code does not exist in the FIFO memory. Therefore, when the address decoder selects the wrong slave, a bus data detection module and a detection method disclosed in the present invention will detect it, and the M1.ECC check module will report an error to the MCU controller.

[0089] When executing this step, if it is determined that the M. data ECC check code is inconsistent with the S. data ECC check code, the fundamental reason for the inconsistency between the M. data ECC check code and the S. data ECC check code is that the bus information in step S4' generates erroneous bus data during the transmission process, which causes the S. ECC generation module in step S9' to generate an erroneous S. data ECC check code.

[0090] Specifically, take the client sending a read signal from the host M1 to the slave S1 as an example. If the address decoder is disturbed by external interference during the compilation process of step S4 and an error occurs, resulting in an error or omission of the bus data in the bus information, then an erroneous S1.ECC check code will be generated in step S5. When the S1.ECC check code is compared with the M1.ECC check code in step S7, there may be inconsistency, and then an error is reported.

[0091] S11' feeds back the signal generated in step S10' to the M.ECC generation module; and feeds back the bus data to the host M, which is finally read out by the client. Before the bus data is fed back to the host M, the transmission sequence processing module first determines whether the host transaction IDs corresponding to two or more of the bus information are consistent. When the host transaction IDs corresponding to two or more of the bus information are the same, the transmission sequence processing module controls the order in which the slave S returns data to be consistent with the order in which the access request is issued. When the host transaction IDs corresponding to two or more of the bus information are not the same, the transmission sequence processing module controls the order in which the slave S returns data to be arbitrary.

[0092] When the host M sends an access request to the slave S, it determines whether to perform write mode processing or read mode processing according to the bus control signal in the bus information. At the same time, the host M will generate the host transaction ID and the slave transaction ID.

[0093] Take the bus control signal as a read mode processing as an example: if the same slave S receives read signal requests from multiple hosts M in succession, and the transmission sequence processing module determines that the host transaction IDs issued by each host M are different, then the transmission sequence processing module controls the order of data returned from the slave S to be different from the order of the host transaction IDs received. That is, when slave S1 receives read data requests from hosts M1, M2, and M3 simultaneously or successively, the host transaction ID of host M1 is 0, the corresponding bus information is X, bus data x, the host transaction ID of host M2 is 1, the corresponding bus information is Y, bus data y, the host transaction ID of host M3 is 2, the corresponding bus information is Z, bus data z. Since the transmission sequence processing module determines that the host transaction ID corresponding to each bus information is different, and the response speed of the slave S1 to the bus data y is faster than that to the bus data x, the transmission sequence processing module controls the slave S1 to return data in the order of bus data y, bus data x, and bus data z, or to return data in the order of bus data y, bus data z, bus data x or other orders.

[0094] If the same slave S receives read signal requests from multiple hosts M in succession, and the transmission sequence processing module determines that the host transaction IDs issued by some of the hosts M are the same, then the transmission sequence processing module controls the order of data returned from the slave S to be different from the order of the host transaction IDs received. That is, when slave S1 receives read data requests from hosts M1, M2, and M3 simultaneously or continuously, the host transaction ID of host M1 is 0, and the corresponding bus information is X, bus data x, the host transaction ID of host M2 is 1, and the corresponding bus information is Y, bus data y, and the host transaction ID of host M3 is 0, and the corresponding bus information is Z, bus data z. At this time, the out-of-order transmission processing module determines that some of the host transaction IDs are the same, and classifies and distinguishes them according to the host transaction ID, and divides them into two types of host transaction IDs. The out-of-order transmission processing module controls the slave S1 to write in the order of bus data y, bus data x, bus data z, or bus data x, bus data y, bus data z, or bus data x, bus data z, bus data y. The bus data x and bus data z must return data in the order in which they are input.

[0095] If the same slave S receives read signal requests from multiple hosts M in succession, and the transmission sequence processing module determines that the host transaction IDs issued by each host M are the same, then the transmission sequence processing module controls the order of data returned from the slave S to be exactly the same as the order of the host transaction IDs received. That is, when slave S1 receives access requests from hosts M1, M2, and M3 simultaneously or continuously, the host transaction ID of host M1 is 0, and the corresponding bus information is X, bus data x, the host transaction ID of host M2 is 0, and the corresponding bus information is Y, bus data y, and the host transaction ID of host M3 is 0, and the corresponding bus information is Z, bus data z. Because the transmission sequence processing module determines that all the host transaction IDs are the same, at this time the transmission sequence processing module controls the slave S1 to only write in the order in which it is received, and the order of reading data is bus data x, bus data y, and bus data z.

[0096] In addition, the same host M may also continuously send multiple read signal requests to the same slave S. That is, the same host M continuously sends multiple bus information read data requests to one of the slaves S to perform read mode processing; at the same time, the host transaction ID and slave transaction ID corresponding to each bus information are sent to the corresponding slave S. The transmission sequence processing module controls the slave S to feed back the bus data to the host M in order or in disorder according to whether the host transaction ID or the slave transaction ID is consistent.

[0097] like Figure 6 As shown, taking the client sending a read signal from the host M1 to the slave S1 as an example, in the above specific steps, all the host M refers to the host M1, the M.ECC generation module refers to the M1.ECC generation module, the M.ECC check module refers to the M1.ECC check module, the M.ECC check code refers to the M1.ECC check code, and the M.data ECC check code refers to the M1.data ECC check code. All the slaves S refer to the slave S1, the S.ECC generation module refers to the S1.ECC generation module, the S.ECC check module refers to the S1.ECC check module, the S.ECC check code refers to the S1.ECC check code, and the S.data ECC check code refers to the S1.data ECC check code.

[0098] Similarly, if the client sends a signal from the host M1 to the slave S2 for example, then all the hosts M in the above specific steps refer to the host M1, M.ECC generation module refers to M1.ECC generation module, M.ECC check module refers to M1.ECC check module, M.ECC check code refers to M1.ECC check code, and M.data ECC check code refers to M1.data ECC check code. All the slaves S refer to slave S2, S.ECC generation module refers to S2.ECC generation module, S.ECC check module refers to S2.ECC check module, S.ECC check code refers to S2.ECC check code, and S.data ECC check code refers to S2.data ECC check code.

[0099] By analogy, if the client sends a signal from the host M2 to the slave S1 for example, then all the hosts M in the above specific steps refer to the host M2, the M.ECC generation module refers to the M2.ECC generation module, the M.ECC verification module refers to the M2.ECC verification module, the M.ECC verification code refers to the M2.ECC verification code, and the M.data ECC verification code refers to the M2.data ECC verification code. All the slaves S refer to slave 1, the S.ECC generation module refers to the S1.ECC generation module, the S.ECC verification module refers to the S1.ECC verification module, the S.ECC verification code refers to the S1.ECC verification code, and the S.data ECC verification code refers to the S1.data ECC verification code. Other embodiments can be inferred from the above embodiments, which will not be repeated here.

[0100] In summary, the number of the M.ECC generation modules and the M.ECC check modules in the present invention is determined by the number of the hosts M. The number of the S.ECC generation modules and the S.ECC check modules is determined by the number of the slaves S.

[0101] There are many implementation methods of the present invention, and all technical solutions formed by equivalent transformation or equivalent transformation fall within the protection scope of the present invention.

Claims

1. A bus data detection module, used for detecting bus data transmitted between a host M and a slave S, wherein the host M generates bus information and corresponding host transaction ID and slave transaction ID when sending an access request to the slave S; the bus information includes a bus address, a bus control signal and bus data; and characterized in that: The bus data detection module includes an address decoder, an M.ECC generation module, an M.ECC check module and an S.ECC generation module; The M.ECC generation module obtains the host transaction ID, and generates a target slave ID and an M.ECC check code according to the bus information; The S.ECC generation module obtains the slave transaction ID, and obtains the host address M.ID of the host currently initiating the access and the slave ID currently to be accessed according to the bus information compiled by the address decoder, and calculates the S.ECC check code of the corresponding slave using the ECC algorithm; The M.ECC check module is provided with a FIFO memory, and by comparing the target slave ID and the slave ID, as well as the M.ECC check code and the S.ECC check code, a comprehensive detection of data transmission and slave selection in bus information transmission is achieved, thereby blocking the transmission of erroneous data.

2. The bus data detection module according to claim 1, characterized in that: It also includes a transmission sequence processing module, which determines whether the host transaction IDs corresponding to two or more of the bus information are consistent; when the host transaction IDs corresponding to two or more of the bus information are the same, the transmission sequence processing module controls the order in which the slave S writes or returns data to be consistent with the order in which the access requests are issued; when the host transaction IDs corresponding to two or more of the bus information are not the same, the transmission sequence processing module controls the order in which the slave S writes or returns data to be arbitrary.

3. The detection method of the bus data detection module according to claim 1, characterized in that: When in bus data write mode, the specific steps include: S1, receiving an access request from a client to write bus data from a host M to a slave S, the host M generates a host transaction ID, a slave transaction ID and corresponding bus information; and transmitting the host transaction ID and the bus information to the M.ECC generation module corresponding to the host M; the bus information includes a bus address, a bus control signal and bus data; S2, the M.ECC generation module transmits the bus information to the address decoder, and generates the M.ECC check code of the corresponding host and the target slave ID according to the bus information; S3, the M.ECC generation module transmits the M.ECC check code, the target slave ID and the host transaction ID to the M.ECC check module corresponding to the host M; Select a corresponding FIFO memory according to the target slave ID and the host transaction ID, and store the M.ECC check code in the FIFO memory; S4, the address decoder compiles the bus information and transmits the compiled bus information to the S.ECC generation module of the corresponding slave; S5, the S.ECC generation module obtains the slave transaction ID, and obtains the host address M.ID of the host currently initiating the access and the slave ID currently to be accessed according to the compiled bus information, and simultaneously uses the ECC algorithm to calculate the S.ECC check code of the corresponding slave; S6, the S.ECC generation module transmits the slave ID, the S.ECC check code and the slave transaction ID to the M.ECC check module corresponding to the host address M.ID; S7, selecting a corresponding FIFO memory according to the slave ID and the slave transaction ID, first determining whether the slave ID and the target slave ID are consistent, reporting an error when they are inconsistent, and retrieving the M.ECC check code stored therein when they are consistent; When the M.ECC check code does not exist in the FIFO memory, an error is reported; when the M.ECC check code exists in the FIFO memory, it is judged whether the M.ECC check code is consistent with the S.ECC check code, and an error is reported when they are inconsistent; when they are consistent, a "transmission correct" signal is output; S8, feeding back the signal generated in step S7 to the S.ECC generation module; S9, writing the compiled bus data in the bus information into the corresponding slave S.

4. The detection method of the bus data detection module according to claim 3, characterized in that: In the step S2, the M.ECC check code includes a bus address check code, a bus control signal check code and a bus data ECC check code.

5. The detection method of the bus data detection module according to claim 3, characterized in that: In the step S4, after the bus information is compiled by the address decoder, the address decoder first selects a slave S and then transmits the compiled bus information to the S.ECC generation module of the corresponding slave S.

6. The detection method of the bus data detection module according to claim 3, characterized in that: In the step S5, the S.ECC check code includes a slave address check code, a slave control signal check code and a slave data ECC check code.

7. The detection method of the bus data detection module according to claim 3, characterized in that: In step S6, the S.ECC check code, the slave ID and the slave transaction ID need to determine the address of the host that currently initiates the access request according to the host address M.ID before reaching the M.ECC check module, and send the S.ECC check code, the slave ID and the slave transaction ID to the M.ECC check module of the corresponding host according to the host address M.ID.

8. The detection method of the bus data detection module according to claim 7, characterized in that: If it is determined based on the host address M.ID that the access request is not initiated by the designated host M, the S.ECC check code will be sent to the M'.ECC check module corresponding to other hosts except the designated M.ECC check module; when the process continues to step S7, it will be determined that the M.ECC check code does not exist in the FIFO memory, and an error will be reported.

9. The detection method of the bus data detection module according to claim 1, characterized in that: When in bus data reading mode, the specific steps include: S1', receiving an access request from a client to read bus data from a host M to a slave S, the host M generates a host transaction ID, a slave transaction ID and corresponding bus information; and transmitting the host transaction ID and the bus information to the M.ECC generation module corresponding to the host M; the bus information includes a bus address and a bus control signal; S2', the M.ECC generation module transmits the bus information to the address decoder, and generates the M.ECC check code of the corresponding host and the target slave ID according to the bus information; S3', the M.ECC generation module transmits the M.ECC check code, the target slave ID and the host transaction ID to the M.ECC check module of the host, selects a corresponding FIFO memory according to the target slave ID and the host transaction ID, and stores the M.ECC check code in the FIFO memory; S4', the address decoder compiles the bus address and transmits the compiled bus information to the S.ECC generation module of the corresponding slave; S5', the S.ECC generation module obtains the slave transaction ID, and obtains the host address M.ID of the host currently initiating the access and the slave ID currently to be accessed according to the compiled bus information, and simultaneously calculates the S.ECC check code of the corresponding slave using the ECC algorithm; S6', the S.ECC generation module transmits the slave ID, the S.ECC check code and the slave transaction ID to the M.ECC check module corresponding to the host address M.ID; S7', selecting a corresponding FIFO memory according to the slave ID and the slave transaction ID, first determining whether the slave ID is consistent with the target slave ID, reporting an error if they are inconsistent, and retrieving the M.ECC check code stored therein if they are consistent; When the M.ECC check code does not exist in the FIFO memory, an error is reported; when the M.ECC check code exists in the FIFO memory, it is judged whether the M.ECC check code is consistent with the S.ECC check code, and an error is reported when they are inconsistent; when they are consistent, a "transmission correct" signal is output; S8', feeding back the signal generated in step S7 to the S.ECC generation module; S9', the S.ECC generation module obtains the bus data to be read from the corresponding slave, and on the one hand, uses the ECC algorithm to calculate the S.Data ECC check code of the bus data, and transmits the S.Data ECC check code together with the slave ID and the slave transaction ID to the M.ECC check module corresponding to the host address M.ID; the M.ECC check module selects the corresponding FIFO memory according to the slave ID and the slave transaction ID, and stores the S.Data ECC check code in the FIFO memory; On the other hand, the bus data is transmitted to the M.ECC generation module after passing through the address decoder, and the M.ECC generation module generates an M.Data ECC check code according to the bus data; S10', the M.ECC generation module transmits the target slave ID, the M.data ECC check code and the acquired host transaction ID to the M.ECC check module corresponding to the host address M.ID; selects the corresponding FIFO memory according to the target slave ID and the host transaction ID, and retrieves the S.data ECC check code stored therein; When the S. data ECC check code does not exist in the FIFO memory corresponding to the target slave ID and the host transaction ID, an error is reported; If the S. data ECC check code exists in the FIFO memory, determine whether the M. data ECC check code is consistent with the S. data ECC check code, and report an error if they are inconsistent; if they are consistent, output a "transmission correct" signal; S11' feeds back the signal generated in step S10' to the M.ECC generation module; and feeds back the bus data in the bus information to the host M, which is finally read out by the client.

10. The detection method of the bus data detection module according to claim 9, characterized in that: In the step S2', the M.ECC check code includes a bus address check code and a bus control signal check code.

11. The detection method of the bus data detection module according to claim 9, characterized in that: In the step S4 ′, after the bus information is compiled by the address decoder, the address decoder selects a slave S and transmits the compiled bus information to the S.ECC generation module of the corresponding slave S.

12. The detection method of the bus data detection module according to claim 9, characterized in that: In the step S5', the S.ECC check code includes a slave address check code and a slave control signal check code.

13. The detection method of the bus data detection module according to claim 9, characterized in that: In the step S6', the S.ECC check code, the slave ID and the slave transaction ID need to determine the address of the host that currently initiates the access request according to the host address M.ID before reaching the M.ECC check module, and send the S.ECC check code, the slave ID and the slave transaction ID to the M.ECC check module of the corresponding host according to the host address M.ID.

14. The detection method of the bus data detection module according to claim 13, characterized in that: If it is determined according to the host address M.ID that the access request is not initiated by the designated host M, the S.ECC check code will be sent to the M'.ECC check modules corresponding to other hosts except the designated M.ECC check module; At this time, when the process continues to execute step S7', it will be determined that there is no ECC check code in the FIFO memory, and an error will be reported.

15. The detection method of the bus data detection module according to claim 9, characterized in that: The S. data ECC check code in step S9' includes the slave data ECC check code; the M. data ECC check code in step S9' includes the bus data ECC check code.

16. The detection method of the bus data detection module according to claim 9, characterized in that: In step S9', the S.data ECC check code, the slave ID and the slave transaction ID need to determine the address of the host that currently initiates the access request according to the host address M.ID before reaching the M.ECC check module, and send the S.data ECC check code, the slave ID and the slave transaction ID to the M.ECC check module of the corresponding host according to the host address M.ID.

17. A detection method for a bus data detection module according to claim 16, characterized in that: If the address decoder makes an error during the compilation process, an erroneous S. data ECC check code will be generated in step S9'; and when continuing to step S10', it will be determined that the M. data ECC check code is inconsistent with the S. data ECC check code, and an error will be reported.

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