Prototype verification method, device and equipment for pipeline-level instruction and medium

Abstract

The invention discloses a prototype verification method and device for a pipeline-level instruction, equipment and a medium, and aims to solve the technical problem that an existing verification means lacks consideration on data relevance. The method comprises the following steps: classifying instruction sets of a processor, generating test cases to verify the execution process of the instructions in the pipeline, and executing the generated test cases on a hardware platform to verify the actual execution condition of the instruction pipeline. According to the method, the data correlation and the control correlation between the instructions can be comprehensively considered, the problems of data conflicts and control conflicts in the instruction pipeline design are effectively found and solved, and the coverage rate and the accuracy of verification are improved. The invention further provides a prototype verification device and equipment for the pipeline-level instruction and a computer readable storage medium so as to realize practical application of the method.

Description

Technical Field

[0001] The present invention relates to the field of digital integrated circuit verification, and in particular to a prototype verification method, device, equipment and medium for pipeline-level instructions. Background Art

[0002] In modern computer systems, the performance and efficiency of processors are one of the most important factors. With the rapid development of fields such as artificial intelligence, high-performance computing, and embedded systems, higher requirements are placed on the computing power and response speed of processors. As a key means to improve the efficiency of instruction execution, processor instruction pipeline technology has become a core component of modern processor architecture design. However, in the design and implementation of the instruction pipeline, how to ensure its correctness and efficiency is an urgent problem to be solved. Especially in the research and development of SoC chips, the verification of the instruction pipeline is particularly important, because the highly integrated characteristics of SoC chips make the performance and reliability of the instruction pipeline directly affect the function and efficiency of the entire chip. Once there is a design defect in the instruction pipeline, it may lead to performance bottlenecks or functional failures of the entire SoC chip, thereby increasing R&D costs and extending product time to market.

[0003] At present, the verification of processor instruction pipelines mainly relies on simulation and testing methods. Common methods include simulation on RTL (Register Transfer Level) circuits and verification of instruction execution results through processor reference models. However, these methods have some limitations in practical applications. Existing verification methods often only focus on the functional verification of a single instruction, but lack comprehensive consideration of the overall execution process of the instruction pipeline and the correlation between instructions, such as data correlation and control correlation. In addition, existing verification methods are also insufficient in test coverage and efficiency, making it difficult to fully verify the performance and reliability of the instruction pipeline within a limited time. For complex multi-stage pipeline structures, existing methods also have certain limitations in dealing with data conflicts and control conflicts, and cannot effectively discover and resolve potential design defects.

[0004] Therefore, a new verification method is urgently needed to solve the above problems, so as to improve the accuracy and efficiency of instruction pipeline verification and ensure the reliability and high performance of the processor in various complex application scenarios. Summary of the invention

[0005] The purpose of the present invention is to provide a prototype verification method, device, equipment and medium for pipeline-level instructions to overcome the shortcomings of existing verification means that lack consideration of data relevance.

[0006] In order to achieve the above object, the present invention adopts the following technical solution: A prototype verification method for pipeline-level instructions, comprising: Classify the instruction sets of processors; Generate test cases based on instruction classification to verify the execution process of instructions in the pipeline; Execute the generated test cases on the hardware platform to verify the actual execution of the instruction pipeline.

[0007] The instruction set of the processor is classified into: Establishing standards for processor instruction classification; Analyze the function of each instruction in the processor instruction set and determine its functional category; According to the functional category analysis results of the processor instructions, the processor instructions are classified according to the classification standards.

[0008] Establish processor instruction classification standards, including: According to the instruction relevance, instructions are divided into four categories: storage instructions, operation instructions, control jump instructions, and special instructions.

[0009] Generate test cases based on instruction classification to verify the execution process of instructions in the pipeline, including: Generate a sequence including a plurality of data-dependent instructions and a sequence including a plurality of control-dependent instructions according to data dependencies and control dependencies between the instructions; Through the sequence of data-related instructions, verify whether there is data conflict during instruction execution; By controlling the sequence of related instructions, verify whether there is a control conflict during the execution of instructions.

[0010] The hardware platform includes FPGA or other programmable logic devices, which are used to simulate the instruction pipeline execution environment of the processor.

[0011] It also includes analyzing the execution result data and comparing the actual execution results with the expected results to determine the correctness and performance indicators of the instruction pipeline.

[0012] Suitable for verifying the instruction pipeline of processors based on the RISC-V instruction set architecture, or suitable for processor design.

[0013] A prototype verification device for pipeline-level instructions, comprising: A classification module, used for classifying the instruction set of the processor; The test case generation module is used to generate test cases according to instruction classification and verify the execution process and relevance of instructions in the pipeline; The execution module is used to execute the generated test cases on the hardware platform to verify the actual execution of the instruction pipeline.

[0014] A device comprising a processor and a memory: The memory is used to store the program code and transmit the program code to the processor; A prototype verification method for a processor to execute pipeline-level instructions according to instructions in program code.

[0015] A computer-readable storage medium is used to store program codes, and the program codes are used to execute a prototype verification method of pipeline-level instructions.

[0016] Compared with the prior art, the present invention has the following beneficial technical effects: The present invention can effectively discover data conflicts and control conflicts in instruction pipeline design by implementing a prototype of the instruction pipeline on a hardware platform and performing detailed testing and verification on it. Compared with traditional simulation and testing methods, this method can more comprehensively cover various execution situations and potential problems of the instruction pipeline, thereby improving the coverage and accuracy of verification and ensuring the correctness and efficiency of the instruction pipeline. The present invention is not only suitable for verifying the instruction pipeline of a processor based on the RISC-V instruction set architecture, but also can be applied to other processor designs. By establishing corresponding classification standards and test case generation strategies according to the characteristics of the processor instruction set, the method has good versatility and adaptability, can meet the verification requirements of different processor instruction set architectures, and provides an effective solution for processor design and verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The figure is a flow chart of a prototype verification method of a pipeline-level instruction in an embodiment of the present invention.

[0018] Figure 2 A schematic diagram of test case generation for a prototype verification method of a pipeline-level instruction in an embodiment of the present invention.

[0019] Figure 3 The diagram is a schematic diagram of instruction classification for a prototype verification method of pipeline-level instructions in an embodiment of the present invention.

[0020] Figure 4 The present invention is a schematic diagram of implementing storage class correlation in a prototype verification method of a pipeline-level instruction in an embodiment of the present invention.

[0021] Figure 5 The present invention is a schematic diagram of implementing storage and operation correlation of a prototype verification method of a pipeline instruction in an embodiment of the present invention.

[0022] Figure 6 The figure is a schematic diagram of implementing the computational correlation of a prototype verification method for pipeline-level instructions in an embodiment of the present invention.

[0023] Figure 7The present invention is a schematic diagram of implementing storage and jump correlation of a prototype verification method of a pipeline-level instruction in an embodiment of the present invention.

[0024] Figure 8 The present invention is a schematic diagram of a prototype verification method for pipeline-level instructions and implementation of jump correlation.

[0025] Fig. 9 Schematic diagram of a prototype verification device for pipeline-level instructions in an embodiment of the present invention.

[0026] Fig.10 A schematic diagram of a prototype verification device for pipeline-level instructions in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In modern computer systems, the performance and efficiency of processors are one of the most important factors. With the rapid development of fields such as artificial intelligence, high-performance computing, and embedded systems, higher requirements are placed on the computing power and response speed of processors. As a key means to improve the efficiency of instruction execution, processor instruction pipeline technology has become a core component of modern processor architecture design. However, in the design and implementation of the instruction pipeline, how to ensure its correctness and efficiency is an urgent problem to be solved. Especially in the research and development of SoC chips, the verification of the instruction pipeline is particularly important, because the highly integrated characteristics of SoC chips make the performance and reliability of the instruction pipeline directly affect the function and efficiency of the entire chip. Once there is a design defect in the instruction pipeline, it may lead to performance bottlenecks or functional failures of the entire SoC chip, thereby increasing R&D costs and extending product time to market.

[0028] At present, the verification of processor instruction pipelines mainly relies on simulation and testing methods. Common methods include simulation on RTL (Register Transfer Level) circuits and verification of instruction execution results through processor reference models. However, these methods have some limitations in practical applications. Existing verification methods often only focus on the functional verification of a single instruction, but lack comprehensive consideration of the overall execution process of the instruction pipeline and the correlation between instructions (such as data correlation, control correlation, etc.). In addition, existing verification methods are also insufficient in test coverage and efficiency, making it difficult to fully verify the performance and reliability of the instruction pipeline within a limited time. For complex multi-stage pipeline structures, existing methods also have certain limitations in dealing with data conflicts and control conflicts, and cannot effectively discover and resolve potential design defects.

[0029] Therefore, a new verification method is urgently needed to solve the above problems, so as to improve the accuracy and efficiency of instruction pipeline verification and ensure the reliability and high performance of the processor in various complex application scenarios. The present application proposes a prototype verification method, device, equipment and medium for pipeline-level instructions. The scheme divides the processor instruction set into categories such as storage instructions, operation instructions, control jump instructions and special instructions to generate instruction stream test cases with different relevance. By implementing the prototype of the instruction pipeline on the hardware platform and conducting detailed testing and verification on it, data conflicts and control conflicts in the instruction pipeline design can be effectively discovered, and the coverage and accuracy of verification can be improved. In addition, the scheme can also conduct in-depth analysis of the overall execution process of the instruction pipeline to ensure its performance and reliability in different application scenarios.

[0030] It should be understood that the content verification method provided in the embodiment of the present application can be applicable to the instruction set architecture design verification of processors in various digital circuits, the design verification process of SoC chips, and the research and development of computer processors.

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] Processor instruction pipelining is a technology used to improve the efficiency of instruction execution in computer systems. An N-stage pipeline processor breaks down the instruction execution process into N independent stages, allowing the processor to process N instructions at the same time, thereby improving the overall processing speed of the processor. However, during the execution of the instruction flow, there will be data conflicts and control conflicts, which will affect the execution of the instruction pipeline and may also affect the execution results of the instruction flow.

[0033] In order to facilitate understanding of the technical solution provided by the embodiment of the present invention, the prototype verification method provided by the present application is introduced below with reference to the accompanying drawings.

[0034] Reference Figure 1 As shown, Figure 1 A prototype verification method for a pipeline-level instruction provided in an embodiment of the present invention includes: S101, classify the instruction set of the processor.

[0035] Specifically, S101 includes: Establishing standards for processor instruction classification; Analyze the function of each instruction in the processor instruction set and determine its functional category; According to the functional category analysis results of the processor instructions, the processor instructions are classified according to the classification standards.

[0036] Establish classification standards for the target processor's instruction set, and classify instructions into four categories based on instruction relevance: storage instructions, operation instructions, control jump instructions, and special instructions. Perform a detailed analysis of each instruction in the processor's instruction set to determine its main functions and operations. This includes the instruction's opcode, operands, and how they affect the processor's state and control flow. Based on the results of the instruction's functional analysis, determine the functional category of each instruction. Compare each instruction with the classification standards based on its functional category and classify it. This process may involve reorganizing and classifying instructions to ensure that they can be effectively used in subsequent test case generation.

[0037] S102, generating test cases according to instruction classification to verify the execution process of the instructions in the pipeline.

[0038] Specifically, S102 includes: Generate a sequence including a plurality of data-dependent instructions and a sequence including a plurality of control-dependent instructions according to data dependencies and control dependencies between the instructions; Through the sequence of data-related instructions, verify whether there is data conflict during instruction execution; By controlling the sequence of related instructions, verify whether there is a control conflict during the execution of instructions.

[0039] Among them, the sequence of data-related instructions includes: Storage class dependency verification verifies whether data dependency affects the execution result of the instruction pipeline by generating a storage class dependency instruction sequence, such as executing a storage instruction (such as SW) to write data to a memory address, followed by one or two instructions (such as LW) to read data from the same address. If the subsequent read instruction can correctly obtain the expected data, it means that the data conflict has been properly handled.

[0040] Storage and operation correlation verification generates a sequence of storage and operation related instructions, which can be divided into two cases. One is that the execution result of the previous storage instruction is the input of the subsequent operation instruction, such as executing SW to write data into the memory first, then executing LW to read the data, and then performing operations such as ADD to verify whether the storage result can be correctly used as the operation input. The other is that the operation result of the operation instruction is the input of the subsequent storage instruction, such as executing operations such as ADD first, and then storing the result in the memory to verify whether the operation result can be correctly used by the storage instruction.

[0041] Operation dependency verification generates an execution sequence of operation combination instructions. The input for the execution of subsequent operation instructions requires the operation results of the previous instructions. For example, first execute operations such as SUB, and then use the results for subsequent operations such as ADD, to verify whether the operation dependency affects the execution results of the instruction pipeline.

[0042] Among them, the sequence of control-related instructions includes: Storage and jump correlation verification generates a storage and jump related instruction sequence. The condition for the instruction to jump is affected by the execution result of the previous storage instruction. For example, first execute storage instructions such as LW, and then decide whether to execute jump instructions such as JALR based on the storage result. Verify whether the storage instruction result can correctly affect the jump condition.

[0043] Verify the correlation between operations and jumps, generate operation and jump related instruction sequences, the conditions for the instruction to jump are affected by the execution results of the operation instructions, such as executing operations such as ADD first, and then deciding whether to execute jump instructions such as JALR based on the operation results, to verify whether the operation results can correctly affect the jump conditions.

[0044] S103, executing the generated test case on the hardware platform to verify the actual execution status of the instruction pipeline.

[0045] Specifically, select a suitable hardware platform, such as an FPGA, to simulate the processor's instruction pipeline. Consider the platform's performance, programmability, and cost-effectiveness. Configure the hardware platform to simulate the behavior of the target processor. This includes programming the FPGA to implement the logic of the instruction set, and setting up the necessary interfaces and control logic. Deploy the generated test cases to the hardware platform. This may involve compiling the test cases into a format executable by the hardware platform, and setting up the test environment. Execute the test cases on the hardware platform, and use a logic analyzer or other monitoring tools to observe and record the execution process of the instructions. Collect data to evaluate the performance and correctness of the instruction pipeline. Analyze the test results and compare the actual execution results with the expected results.

[0046] The following introduces the prototype verification method of the pipeline-level instructions provided in the embodiment of the present application in combination with actual application scenarios.

[0047] A certain MCU processor is used as the target processor, in which the instructions are designed using the RISC_V instruction set architecture and support three-level instruction pipeline. Figure 2 As shown, after obtaining the instruction, according to the execution result of a single instruction and the instruction stream level N, various instruction combinations are arranged to generate instruction stream test cases based on the correlation of instruction execution. Among them, special class instructions have no correlation with other instructions, so they are not considered. The relevant verification points are as follows: Storage class correlation, the execution of storage class instructions mainly has data dependency, that is, instruction A writes certain data to a memory address, and instruction B needs to read the value of the same address, and instruction B depends on the completion of instruction A. Based on this guiding idea, an N-level storage class-related instruction execution sequence is generated to verify whether the storage instruction correlation affects the result of instruction pipeline execution.

[0048] Storage and operation correlation involves two situations of instruction sequences: one is that the execution result of the previous storage instruction is the input of the subsequent operation instruction execution; the other is that the operation result of the operation instruction is the input of the subsequent storage instruction. Based on this guiding idea, an N-level storage and operation correlation instruction execution sequence is generated to verify whether the instruction storage and operation correlation has an impact on the result of the instruction pipeline execution.

[0049] Operation correlation mainly refers to the execution sequence of operation combination instructions. The input of the subsequent operation instruction execution requires the operation result of the previous instruction. Based on the correlation between operation instructions, an N-level operation-related instruction execution sequence is generated to verify whether the operation correlation of the instruction has an impact on the result of the instruction pipeline execution.

[0050] Storage and jump correlation, the condition for an instruction to jump is affected by the execution result of the previous storage instruction. Based on this guiding principle, an N-level storage and jump instruction-related instruction execution sequence is generated to verify whether the instruction storage and jump correlation affects the result of the instruction pipeline execution.

[0051] Operation and jump correlation, the conditions for instruction jump are affected by the execution results of the operation instructions. According to this guiding principle, an N-level operation and jump instruction-related instruction execution sequence is generated to verify whether the instruction operation and jump correlation affects the results of the instruction pipeline execution.

[0052] Reference Figure 2 As shown, the instructions of the target processor are classified, wherein the storage class instructions include: LW (Load Word): Load a word (usually 32 or 64 bits) from memory into a register.

[0053] SW (Store Word): Store a word from a register to memory.

[0054] LB (Load Byte): Load a byte from memory into a register.

[0055] SB (Store Byte): Store a byte in a register to memory.

[0056] LH (Load Halfword): Load a half word (usually 16 bits) from memory into a register.

[0057] SH (Store Halfword): Stores a halfword in a register to memory.

[0058] Operation instructions include: ADD (Add): Adds the values ​​of two registers and stores the result in a third register.

[0059] SUB (Subtract): Subtracts the value of one register from the value of another register and stores the result in the first register.

[0060] AND (Bitwise AND): Performs a bitwise AND operation on the values ​​of two registers and stores the result in the first register.

[0061] OR (Bitwise OR): Performs a bitwise OR operation on the values ​​of two registers and stores the result in the first register.

[0062] XOR (Bitwise XOR): Performs a bitwise exclusive OR operation on the values ​​of two registers and stores the result in the first register.

[0063] SLL (Shift Left Logical): Logically shifts the value of a register left by the specified number of bits and stores the result in the register.

[0064] SRL (Shift Right Logical): Logically shifts the value of a register right by the specified number of bits and stores the result in the register.

[0065] Among them, jump instructions include: JAL (Jump and Link): Jump to the specified memory address and save the current program counter value in the register.

[0066] JALR (Jump and Link Register): Jumps to the address specified in a register and saves the current program counter value in another register.

[0067] BEQ (Branch if Equal): If the values ​​of two registers are equal, jump to the specified memory address.

[0068] BNE (Branch if Not Equal): If the values ​​of two registers are not equal, jump to the specified memory address.

[0069] BLT (Branch if Less Than): Jump to the specified memory address if the value of the first register is less than the value of the second register.

[0070] Among them, special instructions include: WFI (Wait for Interrupt): Puts the processor into a low-power state until the next interrupt occurs.

[0071] NOP (No Operation): Do not perform any operation, usually used for time adjustment or placeholder.

[0072] Ebreak (Exception Break): Triggers an exception, usually used for debugging.

[0073] Test the target processor instructions according to the test cases, and implement the storage class dependencies with reference Figure 4 As shown, instructions are selected from the storage class instruction set to generate a three-level instruction sequence of storage dependency. For example, first execute SW a4, 28 (SP) to store the value of register a4 to the position of stack pointer SP offset 28, then execute LW a2, 28 (SP) to load data from the same position to register a2, and then execute LW a6, 32 (SP) to load data from the position of stack pointer offset 32 ​​to register a6. Such a sequence can verify the data dependency between storage instructions. And so on, traverse all three-level instruction sequences of storage class dependency.

[0074] Storage and operation correlation implementation reference Figure 5 As shown, storage class instructions and operation class instructions are combined to generate a three-level instruction sequence related to storage and operation. For example, first execute LW a2, 28 (SP) and LW a4, 24 (SP) to load data, then execute ADD a6, a2, a4 for addition, and finally execute SW a4, 28 (SP) and SW a2, 24 (SP) to store the result back to the memory. This can verify the data dependency between storage instructions and operation instructions.

[0075] Operational Dependency Implementation Reference Figure 6 As shown, instructions are selected from the operation instruction set to generate a three-level instruction sequence related to the operation. For example, SUB a6, a4, a2 is executed first for subtraction, then ADD a2, a6, a4 is executed for addition, and finally SW a4, 24 (SP) is executed to store the result to the memory. This can verify the data dependency between the operation instructions.

[0076] Store and Jump Dependency Implementation Reference Figure 7As shown, by combining storage class instructions and control jump class instructions, a three-level instruction sequence related to storage and jump is generated. For example, first execute LW a2, 20 (SP) to load data, then execute JALR a2 to jump according to the loaded value, and finally execute SW a2, -20 (SP) to store the data to the memory. This can verify how the execution result of the storage instruction affects the execution of the jump instruction.

[0077] Operation and jump dependency implementation reference Figure 8 As shown, the operation instructions and control jump instructions are combined to generate a three-level instruction sequence related to operation and jump. For example, first execute LW a2, 20 (SP) to load data, then execute ADD a2, a2, 20 to perform addition operation, and finally execute JALR a2 to jump according to the operation result. This can verify how the execution result of the operation instruction affects the execution of the jump instruction.

[0078] With respect to the prototype verification method of pipeline-level instructions described above, the present application also provides a corresponding prototype verification device of internal pipeline-level instructions, so that the above-mentioned content verification method can be applied and implemented in practice.

[0079] Reference Fig. 9 As shown, the prototype verification device includes: A classification module, used for classifying the instruction set of the processor; The test case generation module is used to generate test cases according to instruction classification and verify the execution process and relevance of instructions in the pipeline; The execution module is used to execute the generated test cases on the hardware platform to verify the actual execution of the instruction pipeline.

[0080] The present application also provides a device for performing pipeline-level instruction prototype verification, which device can specifically be a server; Fig.10 The figure shows a schematic diagram of a server structure for verifying content provided by an embodiment of the present application. The server may have relatively large differences due to different configurations or performances, and may include one or more central processing units (CPU) and memories, and one or more storage media for storing applications or data. Among them, the memories and storage media may be short-term storage or permanent storage. The program stored in the storage medium may include one or more modules, each of which may include a series of instruction operations on the server. Furthermore, the central processing unit may be configured to communicate with the storage medium and execute a series of instruction operations in the storage medium on the server.

[0081] The server may also include one or more power supplies, one or more wired or wireless network interfaces, one or more input and output interfaces, and / or one or more operating systems, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0082] The embodiment of the present application also provides a computer-readable storage medium for storing program code, where the program code is used to execute any implementation of a content verification method described in the aforementioned embodiments.

[0083] The embodiment of the present application also provides a computer program product including instructions, which, when executed on a computer, enables the computer to execute any one of the implementations of the content verification method described in the aforementioned embodiments.

[0084] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0085] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0086] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0087] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0088] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk.

[0089] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. The above embodiments and descriptions are only preferred examples of the present invention and are not intended to limit the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A prototype verification method for pipeline-level instructions, characterized in that: include: Classify the instruction sets of processors; Generate test cases based on instruction classification to verify the execution process of instructions in the pipeline; Execute the generated test cases on the hardware platform to verify the actual execution of the instruction pipeline.

2. The prototype verification method of a pipeline-level instruction according to claim 1, characterized in that: The classifying of the instruction set of the processor includes: Establishing standards for processor instruction classification; Analyze the function of each instruction in the processor instruction set and determine its functional category; According to the functional category analysis results of the processor instructions, the processor instructions are classified according to the classification standards.

3. The prototype verification method of a pipeline-level instruction according to claim 2, characterized in that: The establishing of processor instruction classification standards includes: According to the instruction relevance, instructions are divided into four categories: storage instructions, operation instructions, control jump instructions, and special instructions.

4. The prototype verification method of a pipeline-level instruction according to claim 1, characterized in that: The generating of test cases according to instruction classification to verify the execution process of instructions in the pipeline includes: Generate a sequence including a plurality of data-dependent instructions and a sequence including a plurality of control-dependent instructions according to data dependencies and control dependencies between the instructions; Through the sequence of data-related instructions, verify whether there is data conflict during instruction execution; By controlling the sequence of related instructions, verify whether there is a control conflict during the execution of instructions.

5. The prototype verification method of a pipeline-level instruction according to claim 1, characterized in that: The hardware platform includes FPGA or other programmable logic devices, which are used to simulate the instruction pipeline execution environment of the processor.

6. The prototype verification method of a pipeline-level instruction according to claim 1, characterized in that: It also includes analyzing the execution result data and comparing the actual execution results with the expected results to determine the correctness and performance indicators of the instruction pipeline.

7. The prototype verification method of a pipeline-level instruction according to claim 1, characterized in that: Suitable for verifying the instruction pipeline of processors based on the RISC-V instruction set architecture, or suitable for processor design.

8. A prototype verification device for pipeline-level instructions, characterized in that: include: A classification module, used for classifying the instruction set of the processor; The test case generation module is used to generate test cases according to instruction classification and verify the execution process and relevance of instructions in the pipeline; The execution module is used to execute the generated test cases on the hardware platform to verify the actual execution of the instruction pipeline.

9. A device, characterized in that: The device comprises a processor and a memory: The memory is used to store program code and transmit the program code to the processor; The processor is used to execute the prototype verification method of the pipeline-level instruction according to any one of claims 1-7 according to the instructions in the program code.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store program code, and the program code is used to execute the prototype verification method of pipeline-level instructions described in any one of claims 1-7.

Images