Communication control system of radio frequency front end and electronic equipment

Abstract

The invention discloses a communication control system of a radio frequency front end and electronic equipment. The communication control system comprises an MIPI main control module and at least one MIPI bus emission control channel, wherein the MIPI bus emission control channel is respectively connected with a first MIPI module and at least one second MIPI module; wherein the first MIPI module is an MIPI interface module with a read-back MIPI read-write function; the second MIPI module is an MIPI interface module without a read-back function; when the MIPI master control module sends out an MIPI instruction to change the register value of the radio frequency front end, the register value is changed at the end moment of the MIPI instruction. And extra internal communication time and internal crystal oscillator are not needed. Meanwhile, the same common register can be controlled through different buses so as to meet the requirements of various different application scenes.

Description

Technical Field

[0001] The invention relates to a communication control system of a radio frequency front end, and also to electronic equipment comprising the communication control system, belonging to the technical field of data communication. Background Art

[0002] L-PAMiD (LNA-Power Amplifier Module integrated Duplexer) is a highly integrated radio frequency front-end (RFFE) chip. L-PAMiD integrates components such as power amplifier (PA), low noise amplifier (LNA), filter, antenna switch (ASW), multi-band switch (XSW) and duplexers / multiplexers. Its advantage is that it reduces the area and power consumption of the RF front-end.

[0003] As a RF front-end chip, L-PAMiD supports the MIPI (Mobile Industry Processor Interface) protocol. Although the above-mentioned PA and other components are integrated in L-PAMiD, on the one hand, TX (transmit) and RX (receive) in the existing RF front-end control platform are still controlled by different MIPI buses, and there are cases where different buses control the same functional component. On the other hand, due to layout and wiring considerations, different functional components are also distributed on different dies inside the L-PAMiD chip. Therefore, a communication control solution is needed that can take into account these complex application scenarios.

[0004] In the prior art, the communication control implementation scheme of some L-PAMiDs is to concentrate the MIPI functions on TX and RX, and other switch components are controlled by TX using a serial communication method. The disadvantage of this scheme is that it is necessary to add a crystal oscillator circuit inside the chip, and it requires additional information transmission time. For example, in the Chinese invention patent application with application number 201810703855.9, a serial communication device and a serial communication method are disclosed. The serial communication device includes a radio frequency front-end module and a radio frequency device. The first input interface and the second input interface of the radio frequency front-end module are connected to the output interface of the main control module correspondingly. When the first output interface of the radio frequency front-end module is connected to the first input interface of at least one radio frequency device through the first signal bus, the second output interface of the radio frequency front-end module is connected to the second input interface of at least one radio frequency device through the second signal bus. The serial communication device can meet the needs of convenient and fast one-way communication between the chips of the radio frequency front-end module and between the chips. Summary of the invention

[0005] The primary technical problem to be solved by the present invention is to provide a communication control system for a radio frequency front end.

[0006] Another technical problem to be solved by the present invention is to provide an electronic device including the communication control system.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present invention, a communication control system of a radio frequency front end is provided, comprising a MIPI main control module and at least one MIPI bus transmission control path, wherein a first MIPI module and at least one second MIPI module are respectively connected to the MIPI bus transmission control path; wherein,

[0009] The MIPI master control module, the first MIPI module and the second MIPI module are all connected via a MIPI bus to form a communication control path;

[0010] The MIPI master control module is used to control and manage the MIPI communication of the RF front end;

[0011] The first MIPI module is a MIPI interface module with a readback function, which is connected to the transmitting RF component;

[0012] The second MIPI module is a MIPI interface module without a readback function, which is connected to the radio frequency component;

[0013] When the MIPI master control module issues a MIPI instruction to change the register value of the RF front end, the register value is changed at the end time of the MIPI frame of the MIPI instruction.

[0014] Preferably, the communication control system further comprises a MIPI bus receiving control path, and the MIPI bus receiving control path is connected to the first MIPI module; wherein,

[0015] The MIPI master control module is connected to the first MIPI module via a MIPI bus;

[0016] The first MIPI module is connected to the receiving radio frequency component.

[0017] Preferably, when the MIPI master control module performs a read-back operation, only the first MIPI module on the same MIPI bus responds to the read-back operation, takes over the serial data signal, and sends the register value back to the MIPI master control module.

[0018] Preferably, on the same MIPI bus, the first MIPI module is responsible for recording the register value of the second MIPI module. When the MIPI master control module issues an instruction to change the register value of the second MIPI module, the registers with the same register address and bit width in the first MIPI module also change synchronously.

[0019] Preferably, in the communication control system having multiple MIPI bus control paths, when a second MIPI module on one MIPI bus and a second MIPI module on another MIPI bus jointly control a register module, the two second MIPI modules are respectively connected to the common register module through the data bus.

[0020] Preferably, the shared register module includes a shared register and a shared register cache and control logic thereof; the shared register module is responsible for recording the bus that last performed a write operation on the shared register, and the shared register only responds to trigger and reset operations issued by the bus that last performed a write operation on the shared register.

[0021] Preferably, write instructions of different MIPI buses can be received, decoded and sent to the common register module by the second MIPI module connected to the common register module on the corresponding bus, and the value of the common register will change accordingly.

[0022] Preferably, in the trigger mode, when the MIPI bus performs a write operation on the shared register module, the written data first enters the register cache, and then the write register data is called when the shared register is triggered.

[0023] Preferably, when the MIPI bus performs a write operation on the shared register module, or when the bus that last performed a write operation on the shared register recorded by the shared register module performs a trigger and reset operation on the shared register, a flag signal lasting a clock cycle width is generated; the shared register module uses the flag signal to intercept a clock signal from the serial clock signal, and the register data and the register value of the register cache both jump on the rising edge of the clock signal.

[0024] According to a second aspect of an embodiment of the present invention, there is provided an electronic device, comprising the communication control system of the above-mentioned radio frequency front end.

[0025] Compared with the prior art, the communication control system of the RF front end provided by the present invention integrates a separate MIPI module on each crystal grain, and the MIPI instruction takes effect immediately at the end of the MIPI frame, without the need for additional internal serial communication time and internal crystal oscillator. At the same time, the same shared register can be controlled through different buses to meet the needs of various application scenarios. Therefore, the communication control system of the RF front end provided by the present invention has the beneficial effects of ingenious and reasonable structural design, fast response speed and simple substrate routing. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a diagram of the communication control scheme inside L-PAMiD in the prior art;

[0027] Figure 2 It is a timing coordination diagram of the communication control scheme in the prior art;

[0028] Figure 3 A structural block diagram of a communication control system of a radio frequency front end provided by the present invention;

[0029] Figure 4 The structure frame of the communication control system of the radio frequency front end in the embodiment of the present invention is Figure 1 ;

[0030] Figure 5 The structure frame of the communication control system of the radio frequency front end in the embodiment of the present invention is Figure 2 ;

[0031] Figure 6 A timing diagram of a communication control system performing a write operation in an embodiment of the present invention;

[0032] Figure 7 This is a timing coordination diagram when the communication control system performs trigger and reset operations in an embodiment of the present invention.

[0033] Figure 8 The schematic diagram is a schematic diagram of an electronic device of a communication control system using the radio frequency front end provided by the present invention. DETAILED DESCRIPTION

[0034] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] For ease of understanding and explanation, the present invention application first briefly introduces the communication control scheme of the highly integrated RF front end in the prior art, and on this basis, describes in detail the specific technical scheme of the embodiment of the present invention.

[0036] The communication control scheme within L-PAMiD in the prior art is as follows: Figure 1As shown in the figure, the MIPI functions are concentrated on TX and RX in L-PAMiD, and other switches (ASW / XSW) are controlled by TX using serial communication method. Figure 2 As shown, when L-PAMiD receives the MIPI instruction issued by the MIPI master control module, the internal SIPI sending module (SIPI_Send) will send a SIPI instruction frame to the switch module SIPI_ASW / SIPI_XSW. The switch module will change its own switch value only after receiving the SIPI instruction frame. Compared with directly controlling the switch on and off by the MIPI module, the internal serial communication time will be increased by about 0.5us to 1us. At the same time, a crystal oscillator circuit needs to be added inside the chip.

[0037] In order to solve the above problems existing in the prior art, the present invention proposes a communication control scheme of L-PAMiD, which integrates a separate MIPI module on each die. The MIPI instruction takes effect immediately at the end of the MIPI frame, and does not require additional internal serial communication time and internal crystal oscillator.

[0038] like Figure 3 As shown, a communication control system of a radio frequency front end provided by the present invention includes a MIPI main control module and at least one MIPI bus transmission control path, and the MIPI bus transmission control path is respectively connected to a first MIPI module 100 and at least one second MIPI module 101. Among them, the MIPI main control module, the first MIPI module 100 and the second MIPI module 101 are all connected through the MIPI bus to form a communication control path.

[0039] The MIPI master control module is used to control and manage the MIPI communication of the RF front end.

[0040] The first MIPI module 100 is a MIPI interface module with a readback function, which supports various functions that a sub-chip should have as specified in the MIPI protocol, and is connected to a TX RF component.

[0041] The second MIPI module 101 is a MIPI interface module without a readback function. It supports various functions that the sub-chip should have as specified in other MIPI protocols except the readback function. It is connected to a corresponding RF component, usually a switch (ASW and / or XSW) component.

[0042] When the MIPI master control module issues a MIPI instruction to change the register value of the RF front end, the register value is changed at the end time of the MIPI frame of the MIPI instruction.

[0043] Furthermore, the communication control system also includes a MIPI bus receiving control path, and a first MIPI module 100 is connected to the MIPI bus receiving control path. The MIPI main control module and the first MIPI module 100 are connected via a MIPI bus. The first MIPI module 100 is a MIPI interface module with complete MIPI read and write functions, which supports various functions that the sub-chip specified in the MIPI protocol should have, and is connected to the RX RF component.

[0044] In one embodiment of the present invention, Figure 4 As shown, in a communication control system having multiple MIPI bus control paths, when a second MIPI module 101 on one MIPI bus and a second MIPI module 101 on another MIPI bus jointly control a register module 102, the two second MIPI modules 101 are connected to the shared register module 102 via a data bus 103 respectively.

[0045] When the MIPI master control module performs a readback operation, only the first MIPI module 100 on the same MIPI bus will respond to the readback operation, take over the serial data signal SDATA, and send the register value back to the MIPI master control module.

[0046] On the same MIPI bus, the first MIPI module is also responsible for recording the register value of the second MIPI module. When the MIPI master control module issues an instruction to change the register value of the second MIPI module, the registers with the same register address and bit width in the first MIPI module also change synchronously.

[0047] The second MIPI module 101 without the readback function is different from the first MIPI module 100 with complete functions in that it does not respond to the read command of the MIPI master module to avoid competing with the first MIPI module 100 for the control of the serial data signal SDATA. Other functions of the sub-chip specified in the MIPI protocol, such as responding to various write instructions, triggering, resetting, etc., can be implemented in the second MIPI module 101. No matter what MIPI instruction the MIPI master module uses to change the register value of the RF front end, it can be completed at the moment when the MIPI instruction ends, and no additional internal communication time is required.

[0048] It should be noted that the readback function of the second MIPI module 101 can be set to be disabled in a GPIO manner, or a readback address offset function can be added to avoid bus conflicts.

[0049] The shared register module 102 mainly includes a shared register and a shared register cache and its control logic. Among them, the input of the control logic is the data bus 103, and the output is the shared register value. The shared register module 102 also needs to record the bus that last performed a write operation on the shared register, and the shared register only responds to the trigger and reset operations issued by the bus that last performed a write operation on the shared register. Among them, the data transmitted by the data bus 103 includes the serial clock signal SCLK of the second MIPI module 101 and the flag bits and other data of write, trigger, reset, mask write.

[0050] In one embodiment of the present invention, Figure 5 As shown, a communication control system of a radio frequency front end includes a MIPI main control module and three MIPI bus control paths. Among them, the MIPI main control module is connected to the first MIPI module MIPI1_TX, the second MIPI module MIPI1_XSW, and the second MIPI module MIPI1_ASW through the first MIPI bus; the MIPI main control module is connected to the first MIPI module MIPI2_RX through the second MIPI bus; the MIPI main control module is connected to the first MIPI module MIPI3_TX, the second MIPI module MIPI3_XSW, and the second MIPI module MIPI3_ASW through the third MIPI bus. At the same time, the second MIPI module MIPI1_XSW on the first MIPI bus and the second MIPI module MIPI3_XSW on the third MIPI bus are respectively connected to the first shared register module 102 through the data bus 103; the second MIPI module MIPI1_ASW on the first MIPI bus and the second MIPI module MIPI3_ASW on the third MIPI bus are respectively connected to the second shared register module 102 through the data bus 103.

[0051] The communication control system cooperates with the timing of executing the write operation as follows Figure 6 As shown in the figure, MIPI1 and MIPI3 marked on the left represent the first MIPI bus and the third MIPI bus respectively; TX1, TX3, ASW, and XSW all refer to a shared register in the corresponding module, and these registers all work in non-trigger mode, and the register values ​​can be directly changed by MIPI write instructions.

[0052] When the above-mentioned communication control system is performing a write operation, since the switch ASW and switch XSW modules are both equipped with MIPI modules, namely the second MIPI module MIPI1_XSW, the second MIPI module MIPI1_ASW and the second MIPI module MIPI3_XSW, the second MIPI module MIPI3_ASW, when the write instruction issued by the MIPI master control module at a certain moment ends, namely at moments a, b, c, and d in the figure, the switch value of the switch ASW or the switch XSW changes accordingly.

[0053] Since the switch ASW and the switch XSW are both controlled by the shared register in the shared register module 102, for the shared register, the write instructions of different MIPI buses can be received and decoded by the MIPI module in the switch ASW or switch XSW module and sent to the shared register module, and the value of the shared register will change accordingly. Figure 6 At time c, the write instruction sent by the MIPI master module through the first MIPI bus causes the MIPI module in the switch XSW module to receive and decode the instruction and send it to the shared register module, and the value of the shared register changes immediately; at time d, the write instruction sent by the MIPI master module through the third MIPI bus causes the MIPI module in the switch XSW module to receive and decode the instruction and send it to the shared register module, and the value of the shared register changes immediately.

[0054] For the first MIPI bus or the third MIPI bus, although there are three MIPI modules on the same bus, namely the first MIPI module MIPI1_TX, the second MIPI module MIPI1_XSW and the second MIPI module MIPI1_ASW; or, the first MIPI module MIPI3_TX, the second MIPI module MIPI3_XSW and the second MIPI module MIPI3_ASW. However, only the MIPI module of TX, namely the first MIPI module MIPI1_TX or the first MIPI module MIPI3_TX, has a reading function. Therefore, the MIPI module of TX also needs to record the register values ​​of switch ASW and switch XSW. When the MIPI master control module issues instructions to change the register values ​​of switch ASW and switch XSW, the registers with the same register address and bit width in the MIPI module of TX also change synchronously.

[0055] It should be noted that the shared registers in TX can also have their register values ​​changed by different buses. However, considering that the platform usually only uses a certain bus to control a specific shared register, the shared registers in TX may not respond to instructions from multiple buses at the same time, but each bus is equipped with a separate register.

[0056] The communication control system performs the trigger or reset operation in the following order: Figure 7As shown, in the communication control system provided by the present invention, the common register only responds to the trigger and reset operations issued by the bus that last performs the write operation on the common register. Figure 7 The shared register Reg6 is taken as an example to illustrate the timing coordination of this mechanism.

[0057] In trigger mode, when the MIPI1 bus or MIPI3 bus performs a write operation on the shared register Reg6, the written data will not enter the register data Reg6_DATA immediately, but will first enter the register cache Reg6_BUFF, and then call the write register data Reg6_DATA when Reg6 is triggered. After the MIPI1 bus or MIPI3 bus performs a write operation on the shared register Reg6, the register flag Reg6_BUS will record the bus that last performed the write operation, and Reg6 only responds to the trigger and reset operations of the bus recorded by Reg6_BUS. For example, at time b, the MIPI1 bus performs a write operation on the shared register Reg6, and the written data AA first enters the register cache Reg6_BUFF; at the same time, the register flag Reg6_BUS records the bus MIPI1 that performs the write operation.

[0058] When the MIPI1 bus or MIPI3 bus performs a write operation on the shared register Reg6, or the bus recorded by the register flag Reg6_BUS performs a trigger and reset operation on the shared register Reg6, a flag signal with a width of one clock cycle will be generated, namely MIPI1_Write, MIPI1_Trigger, MIPI1_Reset or MIPI3_Write, MIPI3_Trigger, MIPI3_Reset. The shared register module uses the above-mentioned flag signal to intercept a clock signal Reg6_CLK from the serial clock signal SCLK, and the register values ​​of the register data Reg6_DATA and the register buffer Reg6_BUFF both jump on the rising edge of the clock signal Reg6_CLK. For example, at the time b and time e of the rising edge of the clock signal Reg6_CLK, the register buffer Reg6_BUFF and the register data Reg6_DATA jump successively.

[0059] The composition structure and working principle of a communication control system of a radio frequency front end provided by the present invention are described in detail above. Based on the above communication control system, an embodiment of the present invention provides an electronic device, which includes the communication control system of the above radio frequency front end. The system, as an important component of the radio frequency communication component, is used to realize the communication control in the transmission and / or reception related components. The electronic device mentioned here refers to a computer device that can be used in a mobile environment and supports multiple communication standards such as GSM, EDGE, CDMA, TD_SCDMA, WCDMA, TDD_LTE, FDD_LTE, NR, etc., including mobile phones, laptops, tablet computers, car computers, etc. In addition, the technical solution provided by the present invention is also applicable to other occasions where radio frequency integrated circuits are applied, such as communication base stations, smart connected vehicles, etc.

[0060] like Figure 8 As shown, the electronic device at least includes a processor, a memory and a communication component, and may further include a sensor component, a power component, a multimedia component and an input / output interface according to actual needs. Among them, the memory, the communication component, the sensor component, the power component, the multimedia component and the input / output interface are all connected to the processor. The memory may be a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, etc., and the processor may be a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processing (DSP) chip, etc. Other communication components, sensor components, power components, multimedia components, etc. may all be implemented using general components, which will not be specifically described here.

[0061] In summary, compared with the prior art, the communication control system of the RF front end provided by the present invention integrates a separate MIPI module on each crystal grain, and the MIPI instruction takes effect immediately at the end of the MIPI frame, without the need for additional internal serial communication time and internal crystal oscillator. At the same time, the same shared register can also be controlled through different buses to meet the needs of various application scenarios. Therefore, the communication control system of the RF front end provided by the present invention has the beneficial effects of ingenious and reasonable structural design, fast response speed and simple substrate routing, and at the same time, there is no need to suppress the harmonics of the crystal oscillator.

[0062] It should be noted that the above-mentioned multiple embodiments are only examples, and the technical solutions of various embodiments can be combined, all of which are within the protection scope of the present invention.

[0063] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0064] The above is a detailed description of the communication control system and electronic equipment of the radio frequency front end provided by the present invention. For those skilled in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. A communication control system for a radio frequency front end, characterized in that It includes a MIPI master control module and at least one MIPI bus transmission control path, and the MIPI bus transmission control path is respectively connected to a first MIPI module and at least one second MIPI module; wherein, The MIPI master control module, the first MIPI module and the second MIPI module are all connected via a MIPI bus to form a communication control path; The MIPI master control module is used to control and manage the MIPI communication of the RF front end; The first MIPI module is a MIPI interface module with a readback function, which is connected to the transmitting RF component; The second MIPI module is a MIPI interface module without a readback function, which is connected to the radio frequency component; When the MIPI master control module issues a MIPI instruction to change the register value of the RF front end, the register value is changed at the end time of the MIPI frame of the MIPI instruction.

2. The communication control system of the radio frequency front end according to claim 1, characterized in that: The communication control system further includes a MIPI bus receiving control path, and the MIPI bus receiving control path is connected to the first MIPI module; wherein, The MIPI master control module is connected to the first MIPI module via a MIPI bus; The first MIPI module is connected to the receiving radio frequency component.

3. The communication control system of the radio frequency front end according to claim 1, characterized in that: When the MIPI master control module performs a readback operation, only the first MIPI module on the same MIPI bus responds to the readback operation, takes over the serial data signal, and sends the register value back to the MIPI master control module.

4. The communication control system of the radio frequency front end according to claim 1, characterized in that: On the same MIPI bus, the first MIPI module is responsible for recording the register value of the second MIPI module. When the MIPI master control module issues an instruction to change the register value of the second MIPI module, the registers with the same register address and bit width in the first MIPI module also change synchronously.

5. The communication control system of the radio frequency front end according to claim 1, characterized in that: In the communication control system having multiple MIPI bus control paths, when a second MIPI module on one MIPI bus and a second MIPI module on another MIPI bus jointly control a register module, the two second MIPI modules are respectively connected to the common register module through the data bus.

6. The communication control system of the radio frequency front end as claimed in claim 5, characterized in that: The shared register module includes a shared register and a shared register cache and its control logic; the shared register module is responsible for recording the bus that last performed a write operation on the shared register, and the shared register only responds to the trigger and reset operations issued by the bus that last performed a write operation on the shared register.

7. The communication control system of the radio frequency front end as claimed in claim 5, characterized in that: The write instructions of different MIPI buses can be received, decoded and sent to the common register module by the second MIPI module connected to the common register module on the corresponding bus, and the value of the common register will also change accordingly.

8. The communication control system of the radio frequency front end as claimed in claim 5, characterized in that: In the trigger mode, when the MIPI bus performs a write operation on the shared register module, the written data first enters the register cache, and then the write register data is called when the shared register is triggered.

9. The communication control system of the radio frequency front end as claimed in claim 5, characterized in that: When the MIPI bus performs a write operation on the shared register module, or when the bus recorded by the shared register module as the last bus to perform a write operation on the shared register performs a trigger and reset operation on the shared register, a flag signal with a duration of one clock cycle is generated; The shared register module uses the flag signal to intercept a clock signal from the serial clock signal, and the register data and the register value of the register cache both jump at the rising edge of the clock signal.

10. An electronic device, characterized in that A communication control system comprising the radio frequency front end as claimed in any one of claims 1 to 9.

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