DAC data transmission method based on FPGA

Abstract

The invention provides a DAC (Digital-to-Analog Converter) data transmission method based on an FPGA (Field Programmable Gate Array), and belongs to the technical field of DAC testing. The FPGA receives data from a serial port of the serial port chip and analyzes the data; the FPGA is used for storing the data; the FPGA is used for processing the data; the FPGA is used for forwarding the data; and the data enters a DAC data interface. The DAC data transmission method based on the FPGA has the advantages of being efficient, flexible, reliable, high in adaptability, low in delay and the like, and the requirements for DAC data transmission in various application scenes can be effectively met.

Description

Technical Field

[0001] The invention relates to the technical field of DAC testing, and in particular to a DAC data transmission method based on FPGA. Background Art

[0002] In technical testing, data transmission between the host computer and FPGA requires the use of UART serial communication, which has several inconveniences:

[0003] (1) The data transmission baud rate is 115200 bps, which is a slow transmission speed.

[0004] (2) For DACs with specific protocols, such as DACs with JESD204B interfaces, since data transmission has a fixed splicing order, if the host computer directly sends sinusoidal data, the FPGA needs to perform a lot of data processing, such as splitting, sorting, and splicing. Therefore, this part mainly relies on external MATLAB software to process the data first, and then send it down through the FPGA. The process is relatively cumbersome.

[0005] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0006] The object of the present invention is to provide a data transmission method with high data transmission speed and simple data transmission process.

[0007] To achieve the above object, the present invention provides the following solutions:

[0008] A DAC data transmission method based on FPGA, comprising:

[0009] Step 1: The host computer sends DAC data;

[0010] Step 2: FPGA receives data from the serial port of the serial port chip and parses the data; FPGA converts the received single-bit serial data into 8-bit parallel data, and parses the data at the same time, retaining the valid data packet, which includes the DAC valid data;

[0011] Step 3: FPGA stores the data; FPGA calls a BRAM IP core as data storage space, writes the DAC valid data parsed in step 2 into the BRAM space for storage, each address of the BRAM stores 8-bit DAC data, and the BRAM adjusts the BRAM IP core configuration to 8-bit to 16-bit or 8-bit to 32-bit according to the different DAC data bit widths;

[0012] Step 4: FPGA processes the data; reads the data in the RAM from address 0 one by one and sends it to the data forwarding module. After reading the last DAC data sent by the host computer, it continues to read the next round of data, still reading from address 0 to the last address of valid data, and sends data in this regular cycle;

[0013] Step 5: FPGA forwards the data; the data processed in step 4 is sequentially sent to the data forwarding module, and the data forwarding module sends the data to the DAC data interface in a corresponding timing or manner according to different DAC interfaces;

[0014] Step 6: Data enters the DAC data interface.

[0015] Optionally, the hardware connection method used for data transmission is:

[0016] The host computer is connected to the FPGA through a serial port chip. The serial port chip uses the MAX13236EETE chip, and the URAT interface on the FPGA end is converted into a USB port connected to the host computer; the MAX13236EETE chip is powered by 3.3V, the FPGA_RX pin is connected to the PIN6 pin of the serial port chip, and the FPGA_TX pin is connected to the PIN8 pin of the serial port chip; a DB9 interface is reserved on the test board. When in use, the male head of the DB9 interface is connected to the female end of the RS-232 to USB cable, and the other end of the USB interface is connected to the host computer.

[0017] Optionally, the host computer is connected to the serial port chip via a serial port line, the serial port chip is connected to the serial data analysis module on the FPGA, the serial data analysis module is connected to the data storage module; the data storage module is connected to the data forwarding module, and the data forwarding module is connected to the DAC via a DAC data line.

[0018] Optionally, the method for setting up the software used for data transmission includes:

[0019] Install RS-232 driver on the host computer so that after the host computer is connected to the test board, the host computer can identify the serial port in the device manager;

[0020] Install the TestSystem.exe software in the host computer, use this software to read the data in the local path and send the data to the FPGA;

[0021] Set the register and design the number of data that needs to be sent to the FPGA;

[0022] Save the DAC sine data to a TXT document and set the path through the software;

[0023] Run the software, read the data in TXT and send it down.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] 1. Efficient data reception and analysis:

[0026] Serial port reception and analysis: FPGA can efficiently receive and analyze DAC data sent by the host computer from the serial port to ensure the accuracy and integrity of the data.

[0027] Data conversion: Convert single-bit serial data into 8-bit parallel data, improving data processing efficiency.

[0028] 2. Flexible data storage:

[0029] BRAM storage: Using the BRAM IP core inside the FPGA as data storage space, it can flexibly store and read DAC data.

[0030] Bit width adjustment: According to the different bit widths of DAC data, the BRAM IP core configuration can be flexibly adjusted (such as 8-bit to 16-bit or 8-bit to 32-bit) to meet different application requirements.

[0031] 3. Efficient data processing and forwarding:

[0032] Circular read: FPGA can read the data in BRAM cyclically starting from address 0, ensuring that data is sent to DAC continuously.

[0033] Data forwarding module: Through the data forwarding module, the processed data is sent to the DAC data port according to the timing requirements of the DAC interface to ensure the accuracy and real-time performance of data transmission.

[0034] 4. High reliability and stability:

[0035] Data integrity: Ensure data integrity and reliability by parsing and storing valid data packets.

[0036] Cyclic sending mechanism: Cyclic reading and sending of data to avoid data loss or interruption and improve system stability.

[0037] 5. Strong adaptability:

[0038] Support for multiple DAC interfaces: According to different DAC interfaces, the timing and method of data transmission can be flexibly adjusted to adapt to various DAC devices.

[0039] Scalability: The solution has good scalability and can adjust the BRAM configuration and data processing logic as needed to adapt to different application scenarios.

[0040] 6. Low latency and high real-time performance:

[0041] Real-time data processing: FPGA's parallel processing capabilities and high-speed data forwarding modules ensure low latency and high real-time performance of data, making it suitable for application scenarios with high real-time requirements.

[0042] The FPGA-based DAC data transmission method provided by the present invention has the advantages of high efficiency, flexibility, reliability, strong adaptability and low latency, and can effectively meet the needs of DAC data transmission in various application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0044] Figure 1 A schematic diagram of a method flow chart provided by an embodiment of the present invention.

[0045] Figure 2 A flowchart of step 2 provided in an embodiment of the present invention.

[0046] Figure 3 The present invention provides a flowchart of steps three to five.

[0047] Figure 4 A schematic diagram of an FPGA firmware design framework provided in an embodiment of the present invention.

[0048] Figure 5 A hardware connection circuit diagram provided for an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] The purpose of the present invention is to provide a data transmission method with high efficiency in data reception and analysis, flexible data storage, high efficiency in data processing and forwarding, high reliability and stability, strong adaptability, low latency and high real-time performance.

[0051] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0052] Embodiment 1:

[0053] This embodiment provides a DAC data transmission method based on FPGA. Through the cooperation between the host computer and the software, the host computer reads the TXT document in the specified path and transmits the data in the document to the RAM of the FPGA. After the internal processing of the FPGA, the data is sent to the DAC using different interface forms. The DAC output can be adjusted. Figure 1-3 As shown, the specific steps include:

[0054] Step 1: The host computer sends DAC data;

[0055] Step 2: FPGA receives data from the serial port of the serial port chip and parses the data; FPGA converts the received single-bit serial data into 8-bit parallel data, parses the data at the same time, and retains the valid data packet; the valid data packet includes the DAC valid data; the serial port communication baud rate is 115200 Baud, and the actual number of data used can be configured by the host computer.

[0056] Step 3: FPGA stores the data; FPGA calls a BRAM IP core as data storage space, writes the DAC valid data parsed in step 2 into the BRAM space for storage, each address of the BRAM stores 8-bit DAC data, and the BRAM adjusts the BRAM IP core configuration to 8-bit to 16-bit or 8-bit to 32-bit according to the different DAC data bit widths;

[0057] Step 4: FPGA processes the data; reads the data in the RAM from address 0 one by one and sends it to the data forwarding module. After reading the last DAC data sent by the host computer, it continues to read the next round of data, still reading from address 0 to the last address of valid data, and sends data in this regular cycle;

[0058] Step 5: FPGA forwards the data; the data processed in step 4 is sent to the data forwarding module in sequence, and the data forwarding module sends the data to the DAC data interface in a corresponding timing or manner according to the different DAC interfaces; for example, if the DAC data end is a JESD204B interface, the data forwarding module sends the data processed in step 3 to the 204B interface in sequence; if the DAC data end is an LVDS interface, the data forwarding module sends the data processed in step 3 to the DAC data port in LVDS form.

[0059] Step 6: Data enters the DAC data interface.

[0060] In one embodiment, the connection mode of the hardware used for data transmission is:

[0061] The host computer is connected to the FPGA through a serial port chip. The serial port chip uses the MAX13236EETE chip. The URAT interface on the FPGA side is converted to a USB port connected to the host computer. The MAX13236EETE chip is powered by 3.3V, the FPGA_RX pin is connected to the PIN6 pin of the serial port chip, and the FPGA_TX pin is connected to the PIN8 pin of the serial port chip. The DB9 interface is reserved on the test board. When in use, the male end of the DB9 interface is connected to the female end of the RS-232 to USB cable, and the other end of the USB interface is connected to the host computer. The hardware circuit diagram is as follows Figure 5 shown.

[0062] In one embodiment, Figure 4 As shown, the host computer is connected to the serial port chip through a serial port line, the serial port chip is connected to the serial data analysis module on the FPGA, the serial data analysis module is connected to the data storage module; the data storage module is connected to the data forwarding module, and the data forwarding module is connected to the DAC through a DAC data line.

[0063] In one embodiment, a method for setting up software used for data transmission includes:

[0064] Install RS-232 driver on the host computer so that after the host computer is connected to the test board, the host computer can identify the serial port in the device manager;

[0065] Install the TestSystem.exe software in the host computer, use this software to read the data in the local path and send the data to the FPGA;

[0066] Set the register and design the number of data that needs to be sent to the FPGA;

[0067] CB1.SetRegDACta(0X1005,0X00)

[0068] CB1.SetRegDACta(0X1006,0X800)#16bit data number

[0069] CB1.SetRegDACta(0X1007,0X00)

[0070] CB1.SetRegDACta(0X1007,0X01)

[0071] CB1.SetRegDACta(0X000A,0X400)#32-bit data number.

[0072] Save the DAC sine data to a TXT document and set the path through the software: aa=Sys.ReaDACllText("C:\Users\E00077\Desktop\XIANGMU\B8831\SHUJU.txt")#data path.

[0073] Run the software, read the data in TXT and send it down.

[0074] DACTA = Sys.SubStrToByteArray(aa)

[0075] CB1.brustWriteDACta(0x00,DACTA).

[0076] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0077] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A DAC data transmission method based on FPGA, characterized in that: include: Step 1: The host computer sends DAC data; Step 2: FPGA receives data from the serial port of the serial port chip and parses the data; FPGA converts the received single-bit serial data into 8-bit parallel data, and parses the data at the same time, retaining the valid data packet, which includes the DAC valid data; Step 3: FPGA stores the data; FPGA calls a BRAM IP core as data storage space, writes the DAC valid data parsed in step 2 into the BRAM space for storage, each address of the BRAM stores 8-bit DAC data, and the BRAM adjusts the BRAM IP core configuration to 8-bit to 16-bit or 8-bit to 32-bit according to the different DAC data bit widths; Step 4: FPGA processes the data; reads the data in the RAM from address 0 one by one and sends it to the data forwarding module. After reading the last DAC data sent by the host computer, it continues to read the next round of data, still reading from address 0 to the last address of valid data, and sends data in this regular cycle; Step 5: FPGA forwards the data; the data processed in step 4 is sequentially sent to the data forwarding module, and the data forwarding module sends the data to the DAC data interface in a corresponding timing or manner according to different DAC interfaces; Step 6: Data enters the DAC data interface.

2. The DAC data transmission method based on FPGA according to claim 1, characterized in that: The connection method of the hardware used for data transmission is: The host computer is connected to the FPGA through a serial port chip. The serial port chip uses the MAX13236EETE chip, and the URAT interface on the FPGA end is converted into a USB port connected to the host computer; the MAX13236EETE chip is powered by 3.3V, the FPGA_RX pin is connected to the PIN6 pin of the serial port chip, and the FPGA_TX pin is connected to the PIN8 pin of the serial port chip; a DB9 interface is reserved on the test board. When in use, the male head of the DB9 interface is connected to the female end of the RS-232 to USB cable, and the other end of the USB interface is connected to the host computer.

3. The DAC data transmission method based on FPGA according to claim 2, characterized in that: The host computer is connected to the serial port chip through a serial port line, the serial port chip is connected to the serial data analysis module on the FPGA, the serial data analysis module is connected to the data storage module; the data storage module is connected to the data forwarding module, and the data forwarding module is connected to the DAC through a DAC data line.

4. The DAC data transmission method based on FPGA according to claim 1, characterized in that: The software settings for data transfer include: Install RS-232 driver on the host computer so that after the host computer is connected to the test board, the host computer can identify the serial port in the device manager; Install the TestSystem.exe software in the host computer, use this software to read the data in the local path and send the data to the FPGA; Set the register and design the number of data that needs to be sent to the FPGA; Save the DAC sine data to a TXT document and set the path through the software; Run the software, read the data in TXT and send it down.

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