FPGA-Based DAC Data Transmission Method

Abstract

The present invention provides a DAC data transmission method based on FPGA, belonging to the technical field of DAC testing, including: the host computer sends down DAC data; the FPGA receives data from the serial port of the serial port chip and parses the data; the FPGA stores the data; the FPGA processes the data; the FPGA forwards the data; the data enters the DAC data interface. The DAC data transmission method based on FPGA provided by the present invention has the advantages of high efficiency, flexibility, reliability, strong adaptability and low latency, and can effectively meet the requirements for DAC data transmission in various application scenarios.

Description

Technical Field

[0001] The present invention relates to the technical field of DAC testing, and in particular to a DAC data transmission method based on FPGA. Background Art

[0002] When data is transmitted between the host computer and the FPGA during technical testing, UART serial communication needs to be used, and there are mainly several inconveniences in its use:

[0003] (1) The data transmission baud rate is 115,200 bps, and the transmission speed is relatively slow.

[0004] (2) For DACs with specific protocols, such as DACs with JESD204B interfaces, since the data has a fixed splicing order for transmission, if the host computer directly sends sine data, the FPGA needs to perform a large amount of data processing, such as splitting, sorting, splicing, etc. Therefore, this part mainly relies on external MATLAB software to process the data first and then send it through the FPGA, and the process is relatively cumbersome.

[0005] The information disclosed in this background art section is only intended to enhance the overall understanding of the present invention and should not be regarded as an admission or any form of suggestion that this information constitutes prior art already known to those of ordinary skill in the art. Summary of the Invention

[0006] The purpose of the present invention is to provide a data transmission method with fast data transmission speed and simple data transmission process.

[0007] To achieve the above object, the present invention provides the following solution:

[0008] A DAC data transmission method based on FPGA, comprising:

[0009] Step 1: The host computer sends down DAC data;

[0010] Step 2: The FPGA receives data from the serial port of the serial port chip and parses the data; the FPGA converts the received single-bit serial data into 8-bit parallel data, and at the same time parses the data to retain valid data packets, and the valid data packets include DAC valid data;

[0011] Step 3: The FPGA stores the data; the FPGA calls an IP core of a BRAM as a data storage space, writes the DAC valid data parsed in Step 2 into the BRAM space for storage, each address of the BRAM stores 8-bit DAC data, and the BRAM adjusts the IP core configuration of the BRAM to 8-bit to 16-bit or 8-bit to 32-bit according to the different bit widths of the DAC data;

[0012] Step 4: The FPGA processes the data; reads the data in the RAM address by address starting from address 0 and sends it to the data forwarding module. After reading the last DAC data sent by the host computer, continue to start the next round of data reading, still reading from address 0 to the last address of the valid data, and sending the data in this cycle;

[0013] Step 5: The FPGA forwards the data; sends the data processed in Step 4 to the data forwarding module in sequence. The data forwarding module sends the data to the DAC data interface according to the corresponding timing or method according to the different DAC interfaces;

[0014] Step 6: The data enters the DAC data interface.

[0015] Optionally, the connection method of the hardware used for data transmission is as follows:

[0016] The host computer is connected to the FPGA through a serial port chip. The serial port chip selects the MAX13236EETE chip, converts the URAT interface at the FPGA end to a USB port and connects it to the host computer. The power supply of the MAX13236EETE chip is 3.3V. The FPGA_RX pin is connected to the PIN6 pin of the serial port chip, and the FPGA_TX pin is connected to the PIN8 pin of the serial port chip. A DB9 interface is reserved on the test board. When in use, the male head of the DB9 interface is connected to the female head end of the RS-232 to USB cable, and the other end USB interface is connected to the host computer.

[0017] Optionally, the host computer is connected to the serial port chip through a serial cable. The serial port chip is connected to the serial data parsing module on the FPGA. The serial data parsing module is connected to the data storage module. The data storage module is connected to the data forwarding module. The data forwarding module is connected to the DAC through the DAC data line.

[0018] Optionally, the setting method of the software used for data transmission includes:

[0019] The host computer installs the RS-232 driver so that after the host computer is connected to the test board, the host computer can recognize the serial port in the device manager;

[0020] Install the TestSystem.exe software in the host computer, read the data in the local path through this software and send the data to the FPGA;

[0021] Set the register to design the number of data to be sent to the FPGA;

[0022] Save the DAC sine data to a TXT document and set the path through the software;

[0023] Run the software to read the data in the TXT and send it down.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] 1. Efficient data reception and parsing:

[0026] Serial port reception and parsing: The FPGA can efficiently receive and parse the DAC data sent by the host computer from the serial port, ensuring the accuracy and integrity of the data.

[0027] Data conversion: Convert single-bit serial data into 8-bit parallel data, improving the data processing efficiency.

[0028] 2. Flexible data storage:

[0029] BRAM storage: Utilize the BRAM IP core inside the FPGA as the data storage space, which can flexibly store and read DAC data.

[0030] Bit width adjustment: According to the different bit widths of the DAC data, flexibly adjust the configuration of the BRAM IP core (such as 8-bit to 16-bit or 8-bit to 32-bit) to adapt to different application requirements.

[0031] 3. Efficient data processing and forwarding:

[0032] Circular reading: The FPGA can circularly read the data in the BRAM starting from address 0, ensuring that the data is continuously sent to the DAC.

[0033] Data forwarding module: Through the data forwarding module, send the processed data to the DAC data port according to the timing requirements of the DAC interface, ensuring the accuracy and real-time of data transmission.

[0034] 4. High reliability and stability:

[0035] Data integrity: Ensure the integrity and reliability of the data by parsing and storing valid data packets.

[0036] Circular sending mechanism: Circularly read and send data to avoid data loss or interruption, improving the stability of the system.

[0037] 5. Strong adaptability:

[0038] Support for multiple DAC interfaces: According to the different DAC interfaces, flexibly adjust the timing and method of data sending to adapt to multiple DAC devices.

[0039] Scalability: This solution has good scalability and can adjust the configuration of the BRAM and the logic of data processing according to needs to adapt to different application scenarios.

[0040] 6. Low latency and high real-time performance:

[0041] Real-time data processing: The parallel processing ability of the FPGA and the high-speed data forwarding module ensure low latency and high real-time performance of the data, making it suitable for application scenarios with high real-time requirements.

[0042] The DAC data transmission method based on FPGA provided by the present invention has the advantages of high efficiency, flexibility, reliability, strong adaptability, and low latency, and can effectively meet the requirements for DAC data transmission in a variety of application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0044] Figure 1 It is a schematic flow chart of the method provided by the embodiment of the present invention.

[0045] Figure 2 It is a schematic flow chart of Step 2 provided by the embodiment of the present invention.

[0046] Figure 3 It is a schematic flow chart of Steps 3 to 5 provided by the embodiment of the present invention.

[0047] Figure 4 It is a schematic diagram of the FPGA firmware design framework provided by the embodiment of the present invention.

[0048] Figure 5 It is a circuit diagram of the hardware connection provided by the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0049] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0050] The purpose of the present invention is to provide a data transmission method with high efficiency in data reception and parsing, flexible data storage, high efficiency in data processing and forwarding, high reliability and stability, strong adaptability, and low latency and high real-time performance.

[0051] To make the above objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0052] Embodiment 1:

[0053] This embodiment provides a DAC data transmission method based on FPGA. Through the cooperation of the host computer and software, the host computer reads the TXT document in the specified path and transmits the data in the document to the RAM of the FPGA. After internal processing by the FPGA, the data is sent to the DAC using different interface forms, realizing the adjustability of the DAC output. As Figures 1 - 3 shown, the specific steps include:

[0054] Step 1: The host computer issues DAC data;

[0055] Step 2: The FPGA receives data from the serial port of the serial port chip and parses the data; the FPGA converts the received single-bit serial data into 8-bit parallel data, and at the same time parses the data to retain the valid data packet; the valid data packet includes DAC valid data; the serial communication baud rate is 115200 Baud, and the actual number of data used can be configured by the host computer.

[0056] Step 3: The FPGA stores the data; the FPGA calls an IP core of a BRAM as the data storage space, and writes the DAC valid data parsed in Step 2 into the BRAM space for storage. Each address of the BRAM stores 8-bit DAC data, and the BRAM adjusts the IP core configuration of the BRAM to 8-bit to 16-bit or 8-bit to 32-bit according to the different bit widths of the DAC data;

[0057] Step 4: The FPGA processes the data; the data in the RAM is read out one by one from the 0 address and sent to the data forwarding module. After reading the last DAC data issued by the host computer, continue to start the next round of data reading, still reading from the 0 address to the last address of the valid data, and sending the data in this pattern in a loop;

[0058] Step 5: The FPGA forwards the data; the data processed in Step 4 is sequentially sent to the data forwarding module, and the data forwarding module sends the data to the DAC data interface according to the corresponding timing or method according to the different DAC interfaces; for example, if the DAC data terminal is a JESD204B interface, the data forwarding module sequentially sends the data processed in Step 3 to the 204B interface; if the DAC data terminal is an LVDS interface, the data forwarding module sends the data processed in Step 3 to the DAC data port in the form of LVDS.

[0059] Step 6: The data enters the DAC data interface.

[0060] In one embodiment, the connection method of the hardware used for data transmission is as follows:

[0061] The host computer is connected to the FPGA through a serial port chip. The serial port chip is selected as the MAX13236EETE chip, which converts the URAT interface at the FPGA end into a USB port and connects it to the host computer. The power supply of the MAX13236EETE chip is 3.3V. The FPGA_RX pin is connected to the PIN6 pin of the serial port chip, and the FPGA_TX pin is connected to the PIN8 pin of the serial port chip. A DB9 interface is reserved on the test board. When in use, the male head of the DB9 interface is connected to the female head end of the RS-232 to USB cable, and the other end USB interface is connected to the host computer. The hardware circuit diagram is as Figure 5 shown.

[0062] In one embodiment, as Figure 4 shown, the host computer is connected to the serial port chip through a serial cable. The serial port chip is connected to the serial data parsing module on the FPGA, and the serial data parsing module is connected to the data storage module; the data storage module is connected to the data forwarding module, and the data forwarding module is connected to the DAC through the DAC data line.

[0063] In one embodiment, the setting method of the software used for data transmission includes:

[0064] The host computer installs the RS-232 driver so that after the host computer is connected to the test board, the host computer can recognize the serial port in the device manager;

[0065] The TestSystem.exe software is installed in the host computer. Through this software, the data in the local path is read and the data is sent to the FPGA;

[0066] Set the register to design the number of data to be sent to the FPGA;

[0067] CB1.SetRegDACta(0X1005,0X00)

[0068] CB1.SetRegDACta(0X1006,0X800) #16-bit data number

[0069] CB1.SetRegDACta(0X1007,0X00)

[0070] CB1.SetRegDACta(0X1007,0X01)

[0071] CB1.SetRegDACta(0X000A,0X400) # The number of 32-bit data.

[0072] Save the DAC sine data to a TXT document. Set the path through software: aa = Sys.ReaDACllText("C:\Users\E00077\Desktop\XIANGMU\B8831\SHUJU.txt") # Data path.

[0073] Run the software, read the data in the TXT and send it.

[0074] DACTA = Sys.SubStrToByteArray(aa)

[0075] CB1.brustWriteDACta(0x00,DACTA).

[0076] In this specification, each embodiment is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For the system disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method section.

[0077] In this article, specific examples are used to elaborate on the principle and implementation of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. At the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation and application scope. In summary, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A DAC data transmission method based on FPGA, characterized in that, Including: Step 1: The host computer issues DAC data. Step 2: The FPGA receives data from the serial port of the serial port chip and parses the data; the FPGA converts the received single-bit serial data into 8-bit parallel data, and at the same time parses the data, retaining the valid data packets, and the valid data packets include DAC valid data. Step 3: The FPGA stores the data; the FPGA calls an IP core of a BRAM as the data storage space, writes the DAC valid data parsed in Step 2 into the BRAM space for storage, each address of the BRAM stores 8-bit DAC data, and the BRAM adjusts the IP core configuration of the BRAM to 8-bit to 16-bit or 8-bit to 32-bit according to the different bit widths of the DAC data. Step 4: The FPGA processes the data; reads the data in the RAM address by address starting from the 0 address and sends it to the data forwarding module. When the last DAC data issued by the host computer is read, continue to start the next round of data reading, still reading from the 0 address to the last address of the valid data, and sending the data in this regular cycle. Step 5: The FPGA forwards the data; sends the data processed in Step 4 to the data forwarding module in sequence, and the data forwarding module sends the data to the DAC data interface according to the corresponding timing or method according to the different DAC interfaces. Step 6: The data enters the DAC data interface.

2. The DAC data transmission method based on FPGA according to claim 1, wherein The connection method of the hardware used for data transmission is: The host computer is connected to the FPGA through a serial port chip. The serial port chip selects the MAX13236EETE chip, converts the URAT interface at the FPGA end into a USB port and connects it to the host computer; the power supply of the MAX13236EETE chip is 3.3V, the FPGA_RX pin is connected to the PIN6 pin of the serial port chip, and the FPGA_TX pin is connected to the PIN8 pin of the serial port chip; a DB9 interface is reserved on the test board, and when in use, the male head of the DB9 interface is connected to the female head end of the RS-232 to USB cable, and the other end USB interface is connected to the host computer.

3. The DAC data transmission method based on FPGA according to claim 2, wherein, The host computer is connected to the serial port chip through a serial port cable. The serial port chip is connected to the serial data parsing module on the FPGA, and the serial data parsing module is connected to the data storage module; the data storage module is connected to the data forwarding module, and the data forwarding module is connected to the DAC through the DAC data line.

4. The DAC data transmission method based on FPGA according to claim 1, wherein The setting method of the software used for data transmission includes: The host computer installs the RS-232 driver so that after the host computer is connected to the test board, the host computer can recognize the serial port in the device manager. Install the TestSystem.exe software in the host computer, read the data in the local path through this software and issue the data to the FPGA. Set the register to design the number of data to be sent to the FPGA. Save the DAC sine data to a TXT document and set the path through the software. Run the software, read the data in the TXT and issue it.

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