Communication management method and device based on APB bus, equipment and storage medium

Abstract

The invention relates to a communication management method and device based on an APB bus, computer equipment and a storage medium. The method comprises the following steps: receiving an address signal sent by the microcontroller through the APB main interface, and judging whether the address signal is valid or not; in response to the fact that the address signal is valid, performing segmentation judgment on the address signal through a preset address mapping table, determining a target APB slave interface and a target register corresponding to the address signal, and establishing connection between the target APB slave interface and the microcontroller; and in response to a control command of the microcontroller, executing read-write operation on the target register from the interface through the target APB. By adopting the method, the selection of the APB slave interface can be realized through the APB handshake signal and the address segmentation judgment, the wiring congestion of the APB bus is reduced, the delay of the MCU accessing the APB slave interface is reduced, and the access conflict generated by a plurality of APB slave interfaces is avoided.

Description

Technical Field

[0001] The present application relates to the field of bus interface technology, and in particular to a communication management method, device, computer equipment and storage medium based on an APB bus. Background Art

[0002] The APB bus is a low-power, simple and flexible bus architecture, mainly used to connect the communication between the processor and the peripherals. In many embedded systems, the MCU is the master device and the peripheral modules are the slave devices, communicating through the APB bus. Since there are multiple groups of APB bus slave interfaces in the peripheral modules that need to be controlled by the MCU, the prior art usually uses bus interconnection to connect the communication of multiple functional blocks, processors, memories and peripherals. Specifically, the MCU and the bus interconnection are connected through a group of APB bus interfaces, and the bus interconnection adopts a distributed switching structure to realize the interconnection with each peripheral module, so that the MCU can control multiple APB slave interfaces through one APB master interface.

[0003] However, there are still some problems in the actual application of the bus interconnection of the distributed switching structure. For example, too many APB buses connected to the interconnection bus increase power consumption and area, which will cause wiring congestion problems in chip design. In addition, when multiple APB slave interfaces request access at the same time, access conflicts are prone to occur, which increases the waiting time of the bus and affects the overall performance of the system. Summary of the invention

[0004] Based on this, it is necessary to provide a communication management method, apparatus, computer equipment and storage medium based on an APB bus that can automatically identify the selected APB slave interface in order to solve the above technical problems.

[0005] On the one hand, a communication management method based on an APB bus is provided, wherein the APB bus is used to connect a microcontroller and a peripheral module, the microcontroller includes an APB master interface, the peripheral module includes a plurality of APB slave interfaces, and the APB slave interface is connected to at least one group of registers, the method comprising:

[0006] receiving an address signal sent by the microcontroller through the APB master interface, and determining whether the address signal is valid;

[0007] In response to the address signal being valid, segmenting and judging the address signal through a preset address mapping table, determining a target APB slave interface and a target register corresponding to the address signal, and establishing a connection between the target APB slave interface and the microcontroller;

[0008] In response to a control command from the microcontroller, a read and write operation is performed on the target register through the target APB slave interface.

[0009] In one embodiment, the method further comprises:

[0010] Establishing a mapping relationship between the APB slave interface and the address segment of the address signal;

[0011] An address mapping table is constructed according to the mapping relationship, so that the microcontroller generates address signals corresponding to the target APB slave interface and the target register according to the address mapping table.

[0012] In one embodiment, receiving an address signal sent by the microcontroller through the APB master interface and determining whether the address signal is valid includes:

[0013] detecting a selection signal sent by the microcontroller;

[0014] In response to detecting that the selection signal is pulled high, receiving an address signal sent by the microcontroller, the address signal including an address of the target register;

[0015] Matching the address signal with the address mapping table;

[0016] In response to the address signal existing in the address mapping table and the address of the target register being valid, it is determined that the address signal is valid.

[0017] In one of the embodiments, in response to the address signal being valid, segmenting the address signal through a preset address mapping table to determine the target APB slave interface and the target register corresponding to the address signal, including:

[0018] In response to the address signal being valid, acquiring a first address interval and a second address interval of the address signal, wherein the first address interval is a high-order address and the second address interval is a low-order address;

[0019] The first address interval is segmented and judged according to the address mapping table to determine the target APB slave interface corresponding to the first address interval, and the target register corresponding to the target APB slave interface is determined through the second address interval.

[0020] In one embodiment, segmenting the first address interval according to the address mapping table to determine the target APB slave interface corresponding to the first address interval, and determining the target register corresponding to the target APB slave interface through the second address interval includes:

[0021] Dividing the first address interval into a plurality of address segments according to a mapping relationship between the APB slave interface and the address segments of the address signal in the address mapping table;

[0022] detecting the most significant bit in the first address interval;

[0023] In response to the most significant bit being at a low level, determining a first APB slave interface range according to the address mapping table;

[0024] Detecting the level of each position of the first address segment in the first address interval, and determining the target APB slave interface from the first APB slave interface range according to the level of each position of the first address segment;

[0025] In response to the most significant bit being at a high level, determining a second APB slave interface range according to the address mapping table;

[0026] Detecting the level of each position of the second address segment in the first address interval, and determining the target APB slave interface from the second APB slave interface range according to the level of each position of the second address segment;

[0027] After determining the target APB slave interface, a selection signal of the target APB slave interface is pulled high, so that the target APB slave interface determines a target register according to the second address interval.

[0028] In one of the embodiments, the method further includes: in response to the existence of target registers with the same address in multiple APB slave interfaces, saving the mapping relationship between the broadcast mode of the multiple APB slave interfaces and the address segment of the address signal in the address mapping table; in response to determining to start the broadcast mode for the multiple APB slave interfaces according to the address signal and the address mapping table, establishing a connection between the multiple APB slave interfaces and the microcontroller; in response to the control command of the microcontroller, simultaneously performing read and write operations on the target registers with the same address in the multiple APB slave interfaces through the broadcast mode.

[0029] In one of the embodiments, in response to the control command of the microcontroller, performing read and write operations on the target register through the target APB slave interface includes: after determining the target APB slave interface, pulling up the selection signal of the APB slave interface to allow the microcontroller to send control commands through the APB bus; and performing read and write operations on the target register according to the control command.

[0030] On the other hand, a communication management device based on an APB bus is provided, wherein the APB bus is used to connect a microcontroller and a peripheral module, wherein the microcontroller includes an APB master interface, and the peripheral module includes a plurality of APB slave interfaces, wherein the APB slave interfaces are connected to at least one group of registers, and wherein the device includes:

[0031] A receiving module, used for receiving an address signal sent by the microcontroller through the APB main interface, and determining whether the address signal is valid;

[0032] A determination module, configured to, in response to the address signal being valid, perform segmented judgment on the address signal through a preset address mapping table, determine a target APB slave interface and a target register corresponding to the address signal, and establish a connection between the target APB slave interface and the microcontroller;

[0033] A response module is used to respond to the control command of the microcontroller and perform read and write operations on the target register through the target APB slave interface.

[0034] In another aspect, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the following steps are implemented:

[0035] receiving an address signal sent by the microcontroller through the APB master interface, and determining whether the address signal is valid;

[0036] In response to the address signal being valid, segmenting and judging the address signal through a preset address mapping table, determining a target APB slave interface and a target register corresponding to the address signal, and establishing a connection between the target APB slave interface and the microcontroller;

[0037] In response to a control command from the microcontroller, a read and write operation is performed on the target register through the target APB slave interface.

[0038] In another aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0039] receiving an address signal sent by the microcontroller through the APB master interface, and determining whether the address signal is valid;

[0040] In response to the address signal being valid, segmenting and judging the address signal through a preset address mapping table, determining a target APB slave interface and a target register corresponding to the address signal, and establishing a connection between the target APB slave interface and the microcontroller;

[0041] In response to a control command from the microcontroller, a read and write operation is performed on the target register through the target APB slave interface.

[0042] The above-mentioned communication management method, device, computer equipment and storage medium based on the APB bus manage all APB slave interfaces that need to be controlled by the microcontroller through APB handshake signals and address segmentation, and determine the target APB slave interface and target register corresponding to the address signal sent by the MCU through the address mapping table, thereby reducing multiple APB slave interfaces connected to the interconnection bus to one, thereby reducing the bandwidth bottleneck, delay, power consumption and physical layout complexity of the interconnection bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a structural block diagram of an SSD master control chip in the prior art;

[0044] Figure 2 A flowchart of a communication management method based on an APB bus in one embodiment;

[0045] Figure 3 This is a structural block diagram of an SSD master control chip in an embodiment;

[0046] Figure 4 APB bus connection diagram of a PCIE subsystem in one embodiment;

[0047] Figure 5 APB bus connection diagram in broadcast mode in one embodiment;

[0048] Figure 6 is a structural block diagram of a communication management device based on an APB bus in one embodiment;

[0049] Figure 7 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0051] like Figure 1As shown in the figure, taking the architecture of the SSD (Solid State Drive) main control chip as an example, it includes MCU, NIC400, PCIE subsystem and DDR subsystem, and each part is connected by APB bus. The main control chip is responsible for managing and controlling the operation and data transmission of the entire SSD, just like the "brain" of the SSD, coordinating, controlling and managing storage chips, data caching and data transmission. With the continuous popularization of solid-state drives in the storage market, the performance and stability requirements for SSD main control chips are getting higher and higher. PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) is widely used in data transmission between SSD main control chips and hosts. Compared with traditional SATA interface SSDs, PCIE interface SSDs have higher speed and performance and lower latency.

[0052] APB bus (Advanced Peripheral Bus) is a low-power, simple and flexible bus architecture, mainly used to connect the communication between the processor and the peripherals. In the PCIE subsystem, the PCIE function is mainly divided into two parts: the controller and the physical sublayer. In the PCIE controller and the physical sublayer, multiple groups of registers are given to the MCU (Microcontroller Unit) in the SSD main control chip for control. When designing, the PCIE register uses the APB bus to communicate with the MCU. The MCU is the master device and the PCIE subsystem is the slave device. Since the PCIE subsystem has multiple groups of APB bus interfaces that need to be controlled by the MCU, the existing technology uses NIC400 as the bus interconnection. The MCU is interconnected with the PCIE subsystem and the DDR subsystem respectively through NIC400. NIC400 is used to connect the communication of various functional blocks, processors, memories, peripherals and other components. The use of a distributed switching structure can avoid bottlenecks and conflicts in the bus interconnection process, but it will cause wiring congestion problems during chip design.

[0053] In one embodiment, Figure 2-4 As shown, a communication management method based on an APB bus is provided, wherein the APB bus is used to connect a microcontroller and a peripheral module, the microcontroller includes an APB master interface, and the peripheral module includes multiple APB slave interfaces. The method includes the following steps:

[0054] Step S1, receiving an address signal sent by the microcontroller through the APB main interface, and determining whether the address signal is valid.

[0055] In one embodiment, the method also includes: establishing a mapping relationship between the APB slave interface and the address segment of the address signal; constructing an address mapping table based on the mapping relationship, so that the microcontroller generates an address signal corresponding to the target APB slave interface and the target register according to the address mapping table.

[0056] like Figure 3 As shown, taking the SSD main control chip as an example, the MCU communicates with the PCIE subsystem. Two PCIE controllers and two PCIE physical sublayers are used in the design of the PCIE subsystem. The PCIE controller and the PCIE physical layer are interconnected through the PIPE interface. In the PCIE initialization stage, the registers of the PCIE controller and the PCIE physical sublayer need to be configured. In order to facilitate the MCU to control each register of the PCIE controller and the PCIE physical sublayer, the APB bus is uniformly used to communicate with the MCU during the design. Each PCIE controller has an APB slave interface, such as APB0 and APB3, and each PCIE physical layer has two APB slave interfaces, such as APB1, APB2, APB4, and APB5. All APB slave interfaces are uniformly managed and controlled by the APB management module.

[0057] In the APB management module, by specifying the address mapping table corresponding to the APB slave interface, a unique mapping relationship between multiple APB slave interfaces and the high bits of the address bus is defined in the mapping table. The MCU will send the address signal corresponding to the target APB slave interface according to the address mapping table, thereby accessing the target APB slave interface. Table 1 is an example of an address mapping table, as shown below.

[0058] Table 1 Address mapping table

[0059]

[0060] As shown in Table 1, in the PCIe subsystem, since different APB buses control different numbers of registers, the bit widths of the APB bus addresses assigned to the registers are different, but the registers controlled by all APB slave interfaces will not exceed the address space of 0 to 20 bits. For example, APB2 and APB5 control more registers, so the APB bus address signal [17:0] bits are used in address allocation, while other APB slave interfaces only use the APB bus address signal [11:0] bits.

[0061] It can be understood that, in this embodiment, since the PCIE subsystem in the SSD master control chip used includes a total of 6 APB slave interfaces, a bus address is assigned to each APB slave interface through the address mapping table shown in Table 1, and the bit width occupied by the address is assigned according to the number of registers. In actual applications, the address mapping table can be designed according to the number of registers to be configured and the number of APB slave interfaces used.

[0062] Based on the above steps, by using the APB management module, multiple APB slave interfaces can be effectively managed, and the address mapping table can be designed through the mapping relationship between the APB slave interface and the address segment, so that the selection of the APB slave interface can be achieved by segmenting the address signal, which simplifies the design of the APB management module, thereby reducing the physical layout complexity, power consumption and area of ​​the interconnection bus, and improving the overall performance and reliability of the system.

[0063] In another embodiment, when the microcontroller is connected to multiple external devices through the APB bus, the logic resources of the field programmable gate array can be used to implement the APB expansion bus interface, and the APB expansion bus interface includes multiple bus connectors, each of which is connected to a corresponding external device, and includes an external device controller and at least one group of registers; the external device address space is address segmented according to the address depth of the register of the connected bus connector, and a mapping relationship is formed between the address segment and the register address; a peripheral address mapping table is constructed according to the mapping relationship, so that the peripheral address signal sent by the microcontroller through the APB bus is mapped into the register address signal of the corresponding bus connector according to the address mapping table, and further sent to the bus connector; in response to the control command sent by the microcontroller, the external device controller performs read and write operations on the register according to the register address signal.

[0064] In one embodiment, the receiving of the address signal sent by the microcontroller through the APB main interface and determining whether the address signal is valid include: detecting a selection signal sent by the microcontroller; in response to detecting that the selection signal is pulled high, receiving the address signal sent by the microcontroller, the address signal including the address of the target register; matching the address signal with the address mapping table; and in response to the presence of the address signal in the address mapping table and the address of the target register being valid, determining that the address signal is valid.

[0065] For example, take the MCU accessing a register of the APB4 slave interface in the PCIE subsystem as an example, the address of the register is represented by 12'bx. When the APB management module detects that the MCU's selection signal is pulled high, it determines that the MCU wants to access the APB slave interface in the PCIe subsystem. At this time, the MCU will send the address 21'b100000011x through the APB master interface according to the address mapping table. Since the data bit width is 32 bits, each address sent by the MCU is a 4-byte aligned address.

[0066] Based on the above steps, the validity of the address signal is ensured in this way, and by detecting the level of the selection signal, it is determined when the MCU is allowed to access the APB slave interface, thereby improving the accuracy and efficiency of the system's access to the register.

[0067] Step S2, in response to the address signal being valid, segmenting the address signal through a preset address mapping table, determining the target APB slave interface and target register corresponding to the address signal, and establishing a connection between the target APB slave interface and the microcontroller.

[0068] In one embodiment, in response to the address signal being valid, the address signal is segmented and judged through a preset address mapping table to determine the target APB slave interface and target register corresponding to the address signal, including: in response to the address signal being valid, obtaining the first address interval and the second address interval of the address signal, the first address interval being a high-order address, and the second address interval being a low-order address; segmenting and judging the first address interval according to the address mapping table to determine the target APB slave interface corresponding to the first address interval, and determining the target register corresponding to the target APB slave interface through the second address interval.

[0069] Among them, the first address interval is the address range corresponding to the APB slave interface, which is used to distinguish different APB slave interfaces. The second address interval is used to determine the specific register address. According to the different number of registers controlled by each APB slave interface, the bit width of the APB bus address allocated to the register is different, but the registers controlled by all APB slave interfaces will not exceed the address space of 0 to 20 bits.

[0070] In one embodiment, the segmentation judgment of the first address interval is performed according to the address mapping table, the target APB slave interface corresponding to the first address interval is determined, and the target register corresponding to the target APB slave interface is determined through the second address interval, including: dividing the first address interval into multiple address segments according to the mapping relationship between the APB slave interface and the address segment of the address signal in the address mapping table; detecting the most significant bit in the first address interval; in response to the most significant bit being a low level, determining the first APB slave interface range according to the address mapping table; detecting the first The method comprises the steps of: detecting each position level of the address segment, and determining the target APB slave interface from the first APB slave interface range according to each position level of the first address segment; determining the second APB slave interface range according to the address mapping table in response to the most significant bit being a high level; detecting each position level of the second address segment in the first address interval, and determining the target APB slave interface from the second APB slave interface range according to each position level of the second address segment; after determining the target APB slave interface, pulling up the selection signal of the target APB slave interface so that the target APB slave interface determines the target register according to the second address interval.

[0071] Specifically, the address segmentation judgment method based on the address mapping table in Table 1 is: first detect the level of the address signal

[20] bit. When the address signal

[20] bit is detected to be 0, the possible APB slave interface range includes APB2 and APB5, and then detect the address signal

[18] bit to determine the specific APB slave interface; when the address signal

[20] bit is detected to be 1, the possible APB slave interface range includes APB0, APB1, APB3, APB4, and then detect the address signal [13:12] bits to determine which APB slave interface is accessed.

[0072] For example, when the MCU wants to access the APB4 slave interface, the 20th bit of the address signal sent by the MCU is determined. At this time, the 20th bit is 1, and the APB0, APB3, APB1, and APB4 branches are judged. Then the [13:12]th bit of the address signal is obtained. At this time, the [13:12]th bit of the address signal is 2'b11, and the selection signal of the APB4 slave interface in the PCIe subsystem is pulled high, indicating that the APB4 slave interface is selected. The APB4 slave interface searches for the register of the corresponding address according to the [11:0] bit of the address signal, and reads and writes the register according to the instruction sent by the MCU.

[0073] It should be noted that in the prior art, when the MCU accesses a certain APB slave interface, it will also judge and select the APB slave interface according to the APB bus address signal, but generally a relatively large bit width address is used for logical judgment, for example, the address signal [20:12] in Table 1 is used to select and judge the APB slave interface, but the signal with a large bit width will cause wiring congestion and difficulty in timing convergence during chip design. In this embodiment, the selection of the APB slave interface is realized by the APB handshake signal and the address segmentation judgment method through the address segmentation judgment method, which simplifies the design of the APB management module, reduces wiring congestion, reduces the delay of the MCU accessing the APB slave interface, avoids access conflicts of multiple APB slave interfaces, reduces the waiting time of the bus, and reduces the number of interfaces connected to the interconnection bus, thereby reducing the physical layout complexity, power consumption and area of ​​the interconnection bus, and improving the performance of the interconnection bus.

[0074] In one embodiment, the method further includes: in response to the existence of target registers with the same address in multiple APB slave interfaces, saving the mapping relationship between the broadcast mode of the multiple APB slave interfaces and the address segment of the address signal in the address mapping table; in response to determining to start the broadcast mode for the multiple APB slave interfaces according to the address signal and the address mapping table, establishing a connection between the multiple APB slave interfaces and the microcontroller; in response to the control command of the microcontroller, simultaneously performing read and write operations on the target registers with the same address in the multiple APB slave interfaces through the broadcast mode.

[0075] like Figure 5 As shown in FIG. 1 , when the MCU expects to configure registers with the same address to multiple APB slave interfaces at one time, for example, to write to registers with the same address in APB2 and APB5 at the same time, a set of address mapping relationships can be added to the address mapping table of the APB management module to implement the broadcast function. The new address mapping table is as follows: Figure 2 shown.

[0076] Table 2 Address mapping table with broadcast mode

[0077]

[0078] As shown in Table 2, when the APB management module detects that [20:18] in the address signal is 010, it confirms that the broadcast mode is turned on for the APB2 and APB5 slave interfaces, so that the MCU can simultaneously control the APB2 and APB5 slave interfaces to read and write registers.

[0079] Based on the above steps, when the MCU expects to configure registers with the same address to multiple APB slave interfaces at one time, by adding the mapping relationship of the broadcast mode to the address mapping table, the MCU can control multiple registers with the same address at the same time, reducing the MCU configuration process and improving the performance of the interconnect bus.

[0080] Step S3, in response to the control command of the microcontroller, performing read and write operations on the target register through the target APB slave interface.

[0081] In one embodiment, in response to the control command of the microcontroller, the read and write operations are performed on the target register through the target APB slave interface, including: after determining the target APB slave interface, pulling up the selection signal of the APB slave interface to allow the microcontroller to send control commands through the APB bus; and performing read and write operations on the target register according to the control command.

[0082] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0083] In one embodiment, Figure 6 As shown, a communication management device based on an APB bus is provided, comprising: a receiving module, a determining module and a responding module, wherein:

[0084] A receiving module, used for receiving an address signal sent by the microcontroller through the APB main interface, and determining whether the address signal is valid;

[0085] A determination module, configured to, in response to the address signal being valid, perform segmented judgment on the address signal through a preset address mapping table, determine a target APB slave interface and a target register corresponding to the address signal, and establish a connection between the target APB slave interface and the microcontroller;

[0086] A response module is used to respond to the control command of the microcontroller and perform read and write operations on the target register through the target APB slave interface.

[0087] In one embodiment, the device also includes a mapping module, which is used to establish a mapping relationship between the APB slave interface and the address segment of the address signal; construct an address mapping table according to the mapping relationship, so that the microcontroller generates the address signal corresponding to the target APB slave interface and the target register according to the address mapping table.

[0088] In one embodiment, the receiving module is also used to detect a selection signal sent by the microcontroller; in response to detecting that the selection signal is pulled high, receiving an address signal sent by the microcontroller, the address signal including the address of the target register; matching the address signal with the address mapping table; in response to the address signal existing in the address mapping table and the address of the target register being valid, determining that the address signal is valid.

[0089] In one embodiment, the determination module is also used to obtain a first address interval and a second address interval of the address signal in response to the address signal being valid, the first address interval being a high-order address, and the second address interval being a low-order address; perform segmented judgment on the first address interval according to the address mapping table, determine the target APB slave interface corresponding to the first address interval, and determine the target register corresponding to the target APB slave interface through the second address interval.

[0090] In one embodiment, the determination module is also used to divide the first address interval into multiple address segments according to the mapping relationship between the APB slave interface and the address segment of the address signal in the address mapping table; detect the most significant bit in the first address interval; in response to the most significant bit being a low level, determine the first APB slave interface range according to the address mapping table; detect the position levels of each position of the first address segment in the first address interval, and determine the target APB slave interface from the first APB slave interface range according to the position levels of each position of the first address segment; in response to the most significant bit being a high level, determine the second APB slave interface range according to the address mapping table; detect the position levels of each position of the second address segment in the first address interval, and determine the target APB slave interface from the second APB slave interface range according to the position levels of each position of the second address segment; after determining the target APB slave interface, pull up the selection signal of the target APB slave interface so that the target APB slave interface determines the target register according to the second address interval.

[0091] In one embodiment, the device also includes a broadcast module, which is used to save the mapping relationship between the broadcast mode of the multiple APB slave interfaces and the address segment of the address signal in the address mapping table in response to the existence of target registers with the same address in multiple APB slave interfaces; establish connections between the multiple APB slave interfaces and the microcontroller in response to determining to start the broadcast mode for the multiple APB slave interfaces according to the address signal and the address mapping table; and perform read and write operations on the target registers with the same address in the multiple APB slave interfaces at the same time through the broadcast mode in response to the control command of the microcontroller.

[0092] In one embodiment, the response module is also used to pull up the selection signal of the APB slave interface after determining the target APB slave interface, allowing the microcontroller to send control commands through the APB bus; and perform read and write operations on the target register according to the control commands.

[0093] For the specific definition of the communication management device based on the APB bus, please refer to the definition of the communication management method based on the APB bus above, which will not be repeated here. The various modules in the above-mentioned communication management device based on the APB bus can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0094] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 7 As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store address mapping table data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a communication management method based on the APB bus is implemented.

[0095] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0096] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program:

[0097] receiving an address signal sent by the microcontroller through the APB master interface, and determining whether the address signal is valid;

[0098] In response to the address signal being valid, segmenting and judging the address signal through a preset address mapping table, determining a target APB slave interface and a target register corresponding to the address signal, and establishing a connection between the target APB slave interface and the microcontroller;

[0099] In response to a control command from the microcontroller, a read and write operation is performed on the target register through the target APB slave interface.

[0100] In one embodiment, when the processor executes the computer program, the following steps are also implemented: establishing a mapping relationship between the APB slave interface and the address segment of the address signal; constructing an address mapping table according to the mapping relationship, so that the microcontroller generates the address signal corresponding to the target APB slave interface and the target register according to the address mapping table.

[0101] In one embodiment, the processor further implements the following steps when executing the computer program: detecting a selection signal sent by the microcontroller; in response to detecting that the selection signal is pulled high, receiving an address signal sent by the microcontroller, the address signal including the address of the target register; matching the address signal with the address mapping table; in response to the address signal existing in the address mapping table and the address of the target register being valid, determining that the address signal is valid.

[0102] In one embodiment, when the processor executes the computer program, the following steps are also implemented: in response to the address signal being valid, a first address interval and a second address interval of the address signal are obtained, the first address interval is a high-order address, and the second address interval is a low-order address; segmenting the first address interval according to the address mapping table, determining the target APB slave interface corresponding to the first address interval, and determining the target register corresponding to the target APB slave interface through the second address interval.

[0103] In one embodiment, the processor further implements the following steps when executing the computer program: dividing the first address interval into multiple address segments according to the mapping relationship between the APB slave interface and the address segment of the address signal in the address mapping table; detecting the most significant bit in the first address interval; in response to the most significant bit being a low level, determining the first APB slave interface range according to the address mapping table; detecting the level of each position of the first address segment in the first address interval, and determining the target APB slave interface from the first APB slave interface range according to the level of each position of the first address segment; in response to the most significant bit being a high level, determining the second APB slave interface range according to the address mapping table; detecting the level of each position of the second address segment in the first address interval, and determining the target APB slave interface from the second APB slave interface range according to the level of each position of the second address segment; after determining the target APB slave interface, pulling up the selection signal of the target APB slave interface so that the target APB slave interface determines the target register according to the second address interval.

[0104] In one embodiment, the processor further implements the following steps when executing the computer program: in response to the existence of target registers with the same address in multiple APB slave interfaces, saving the mapping relationship between the broadcast mode of the multiple APB slave interfaces and the address segment of the address signal in the address mapping table; in response to determining to start the broadcast mode for the multiple APB slave interfaces according to the address signal and the address mapping table, establishing a connection between the multiple APB slave interfaces and the microcontroller; in response to the control command of the microcontroller, simultaneously performing read and write operations on the target registers with the same address in the multiple APB slave interfaces through the broadcast mode.

[0105] In one embodiment, when the processor executes the computer program, the following steps are also implemented: after determining the target APB slave interface, pulling up the selection signal of the APB slave interface to allow the microcontroller to send control commands through the APB bus; and performing read and write operations on the target register according to the control command.

[0106] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0107] receiving an address signal sent by the microcontroller through the APB master interface, and determining whether the address signal is valid;

[0108] In response to the address signal being valid, segmenting and judging the address signal through a preset address mapping table, determining a target APB slave interface and a target register corresponding to the address signal, and establishing a connection between the target APB slave interface and the microcontroller;

[0109] In response to a control command from the microcontroller, a read and write operation is performed on the target register through the target APB slave interface.

[0110] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: establishing a mapping relationship between the APB slave interface and the address segment of the address signal; constructing an address mapping table according to the mapping relationship, so that the microcontroller generates the address signal corresponding to the target APB slave interface and the target register according to the address mapping table.

[0111] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: detecting a selection signal sent by the microcontroller; in response to detecting that the selection signal is pulled high, receiving an address signal sent by the microcontroller, the address signal including the address of the target register; matching the address signal with the address mapping table; in response to the address signal existing in the address mapping table and the address of the target register being valid, determining that the address signal is valid.

[0112] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to the address signal being valid, a first address interval and a second address interval of the address signal are obtained, the first address interval is a high-order address, and the second address interval is a low-order address; segmenting the first address interval according to the address mapping table, determining the target APB slave interface corresponding to the first address interval, and determining the target register corresponding to the target APB slave interface through the second address interval.

[0113] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: according to the mapping relationship between the APB slave interface and the address segment of the address signal in the address mapping table, the first address interval is divided into multiple address segments; the most significant bit in the first address interval is detected; in response to the most significant bit being a low level, the first APB slave interface range is determined according to the address mapping table; the level of each position of the first address segment in the first address interval is detected, and the target APB slave interface is determined from the first APB slave interface range according to the level of each position of the first address segment; in response to the most significant bit being a high level, the second APB slave interface range is determined according to the address mapping table; the level of each position of the second address segment in the first address interval is detected, and the target APB slave interface is determined from the second APB slave interface range according to the level of each position of the second address segment; after determining the target APB slave interface, the selection signal of the target APB slave interface is pulled high so that the target APB slave interface determines the target register according to the second address interval.

[0114] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to the existence of target registers with the same address in multiple APB slave interfaces, the mapping relationship between the broadcast mode of the multiple APB slave interfaces and the address segment of the address signal is saved in the address mapping table; in response to determining to start the broadcast mode for the multiple APB slave interfaces according to the address signal and the address mapping table, the connection between the multiple APB slave interfaces and the microcontroller is established; in response to the control command of the microcontroller, the read and write operations are simultaneously performed on the target registers with the same address in the multiple APB slave interfaces through the broadcast mode.

[0115] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: after determining the target APB slave interface, pulling up the selection signal of the APB slave interface to allow the microcontroller to send control commands through the APB bus; and performing read and write operations on the target register according to the control command.

[0116] In one embodiment, a computer product is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0117] receiving an address signal sent by the microcontroller through the APB master interface, and determining whether the address signal is valid;

[0118] In response to the address signal being valid, segmenting and judging the address signal through a preset address mapping table, determining a target APB slave interface and a target register corresponding to the address signal, and establishing a connection between the target APB slave interface and the microcontroller;

[0119] In response to a control command from the microcontroller, a read and write operation is performed on the target register through the target APB slave interface.

[0120] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: establishing a mapping relationship between the APB slave interface and the address segment of the address signal; constructing an address mapping table according to the mapping relationship, so that the microcontroller generates the address signal corresponding to the target APB slave interface and the target register according to the address mapping table.

[0121] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: detecting a selection signal sent by the microcontroller; in response to detecting that the selection signal is pulled high, receiving an address signal sent by the microcontroller, the address signal including the address of the target register; matching the address signal with the address mapping table; in response to the address signal existing in the address mapping table and the address of the target register being valid, determining that the address signal is valid.

[0122] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to the address signal being valid, a first address interval and a second address interval of the address signal are obtained, the first address interval is a high-order address, and the second address interval is a low-order address; segmenting the first address interval according to the address mapping table, determining the target APB slave interface corresponding to the first address interval, and determining the target register corresponding to the target APB slave interface through the second address interval.

[0123] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: according to the mapping relationship between the APB slave interface and the address segment of the address signal in the address mapping table, the first address interval is divided into multiple address segments; the most significant bit in the first address interval is detected; in response to the most significant bit being a low level, the first APB slave interface range is determined according to the address mapping table; the level of each position of the first address segment in the first address interval is detected, and the target APB slave interface is determined from the first APB slave interface range according to the level of each position of the first address segment; in response to the most significant bit being a high level, the second APB slave interface range is determined according to the address mapping table; the level of each position of the second address segment in the first address interval is detected, and the target APB slave interface is determined from the second APB slave interface range according to the level of each position of the second address segment; after determining the target APB slave interface, the selection signal of the target APB slave interface is pulled high so that the target APB slave interface determines the target register according to the second address interval.

[0124] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to the existence of target registers with the same address in multiple APB slave interfaces, the mapping relationship between the broadcast mode of the multiple APB slave interfaces and the address segment of the address signal is saved in the address mapping table; in response to determining to start the broadcast mode for the multiple APB slave interfaces according to the address signal and the address mapping table, the connection between the multiple APB slave interfaces and the microcontroller is established; in response to the control command of the microcontroller, the read and write operations are simultaneously performed on the target registers with the same address in the multiple APB slave interfaces through the broadcast mode.

[0125] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: after determining the target APB slave interface, pulling up the selection signal of the APB slave interface to allow the microcontroller to send control commands through the APB bus; and performing read and write operations on the target register according to the control command.

[0126] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0127] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0128] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A communication management method based on APB bus, characterized in that: The APB bus is used to connect a microcontroller and a peripheral module, the microcontroller includes an APB master interface, the peripheral module includes a plurality of APB slave interfaces, the APB slave interface is connected to at least one group of registers, and the method includes: receiving an address signal sent by the microcontroller through the APB master interface, and determining whether the address signal is valid; In response to the address signal being valid, segmenting and judging the address signal through a preset address mapping table, determining a target APB slave interface and a target register corresponding to the address signal, and establishing a connection between the target APB slave interface and the microcontroller; In response to a control command from the microcontroller, a read and write operation is performed on the target register through the target APB slave interface.

2. The communication management method based on APB bus according to claim 1, characterized in that: The method further comprises: Establishing a mapping relationship between the APB slave interface and the address segment of the address signal; An address mapping table is constructed according to the mapping relationship, so that the microcontroller generates address signals corresponding to the target APB slave interface and the target register according to the address mapping table.

3. The communication management method based on APB bus according to claim 1 or 2, characterized in that: The receiving an address signal sent by the microcontroller through the APB main interface and determining whether the address signal is valid includes: detecting a selection signal sent by the microcontroller; In response to detecting that the selection signal is pulled high, receiving an address signal sent by the microcontroller, the address signal including an address of the target register; Matching the address signal with the address mapping table; In response to the address signal existing in the address mapping table and the address of the target register being valid, it is determined that the address signal is valid.

4. The communication management method based on APB bus according to claim 1 or 2, characterized in that: In response to the address signal being valid, segmenting the address signal through a preset address mapping table to determine a target APB slave interface and a target register corresponding to the address signal, including: In response to the address signal being valid, acquiring a first address interval and a second address interval of the address signal, wherein the first address interval is a high-order address and the second address interval is a low-order address; The first address interval is segmented and judged according to the address mapping table to determine the target APB slave interface corresponding to the first address interval, and the target register corresponding to the target APB slave interface is determined through the second address interval.

5. The communication management method based on APB bus according to claim 4, characterized in that: The segmenting and judging the first address interval according to the address mapping table, determining the target APB slave interface corresponding to the first address interval, and determining the target register corresponding to the target APB slave interface through the second address interval, includes: Dividing the first address interval into a plurality of address segments according to a mapping relationship between the APB slave interface and the address segments of the address signal in the address mapping table; detecting the most significant bit in the first address interval; In response to the most significant bit being at a low level, determining a first APB slave interface range according to the address mapping table; Detecting the level of each position of the first address segment in the first address interval, and determining the target APB slave interface from the first APB slave interface range according to the level of each position of the first address segment; In response to the most significant bit being at a high level, determining a second APB slave interface range according to the address mapping table; Detecting the level of each position of the second address segment in the first address interval, and determining the target APB slave interface from the second APB slave interface range according to the level of each position of the second address segment; After determining the target APB slave interface, a selection signal of the target APB slave interface is pulled high, so that the target APB slave interface determines a target register according to the second address interval.

6. The communication management method based on APB bus according to claim 1 or 2, characterized in that: The method further comprises: In response to the presence of target registers with the same address in multiple APB slave interfaces, storing a mapping relationship between the broadcast modes of the multiple APB slave interfaces and the address segments of the address signal in the address mapping table; In response to determining, according to the address signal and the address mapping table, to enable broadcast mode for the plurality of APB slave interfaces, establishing connections between the plurality of APB slave interfaces and the microcontroller; In response to a control command from the microcontroller, read and write operations are simultaneously performed on target registers at the same address in the plurality of APB slave interfaces through the broadcast mode.

7. The communication management method based on APB bus according to claim 1, characterized in that: The step of performing read and write operations on the target register through the target APB slave interface in response to a control command of the microcontroller comprises: After determining the target APB slave interface, pulling up a selection signal of the APB slave interface to allow the microcontroller to send a control command through the APB bus; Perform read and write operations on the target register according to the control command.

8. A communication management device based on APB bus, characterized in that: The APB bus is used to connect a microcontroller and a peripheral module, the microcontroller includes an APB master interface, the peripheral module includes a plurality of APB slave interfaces, the APB slave interface is connected to at least one group of registers, and the device includes: A receiving module, used for receiving an address signal sent by the microcontroller through the APB main interface, and determining whether the address signal is valid; A determination module, configured to, in response to the address signal being valid, perform segmented judgment on the address signal through a preset address mapping table, determine a target APB slave interface and a target register corresponding to the address signal, and establish a connection between the target APB slave interface and the microcontroller; A response module is used to respond to the control command of the microcontroller and perform read and write operations on the target register through the target APB slave interface.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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