PCIE (Peripheral Component Interface Express) bus-based Cameralink protocol communication module

Abstract

The invention provides a Cameralink protocol communication module based on a PCIE (Peripheral Component Interface Express) bus. The Cameralink protocol communication module comprises a signal processing carrier plate of a PCIE interface and a Cameralink protocol output daughter board, signals between the signal processing carrier board of the PCIE interface and the Cameralink protocol output daughter board are connected through an FMC interface. The signal processing carrier plate comprises an FPGA (Field Programmable Gate Array), a power supply module, a cache module and a clock module; the power supply module supplies power to the signal processing carrier plate and the Cameralink protocol output daughter board, the FPGA serves as a module processor and is responsible for logic processing of interaction between the PCIE bus and the Cameralink protocol, and the clock module provides an operation clock for the FPGA and the Cameralink protocol output daughter board; the FPGA receives image data and a control instruction through a PCIE bus, processes the received image data into a Medium mode image and a Base mode image, and stores the Medium mode image and the Base mode image to the cache module; sending the image data in the cache to a Cameralink protocol output daughter board according to a control command; and the Cameralink protocol output daughter board converts the image data into Cameralink protocol data and a clock and outputs the Cameralink protocol data and the clock.

Description

Technical Field

[0001] The present invention relates to the field of high-speed image transmission. The communication module can convert image data generated by a PCIE bus device (computer) into Cameralink protocol data and send it out. The computer can transmit images with other devices having a Cameralink protocol communication function through the module. Background Art

[0002] The Cameralink protocol is a bus interface specifically used for digital image transmission. Currently, various manufacturers on the market have launched a wide variety of Cameralink protocol image output products. Most of these products cannot flexibly output images from the user's computer. Although some products can change the output image through tools provided by the company, their adaptability is poor, the calling process is complicated and cannot meet the needs of users. Summary of the invention

[0003] The technical problem solved by the present invention is to provide a Cameralink protocol communication module based on a PCIE bus.

[0004] The technical solution of the present invention is: a Cameralink protocol communication module based on PCIE bus, including a signal processing carrier board of PCIE interface and a Cameralink protocol output subboard;

[0005] The signal between the signal processing carrier board of the PCIE interface and the Cameralink protocol output sub-board is connected through the FMC interface; the signal processing carrier board includes an FPGA, a power module, a cache module, and a clock module; the power module supplies power to the signal processing carrier board and the Cameralink protocol output sub-board, the FPGA is responsible for the logical processing of the interaction between the PCIE bus and the Cameralink protocol as a module processor, and the clock module provides a running clock for the FPGA and the Cameralink protocol output sub-board;

[0006] FPGA receives image data and control instructions through the PCIE bus, processes the received image data into Medium mode images and Base mode images, and stores them in the cache module; according to the control command, the image data in the cache is sent to the Cameralink protocol output daughter board;

[0007] The Cameralink protocol output daughter board converts the image data into Cameralink protocol data and clock and outputs them.

[0008] Preferably, the Cameralink protocol output daughter board is stacked on the signal processing carrier board of the PCIE interface.

[0009] Preferably, the FPGA implements PCIE bus interaction through a PCIE XJ3 connector and a PCIE XJ4 connector, and uses a ping-pong cache method to store the processed image data in two cache modules.

[0010] Preferably, the FPGA calls the XDMAIP core to receive image data and control instructions from the PCIE bus, and ping-pong caches the image data in a cache module inside the FPGA according to the control instructions. The Cameralink protocol IP core extracts the image data from the DDR3 SDRAM cache module according to the control instructions and converts it into Cameralink protocol data output.

[0011] Preferably, Nor BPI Flash and JTAG are arranged on the signal processing carrier board of the PCIE interface, Nor BPIFlash is used to store the logic code of FPGA; JTAG is used to support debugging during the module development process; and the FPGA logic code in Nor BPI Flash is updated by downloading through JTAG.

[0012] Preferably, the Cameralink protocol output daughter board includes a plurality of Cameralink transmission modules, an FMC interface and an output connector;

[0013] Every two Cameralink sending modules form a Cameralink sending channel in Medium mode, and the remaining Cameralink sending modules form a Cameralink sending channel in Base mode. The number of Cameralink sending channels is the same as the number of remaining Cameralink sending modules. The clock signal and image data are received through the FMC interface.

[0014] The Cameralink sending module of the corresponding mode converts the received Medium mode image and Base mode image into Cameralink data and Cameralink clock, and outputs the data and clock through the output connector.

[0015] Preferably, the Cameralink protocol output sub-board includes 4 Cameralink sending modules; 2 Cameralink sending modules constitute 1 Medium mode Cameralink sending channel, and the other 2 Cameralink sending modules constitute 2 Base mode Cameralink sending channels.

[0016] The beneficial effects of the present invention compared with the prior art are:

[0017] The present invention enables a computer based on a PCIE bus device to have a Cameralink protocol communication function, and can convert image data generated by the computer into Cameralink protocol data for transmission; and the communication module of the present invention has 4 Cameralink protocol transmission channels, and can simultaneously implement the data transmission of the Cameralink protocol in Medium mode and Base mode, and can perform image transmission in parallel.

[0018] The present invention can realize the transmission and output of the data generated by the user on the PCIE bus terminal according to the Cameralink protocol, meeting the interface requirements for high-speed transmission of analog images;

[0019] The present invention adopts a stacking structure of a carrier board and a daughter board, and the number of Cameralink sending modules can be changed by simply changing the design of the daughter board, thereby reducing production costs and shortening the development cycle;

[0020] The module of the present embodiment can simultaneously support 1 channel of Medium mode Cameralink protocol data transmission and 2 channels of Base mode Cameralink protocol data transmission;

[0021] The present invention ensures the correctness of image numbers and improves the reliability of the module through FPGA logic design and dual DDR3 SDRAM cache modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is the schematic diagram of the signal processing carrier board for the PCIE interface;

[0023] Figure 2 Output daughter board schematics for the Cameralink protocol. DETAILED DESCRIPTION

[0024] The present invention will be further described below in conjunction with the embodiments.

[0025] Figure 1 This is the schematic diagram of the signal processing carrier board of the PCIE interface. The carrier board consists of FPGA, power module, DDR3 SDRAM cache module, clock module, Nor BPI Flash, JTAG, FMC interface, PCIE XJ3 connector and PCIE XJ4 connector. Nor BPI Flash is used to store the logic code of FPGA; JTAG is used to support debugging during the module development process; the FPGA logic code in Nor BPI Flash can be downloaded and updated through JTAG.

[0026] Figure 2This is the schematic diagram of the Cameralink protocol output daughter board, which consists of 4 Cameralink send modules, FMC interface and output connector. 2 Cameralink send modules can form 1 Medium mode Cameralink send channel, and the other 2 Cameralink send modules can form 2 Base mode Cameralink send channels.

[0027] The Cameralink protocol output daughter board is stacked on the signal processing carrier board of the PCIE interface to form a Cameralink protocol communication module based on the PCIE bus. All signals between the carrier board and the daughter board are connected through the FMC interface. The power module takes power from the PCIE XJ3 connector and supplies power to the carrier board and daughter board after voltage conversion and ripple processing; the clock module provides the necessary reference clock for the carrier board and daughter board during operation.

[0028] The signal processing carrier board of the PCIE interface is developed and designed based on Xilinx's FPGA. As the processor of the communication module, FPGA is responsible for all logic and data interaction. FPGA realizes PCIE bus interaction through PCIE XJ3 connector and PCIE XJ4 connector. FPGA receives computer-generated image data and control instructions from PCIE bus by calling XDMAIP core; FPGA ping-pong caches the image data received from the computer in the DDR3 SDRAM cache module inside FPGA according to the control instructions. The ping-pong cache method can avoid conflicts in image data storage and retrieval, and ensure the correctness of stored and retrieved data; FPGA's Cameralink protocol IP core extracts image data from the DDR3 SDRAM cache module according to the control instructions and converts it into Medium image data and Base mode image of Cameralink protocol and sends it to Cameralink protocol output daughter board; Cameralink transmission module of Cameralink protocol output daughter board receives processed image data and converts it into Cameralink data and Cameralink clock, and outputs data and clock through the output connector on the daughter board.

[0029] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

[0030] Parts not described in detail in the present invention belong to common knowledge of those skilled in the art.

Claims

1. A Cameralink protocol communication module based on PCIE bus, characterized in that: Including PCIE interface signal processing carrier board and Cameralink protocol output daughter board; The signal between the signal processing carrier board of the PCIE interface and the Cameralink protocol output sub-board is connected through the FMC interface; the signal processing carrier board includes an FPGA, a power module, a cache module, and a clock module; the power module supplies power to the signal processing carrier board and the Cameralink protocol output sub-board, the FPGA is responsible for the logical processing of the interaction between the PCIE bus and the Cameralink protocol as a module processor, and the clock module provides a running clock for the FPGA and the Cameralink protocol output sub-board; FPGA receives image data and control instructions through the PCIE bus, processes the received image data into Medium mode images and Base mode images, and stores them in the cache module; according to the control command, the image data in the cache is sent to the Cameralink protocol output daughter board; The Cameralink protocol output daughter board converts the image data into Cameralink protocol data and clock and outputs them.

2. The Cameralink protocol communication module based on PCIE bus according to claim 1, characterized in that: The Cameralink protocol output daughter board is stacked on the signal processing carrier board of the PCIE interface.

3. The Cameralink protocol communication module based on PCIE bus according to claim 1, characterized in that: FPGA realizes PCIE bus interaction through PCIE XJ3 connector and PCIE XJ4 connector, and uses ping-pong cache to store the processed image data in two cache modules.

4. The Cameralink protocol communication module based on PCIE bus according to claim 1, characterized in that: FPGA calls the XDMA IP core to receive image data and control instructions from the PCIE bus, and ping-pong caches the image data in the cache module inside the FPGA according to the control instructions. The Cameralink protocol IP core extracts the image data from the DDR3 SDRAM cache module according to the control instructions and converts it into Cameralink protocol data output.

5. The Cameralink protocol communication module based on PCIE bus according to claim 1, characterized in that: The signal processing carrier board of the PCIE interface is provided with Nor BPI Flash and JTAG, wherein Nor BPI Flash is used to store the logic code of FPGA; JTAG is used to support debugging during the module development process; and the FPGA logic code in Nor BPI Flash is updated by downloading through JTAG.

6. The Cameralink protocol communication module based on PCIE bus according to claim 1, characterized in that: The Cameralink protocol output daughter board includes multiple Cameralink sending modules, FMC interfaces and output connectors; Every two Cameralink sending modules form a Cameralink sending channel in Medium mode, and the remaining Cameralink sending modules form a Cameralink sending channel in Base mode. The number of Cameralink sending channels is the same as the number of remaining Cameralink sending modules. The clock signal and image data are received through the FMC interface. The Cameralink sending module of the corresponding mode converts the received Medium mode image and Base mode image into Cameralink data and Cameralink clock, and outputs the data and clock through the output connector.

7. The Cameralink protocol communication module based on PCIE bus according to claim 6, characterized in that: The Cameralink protocol output daughter board includes 4 Cameralink sending modules; 2 Cameralink sending modules form 1 Medium mode Cameralink sending channel, and the other 2 Cameralink sending modules form 2 Base mode Cameralink sending channels.

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