Storage, multiplication and accumulation circuit of capacitance coupling memristor array

Abstract

The invention provides a storage, multiplication and accumulation circuit of a capacitance coupling memristor array. The storage, multiplication and accumulation circuit comprises an input decoding circuit, a pulse current generating circuit, a memristor mixed array circuit and an analog-to-digital conversion circuit which are connected in sequence, wherein the memristor hybrid array circuit is composed of a plurality of memristor hybrid array units; the memristor hybrid array unit comprises a transistor, a memristor and a capacitor; wherein one end of the capacitor is connected with the source electrode of the transistor, the other end of the capacitor is connected to one end of the common bit line, and the other end of the common bit line is connected with the analog-to-digital conversion circuit. The capacitor is coupled to the memristor array, the memristor hybrid array basic unit is constructed, and then the hybrid array circuit is formed, so that the accumulated magnitude of current during concurrence of the memristor array can be greatly reduced, the calculation efficiency is improved, and a peripheral digital circuit is simplified.

Description

Technical Field

[0001] The present invention relates to neuromorphic computing technology, and in particular to a storage-calculation-multiplication-accumulation circuit of a capacitive-coupled memristor array. Background Art

[0002] Neuromorphic computing technology is known as the next generation of artificial intelligence. By simulating the organizational structure and information processing methods of the human brain, it can greatly improve data processing capabilities and solve the "power consumption wall" problem. It is an effective solution to the challenge of massive data computing. At present, memristors (Resistive Random Access Memory, RRAM) with continuously adjustable resistance are ideal electronic devices that can be used in neuromorphic computing platforms and have received widespread attention. At the same time, memristors control the resistance of memristors through specific writing schemes to store different information. It is a new type of non-volatile memory device with both storage and computing capabilities. It avoids the "storage wall" problem at the device level and provides a revolutionary technical route for the development of neuromorphic intelligent computing systems.

[0003] Figure 1 It is a gate-free memristor computing array in the prior art. Figure 1 As shown in the figure, the conventional gateless memristor computing array usually adopts the current accumulation and summation method. First, the writing process converts the weight w required for the memristor calculation into a specific conductance value, and then the specified voltage x is applied by the word line, and the memristor obtains currents of different sizes. Finally, the currents input by different word lines are accumulated in the bit line to obtain the corresponding calculation result y. The relationship between the calculation result y, the weight w and the voltage x is y=∑w·x, that is, the multiplication and addition operations are completed simultaneously in one power-on process.

[0004] However, this multiplication and accumulation calculation function based on Kirchhoff's current law cannot solve the gating problem. For this reason, gating tubes (CMOS and other devices) are added to the memristor array to form a hybrid architecture circuit composed of transistors (transistor, T) and memristors (RRAM, R), such as Figure 2 shown. Figure 2 This is a memristor computing array with transistors in the prior art, showing the common 1T1R (a), 1T2R (b), and 2T2R (c) architectures, which solve the gating problem of the memristor by adding transistors. However, the multiplication and accumulation operator composed of the memristor array of this solution usually uses the splicing and shifting method to obtain high-precision data, which will cause huge current accumulation in the computing array when performing large-scale calculations.

[0005] It can be seen that the existing memristor storage-computation integrated convolution kernel has two main problems:

[0006] (1) Memristor array architecture problem: The computing array cannot support large-scale concurrent operation. The existing structure is usually composed of a hybrid architecture of gates and memristors. Relying on the Kirchhoff current to perform multiplication and addition accumulation, a huge cumulative current is generated in the memristor array, which hinders the scale of concurrent calculations of the memristor in-memory computing circuit, reduces the speed of in-memory computing, and greatly increases the power consumption of in-memory computing.

[0007] (2) The problem of multiplication and accumulation result resolution: Because the input is split, the output result of the multiplication and accumulation is highly dependent on the peripheral digital circuit for shift and addition operations. Such operations require targeted design of the timing and logic of the peripheral circuit, which brings additional circuit overhead. At the same time, because the full-precision result is not output during the calculation resolution, specific compensation needs to be made in the calculation method, which limits the versatility of the multiplication and accumulation operation.

[0008] The above two problems lead to low concurrent efficiency of existing memristor convolution operators when in use, and low system versatility. Therefore, a universal storage and calculation convolution kernel that can achieve high concurrent computing and less peripheral digital circuits is needed. Summary of the invention

[0009] The object of the present invention is to provide a storage-computation-multiplication-accumulation circuit of a capacitively coupled memristor array to solve the problems of low concurrent efficiency and low system versatility of the above-mentioned memristor convolution operator when in use.

[0010] On the one hand, the present invention provides a storage-calculation-multiplication-accumulation circuit of a capacitive-coupled memristor array, comprising: an input decoding circuit, a pulse current generating circuit, a memristor hybrid array circuit, and an analog-to-digital conversion circuit connected in sequence; wherein the memristor hybrid array circuit is composed of a plurality of memristor hybrid array units; the memristor hybrid array unit comprises a transistor, a memristor, and a capacitor; wherein one end of the capacitor is connected to a source of the transistor, and the other end is connected to one end of a common bit line, and the other end of the common bit line is connected to the analog-to-digital conversion circuit.

[0011] In some implementations of the present invention, a top electrode terminal of the memristor is connected to a source of the transistor, and a bottom electrode terminal of the memristor is connected to a terminal of a reference voltage.

[0012] In some implementations of the present invention, the gate of the transistor is connected to one end of the word line, and the drain of the transistor is connected to one end of the source line.

[0013] In some implementations of the present invention, the other end of the reference voltage is connected to a pulse current generating circuit.

[0014] In some implementations of the present invention, the other end of the word line is connected to a pulse current generating circuit.

[0015] In some implementations of the present invention, the other end of the source line is connected to a pulse current generating circuit.

[0016] In some implementations of the present invention, the encoding method used by the pulse current generating circuit includes thermometer encoding.

[0017] In some implementations of the present invention, the memristor hybrid array includes a row, column, and differential array structure.

[0018] In some implementations of the present invention, the analog-to-digital conversion circuit includes: a comparator and a counter.

[0019] In some implementations of the invention, the counter includes an asynchronous clock structure.

[0020] Based on the above, the storage, calculation, multiplication and accumulation circuit of the capacitor-coupled memristor array of the embodiment of the present invention, by coupling the capacitor to the memristor array, constructs a 1T1R1C memristor mixer basic unit, and then forms a hybrid array circuit in the arrangement of rows, columns and differentials, which can greatly reduce the accumulated current during the concurrency of the memristor array, improve the calculation efficiency, and simplify the peripheral digital circuit. In addition, in the charge transfer comparison, the charge packet size can be dynamically adjusted by the memristor differential to the accumulated unit charge, thereby realizing the function of segmented adjustable charge packet counting, which is significantly faster than the existing non-adjustable charge packet analog-to-digital converter counting method. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a gate-free memristor computing array in the prior art;

[0022] Figure 2 It is a memristor computing array with transistors in the prior art;

[0023] Figure 3 The structure of a storage-calculation-multiplication-accumulation circuit of a capacitively coupled memristor array according to an embodiment of the present invention is schematically shown;

[0024] Figure 4 A memristor hybrid array unit according to an embodiment of the present invention is schematically shown;

[0025] Figure 5 The charge coupling process of the memristor hybrid array according to an embodiment of the present invention is schematically shown;

[0026] Figure 6 The analog-to-digital conversion circuit according to an embodiment of the present invention is schematically shown;

[0027] Figure 7 A schematic diagram of a 14-bit output result obtained by a counter according to an embodiment of the present invention is shown;

[0028] Figure 8The diagram schematically shows the convolution calculation effect that can be realized by the storage-calculation-multiplication-accumulation circuit of the capacitively coupled memristor array according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0030] Figure 3 The structure of a storage-calculation-multiplication-accumulation circuit of a capacitively coupled memristor array according to an embodiment of the present invention is schematically shown.

[0031] like Figure 3 As shown, in this embodiment, the storage-calculation multiplication-accumulation circuit structure of the capacitive-coupled memristor array is composed of an input decoding circuit, a pulse current generating circuit, a memristor hybrid array circuit, and an analog-to-digital conversion circuit connected in sequence. The process can be briefly described as follows: first, the input decoding circuit converts the binary digital bit code of the peripheral input into the thermometer code in the analog switch; second, the pulse current generating circuit generates a current of a specified magnitude for the signal given by the thermometer code; then, the memristor hybrid array stores the weights and performs multiplication-accumulation (convolution) calculations; finally, the analog-to-digital conversion circuit compares and moves the charge stored in the memristor hybrid array to obtain the result of multiplication-accumulation.

[0032] Figure 4 A memristor hybrid array unit according to an embodiment of the present invention is schematically shown.

[0033] like Figure 4 As shown, in this embodiment, the memristor hybrid array unit includes a transistor T, a memristor R and a capacitor C, which are connected in series and parallel. One end of the capacitor C is connected to the source of the transistor T, and the other end is connected to one end of the common bit line CBL. The top electrode end of the memristor R is connected to the source of the transistor T, and the bottom electrode end of the memristor R is connected to the reference voltage V ref The gate of the transistor T is connected to one end of the word line WL, and the drain of the transistor T is connected to one end of the source line SL.

[0034] Please also refer to Figure 3 , Figure 4 The other end of the common bit line CBL is connected to the analog-to-digital conversion circuit. ref The other end of the word line WL, the other end of the source line SL are respectively connected to the corresponding ports of the pulse current generating circuit.

[0035] In this embodiment, the pulse current generating circuit can be implemented by thermometer coding to ensure the accuracy of the output current. For example, under the SMIC 0.18 μm process, the standard deviation of the output current of 1 μA is 6.9 nA.

[0036] As an example, a bipolar oxide memristor may be used, such as a memristor with tantalum oxide or hafnium oxide as the oxide resistance layer, and the top electrode and bottom electrode materials are TiN, which is compatible with common CMOS processes, but the present invention is not limited thereto.

[0037] Please continue to refer to Figure 4 In this embodiment, the word line WL is connected to the gate of the transistor T to control the on and off of the transistor T, so as to determine the different stages of the calculation process. One end of the capacitor C is connected to the source of the transistor T, and the other end is connected to the common bit line CBL for analyzing the calculation results.

[0038] For ease of description, we can Figure 4 The memristor hybrid array unit shown includes a transistor T, a memristor R, and a capacitor C, which is represented by 1T1R1C. In this article, unless otherwise specified, 1T1R1C is used to represent Figure 4 The memristor hybrid array cell shown.

[0039] Figure 5 The charge coupling process of the memristor hybrid array according to an embodiment of the present invention is schematically shown.

[0040] like Figure 5 As shown, in this embodiment, multiple 1T1R1C memristor hybrid array units are connected in series through a common bit line CBL, which can realize charge accumulation and transfer, greatly reducing power consumption during calculation.

[0041] In the precharge stage: the word line WL controls the transistor to turn on, and the source line SL inputs current signals of different amplitudes and the same pulse width. Different currents pass through the word line WL into the memristor R with different resistance values, and the reference voltage V ref The word line WL flows out. At this time, the voltage U generated by the current and the memristor R is U=I×R, that is, the current input I interacts with the resistance value of the memristor R to generate a voltage U of a certain magnitude. The coupling effect of the voltage U and the capacitor C can be expressed as Q=C×U, that is, the voltage U interacts with the capacitor C to obtain a certain amount of charge value Q. At this point, the word line WL is closed, completing the pre-charging stage of the memristor hybrid array unit. This charging process reduces the huge accumulated current in the array through capacitive coupling, that is, there is no large converged static current and dynamic current.

[0042] In the calculation stage: the capacitors of different memristor hybrid array units are connected to the common bit line CBL, and the subsequent analog-to-digital conversion module connected through the common bit line CBL obtains the cumulative calculation results. In this process, no huge cumulative current passes through the memristor array, and the static current in the memristor array circuit is extremely small, which greatly reduces the power consumption during calculation.

[0043] Please continue to refer to Figure 5 In this embodiment, the memristor hybrid array may include a row, column, and differential array structure. For example, 1×9×2 represents a memristor hybrid array of 1 row, 9 columns, and 2 differentials, which includes a total of 18 memristor hybrid array units. Differentials can achieve positive and negative weights, and can effectively reduce common-mode noise interference. In the charge transfer comparison, the charge packet size can be dynamically adjusted by the memristor differential to the accumulated unit charge, thereby realizing the function of segmented adjustable charge packet counting, which greatly improves the speed compared to the original non-adjustable charge packet analog-to-digital converter counting method.

[0044] Figure 6 The analog-to-digital conversion circuit according to an embodiment of the present invention is schematically shown.

[0045] like Figure 6 Please combine Figure 3 In this embodiment, the analog-to-digital conversion circuit includes a comparator and a counter.

[0046] The comparator compares and shifts the accumulated charges on all capacitors one by one to obtain the total number of charges, which is the result of the multiplication and addition operation.

[0047] The counter is used to count the number of comparison and transfer, that is, the result of multiplication and accumulation. In this implementation, the counter can be an asynchronous clock structure, without the need for clock alignment, and the dynamic power consumption is only μW level, which reduces energy consumption.

[0048] Figure 7 The timing diagram of the 14-bit output result obtained by the counter according to the embodiment of the present invention is schematically shown.

[0049] like Figure 7 As shown, the horizontal axis Time (us) represents the time for the counter to process data, in microseconds; the vertical axis Output Signal represents the result of the output signal. In this embodiment, the calculation result of the comparator is latched by a 14-bit counter to obtain a 14-bit output result.

[0050] Figure 8 It is a schematic diagram of convolution calculation that can be implemented by the storage-calculation-multiplication-accumulation circuit of the capacitive-coupled memristor array according to an embodiment of the present invention.

[0051] like Figure 8 As shown, in this embodiment, each position of the original data can represent 4-bit data, and higher-bit information can be processed by segmented input. Each position of the convolution kernel can represent 6-bit information, and the final output result is 14-bit high-precision uncompressed information.

[0052] In summary, the memristor hybrid array coupling capacitor transfers the charge to the comparator level for comparison through the common bit line. Such a charge packet analog-to-digital conversion form directly moves and counts the charge in the capacitor coupling array in the form of the smallest unit, and the result is expressed by a counter. At the same time, the present invention performs segmented processing on the smallest unit, speeds up the comparison process in the high-bit counting, and realizes high-precision calculation results without external digital circuit splicing.

[0053] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A storage-calculation-multiplication-accumulation circuit of a capacitively coupled memristor array, characterized in that: include: An input decoding circuit, a pulse current generating circuit, a memristor hybrid array circuit, and an analog-to-digital conversion circuit are connected in sequence; wherein, The memristor hybrid array circuit is composed of a plurality of memristor hybrid array units; The memristor hybrid array unit comprises: a transistor, a memristor and a capacitor; wherein, One end of the capacitor is connected to the source of the transistor, and the other end is connected to one end of a common bit line, and the other end of the common bit line is connected to the analog-to-digital conversion circuit.

2. The storage-multiplication-accumulation circuit according to claim 1, characterized in that: The top electrode terminal of the memristor is connected to the source of the transistor, and the bottom electrode terminal of the memristor is connected to one end of a reference voltage.

3. The storage-multiplication-accumulation circuit according to claim 2, characterized in that: The gate of the transistor is connected to one end of a word line, and the drain of the transistor is connected to one end of a source line.

4. The storage-multiplication-accumulation circuit according to claim 2, characterized in that: The other end of the reference voltage is connected to a pulse current generating circuit.

5. The storage-multiplication-accumulation circuit according to claim 3, characterized in that: The other end of the word line is connected to a pulse current generating circuit.

6. The storage-multiplication-accumulation circuit according to claim 3, characterized in that: The other end of the source line is connected to a pulse current generating circuit.

7. The storage-multiplication-accumulation circuit according to any one of claims 4 to 6, characterized in that: The encoding method adopted by the pulse current generating circuit includes thermometer encoding.

8. The storage-multiplication-accumulation circuit according to claim 1, characterized in that: The memristor hybrid array comprises a row, column and differential array structure.

9. The storage-multiplication-accumulation circuit according to claim 1, characterized in that: The analog-to-digital conversion circuit includes: a comparator and a counter.

10. The storage-multiplication-accumulation circuit according to claim 9, characterized in that: The counter includes an asynchronous clock structure.

Images