Hybrid in-memory calculation method and device based on monolithic three-dimensional integration

Abstract

The invention relates to a hybrid in-memory calculation method and device based on monolithic three-dimensional integration, and the method comprises the steps: constructing a first silicon-based control circuit layer, a second simulation in-memory calculation array layer, a third digital storage array layer and a fourth digital storage array layer, and carrying out the in-situ vertical stacking of the layers, all the layers are connected in sequence through interlayer dielectric via holes to construct a monolithic three-dimensional integrated system; a target to-be-recognized image is converted into a read voltage signal through a single-chip three-dimensional integrated system, the read voltage signal is respectively input into each in-memory calculation array layer to obtain a corresponding output current, and signal calculation and conversion operation is performed on the output current to obtain a target voltage signal; and executing the neural network calculation operation in the hybrid memory corresponding to the target to-be-recognized image. Therefore, the problems that communication delay and power consumption of an existing high-density hybrid in-memory computing architecture are large, the overall area of an in-memory computing array is large, and the computing performance in a high-density hybrid memory is greatly affected are solved.

Description

Technical Field

[0001] The present application relates to the field of hybrid energy storage technology, and in particular to a hybrid in-memory computing method and device based on monolithic three-dimensional integration. Background Art

[0002] In-memory computing is a new architecture that integrates computing functions into storage units at the device level, which can fundamentally reduce the repeated transfer of large amounts of data between data storage and computing modules during the computing process. Its core unit is a storage array composed of circuit units with storage functions (i.e., storage computing units), which is used to simulate weight operations in neural network structures. Compared with the von Neumann architecture, the in-memory computing architecture has the advantages of fast computing speed, low power consumption, and high integration density. It has been widely used in large-scale neural network computing tasks.

[0003] Figure 1 It is a typical in-memory computing array structure based on non-volatile memory, using non-volatile memory such as resistive random access memory (RRAM) as storage and computing units. According to Kirchhoff's law, the array can complete the matrix-vector multiplication operation process, map the data to be stored into the conductance value of each storage and computing unit memory and write it into the array, and map the input vector into the read voltage of each row of the array; Figure 2 The figure shows a typical in-memory computing array structure based on SRAM cells, which uses SRAM as the storage and computing unit.

[0004] According to the different types of stored weight values, the in-memory computing architecture can be divided into analog in-memory computing and digital in-memory computing. Analog in-memory computing means that the information stored in each storage unit is a multi-bit value, which can only be implemented by a non-volatile memory with multi-bit storage function. The advantage is that the weight storage density is high, and a single device can be used to store multi-bit information, thereby reducing the area and power consumption of a single storage array; but the disadvantage is that it is difficult for new non-volatile memories such as RRAM to achieve long-term correct information storage, which will lead to a decrease in calculation accuracy.

[0005] Digital in-memory computing means that the information stored in each computing unit is discrete digital information (i.e., 0 or 1), which is reflected as high resistance / low resistance in resistors and low level / high level in SRAM. Compared with the analog in-memory computing architecture, the information storage of computing units in the digital in-memory computing array is more reliable and the calculation accuracy is higher; the disadvantage is that the storage density is reduced, and each computing unit in the digital in-memory computing array can only store 1 bit of information, so the array area and power consumption required to complete the same computing task are larger.

[0006] Resistive random access memory (RRAM) is one of the most promising new storage and computing fusion devices, with the advantages of simple structure, CMOS process compatibility, high integration density, and high performance, such as high speed, low power consumption, and multi-bit storage. Figure 3 As shown, a typical RRAM is composed of upper and lower electrodes and an oxide in the middle as a resistive switching layer. Under the action of an external voltage pulse, the movement of oxygen ions in the oxide forms conductive filaments based on oxygen vacancies to connect the upper and lower electrodes. By regulating the morphology of the conductive filaments, the conductance of the memristor can be continuously adjusted, showing analog resistive switching characteristics. On a macro scale, the resistance of the RRAM device can be changed by an external voltage pulse, so that the RRAM device can store a specified value and complete the calculation.

[0007] However, due to the random movement of oxygen vacancies in the device, the conductivity of the RRAM device will drift over time. In multi-bit or analog storage and computing applications, the information to be stored will be mapped to multiple densely arranged target conductivity values ​​of the RRAM device. Once the conductivity drift of the RRAM device exceeds the target conductivity value interval, storage information errors will occur, such as Figure 4 As shown in Figure 2. In contrast, in digital storage and computing applications, each RRAM device has only two target conductivity states: low conductivity state and high conductivity state. The target conductivity state interval becomes larger, so the tolerance for RRAM device conductivity drift becomes higher. However, the disadvantage is that the storage density becomes smaller, and each storage unit in the digital storage computing array can only store 1 bit of information, such as Figure 5 shown.

[0008] In order to improve data communication capabilities, academia and industry have begun to experiment with three-dimensional integration technology, among which monolithic three-dimensional integration technology is one of the most promising technologies.

[0009] In order to simultaneously obtain the high calculation accuracy of the digital in-memory computing architecture and the low area / power consumption overhead of the analog in-memory computing architecture, the existing technology can split each multi-bit weight value based on a hybrid in-memory computing architecture, map the high bit of each value to the digital in-memory computing array, and map the low bit to the analog in-memory computing array. However, the hybrid in-memory computing architecture requires complex processing circuits to splice and process the calculation results of the digital and analog in-memory computing arrays. The communication delay and power consumption required for a large amount of data to enter and exit the processing circuit seriously restrict the chip performance; in addition, using multiple in-memory computing arrays to map a weight matrix will also cause the overall area of ​​the in-memory computing array to increase.

[0010] In summary, the existing high-density hybrid in-memory computing architecture has large communication delay and power consumption, and the overall area of ​​the in-memory computing array is large, which greatly affects the performance of high-density hybrid in-memory computing and needs to be urgently resolved. Summary of the invention

[0011] The present application provides a hybrid in-memory computing method and device based on monolithic three-dimensional integration to solve the problems of existing high-density hybrid in-memory computing architecture, such as large communication delay and power consumption, and large overall area of ​​the in-memory computing array, which greatly affects the high-density hybrid in-memory computing performance.

[0012] The first aspect of the present application provides a hybrid in-memory computing method based on monolithic three-dimensional integration, comprising the following steps: constructing a first silicon-based control circuit layer, a second analog in-memory computing array layer, a third digital in-memory computing array layer and a fourth digital in-memory computing array layer; performing in-situ vertical stacking operations on the first silicon-based control circuit layer, the second analog in-memory computing array layer, the third digital in-memory computing array layer and the fourth digital in-memory computing array layer, and sequentially connecting each layer through interlayer dielectric vias to construct a monolithic three-dimensional integrated system; converting a target image to be identified into a read voltage signal that meets preset compatibility requirements through the monolithic three-dimensional integrated system, and inputting the read voltage signal into the second analog in-memory computing array layer, the third digital in-memory computing array layer and the fourth digital in-memory computing array layer, respectively, to obtain a corresponding output current; performing signal calculation and conversion operations on the output current to obtain a target voltage signal, and performing a hybrid in-memory neural network computing operation corresponding to the target image to be identified according to the target voltage signal.

[0013] Optionally, in one embodiment of the present application, the construction of the first silicon-based control circuit layer, the second analog in-memory computing array layer, the third digital storage computing array layer and the fourth digital storage computing array layer includes: based on a preset standard silicon-based CMOS process, constructing the first silicon-based control circuit layer, and constructing the second analog in-memory computing array layer through a first preset base resistive memory; using preset carbon nano transistors and a second preset base resistive memory to construct the third digital storage computing array layer and the fourth digital storage computing array layer.

[0014] Optionally, in one embodiment of the present application, before converting the target image to be identified into a read voltage signal that meets the preset compatibility requirements through the monolithic three-dimensional integrated system, it also includes: inputting a preset weight matrix into a routing array in the third digital storage and computing array layer, so as to decompose the weight matrix into high-order weight data that meets the preset high-order requirements and low-order weight data that meets the preset low-order requirements through the routing array; storing the low-order weight data in the second analog memory computing array layer, and storing the high-order weight data in the third digital storage and computing array layer and the fourth digital storage and computing array layer.

[0015] Optionally, in one embodiment of the present application, the target image to be identified is converted into a read voltage signal that meets preset compatibility requirements through the monolithic three-dimensional integrated system, and the read voltage signal is respectively input into the second analog memory computing array layer, the third digital memory computing array layer and the fourth digital memory computing array layer to obtain a corresponding output current, including: storing the target image to be identified in a cache array in the monolithic three-dimensional integrated system, and inputting the target image to be identified in the cache array into a preset signal conversion circuit to output the read voltage signal; inputting the read voltage signal into the second analog memory computing array layer, the third digital memory computing array layer and the fourth digital memory computing array layer to obtain the output currents corresponding to the second analog memory computing array layer, the third digital memory computing array layer and the fourth digital memory computing array layer, respectively.

[0016] Optionally, in one embodiment of the present application, the signal calculation and conversion operations are performed on the output current to obtain a target voltage signal, and a hybrid in-memory neural network calculation operation corresponding to the target image to be identified is performed according to the target voltage signal, including: adding the output currents of the second analog in-memory calculation array layer, the third digital in-memory calculation array layer and the fourth digital in-memory calculation array layer through preset inter-layer interconnection lines to obtain a total read current, and sending the total read current to the signal conversion circuit to generate a target voltage signal corresponding to the total read current; storing the target voltage signal in the cache array, reading the cache array to obtain the target voltage signal, and based on the target voltage signal, performing a hybrid in-memory neural network calculation operation corresponding to the target image to be identified.

[0017] The second aspect of the present application provides a hybrid in-memory computing device based on monolithic three-dimensional integration, including: a construction module, used to construct a first silicon-based control circuit layer, a second analog in-memory computing array layer, a third digital storage computing array layer and a fourth digital storage computing array layer; an in-situ vertical stacking module, used to perform in-situ vertical stacking operations on the first silicon-based control circuit layer, the second analog in-memory computing array layer, the third digital storage computing array layer and the fourth digital storage computing array layer, and connect each layer in sequence through interlayer dielectric vias to construct a monolithic three-dimensional integrated system; a hybrid in-memory computing module, used to convert a target image to be identified into a read voltage signal that meets preset compatibility requirements through the monolithic three-dimensional integrated system, and input the read voltage signal into the second analog in-memory computing array layer, the third digital storage computing array layer and the fourth digital storage computing array layer respectively to obtain a corresponding output current; an execution module, used to perform signal calculation and conversion operations on the output current to obtain a target voltage signal, and execute a hybrid in-memory neural network calculation operation corresponding to the target image to be identified according to the target voltage signal.

[0018] Optionally, in one embodiment of the present application, the construction module includes: a first construction unit, used to construct the first silicon-based control circuit layer based on a preset standard silicon-based CMOS process, and to construct the second analog in-memory computing array layer through a first preset base resistive memory; a second construction unit, used to construct the third digital storage computing array layer and the fourth digital storage computing array layer using preset carbon nano transistors and a second preset base resistive memory.

[0019] Optionally, in one embodiment of the present application, it also includes: a decomposition module, which is used to input a preset weight matrix into a routing array in the third digital storage and computing array layer before converting the target image to be identified into a read voltage signal that meets the preset compatibility requirement through the monolithic three-dimensional integrated system, so as to decompose the weight matrix into high-order weight data that meets the preset high-order requirement and low-order weight data that meets the preset low-order requirement through the routing array; a storage module, which is used to store the low-order weight data to the second analog memory computing array layer, and store the high-order weight data to the third digital storage and computing array layer and the fourth digital storage and computing array layer.

[0020] Optionally, in one embodiment of the present application, the hybrid in-memory computing module includes: a signal conversion unit, used to store the target image to be identified in the cache array in the monolithic three-dimensional integrated system, and input the target image to be identified in the cache array to a preset signal conversion circuit to output the read voltage signal; an input unit, used to input the read voltage signal into the second analog in-memory computing array layer, the third digital in-memory computing array layer and the fourth digital in-memory computing array layer, respectively, to obtain the output currents corresponding to the second analog in-memory computing array layer, the third digital in-memory computing array layer and the fourth digital in-memory computing array layer, respectively.

[0021] Optionally, in one embodiment of the present application, the execution module includes: an addition unit, used to add the output currents of the second analog in-memory computing array layer, the third digital in-memory computing array layer and the fourth digital in-memory computing array layer through preset inter-layer interconnection lines to obtain a total read current, and send the total read current to the signal conversion circuit to generate a target voltage signal corresponding to the total read current; an execution unit, used to store the target voltage signal in the cache array, and read the cache array to obtain the target voltage signal, and based on the target voltage signal, execute a hybrid in-memory neural network calculation operation corresponding to the target image to be identified.

[0022] The third aspect of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the hybrid in-memory computing method based on monolithic three-dimensional integration as described in the above embodiment.

[0023] The fourth aspect of the present application provides a computer-readable storage medium, which stores a computer program. When the program is executed by a processor, it implements the above-mentioned hybrid in-memory computing method based on monolithic three-dimensional integration.

[0024] The fifth aspect of the present application provides a computer program product, including a computer program, which is executed to implement the above-mentioned hybrid in-memory computing method based on monolithic three-dimensional integration.

[0025] Therefore, the embodiments of the present application have the following beneficial effects:

[0026] The embodiments of the present application can be achieved by constructing a first silicon-based control circuit layer, a second analog in-memory computing array layer, a third digital in-memory computing array layer, and a fourth digital in-memory computing array layer; performing in-situ vertical stacking operations on the first silicon-based control circuit layer, the second analog in-memory computing array layer, the third digital in-memory computing array layer, and the fourth digital in-memory computing array layer, and sequentially connecting each layer through interlayer dielectric vias to construct a monolithic three-dimensional integrated system; converting a target image to be identified into a read voltage signal that meets preset compatibility requirements through the monolithic three-dimensional integrated system, and inputting the read voltage signal into the second analog in-memory computing array layer, the third digital in-memory computing array layer, and the fourth digital in-memory computing array layer, respectively, to obtain a corresponding output current, and performing signal calculation and conversion operations on the output current to obtain a target voltage signal, and performing a hybrid in-memory neural network calculation operation corresponding to the target image to be identified according to the target voltage signal. This application vertically stacks the digital storage array, analog storage array, and peripheral processing circuits, and uses high-density interlayer interconnection for communication, which can reduce the overall circuit area, significantly improve the communication bandwidth, and reduce power consumption; in addition, this application uses RRAM devices of different material systems to construct analog in-memory computing arrays and digital in-memory computing arrays, thereby achieving better computing performance. This solves the problems of the existing high-density hybrid in-memory computing architecture, such as large communication delay and power consumption, and the large overall area of ​​the in-memory computing array, which greatly affects the performance of high-density hybrid in-memory computing.

[0027] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0029] Figure 1 A schematic diagram of an in-memory computing array structure based on a non-volatile memory is provided for one embodiment of the present application;

[0030] Figure 2 A schematic diagram of an in-memory computing array structure based on SRAM cells provided for one embodiment of the present application;

[0031] Figure 3 A schematic diagram of a RRAM device structure and conductive mechanism provided for one embodiment of the present application;

[0032] Figure 4 A schematic diagram showing how the conductance value of an RRAM device with a multi-bit storage function changes over time, provided in accordance with an embodiment of the present application;

[0033] Figure 5 A schematic diagram of conductivity drift tolerance of a RRAM device provided for one embodiment of the present application;

[0034] Figure 6 A flow chart of a hybrid in-memory computing method based on monolithic three-dimensional integration provided according to an embodiment of the present application;

[0035] Figure 7 A schematic diagram of a sample cross-section transmission electron microscope provided for one embodiment of the present application;

[0036] Figure 8 A schematic diagram of a hybrid in-memory computing architecture based on three-dimensional integration provided for one embodiment of the present application;

[0037] Fig. 9 A schematic diagram of a ResNET-32 network structure provided for an embodiment of the present application;

[0038] Fig.10 A circuit diagram of a monolithic three-dimensional integrated system provided for one embodiment of the present application;

[0039] Fig.11 A schematic diagram showing a speed comparison between using a single-chip three-dimensional integration to implement hybrid in-memory computing and using a two-dimensional chip to implement hybrid in-memory computing, provided in one embodiment of the present application;

[0040] Fig.12 is an exemplary diagram of a hybrid in-memory computing device based on monolithic three-dimensional integration according to an embodiment of the present application;

[0041] Fig.13A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0042] Among them, 10-a hybrid in-memory computing device based on monolithic three-dimensional integration; 100-a building module, 200-an in-situ vertical stacking module, 300-a hybrid in-memory computing module, 400-an execution module; 1301-a memory, 1302-a processor, 1303-a communication interface. DETAILED DESCRIPTION

[0043] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0044] The following describes the hybrid in-memory computing method and device based on monolithic three-dimensional integration of the embodiment of the present application with reference to the accompanying drawings. In view of the problems mentioned in the above background technology, the present application provides a hybrid in-memory computing method based on monolithic three-dimensional integration, in which a first silicon-based control circuit layer, a second analog in-memory computing array layer, a third digital in-memory computing array layer and a fourth digital in-memory computing array layer are constructed; the first silicon-based control circuit layer, the second analog in-memory computing array layer, the third digital in-memory computing array layer and the fourth digital in-memory computing array layer are vertically stacked in situ, and each layer is sequentially connected through interlayer dielectric vias to construct a monolithic three-dimensional integrated system; the target image to be identified is converted into a read voltage signal that meets the preset compatibility requirements through the monolithic three-dimensional integrated system, and the read voltage signal is respectively input into the second analog in-memory computing array layer, the third digital in-memory computing array layer and the fourth digital in-memory computing array layer to obtain the corresponding output current, and the output current is subjected to signal calculation and conversion operations to obtain the target voltage signal, and the hybrid in-memory neural network computing operation corresponding to the target image to be identified is performed according to the target voltage signal. This application vertically stacks the digital storage array, analog storage array, and peripheral processing circuits, and uses high-density interlayer interconnection for communication, which can reduce the overall circuit area, significantly improve the communication bandwidth, and reduce power consumption; in addition, this application uses RRAM devices of different material systems to construct analog in-memory computing arrays and digital in-memory computing arrays, thereby achieving better computing performance. This solves the problems of the existing high-density hybrid in-memory computing architecture, such as large communication delay and power consumption, and the large overall area of ​​the in-memory computing array, which greatly affects the performance of high-density hybrid in-memory computing.

[0045] Specifically, Figure 6 A flow chart of a hybrid in-memory computing method based on monolithic three-dimensional integration provided in an embodiment of the present application.

[0046] like Figure 6As shown, the hybrid in-memory computing method based on monolithic three-dimensional integration includes the following steps:

[0047] In step S601, a first silicon-based control circuit layer, a second analog in-memory computing array layer, a third digital in-memory computing array layer and a fourth digital in-memory computing array layer are constructed.

[0048] The embodiment of the present application can firstly adopt a first silicon-based control circuit layer manufactured by a standard silicon-based CMOS process, and adopt HfAlO x The second analog in-memory computing array layer is constructed based on the resistive memory, and the third digital storage computing array layer, the fourth digital storage computing array layer, the cache array and the routing array are constructed based on the carbon nanotube transistor (CNTFET) and the Ta2O5 based resistive memory, so as to complete the subsequent signal control, the complex calculations involved in the neural network image recognition and other functions through the first silicon-based control circuit layer, the second analog in-memory computing array layer, the third digital storage computing array layer and the fourth digital storage computing array layer.

[0049] Optionally, in one embodiment of the present application, a first silicon-based control circuit layer, a second analog in-memory computing array layer, a third digital storage computing array layer and a fourth digital storage computing array layer are constructed, including: based on a preset standard silicon-based CMOS process, constructing a first silicon-based control circuit layer, and constructing a second analog in-memory computing array layer through a first preset base resistive memory; using preset carbon nano transistors and a second preset base resistive memory to construct a third digital storage computing array layer and a fourth digital storage computing array layer.

[0050] Specifically, in the embodiment of the present application, the first silicon-based control circuit layer (i.e., the first layer) is manufactured using a foundry-standard CMOS logic process; the second analog in-memory computing array layer (i.e., the second layer), the third digital storage computing array layer (i.e., the third layer), and the fourth digital storage computing array layer (i.e., the fourth layer) are all manufactured using a low-temperature (no greater than 300° C.) back-end integration process, and the specific manufacturing process is as follows:

[0051] 1. The second layer HfAlO x RRAM device manufacturing:

[0052] 1) Deposition of 30nm TiN (physical vapor deposition, lower electrode) / 8nm HfAlO x (Atomic layer deposition, resistive layer) / 45nm TaO x (physical vapor deposition, thermal enhancement layer) / 30nm TiN (physical vapor deposition, top electrode) stack;

[0053] 2) Use photolithography and dry etching process to selectively etch TiN / HfAlO x / TaO x / TiN stacking to achieve the patterning of resistive memory;

[0054] 3) Plasma enhanced chemical vapor deposition was used to deposit a 400 nm SiO2 film (passivation layer);

[0055] 4) Using photolithography and dry etching processes, the SiO2 film is etched to form openings for interconnection line connection points;

[0056] 5) A layer of W is deposited by electroplating, and then chemical mechanical polishing is used to grind the W except the SiO2 hole clean (to form a metal via);

[0057] 6) Using physical vapor deposition, deposit 400nm of metal Al (metal interconnection);

[0058] 7) Using photolithography and dry etching processes, selectively etching Al to form Al metal interconnects;

[0059] 8) Plasma enhanced chemical vapor deposition was used to deposit a 100nm SiO2 / 900nm Si3N4 film (passivation layer);

[0060] 9) Photolithography and dry etching processes are used to selectively etch the SiO2 / Si3N4 film to form openings.

[0061] 2. Third-layer RRAM device manufacturing:

[0062] 1) Atomic layer deposition was used to grow 45nm Al2O3 as a passivation layer;

[0063] 2) using photolithography and wet etching processes to selectively etch Al2O3 to form a lower electrode contact hole of the resistive memory;

[0064] 3) Using physical vapor deposition to grow TaO x (oxygen-deficient layer, 20nm) / Ta2O5 (resistive layer, 10nm) / Pt (upper electrode, 90nm) are stacked, and photolithography, stripping and other processes are used to form a resistive memory structure.

[0065] 3. Third layer CNTFET device manufacturing:

[0066] 1) Using photolithography and electron beam evaporation to deposit 40nm Au, followed by peeling off to form a pattern, which serves as the back gate of the carbon nanotube transistor;

[0067] 2) Atomic layer deposition is used to grow 3nm Al2O3 and 8nm HfO2, and photolithography and wet etching processes are used for etching to form a gate oxide layer structure;

[0068] 3) Using a wet transfer method, a layer of carbon nanotubes is deposited, and an O2 plasma is used to define the channel region to form a channel of a carbon nanotube transistor;

[0069] 4) Using photolithography, electron beam evaporation of 40nm Pd, and then peeling to form a pattern as the source and drain electrodes of the carbon nanotube transistor;

[0070] 5) Performing atomic layer deposition to grow 7nm HfO2 and 11nm ALN to form doping for the channel and prepare CNT-NMOS;

[0071] 6) Remove the HfO2 and ALN on the PMOS structure, and use electron beam evaporation to grow 2nm Y2O3 and atomic layer deposition to grow 11nm HfO2 as a passivation layer.

[0072] 4. Fourth layer device manufacturing:

[0073] 1) Deposit 300nm SiO2 as an isolation layer on top of the third layer device using physical vapor deposition.

[0074] Afterwards, the steps of manufacturing the third layer CNTFET device and the steps of manufacturing the RRAM device are repeated in sequence; wherein, the order of manufacturing the CNTFET and the RRAM in the third layer and the fourth layer is opposite, in order to ensure that the two layers of CNTFET devices are continuously prepared, so as to have better uniformity. After the process is completed, the following can be obtained: Figure 7 Transmission electron microscopy of a cross-section of the sample shown.

[0075] It can be understood that in the prior art, the RRAM device material system used in the analog in-memory computing and digital in-memory computing arrays is the same, and the digital and analog storage functions are achieved only by setting different target conductivity states. However, RRAM devices of different material systems are suitable for different applications. Using RRAM devices of a single material system to complete digital / analog storage functions will inevitably cause the loss of one of the storage functions; and the embodiments of the present application can manufacture different memory computing arrays at different layers, so RRAM devices of different material systems can be used to construct analog in-memory computing arrays and digital in-memory computing arrays, thereby achieving better computing performance.

[0076] It should be noted that the resistive memory used in the analog in-memory computing array of the second layer in the embodiment of the present application requires good analog characteristics, and the resistive memory used in the digital in-memory computing array of the third and fourth layers requires a good resistive window. Therefore, those skilled in the art of the present application may also use TiN / HfO2 / TaO x / TiN, TiN / HfO2 / TiN, TiN / HfZrO x / TaO x The analog in-memory computing array of the second layer can be manufactured using a material system such as TiN / AlN / Pd; and the digital in-memory computing array of the third and fourth layers can be manufactured using a material system such as TiN / AlN / Pd.

[0077] Secondly, the resistive memory in the embodiment of the present application can be replaced by any memristor such as phase change memory, magnetic memory and ferroelectric memory, as long as it can realize the in-memory computing function and meet the analog / switch ratio characteristics of each layer of devices.

[0078] In addition, the carbon nanotransistor in the embodiment of the present application can be replaced by other transistors that can be prepared using a low-temperature process, are separated from the substrate material, and can achieve P-type and N-type characteristics (or integrate two unipolar transistors). For example, MoS2 transistors, IGZO transistors, IWO transistors and WeS2 transistors can be used, and no specific limitations are made here.

[0079] In step S602, the first silicon-based control circuit layer, the second analog memory computing array layer, the third digital memory computing array layer and the fourth digital memory computing array layer are vertically stacked in situ, and each layer is connected in sequence through interlayer dielectric vias to construct a monolithic three-dimensional integrated system.

[0080] It should be noted that, due to the low storage density of the digital in-memory computing array, two layers of digital in-memory computing arrays are stacked to achieve a storage density equivalent to that of the analog in-memory computing array, and each functional layer relies on high-density and low parasitic interlayer dielectric vias to achieve communication. In addition, the first silicon-based control circuit layer, the second analog in-memory computing array layer, the third digital in-memory computing array layer, and the fourth digital in-memory computing array layer in the embodiment of the present application are vertically stacked in situ, and the analog in-memory computing array and the digital in-memory computing array are connected through interlayer dielectric vias, thereby constructing a hybrid in-memory computing architecture based on three-dimensional integration, such as Figure 8 shown.

[0081] It should be noted that the core part of the embodiment of the present application is the vertical stacking of the hybrid in-memory computing array, and other circuit modules (cache array, routing array, signal conversion circuit, control circuit, etc.) only play an auxiliary role. Those skilled in the art can modify other circuit modules according to the actual needs of the circuit.

[0082] It can be understood that the chip in the prior art is a planar architecture, and the digital storage and computing array, analog storage and computing array, and processing circuit are all manufactured on the same device layer, occupying a large area, and the on-chip bus bandwidth used for communication is limited, and this communication needs to be carried out frequently. Therefore, the embodiment of the present application can vertically stack the digital storage and computing array, analog storage and computing array, and peripheral processing circuits, and use high-density inter-layer interconnection for communication, thereby reducing the overall circuit area, significantly improving the communication bandwidth, and reducing power consumption.

[0083] In step S603, the target image to be recognized is converted into a read voltage signal that meets the preset compatibility requirements through the monolithic three-dimensional integrated system, and the read voltage signal is respectively input into the second analog memory calculation array layer, the third digital memory calculation array layer and the fourth digital memory calculation array layer to obtain the corresponding output current;

[0084] In step S604, signal calculation and conversion operations are performed on the output current to obtain a target voltage signal, and a hybrid in-memory neural network calculation operation corresponding to the target image to be recognized is performed according to the target voltage signal.

[0085] Furthermore, the embodiments of the present application also need to convert the target image to be identified into a read voltage signal through a monolithic three-dimensional integrated system, and input it into the analog memory computing array layer and the digital memory computing array layer to obtain the corresponding output current, and perform signal calculation and conversion operations on the output current to obtain the target voltage signal, so as to perform the hybrid memory neural network calculation operation corresponding to the target image to be identified according to the target voltage signal.

[0086] Optionally, in one embodiment of the present application, before converting the target image to be identified into a read voltage signal that meets preset compatibility requirements through a monolithic three-dimensional integrated system, it also includes: inputting a preset weight matrix into a routing array in a third digital storage and computing array layer, so as to decompose the weight matrix into high-order weight data that meets preset high-order requirements and low-order weight data that meet preset low-order requirements through the routing array; storing the low-order weight data in the second analog memory computing array layer, and storing the high-order weight data in the third digital storage and computing array layer and the fourth digital storage and computing array layer.

[0087] It should be noted that before converting the target image to be identified into a read voltage signal that meets the preset compatibility requirements through a monolithic three-dimensional integrated system (i.e., performing inference on the image to be identified), the embodiment of the present application also needs to input a weight matrix, and split the weight values ​​through the routing array of the third layer, and store the high-order weight data in the digital memory calculation array, and the low-order weight data in the analog memory calculation array, thereby providing data guidance and basis for the subsequent hybrid memory neural network calculation corresponding to the image to be identified.

[0088] In the actual process of neural network calculations, different neural network layers have different effects on the overall calculation accuracy of the neural network. Technical personnel in this field can adopt different configuration methods for the weight matrices corresponding to different neural network layers as needed to adjust the usage ratio of the digital storage array and the analog storage array to achieve the optimal compromise between performance and calculation accuracy.

[0089] As a possible way to achieve this, Fig. 9As shown, the ResNET-32 network demonstrated in the embodiment of the present application can set all weights to 5-bit binary numbers, and the storage location of the 5-bit value can be flexibly adjusted as needed. For the embodiment of the present application, the most ideal quantization method is as follows Fig. 9 As shown in the lower right corner, the two-layer digital storage array stores 1 bit of data each, and the remaining 3 low-order data are stored in the analog storage array, which can ensure that 1 storage unit in the three-layer array stores 1 data, and the three-layer storage array has the same area; in addition, the initial convolution layer has a greater impact on the accuracy of the neural network, so the weights of this layer are completely stored in the digital storage array; the fully connected layer connected to the output layer also has a greater impact on the reasoning accuracy, so it is set that the higher 3 bits of data in this layer are stored in the digital storage array, and the 2 low-order data are stored in the analog storage array.

[0090] Since the initial few residual modules have little effect on the calculation accuracy, the embodiment of the present application can store all numerical values ​​into the analog storage array, thereby saving area and power consumption.

[0091] It should be noted that the embodiments of the present application only propose a possible algorithm implementation mapping method for the ResNET-32 network. Those skilled in the art can make changes according to actual conditions. They only need to ensure the overall rule of storing high-order weight data in the digital storage array and low-order values ​​in the analog storage array.

[0092] Optionally, in one embodiment of the present application, the target image to be identified is converted into a read voltage signal that meets preset compatibility requirements through a monolithic three-dimensional integrated system, and the read voltage signal is respectively input into the second analog memory computing array layer, the third digital memory computing array layer, and the fourth digital memory computing array layer to obtain a corresponding output current, including: storing the target image to be identified in a cache array in the monolithic three-dimensional integrated system, and inputting the target image to be identified in the cache array into a preset signal conversion circuit to output a read voltage signal; inputting the read voltage signal into the second analog memory computing array layer, the third digital memory computing array layer, and the fourth digital memory computing array layer, respectively, to obtain the output currents corresponding to the second analog memory computing array layer, the third digital memory computing array layer, and the fourth digital memory computing array layer, respectively.

[0093] In the actual execution of image recognition reasoning, the embodiment of the present application can input the image to be reasoned into the cache array in the single-chip three-dimensional integrated system, such as Fig.10 As shown, the signal is then input into a signal conversion circuit, converted into a read voltage signal compatible with the storage and computing array, and input into the three layers of storage and computing arrays respectively, and the output current of each layer of the storage and computing array is read respectively.

[0094] Optionally, in one embodiment of the present application, signal calculation and conversion operations are performed on the output current to obtain a target voltage signal, and a hybrid in-memory neural network calculation operation corresponding to the target image to be identified is performed based on the target voltage signal, including: adding the output currents of the second analog in-memory calculation array layer, the third digital in-memory calculation array layer, and the fourth digital in-memory calculation array layer through preset inter-layer interconnection lines to obtain a total read current, and sending the total read current to the signal conversion circuit to generate a target voltage signal corresponding to the total read current; storing the target voltage signal in a cache array, and reading the cache array to obtain the target voltage signal, and based on the target voltage signal, performing a hybrid in-memory neural network calculation operation corresponding to the target image to be identified.

[0095] Secondly, the embodiment of the present application can directly add the output current of each layer of the storage and computing array through high-density interlayer interconnection lines to obtain the total read current, and convert the total read current input signal conversion circuit into a voltage signal and store it in the cache array, after which data can be read from the cache array for subsequent calculations.

[0096] It should be noted that in order to realize the above-mentioned high-density hybrid in-memory computing architecture, it is required that the scale of each layer of in-memory computing array is comparable (therefore, 2 layers of digital storage computing arrays are stacked so that the area of ​​a single digital storage computing array and the analog storage computing array is comparable), the computing principles are similar, and at least the output signals are required to be unified current / voltage signals, and can be simply added through inter-layer interconnection. Therefore, according to the different functional requirements of the analog / digital storage computing array, taking advantage of the heterogeneous integration of different devices in a monolithic three-dimensional integrated architecture, the embodiment of the present application uses RRAM devices with the same working principle but different specific material components as array working units in the analog / digital storage computing array.

[0097] It should be noted that, due to process limitations, the embodiments of the present application only manufacture two layers of digital storage arrays. Those skilled in the art may configure different numbers of digital storage arrays according to the performance and accuracy requirements of the image recognition algorithm.

[0098] Fig.11 The figure is a schematic diagram showing the speed comparison between using a single chip 3D integration to realize hybrid in-memory computing and using a 2D chip to realize hybrid in-memory computing. Fig.11 It can be seen that the monolithic three-dimensional integration method of the embodiment of the present application greatly reduces the communication time such as caching, and the speed is increased by 118.74 times.

[0099] According to the hybrid in-memory computing method based on monolithic three-dimensional integration proposed in the embodiment of the present application, a first silicon-based control circuit layer, a second analog in-memory computing array layer, a third digital storage computing array layer and a fourth digital storage computing array layer are constructed; the first silicon-based control circuit layer, the second analog in-memory computing array layer, the third digital storage computing array layer and the fourth digital storage computing array layer are vertically stacked in situ, and each layer is sequentially connected through interlayer dielectric vias to construct a monolithic three-dimensional integrated system; the target image to be identified is converted into a read voltage signal that meets the preset compatibility requirements through the monolithic three-dimensional integrated system, and the read voltage signal is respectively input into the second analog in-memory computing array layer, the third digital storage computing array layer and the fourth digital storage computing array layer to obtain a corresponding output current, and a signal calculation and conversion operation is performed on the output current to obtain a target voltage signal, and a hybrid in-memory neural network computing operation corresponding to the target image to be identified is performed according to the target voltage signal. The present application vertically stacks a digital storage and computing array, an analog storage and computing array, and a peripheral processing circuit, and uses high-density interlayer interconnection for communication, thereby reducing the overall circuit area, significantly improving the communication bandwidth, and reducing power consumption; in addition, the present application uses RRAM devices of different material systems to construct an analog in-memory computing array and a digital in-memory computing array, thereby achieving better computing performance.

[0100] Secondly, a hybrid in-memory computing device based on monolithic three-dimensional integration proposed according to an embodiment of the present application is described with reference to the accompanying drawings.

[0101] Fig.12 It is a block diagram of a hybrid in-memory computing device based on monolithic three-dimensional integration according to an embodiment of the present application.

[0102] like Fig.12 As shown, the hybrid in-memory computing device 10 based on monolithic three-dimensional integration includes: a building module 100, an in-situ vertical stacking module 200, a hybrid in-memory computing module 300 and an execution module 400.

[0103] Among them, the construction module 100 is used to construct a first silicon-based control circuit layer, a second analog in-memory computing array layer, a third digital storage computing array layer and a fourth digital storage computing array layer.

[0104] The in-situ vertical stacking module 200 is used to perform in-situ vertical stacking operations on the first silicon-based control circuit layer, the second analog memory computing array layer, the third digital memory computing array layer and the fourth digital memory computing array layer, and connect each layer in sequence through interlayer dielectric vias to build a monolithic three-dimensional integrated system.

[0105] The hybrid in-memory computing module 300 is used to convert the target image to be recognized into a read voltage signal that meets the preset compatibility requirements through a single-chip three-dimensional integrated system, and input the read voltage signal into the second analog in-memory computing array layer, the third digital in-memory computing array layer, and the fourth digital in-memory computing array layer, respectively, to obtain a corresponding output current;

[0106] The execution module 400 is used to perform signal calculation and conversion operations on the output current to obtain a target voltage signal, and to perform a hybrid in-memory neural network calculation operation corresponding to the target image to be identified according to the target voltage signal.

[0107] Optionally, in one embodiment of the present application, the building module 100 includes: a first building unit and a second building unit.

[0108] Among them, the first establishment unit is used to construct a first silicon-based control circuit layer based on a preset standard silicon-based CMOS process, and to construct a second analog in-memory computing array layer through a first preset base resistive memory.

[0109] The second establishing unit is used to construct a third digital storage and computing array layer and a fourth digital storage and computing array layer by using the preset carbon nanotube transistors and the second preset base resistive memory.

[0110] Optionally, in one embodiment of the present application, the hybrid in-memory computing device 10 based on monolithic three-dimensional integration of the embodiment of the present application further includes: a decomposition module and a storage module.

[0111] Among them, the decomposition module is used to input the preset weight matrix into the routing array in the third digital storage array layer before converting the target image to be identified into a read voltage signal that meets the preset compatibility requirements through the monolithic three-dimensional integrated system, so as to decompose the weight matrix into high-order weight data that meets the preset high-order requirements and low-order weight data that meet the preset low-order requirements through the routing array.

[0112] The storage module is used to store low-order weight data in the second analog memory computing array layer, and store high-order weight data in the third digital memory computing array layer and the fourth digital memory computing array layer.

[0113] Optionally, in one embodiment of the present application, the hybrid in-memory computing module 300 includes: a signal conversion unit and an input unit.

[0114] The signal conversion unit is used to store the target image to be identified in the cache array in the monolithic three-dimensional integrated system, and input the target image to be identified in the cache array to a preset signal conversion circuit to output a read voltage signal.

[0115] The input unit is used to input the read voltage signal into the second analog memory computing array layer, the third digital memory computing array layer and the fourth digital memory computing array layer respectively, so as to obtain the output current corresponding to the second analog memory computing array layer, the third digital memory computing array layer and the fourth digital memory computing array layer respectively.

[0116] Optionally, in one embodiment of the present application, the execution module 400 includes: an adding unit and an execution unit.

[0117] Among them, the adding unit is used to add the output currents of the second analog memory computing array layer, the third digital memory computing array layer and the fourth digital memory computing array layer through preset inter-layer interconnection lines to obtain a total read current, and send the total read current to the signal conversion circuit to generate a target voltage signal corresponding to the total read current.

[0118] The execution unit is used to store the target voltage signal in a cache array, read the cache array to obtain the target voltage signal, and based on the target voltage signal, execute the hybrid in-memory neural network calculation operation corresponding to the target image to be identified.

[0119] It should be noted that the aforementioned explanation of the embodiment of the hybrid in-memory computing method based on monolithic three-dimensional integration is also applicable to the hybrid in-memory computing device based on monolithic three-dimensional integration of this embodiment, and will not be repeated here.

[0120] A hybrid in-memory computing device based on monolithic three-dimensional integration proposed in an embodiment of the present application includes a construction module for constructing a first silicon-based control circuit layer, a second analog in-memory computing array layer, a third digital in-memory computing array layer and a fourth digital in-memory computing array layer; an in-situ vertical stacking module for performing in-situ vertical stacking operations on the first silicon-based control circuit layer, the second analog in-memory computing array layer, the third digital in-memory computing array layer and the fourth digital in-memory computing array layer, and connecting each layer in sequence through interlayer dielectric vias to construct a monolithic three-dimensional integrated system; a hybrid in-memory computing module for converting a target image to be identified into a read voltage signal that meets preset compatibility requirements through a monolithic three-dimensional integrated system, and inputting the read voltage signal into the second analog in-memory computing array layer, the third digital in-memory computing array layer and the fourth digital in-memory computing array layer respectively to obtain a corresponding output current; an execution module for performing signal calculation and conversion operations on the output current to obtain a target voltage signal, and executing a hybrid in-memory neural network calculation operation corresponding to the target image to be identified according to the target voltage signal. The present application vertically stacks a digital storage and computing array, an analog storage and computing array, and a peripheral processing circuit, and uses high-density interlayer interconnection for communication, thereby reducing the overall circuit area, significantly improving the communication bandwidth, and reducing power consumption; in addition, the present application uses RRAM devices of different material systems to construct an analog in-memory computing array and a digital in-memory computing array, thereby achieving better computing performance.

[0121] Fig.13 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may include:

[0122] A memory 1301 , a processor 1302 , and a computer program stored in the memory 1301 and executable on the processor 1302 .

[0123] When the processor 1302 executes the program, the hybrid in-memory computing method based on single-chip three-dimensional integration provided in the above embodiment is implemented.

[0124] Furthermore, the electronic device further comprises:

[0125] The communication interface 1303 is used for communication between the memory 1301 and the processor 1302 .

[0126] The memory 1301 is used to store computer programs that can be executed on the processor 1302 .

[0127] The memory 1301 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0128] If the memory 1301, the processor 1302 and the communication interface 1303 are implemented independently, the communication interface 1303, the memory 1301 and the processor 1302 can be connected to each other through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.13 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0129] Optionally, in a specific implementation, if the memory 1301, the processor 1302 and the communication interface 1303 are integrated on a chip, the memory 1301, the processor 1302 and the communication interface 1303 can communicate with each other through an internal interface.

[0130] The processor 1302 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0131] An embodiment of the present application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-mentioned hybrid in-memory computing method based on single-chip three-dimensional integration.

[0132] An embodiment of the present application also provides a computer program product, including a computer program, which, when executed, is used to implement the above-mentioned hybrid in-memory computing method based on monolithic three-dimensional integration.

[0133] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0134] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0135] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or N executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0136] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or N wirings (electronic devices), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways as necessary and then storing it in a computer memory.

[0137] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above embodiment, the N steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0138] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0139] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0140] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A hybrid in-memory computing method based on monolithic three-dimensional integration, characterized in that: The following steps are involved: Constructing a first silicon-based control circuit layer, a second analog in-memory computing array layer, a third digital memory computing array layer, and a fourth digital memory computing array layer; The first silicon-based control circuit layer, the second analog in-memory computing array layer, the third digital memory computing array layer and the fourth digital memory computing array layer are vertically stacked in situ, and each layer is sequentially connected through interlayer dielectric vias to construct a monolithic three-dimensional integrated system; The target image to be recognized is converted into a read voltage signal that meets preset compatibility requirements through the monolithic three-dimensional integrated system, and the read voltage signal is respectively input into the second analog memory computing array layer, the third digital memory computing array layer and the fourth digital memory computing array layer to obtain a corresponding output current; Signal calculation and conversion operations are performed on the output current to obtain a target voltage signal, and a hybrid in-memory neural network calculation operation corresponding to the target image to be recognized is performed according to the target voltage signal.

2. The method according to claim 1, characterized in that The construction of the first silicon-based control circuit layer, the second analog in-memory computing array layer, the third digital storage computing array layer and the fourth digital storage computing array layer includes: Based on a preset standard silicon-based CMOS process, the first silicon-based control circuit layer is constructed, and the second analog in-memory computing array layer is constructed through a first preset base resistive memory; The third digital storage and computing array layer and the fourth digital storage and computing array layer are constructed using preset carbon nanotube transistors and a second preset base resistive memory.

3. The method according to claim 1, characterized in that Before converting the target image to be recognized into a read voltage signal that meets the preset compatibility requirement through the monolithic three-dimensional integrated system, the method further includes: Inputting a preset weight matrix into a routing array in the third digital storage array layer, so as to decompose the weight matrix into high-order weight data meeting a preset high-order requirement and low-order weight data meeting a preset low-order requirement through the routing array; The low-order weight data is stored in the second analog in-memory computing array layer, and the high-order weight data is stored in the third digital in-memory computing array layer and the fourth digital in-memory computing array layer.

4. The method according to claim 3, characterized in that The target image to be identified is converted into a read voltage signal that meets preset compatibility requirements through the monolithic three-dimensional integrated system, and the read voltage signal is respectively input into the second analog in-memory computing array layer, the third digital in-memory computing array layer, and the fourth digital in-memory computing array layer to obtain a corresponding output current, and a signal calculation and conversion operation is performed on the output current to obtain a target voltage signal, and a hybrid in-memory neural network calculation operation corresponding to the target image to be identified is performed according to the target voltage signal, including: storing the target image to be identified in a cache array in the monolithic three-dimensional integrated system, and inputting the target image to be identified in the cache array into a preset signal conversion circuit to output the read voltage signal; The read voltage signal is input into the second analog memory computing array layer, the third digital memory computing array layer and the fourth digital memory computing array layer respectively to obtain the output currents corresponding to the second analog memory computing array layer, the third digital memory computing array layer and the fourth digital memory computing array layer respectively.

5. The method according to claim 4, characterized in that The performing of signal calculation and conversion operations on the output current to obtain a target voltage signal, and performing a hybrid in-memory neural network calculation operation corresponding to the target image to be recognized according to the target voltage signal, comprises: The output currents of the second analog memory computing array layer, the third digital memory computing array layer and the fourth digital memory computing array layer are added together through a preset inter-layer interconnection line to obtain a total readout current, and the total readout current is sent to the signal conversion circuit to generate a target voltage signal corresponding to the total readout current; The target voltage signal is stored in the cache array, and the cache array is read to obtain the target voltage signal, and based on the target voltage signal, a hybrid in-memory neural network calculation operation corresponding to the target image to be identified is performed.

6. A hybrid in-memory computing device based on a single-chip three-dimensional integration, characterized in that: include: A construction module for constructing a first silicon-based control circuit layer, a second analog in-memory computing array layer, a third digital in-memory computing array layer, and a fourth digital in-memory computing array layer; An in-situ vertical stacking module, used to perform an in-situ vertical stacking operation on the first silicon-based control circuit layer, the second analog in-memory computing array layer, the third digital storage computing array layer and the fourth digital storage computing array layer, and sequentially connect each layer through interlayer dielectric vias to construct a monolithic three-dimensional integrated system; a hybrid in-memory computing module, configured to convert the target image to be recognized into a read voltage signal that meets preset compatibility requirements through the monolithic three-dimensional integrated system, and input the read voltage signal into the second analog in-memory computing array layer, the third digital in-memory computing array layer, and the fourth digital in-memory computing array layer, respectively, to obtain a corresponding output current; An execution module is used to perform signal calculation and conversion operations on the output current to obtain a target voltage signal, and to perform a hybrid in-memory neural network calculation operation corresponding to the target image to be identified according to the target voltage signal.

7. The device according to claim 6, characterized in that The building blocks include: A first establishing unit is used to construct the first silicon-based control circuit layer based on a preset standard silicon-based CMOS process, and to construct the second analog in-memory computing array layer through a first preset base resistive memory; The second establishing unit is used to construct the third digital storage and computing array layer and the fourth digital storage and computing array layer by using the preset carbon nano transistors and the second preset base resistive memory.

8. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the hybrid in-memory computing method based on monolithic three-dimensional integration as described in any one of claims 1 to 5.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the hybrid in-memory computing method based on monolithic three-dimensional integration as described in any one of claims 1 to 5.

10. A computer program product, comprising a computer program, characterized in that The computer program is executed to implement the hybrid in-memory computing method based on monolithic three-dimensional integration as described in any one of claims 1-5.

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