Integrated circuit 3D packaging structure based on general IP and packaging method thereof

Abstract

The invention discloses an integrated circuit 3D packaging structure based on general IPs and a packaging method thereof, and belongs to the technical field of semiconductors. Hot spot areas of all layers of general IPs can be accurately identified through thermal simulation, stress concentration areas are identified in combination with simulation, then through-silicon-via parameters are adjusted, heat conduction paths are optimized, local temperature is effectively reduced, and the packaging efficiency is improved. Mechanical stress is relieved while the thermal reliability of the chip is improved, chip cracking or failure caused by stress concentration is avoided, and the structural reliability of packaging is improved; and comparing the cross-sectional view of the through-silicon via with a corresponding expected cross-sectional view of the through-silicon via, identifying abnormal depth points, adjusting etching parameters of the corresponding through-silicon via at the abnormal depth points, and repeatedly adjusting the etching parameters until the number of the abnormal depth points is zero, so that the aperture of the etched through-silicon via is close to an expected value, and the packaging quality is improved. The finished product performance is ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a 3D packaging structure of an integrated circuit based on a universal IP and a packaging method thereof. Background Art

[0002] With the rapid development of modern society, the performance requirements of electronic devices are constantly increasing, and the requirements for integrated circuit packaging technology are getting higher and higher. Traditional two-dimensional integrated circuit packaging technology has problems such as low space utilization, limited electrical performance and insufficient heat dissipation capacity, which restricts the further development and improvement of electronic devices.

[0003] Three-dimensional integrated circuit packaging usually uses silicon vias to connect the vertically stacked layers. Therefore, silicon vias have a great impact on the performance of the finished package. Therefore, how to improve the performance of the finished product by optimizing the setting of silicon vias during the packaging process is an important issue in the field of semiconductor packaging. Summary of the invention

[0004] The present invention is to solve the technical problems existing in the prior art. The present invention provides a 3D packaging method for integrated circuits based on a universal IP, comprising the following steps: S1. Construct corresponding packaging models according to each stacked packaging module and the through silicon via parameters set for each layer of general IP, and perform thermal simulation on each packaging model to obtain the hot spot area and stress concentration area of ​​each layer of general IP; S2. For a common IP layer having hot spots and / or stress concentration areas, readjust the through silicon via parameters; S3, repeat S1 to S2 until there are no hot spots and stress concentration areas in each layer of the universal IP, and obtain the final through silicon via parameters of each layer of the universal IP, and thereby establish the expected cross-sectional diagram of the through silicon via of each layer of the universal IP; S4, after performing TSV etching according to the final TSV parameters of each layer of the universal IP and the corresponding set etching parameters, a TSV cross-sectional view of each layer of the universal IP is obtained; S5, comparing the through silicon via cross-sectional image with the corresponding through silicon via expected cross-sectional image, and identifying abnormal depth points; S6, adjusting the etching parameters of the corresponding through silicon via at the abnormal depth point; S7, repeat S4 to S6 until the number of abnormal depth points is zero, obtain the final etching parameters of the common IPs of each layer, and perform packaging according to the final through silicon via parameters and etching parameters of the common IPs of each layer.

[0005] Furthermore, the through silicon via parameters include quantity, distribution spacing, hole diameter and hole depth.

[0006] Furthermore, the etching parameters include the amount of etching gas and the amount of passivation gas.

[0007] Furthermore, the thermal simulation is performed on each packaging model to obtain the hotspot area and stress concentration area of ​​each layer of the general IP, specifically: Perform thermal simulation on each package model to obtain the temperature distribution of each layer of common IP under the preset working time of each package model; Perform thermal stress simulation based on temperature distribution to obtain the thermal stress distribution of each layer of general IP for each packaging model under preset working time; The area where the temperature is greater than the preset temperature threshold is regarded as the hot spot area, and the area where the stress is greater than the preset stress threshold is regarded as the stress concentration area.

[0008] Further, the expected cross-sectional view of the through silicon via is established based on the final hole diameter and hole depth, and in the expected cross-sectional view of the through silicon via, the expected verticality of the expected hole wall of the through silicon via is 90 degrees.

[0009] Furthermore, the cross-sectional view of the through silicon via is compared with the corresponding expected cross-sectional view of the through silicon via to identify abnormal depth points, specifically: Comparing the through silicon via cross-sectional image with the corresponding through silicon via expected cross-sectional image, identifying from the through silicon via cross-sectional image a plurality of first deviated hole wall segments that deviate from the expected hole wall in the corresponding through silicon via expected cross-sectional image; If there is a turning point on the first deviated hole wall segment, the corresponding first deviated hole wall segment is divided into a plurality of second deviated hole wall segments according to the turning point; if there is no turning point on the first deviated hole wall segment, the corresponding first deviated hole wall segment is used as the second deviated hole wall segment; The second deviated hole wall segment whose angle of deviation from the expected verticality is greater than or equal to the preset deviation angle threshold is taken as the third deviated hole wall segment, and the starting endpoint of the third deviated hole wall segment is taken as the abnormal depth point.

[0010] Furthermore, the etching parameters of the corresponding through silicon via are adjusted at the abnormal depth point, specifically: If the aperture corresponding to the abnormal depth point is larger than the aperture in the final through-silicon via parameter of the corresponding general IP, the ratio of the etching gas amount to the passivation gas amount is reduced; If the aperture corresponding to the abnormal depth point is smaller than the aperture in the final through silicon via parameter of the corresponding general IP, the ratio of the etching gas amount to the passivation gas amount is increased.

[0011] The present invention also provides an integrated circuit 3D packaging structure based on universal IP, applying the above-mentioned integrated circuit 3D packaging method based on universal IP, comprising: a substrate and a chip layer; The chip layer includes one or more stacked packaging modules; the stacked packaging modules include multiple layers of universal IP layers, and the universal IP layers of the stacked packaging modules are electrically connected through silicon vias.

[0012] The present invention also provides an electronic device, including a processor and a memory, wherein the memory is used to store computer program code, and the computer program code includes computer instructions. When the processor executes the computer instructions, the electronic device executes the above-mentioned integrated circuit 3D packaging method based on universal IP.

[0013] The present invention also provides a computer-readable storage medium, in which a computer program is stored. The computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes the above-mentioned integrated circuit 3D packaging method based on universal IP.

[0014] Compared with the prior art, the present invention has the following beneficial effects: The present invention can accurately identify the hot spots of each layer of the general IP through thermal simulation, and identify the stress concentration area in combination with simulation, and then adjust the through silicon via parameters to optimize the heat conduction path, effectively reduce the local temperature, improve the thermal reliability of the chip, and relieve mechanical stress, avoid chip cracking or failure caused by stress concentration, and improve the structural reliability of the package; By comparing the TSV cross-sectional image with the corresponding expected TSV cross-sectional image and identifying abnormal depth points, the etching parameters of the corresponding TSV are adjusted at the abnormal depth points. The etching parameters are adjusted repeatedly in this step until the number of abnormal depth points is zero, so that the aperture of the etched TSV is close to the expected value, thereby improving the packaging quality and ensuring the performance of the finished product. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0017] Figure 1 It is a flow chart of a 3D packaging method of integrated circuit based on universal IP of the present invention; Figure 2 It is a flow chart of step S5 in a method for 3D packaging of integrated circuits based on universal IP of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0020] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0021] Embodiment 1 See also Figure 1 As shown, the present invention provides a 3D packaging method for integrated circuits based on universal IP, which specifically includes the following steps: S1. Construct corresponding packaging models according to each stacked packaging module and the through silicon via parameters set for each layer of general IP, and perform thermal simulation on each packaging model to obtain the hot spot area and stress concentration area of ​​each layer of general IP; S2. For a common IP layer having hot spots and / or stress concentration areas, readjust the through silicon via parameters; S3, repeat S1 to S2 until there are no hot spots and stress concentration areas in each layer of the universal IP, and obtain the final through silicon via parameters of each layer of the universal IP, and thereby establish the expected cross-sectional diagram of the through silicon via of each layer of the universal IP; S4, after performing TSV etching according to the final TSV parameters of each layer of the universal IP and the corresponding set etching parameters, a TSV cross-sectional view of each layer of the universal IP is obtained; S5, comparing the through silicon via cross-sectional image with the corresponding through silicon via expected cross-sectional image, and identifying abnormal depth points; S6, adjusting the etching parameters of the corresponding through silicon via at the abnormal depth point; S7, repeat S4 to S6 until the number of abnormal depth points is zero, obtain the final etching parameters of the common IPs of each layer, and perform packaging according to the final through silicon via parameters and etching parameters of the common IPs of each layer.

[0022] In step S1, a corresponding packaging model is constructed according to each stacked packaging module and the TSV parameters set for each layer of general IP, and a thermal simulation is performed on each packaging model to obtain the hotspot area and stress concentration area of ​​each layer of general IP: The through silicon via parameters include quantity, distribution spacing, hole diameter and hole depth.

[0023] The stacking packaging module is obtained by predetermining the packaging layout of the general IP, for example, the stacking packaging module A is formed by stacking and packaging three layers of general IP, and the stacking packaging module B is formed by stacking and packaging two layers of general IP; When the TSV parameters set by the general IP of each layer are initially set, they are specifically preliminarily set in each stacked packaging module according to the signal requirements and overcurrent requirements of the general IP of each layer.

[0024] Universal IP refers to pre-designed, verified and optimized functional modules that can be reused in different chip designs or 3D packages, such as processor cores, DRAM memories, analog modules, interface modules and sensor modules, etc. For example, HBM, or high-bandwidth memory, is composed of multiple layers of DRAM memories stacked together, with inter-layer interconnection achieved through silicon vias (TSVs).

[0025] Signal requirements refer to the signal type, signal bandwidth, delay requirements, and signal integrity that need to be transmitted between layers. For example, high-frequency signals may require shorter paths to reduce delays and signal attenuation, which may require more TSVs to provide sufficient interconnection bandwidth. Overcurrent requirements involve the design of power and ground lines to ensure sufficient current carrying capacity to avoid voltage drops and overheating problems. Different functional layers (such as logic layers and storage layers) may have different current requirements, and the number of TSVs needs to be allocated based on the power consumption of each layer.

[0026] The thermal simulation of each package model is performed to obtain the hot spots and stress concentration areas of each layer of the general IP, specifically: S11, performing thermal simulation on each package model to obtain the temperature distribution of each layer of the general IP of each package model under a preset working time; S12, performing thermal stress simulation based on the temperature distribution to obtain the thermal stress distribution of each layer of the general IP of each packaging model under a preset working time; S13, taking the area where the temperature is greater than the preset temperature threshold as the hot spot area, and taking the area where the stress is greater than the preset stress threshold as the stress concentration area.

[0027] In step S1, the packaging model is constructed and thermal simulation is performed by using existing corresponding simulation software. The specific simulation steps belong to conventional technical means in the field and will not be described in detail here.

[0028] In step S2, the parameters of the through silicon vias are readjusted for the general IP layer having the hot spot area and / or the stress concentration area. Specifically, the R&D personnel empirically adjust the through silicon via parameters according to the specific numerical conditions of the hot spot area and the stress concentration area and the parameters of the actual general IP. For example, if the temperature is too high, the number of through silicon vias can be appropriately increased. The specific adjustment belongs to the prior art and will not be repeated here. It should be noted that in order not to affect the circuit of the general IP and the signal transmission between the general IPs of each layer, the corresponding preset adjustment threshold range is set in advance, and when the silicon through hole parameters are adjusted, they are adjusted within the corresponding preset adjustment threshold range.

[0029] S3. Repeat steps S1 to S2 until there are no hot spots and stress concentration areas in each layer of the general IP, obtain the final through silicon via parameters of each layer of the general IP, and obtain the expected cross-sectional view of the through silicon via of each layer of the general IP: The expected cross-sectional view of the through silicon via is established based on the final hole diameter and hole depth, and in the expected cross-sectional view of the through silicon via, the expected verticality of the expected hole wall of the through silicon via is 90 degrees.

[0030] S4. After performing TSV etching according to the final TSV parameters of each layer of the universal IP and the corresponding set etching parameters, a TSV cross-sectional view of each layer of the universal IP is obtained: The etching parameters include the amount of etching gas and the amount of passivation gas, etc.

[0031] The TSV etching may be simulated etching or actual test etching.

[0032] The simulated etching can be specifically simulated by using existing corresponding simulation software according to the preliminarily set etching parameters and the performance parameters of the etching equipment.

[0033] The actual test etching is to actually perform TSV etching in the test silicon wafer according to the final TSV parameters of each layer of the universal IP and the corresponding set etching parameters, and the TSV cross-section in the actual test etching is obtained by microscopic slicing; The etching parameters set for the first time are set according to the corresponding through silicon via parameters.

[0034] See also Figure 2 As shown, in step S5, the cross-sectional view of the through silicon via is compared with the corresponding expected cross-sectional view of the through silicon via to identify abnormal depth points, specifically: S51, comparing the through silicon via cross-sectional image with the corresponding expected through silicon via cross-sectional image, and identifying from the through silicon via cross-sectional image a plurality of first deviated hole wall segments that deviate from the expected hole wall in the corresponding expected through silicon via cross-sectional image; Only the starting endpoint and the ending endpoint of the first deviated hole wall segment can be mapped on the expected hole wall, or only the starting endpoint can be mapped on the expected hole wall.

[0035] For example, after etching, the hole wall deviates from the expected hole wall, and before reaching the final etching depth, it deviates back to intersect with the vertical expected hole wall to obtain an intersection. The hole wall between the deviation point and the intersection is a first deviated hole wall segment, and the intersection is the end endpoint of the current first deviated hole wall segment. Only the starting endpoint and the end endpoint of the current first deviated hole wall segment can be mapped on the expected hole wall. At the same time, the end endpoint of the current first deviated hole wall segment is also the starting endpoint of the next first deviated hole wall segment. For another example, the hole wall deviates from the expected hole wall until the final etching depth, and there is no intersection with the vertical expected hole wall in the middle. Then the through silicon via has only this first deviated hole wall segment, and only the starting endpoint can be mapped on the expected hole wall.

[0036] S52, if there is a turning point on the first deviated hole wall segment, dividing the corresponding first deviated hole wall segment into a plurality of second deviated hole wall segments according to the turning point; if there is no turning point on the first deviated hole wall segment, taking the corresponding first deviated hole wall segment as the second deviated hole wall segment; Description of the turning point: If the first deviated hole wall segment does not extend downward according to the original deviation angle, but deviates again, then the first deviated hole wall segment has a turning point. If the first deviated hole wall segment deviates N times, there are N turning points.

[0037] S53: taking the second deviated hole wall segment whose angle of deviation from the expected verticality is greater than or equal to the preset deviation angle threshold as the third deviated hole wall segment, and taking the starting endpoint of the third deviated hole wall segment as the abnormal depth point.

[0038] In step S6, the etching parameters of the corresponding through silicon via are adjusted at the abnormal depth point, specifically: If the aperture corresponding to the abnormal depth point is larger than the aperture in the final through-silicon via parameter of the corresponding general IP, the ratio of the etching gas amount to the passivation gas amount is reduced; If the aperture corresponding to the abnormal depth point is smaller than the aperture in the final through silicon via parameter of the corresponding general IP, the ratio of the etching gas amount to the passivation gas amount is increased.

[0039] In silicon via etching, the main function of the etching gas is to generate active free radicals through plasma decomposition. These free radicals react chemically with silicon materials to generate volatile compounds to remove silicon materials and form through holes. If the etching gas is insufficient, the pore size will be reduced. On the contrary, if the etching gas is excessive, it will cause over-etching and increase the pore size. The function of the passivation gas is to form a protective layer during the etching process to prevent the sidewalls from being over-etched. If the passivation gas is excessive, the protective layer will be too thick, resulting in a reduction in the pore size. On the contrary, insufficient passivation gas will lead to a lack of protection of the sidewalls and an increase in the pore size. Therefore, where the pore size increases, the amount of etching gas needs to be reduced and / or the amount of passivation gas needs to be increased, and where the pore size decreases, the amount of etching gas needs to be increased and / or the amount of passivation gas needs to be reduced.

[0040] Embodiment 2 The present invention also provides an integrated circuit 3D packaging structure based on a universal IP, applying the above-mentioned integrated circuit 3D packaging method based on a universal IP, comprising: a substrate and a chip layer; The chip layer includes one or more stacked packaging modules; the stacked packaging modules include multiple layers of universal IP layers, and the universal IP layers of the stacked packaging modules are electrically connected through silicon vias.

[0041] Embodiment 3 The present invention also provides an electronic device, including: a processor, a sending device, an input device, an output device and a memory. The processor can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit, or one or more integrated circuits, and is used to execute relevant programs to implement the technical solution provided in the embodiment of the present application. The memory can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device or a random access memory (RAM), and is used to store computer program code. The computer program code includes computer instructions. When the processor executes the computer instructions, the electronic device executes a method as described in any of the above possible implementation methods.

[0042] Embodiment 4 The present invention also provides a computer-readable storage medium, in which a computer program is stored. The computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes a method as described in any possible implementation manner.

[0043] The beneficial effects of the present invention are: The present invention can accurately identify the hot spots of each layer of the general IP through thermal simulation, and identify the stress concentration area in combination with simulation, and then adjust the through silicon via parameters to optimize the heat conduction path, effectively reduce the local temperature, improve the thermal reliability of the chip, and relieve mechanical stress, avoid chip cracking or failure caused by stress concentration, and improve the structural reliability of the package; By comparing the TSV cross-sectional image with the corresponding expected TSV cross-sectional image and identifying abnormal depth points, the etching parameters of the corresponding TSV are adjusted at the abnormal depth points. The etching parameters are adjusted repeatedly in this step until the number of abnormal depth points is zero, so that the aperture of the etched TSV is close to the expected value, thereby improving the packaging quality and ensuring the performance of the finished product.

[0044] In the description of the specification, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0045] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit. If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method of each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (RandomAccess Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0046] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A 3D packaging method for integrated circuits based on universal IP, characterized in that: The following steps are involved: S1. Construct corresponding packaging models according to each stacked packaging module and the through silicon via parameters set for each layer of general IP, and perform thermal simulation on each packaging model to obtain the hot spot area and stress concentration area of ​​each layer of general IP; S2. For a common IP layer having hot spots and / or stress concentration areas, readjust the through silicon via parameters; S3, repeat S1 to S2 until there are no hot spots and stress concentration areas in each layer of the universal IP, and obtain the final through silicon via parameters of each layer of the universal IP, and thereby establish the expected cross-sectional diagram of the through silicon via of each layer of the universal IP; S4, after performing TSV etching according to the final TSV parameters of each layer of the universal IP and the corresponding set etching parameters, a TSV cross-sectional view of each layer of the universal IP is obtained; S5, comparing the through silicon via cross-sectional image with the corresponding through silicon via expected cross-sectional image, and identifying abnormal depth points; S6, adjusting the etching parameters of the corresponding through silicon via at the abnormal depth point; S7, repeat S4 to S6 until the number of abnormal depth points is zero, obtain the final etching parameters of the common IPs of each layer, and perform packaging according to the final through silicon via parameters and etching parameters of the common IPs of each layer.

2. The integrated circuit 3D packaging method based on universal IP according to claim 1, characterized in that: The through silicon via parameters include quantity, distribution spacing, hole diameter and hole depth.

3. The integrated circuit 3D packaging method based on universal IP according to claim 1, characterized in that: The etching parameters include the amount of etching gas and the amount of passivation gas.

4. The integrated circuit 3D packaging method based on universal IP according to claim 1, characterized in that: The thermal simulation of each package model is performed to obtain the hotspot area and stress concentration area of ​​each layer of the general IP, specifically: Perform thermal simulation on each package model to obtain the temperature distribution of each layer of common IP under the preset working time of each package model; Perform thermal stress simulation based on temperature distribution to obtain the thermal stress distribution of each layer of general IP for each packaging model under preset working time; The area where the temperature is greater than the preset temperature threshold is regarded as the hot spot area, and the area where the stress is greater than the preset stress threshold is regarded as the stress concentration area.

5. The integrated circuit 3D packaging method based on universal IP according to claim 2, characterized in that: The expected cross-sectional view of the through silicon via is established based on the final hole diameter and hole depth, and in the expected cross-sectional view of the through silicon via, the expected verticality of the expected hole wall of the through silicon via is 90 degrees.

6. The integrated circuit 3D packaging method based on universal IP according to claim 5, characterized in that: The through silicon via cross-sectional image is compared with the corresponding through silicon via expected cross-sectional image to identify abnormal depth points, specifically: Comparing the through silicon via cross-sectional image with the corresponding through silicon via expected cross-sectional image, identifying from the through silicon via cross-sectional image a plurality of first deviated hole wall segments that deviate from the expected hole wall in the corresponding through silicon via expected cross-sectional image; If there is a turning point on the first deviated hole wall segment, the corresponding first deviated hole wall segment is divided into a plurality of second deviated hole wall segments according to the turning point; if there is no turning point on the first deviated hole wall segment, the corresponding first deviated hole wall segment is used as the second deviated hole wall segment; The second deviated hole wall segment whose angle of deviation from the expected verticality is greater than or equal to the preset deviation angle threshold is taken as the third deviated hole wall segment, and the starting endpoint of the third deviated hole wall segment is taken as the abnormal depth point.

7. The integrated circuit 3D packaging method based on universal IP according to claim 3, characterized in that: The step of adjusting the etching parameters of the corresponding through silicon via at the abnormal depth point is specifically as follows: If the aperture corresponding to the abnormal depth point is larger than the aperture in the final through-silicon via parameter of the corresponding general IP, the ratio of the etching gas amount to the passivation gas amount is reduced; If the aperture corresponding to the abnormal depth point is smaller than the aperture in the final through silicon via parameter of the corresponding general IP, the ratio of the etching gas amount to the passivation gas amount is increased.

8. An integrated circuit 3D packaging structure based on a universal IP, using the integrated circuit 3D packaging method based on a universal IP as claimed in any one of claims 1 to 7, characterized in that: include: Substrate and chip layers; The chip layer includes one or more stacked package modules; The stacked packaging module includes multiple layers of universal IP layers, and the universal IP layers of the stacked packaging module are electrically connected through silicon vias.

9. An electronic device, characterized in that: It includes a processor and a memory, the memory is used to store computer program code, the computer program code includes computer instructions, and when the processor executes the computer instructions, the electronic device executes the integrated circuit 3D packaging method based on universal IP as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes the integrated circuit 3D packaging method based on universal IP as described in any one of claims 1 to 7.

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