Method and system for evaluating pin access efficiency

Abstract

The invention relates to the technical field of integrated circuits, and discloses a method and system for evaluating pin access efficiency. The method comprises the following steps: arranging units corresponding to a logic netlist synthesized by user circuit design on a chip, and calculating the total number of multiplexers in each switch unit on the chip; calculating the total number of multiplexers used by each line network in each switch unit according to the logic netlist and the description file thereof; calculating the total number of multiplexers used by all wire nets in each switch unit; and calculating the resource utilization rate of each switch unit according to the total number of the multiplexers in each switch unit and the total number of the multiplexers used by all the wire networks, so as to evaluate the pin access efficiency. According to the method, the pin access efficiency can be evaluated in real time and the layout strategy can be adjusted in time in the operation process, so that wiring is optimized, congestion is reduced, the wiring convergence speed is increased, and the method has the advantages of being lighter, more flexible and more efficient.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a method and system for evaluating pin access efficiency. Background Art

[0002] Through the process of logic synthesis, layout, and routing, the user's circuit design can be implemented on the FPGA (Field Programmable Gate Array) chip. After the logic synthesis process is completed, the user's circuit design will become a logic netlist, and the layout will reasonably place the bottom-level units in the logic netlist on the hardware structure resources of the chip.

[0003] The layout will follow certain rules when placing, such as logical area division, clock area division, constraint-driven layout, timing-driven layout, resource optimization layout, etc. For example, modules on the critical path are placed in adjacent positions to reduce the path length, or clock-related modules are placed together to reduce clock delay, etc. The local resources of the chip are limited, and all related modules cannot be placed together. Even if the area can accommodate so many modules, there may not be enough wiring resources. Wiring is to map the wire nets in the circuit design to the wiring resources of the chip and connect the units at the bottom of the hardware. When the wiring resources in a certain area are used in large quantities, it will cause line congestion. When different wire nets use the same wiring resources, it will cause conflicts. A certain degree of wiring results can be fed back to guide the layout, of course, this will have a certain runtime overhead. And IMX (input multiplexer) is a wiring resource that is used frequently in a local unit. Its usage can reflect whether the layout maximizes the use of resources in the local area and whether it is placed well enough, that is, the pin access efficiency. The number of imux used can be calculated without relying on routing, and can be calculated based on layout alone. Generally speaking, the less resources are used, the better the layout and routing results will be.

[0004] Currently, there is no effective and feasible standard to evaluate the pin accessment efficiency of the layout. The commonly used area report is generally to count the total number of specific resources such as logic cells, registers, lookup tables (LUTs), memories, input and output (I / O) used in the entire design after the entire logic synthesis, layout, and routing process is completed, and the resource usage and power consumption are analyzed to evaluate and optimize the design.

[0005] Existing evaluation and optimization usually lack runtime feedback after the entire logic synthesis, placement, and routing process is completed.

[0006] This section is intended to provide a background or context for understanding the embodiments of the present application and is for reference only. The applicant should not be considered to admit that this section belongs to the prior art that has been disclosed before the filing date of the present application. Summary of the invention

[0007] The purpose of the present application is to provide a method and system for evaluating pin access efficiency, which can evaluate the pin access efficiency in real time during operation and adjust the layout strategy in time according to the score.

[0008] The present application discloses a method for evaluating pin access efficiency, comprising:

[0009] Place the units corresponding to the logic netlist synthesized from the user circuit design on the chip, and calculate the total number of multiplexers in each switch unit on the chip;

[0010] Calculate the total number of multiplexers used by each line net in each switch unit according to the logic netlist and its description file;

[0011] Calculate the total number of multiplexers used by all nets in each switch cell; and

[0012] The resource utilization of each switch unit is calculated according to the total number of multiplexers in each switch unit and the total number of multiplexers used by all line nets to evaluate the pin access efficiency.

[0013] In a preferred example, the resource utilization rate of each switch unit is calculated using the following formula:

[0014]

[0015] The score (c,r) represents the resource utilization rate of the switch unit in the cth row and the rth column, G (C,r) represents the total number of multiplexers in the switch unit in row c and column r, sum (C,r) Represents the total number of multiplexers used by all the nets in the switch unit in the cth row and the rth column.

[0016] In a preferred embodiment, according to the score (c,r) The value of the switch unit pin access efficiency is divided into four levels in order. (c,r) When the score is greater than or equal to 0 and less than or equal to 25, the pin access efficiency is classified as the first level. (c,r) When the score is greater than 25 and less than or equal to 50, the pin access efficiency is classified as the second level. (c,r) When the score is greater than 50 and less than or equal to 75, the pin access efficiency is classified as the third level. (c,r)When it is greater than 75 and less than or equal to 100, the pin access efficiency is classified into the fourth level, and the lower the value of the resource utilization rate is, the lower the pin access efficiency is.

[0017] In a preferred embodiment, it also includes:

[0018] Calculate the average value of resource utilization of all switch units;

[0019] When the resource utilization rate of the switch unit is less than the average value, adjusting the layout of the switch unit; and

[0020] The resource utilization of the switch unit is recalculated until the resource utilization of the switch unit is greater than the average value.

[0021] In a preferred embodiment, it also includes:

[0022] When the resource utilization rate of the switch unit is less than a first preset value, adjusting the layout of the switch unit; and

[0023] The resource utilization rate of each switch unit is recalculated until the resource utilization rate of each switch unit is greater than or equal to a first preset value.

[0024] In a preferred example, the method further includes: performing routing according to the adjusted layout, and generating an FPGA code stream according to the results of the layout and the routing.

[0025] In a preferred embodiment, each line net is connected to one or more lookup tables in the configurable logic block by one or more multiplexers.

[0026] In a preferred example, each lookup table has multiple pin interfaces.

[0027] The present application also discloses a system for evaluating pin access efficiency, comprising:

[0028] a memory for storing computer executable instructions; and,

[0029] A processor, coupled to the memory, is configured to implement the steps in the method described above when executing the computer executable instructions.

[0030] The present application also discloses a non-transitory computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, the steps in the method described above are implemented.

[0031] In the implementation of the present application, a method is proposed to evaluate the efficiency of pin accessment by calculating the usage of multiplexer imux and converting it into a score in a certain way, thereby guiding layout and routing. imux is a necessary resource to reach the lookup table LUT and trigger DFF. The efficiency score is used to guide the layout to reduce the local imux usage, thereby reducing routing congestion, speeding up routing convergence, and optimizing timing. Compared with guiding design optimization based on area reports and power consumption after the entire logic synthesis, layout, and routing process is completed, the method proposed in the present application can evaluate the pin accessment efficiency in real time during the layout operation, and adjust the layout strategy in time through the efficiency score, which has the advantages of being more timely, more detailed, and more lightweight.

[0032] Each technical feature disclosed in the above invention content, each technical feature disclosed in each implementation mode and example below, and each technical feature disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should be deemed to have been recorded in this specification), unless such combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, while the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a flowchart of a method for evaluating pin access efficiency according to the first embodiment of the present application.

[0034] Figure 2 This is a schematic diagram of partial hardware resources of a local unit of a chip in one embodiment of the present application.

[0035] Figure 3 It is a schematic diagram of the scoring calculation process according to one embodiment of the present application. DETAILED DESCRIPTION

[0036] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0037] Description of some concepts

[0038] Logic synthesis: It is the process of converting high-level design description (such as RTL-level code) into lower-level hardware implementation (such as gate-level netlist) in integrated circuit design. Its purpose is to optimize the circuit design while meeting multiple constraints such as functionality, performance and area.

[0039] Logic Netlist: A file that describes the logic structure of a digital circuit, usually in text form, representing various logic units in the circuit and their connections. The logic netlist is in the middle stage between RTL description and physical implementation in the design flow.

[0040] Net: In digital circuit design, it refers to the signal path between multiple circuit elements (such as logic gates, registers, triggers, etc.). It is a way to describe how signals are transmitted in the circuit.

[0041] Switch Box: In integrated circuits (especially programmable logic devices such as FPGAs), the switch box is a key component for managing signal routing. It allows signals to switch between different wires, thereby achieving flexible signal transmission and connectivity.

[0042] Placement: The main task is to place logic units (such as gate circuits, triggers, etc.) into the physical area of ​​the chip while meeting functional requirements, timing constraints, and area optimization goals. Layout is an important part of the physical design process and is usually performed after logic synthesis and before routing.

[0043] Routing: refers to the process of connecting signals between logic units through physical wires after layout is completed. Routing directly affects the timing performance, power consumption and signal integrity of the chip, and is one of the key steps in successful chip manufacturing.

[0044] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0045] The first embodiment of the present application relates to a method for evaluating pin access efficiency, the process of which is as follows: Figure 1As shown. In the integrated circuit design process, the RTL (Register Transfer Level Code) of the user circuit design is first synthesized into a logic netlist. The logic netlist includes multiple wire nets. Then the logic units in the netlist are laid out to the physical area of ​​the FPGA chip, and finally the logic units are wired to achieve signal connectivity. CLB (Configurable Logic Block) and switch box are the basic components of FPGA chips. CLB is responsible for logic processing, and the switch box is responsible for line jumps. IMU is a type of component in the switch box. The lookup table LUT and the trigger DFF are both components of CLB. One LUT is generally connected to two DFFs. The signal can jump from a certain LUT / IO / IP of a coordinate through multiple switch units or clock trees to another indicator's IO / LUT / IP and other resources. Among them, selecting the shortest path and the timing meeting certain conditions is called wiring, and placing the two ends of the wire net in a legal position is called layout. The entire process of EDA tools is roughly: logic synthesis, layout, wiring, and code stream generation. The algorithm of this application provides guidance for layout. The congestion level of the layout will affect the success rate of routing, and it does not directly target routing. Figure 1 As shown, the method includes the following steps 101-104.

[0046] Step 101, layout the logic units corresponding to the logic netlist synthesized by the user circuit design on the FPGA chip, and calculate the total number of multiplexers imux in each switch box on the FPGA chip.

[0047] Step 102, calculate the total number of multiplexers imux used by each line net net in each switch unit switch box according to the logic net list and its description file. In one embodiment, each line net (net) is connected to one or more lookup tables LUT in the configurable logic block CLB by one or more multiplexers. In one embodiment, each lookup table LUT has multiple pin interfaces (pins).

[0048] Step 103, calculating the total number of multiplexers imux used by all the nets net in each switch box.

[0049] Step 104, calculating the resource utilization of each switch box according to the total number of multiplexers imux in each switch box and the total number of multiplexers imux used by all nets net, so as to evaluate the pin accessment efficiency.

[0050] In one embodiment, the resource utilization rate of each switch unit is calculated using the following formula:

[0051]

[0052] The score (c,r) represents the resource utilization of the switch box in row c and column r, G (C,r) represents the total number of multiplexers imux in the switch box in row c and column r, sum (C,r) Represents the total number of multiplexers imux used by all nets in the switch box at row c and column r.

[0053] In one embodiment, according to Score (c,r) The value of the switch box pin access efficiency is divided into four levels in order. (c,r) When Score is greater than or equal to 0 and less than or equal to 25, the pin access efficiency is classified as the first level. (c,r) When the score is greater than 25 and less than or equal to 50, the pin access efficiency is classified as the second level. (c,r) When the score is greater than 50 and less than or equal to 75, the pin access efficiency is classified as the third level. (c,r) When the value is greater than 75 and less than or equal to 100, the pin access efficiency is classified as the fourth level. (c,r) The lower the value of indicates the lower the pin access efficiency. It should be understood that in other embodiments of the present application, the efficiency rating can also be divided into three levels, five levels, etc. The values ​​of the divided levels are only examples, and the present application is not limited to this. For example, the pin access efficiency is divided into five levels in order, where score (c,r) When the score is greater than or equal to 0 and less than or equal to 20, the pin access efficiency is classified as the first level. (c,r) When the score is greater than 20 and less than or equal to 40, the pin access efficiency is classified as the second level. (c,r) When the score is greater than 40 and less than or equal to 60, the pin access efficiency is classified as the third level. (c,r) When the score is greater than 60 and less than or equal to 80, the pin access efficiency is classified as the fourth level. (c,r) When it is greater than 80 and less than or equal to 100, the pin access efficiency is classified into the fifth level.

[0054] In one embodiment, the method further includes the following steps: step 201, calculating the average value of resource utilization of all switch units; step 202, when the resource utilization of a switch unit is less than the average value, adjusting the layout of the switch unit; step 203, recalculating the resource utilization of the switch unit until the resource utilization of the switch unit is greater than the average value.

[0055] In one embodiment, the method further includes the following steps: Step 301, when the resource utilization of the switch unit is less than the first preset value, adjusting the layout of the switch unit; Step 302, recalculating the resource utilization of each switch unit until the resource utilization of each switch unit is greater than or equal to the first preset value. It should be understood that the first preset value can be a preset value determined according to the layout algorithm, for example, it can be a range value of 25 for the first level or a range value of 50 for the second level, and after adjustment, the score of the unit can be increased by one level. Of course, the preset value in this embodiment can also be other preset values, which can be set based on experience.

[0056] In the present application, the layout optimization strategy depends on the layout algorithm, which can optimize low-scoring cells to the average level of the global score, or improve the score of low-scoring cells by one level, or improve the score of cells with scores below a preset value to above a preset value, where the preset value can be set based on experience. Of course, other optimization methods can also be used in the present application.

[0057] It should be noted that during the layout optimization process, when the score of a unit still does not meet the conditions after optimization, it does not mean that it cannot be iterated infinitely, but the optimization stops after reaching the preset number of iterations.

[0058] In one embodiment, the method further includes: performing routing according to the adjusted layout, and generating an FPGA code stream according to the results of the layout and routing.

[0059] In order to better understand the technical solution of the present application, a specific example is provided below for illustration. The details listed in the example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

[0060] Figure 2It is a schematic diagram of some hardware resources of a local unit of the chip. A multiplexer imux can go to 5 ports, and a lookup table LUT has 5 ports a, b, c, d, and e (the number of ports here is assumed). For example, multiplexer imux0 can go to a and d of lookup table LUT0, d of lookup table LUT1, and b and c of lookup table LUT2, while multiplexer imux1 can go to a and b of lookup table LUT0, b and c of lookup table LUT1, and e of lookup table LUT3. How many ports can go to where depends on the hardware design. When the hardware design is done, these are all known constants.

[0061] After the user circuit design is synthesized into a logic netlist, the layout needs to put each unit on the hardware. For example, a line net (net) will go from a source point (driver) to 4 sinks (sinks). Let's ignore the source point driver for now. Assuming that these 4 sinks are to be placed on the 4 ports a, b, c, and d of the lookup table LUT, the layout can put these 4 sinks on the lookup table LUT0 and LUT1 respectively. At this time, if the signal wants to reach a, b, c, and d, it will use the two resources of multiplexer imux0 and multiplexer imux1. However, if it is placed in the lookup table LUT0 and LUT2, only one multiplexer imux0 can be used to achieve the purpose, so the resource utilization rate is improved, because the multiplexer imux cannot be shared by two line nets, so it is necessary to use the least multiplexer imux as much as possible to complete the most line nets. Therefore, the number of multiplexers imux used can reflect the pin accessment efficiency of the FPGA chip, and give real-time feedback to the layout so that it can adjust the placement to achieve the maximum resource utilization effect.

[0062] When the layout is completed, the corresponding units of the entire logic netlist have been placed on the chip, such as the source driver and sink mentioned in the first step. The total number of multiplexer imux resources at each location on the chip is fixed. It is known that different companies have different design methods for where the multiplexer imux resources can go. In short, there will be a set of corresponding description files to describe the wiring resources. From this file plus the layout placement information, the number of multiplexer imux used by each line network at each location can be calculated. According to a certain formula, the "score" under the coordinate can be obtained, and the local resource usage can be quantified.

[0063] The scoring process is as follows: Figure 3 As shown, c and r are the row and column numbers of the unit respectively, G (c,r) Indicates the total number of imux resources in row c and column r, Nnm (c·r) Indicates the number of multiplexer imux resources required for a line network at this coordinate, sum(c,r) It indicates the sum of the number of imux resources required by all the lines under this coordinate. It should be noted that the entire FPGA chip is in the form of a matrix array, and each row and column has a switch unit switch box and a logic block CLB, which constitute the basic unit. The switch box is a switch box that can realize line jump. For simplicity, the switch unit in the entire FPGA chip is described as c rows and r columns.

[0064] The resource utilization of imux at this coordinate is:

[0065]

[0066] score is a value ranging from 0 to 100. A higher value indicates higher resource utilization, higher pin accessment efficiency, and less imux usage.

[0067] The scores can be divided into four levels: 0-25, 25-50, 50-75, and 75-100 to guide the layout.

[0068] The evaluation method proposed in the present invention can effectively quantify the local resource usage and the pin accessment efficiency. It is an effective feedback mechanism, can guide the layout process in real time, adjust the layout to maximize the resource utilization, thereby optimizing the wiring, reducing congestion, and accelerating the wiring convergence speed. It has the characteristics of being more lightweight, flexible, and efficient.

[0069] The second embodiment of the present application relates to a system for evaluating pin access efficiency, which includes a calculation unit. The calculation unit is configured to: layout the unit corresponding to the logic netlist synthesized by the user circuit design on the chip, calculate the total number of multiplexers in each switch unit on the chip; calculate the total number of multiplexers used by each line network in each switch unit according to the logic netlist and its description file; calculate the total number of multiplexers used by all lines in each switch unit; calculate the resource utilization of each switch unit according to the total number of multiplexers in each switch unit and the total number of multiplexers used by all lines, so as to evaluate the pin access efficiency.

[0070] The first implementation manner is a method implementation manner corresponding to the present implementation manner. The technical details in the first implementation manner can be applied to the present implementation manner, and the technical details in the present implementation manner can also be applied to the first implementation manner.

[0071] Accordingly, the embodiments of the present application also provide a computer-readable storage medium, in which computer executable instructions are stored, and when the computer executable instructions are executed by the processor, the various method embodiments of the present application are implemented. Computer-readable storage media include permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be a computer-readable instruction, a data structure, a module of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. According to the definition herein, computer-readable storage media do not include transient computer-readable media (transitory media), such as modulated data signals and carriers.

[0072] In addition, the embodiments of the present application also provide a system for evaluating pin access efficiency, which includes a memory for storing computer executable instructions, and a processor; the processor is used to implement the steps in the above-mentioned method implementations when executing the computer executable instructions in the memory. Among them, the processor can be a central processing unit (Central Processing Unit, referred to as "CPU"), a graphic processor (Graphic Processing Unit, referred to as "GPU"), a digital signal processor (Digital Signal Processor, referred to as "DSP"), a microcontroller unit (Microcontroller Unit, referred to as "MCU"), a neural network processor (referred to as "NPU"), an application specific integrated circuit (Application Specific Integrated Circuit, referred to as "ASIC"), a field programmable gate array (Field Programmable Gate Array, referred to as "FPGA") or other programmable logic devices, etc. The aforementioned memory can be a read-only memory (read-only memory, referred to as "ROM"), a random access memory (random access memory, referred to as "RAM"), a flash memory (Flash), a hard disk or a solid state drive, etc. The steps of the method disclosed in each embodiment of the present invention can be directly embodied as a hardware processor to be executed, or a combination of hardware and software modules in the processor to be executed.

[0073] In addition, an embodiment of the present application further provides a computer program product, which includes computer executable instructions, and when the computer executable instructions are executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0074] It should be noted that, in the present application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "include one" do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. In the present application, if it is mentioned that a certain action is performed according to a certain element, it means at least the meaning of performing the action according to the element, which includes two situations: performing the action only according to the element and performing the action according to the element and other elements. Multiple, multiple, multiple, etc. expressions include 2, 2 times, 2 kinds and more than 2, more than 2 times, more than 2 kinds.

[0075] The serial numbers used in describing the steps of the method do not themselves constitute any limitation on the order of these steps. For example, the step with a larger serial number does not necessarily have to be executed after the step with a smaller serial number. The step with a larger serial number may be executed first and then the step with a smaller serial number. They may also be executed in parallel, as long as this execution order is reasonable for those skilled in the art. For another example, multiple steps with consecutive serial numbers (e.g., step 101, step 102, step 103, etc.) do not limit other steps that can be executed in between. For example, there may be other steps between step 101 and step 102.

[0076] This specification includes combinations of the various embodiments described herein. Individual references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments"); however, these embodiments are not mutually exclusive unless indicated as mutually exclusive or clear to one skilled in the art. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.

[0077] All documents mentioned in this specification are considered to be included in the disclosure of this application as a whole, so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.

[0078] In some cases, the actions or steps described in the claims may be performed in a different order than in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A method for evaluating pin access efficiency, characterized in that: include: Place the units corresponding to the logic netlist synthesized from the user circuit design on the chip, and calculate the total number of multiplexers in each switch unit on the chip; Calculate the total number of multiplexers used by each line net in each switch unit according to the logic netlist and its description file; Calculate the total number of multiplexers used by all nets in each switch unit; as well as The resource utilization of each switch unit is calculated according to the total number of multiplexers in each switch unit and the total number of multiplexers used by all line nets to evaluate the pin access efficiency.

2. The method according to claim 1, characterized in that The resource utilization rate of each switch unit is calculated using the following formula: The score (c,r) represents the resource utilization rate of the switch unit in the cth row and the rth column, G (C,r) represents the total number of multiplexers in the switch unit in row c and column r, sum (C,r) Represents the total number of multiplexers used by all the nets in the switch unit in the cth row and the rth column.

3. The method according to claim 2, characterized in that According to score (c,r) The value of the switch unit pin access efficiency is divided into four levels in order. (c,r) When the score is greater than or equal to 0 and less than or equal to 25, the pin access efficiency is classified as the first level. (c,r) When the score is greater than 25 and less than or equal to 50, the pin access efficiency is classified as the second level. (c,r) When the score is greater than 50 and less than or equal to 75, the pin access efficiency is classified as the third level. (c,r) When it is greater than 75 and less than or equal to 100, the pin access efficiency is classified into the fourth level, and the lower the value of the resource utilization rate is, the lower the pin access efficiency is.

4. The method according to claim 1, characterized in that: Also includes: Calculate the average value of resource utilization of all switch units; When the resource utilization rate of the switch unit is less than the average value, adjusting the layout of the switch unit; as well as The resource utilization of the switch unit is recalculated until the resource utilization of the switch unit is greater than the average value.

5. The method according to claim 1, characterized in that Also includes: When the resource utilization rate of the switch unit is less than a first preset value, adjusting the layout of the switch unit; as well as The resource utilization rate of each switch unit is recalculated until the resource utilization rate of each switch unit is greater than or equal to a first preset value.

6. The method according to claim 4 or 5, characterized in that: Also includes: Routing is performed according to the adjusted layout, and an FPGA code stream is generated according to the results of the layout and the routing.

7. The method according to claim 1, characterized in that Each net is connected to one or more lookup tables in a configurable logic block by one or more multiplexers.

8. The method according to claim 7, characterized in that Each lookup table has a plurality of pin interfaces.

9. A system for evaluating pin access efficiency, characterized in that: include: A memory for storing computer executable instructions; as well as, A processor, coupled to the memory, configured to implement the steps of the method according to any one of claims 1 to 8 when executing the computer executable instructions.

10. A non-transitory computer-readable storage medium, characterized in that: The non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the steps in the method according to any one of claims 1 to 8 are implemented.

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