Simulation verification method of to-be-tested design, electronic equipment and storage medium

Abstract

The invention discloses a simulation verification method for a to-be-tested design, electronic equipment and a storage medium, and belongs to the field of computers. The method comprises the following steps: acquiring a first clock signal for a first to-be-tested design and a second clock signal for a second to-be-tested design, wherein at least one of the first clock signal and the second clock signal is a clock signal with frequency offset; inputting the first clock signal to the first to-be-tested design, and inputting the second clock signal to the second to-be-tested design; performing simulation verification on the first to-be-tested design and the second to-be-tested design; wherein the first to-be-tested design is in communication connection with the second to-be-tested design.

Description

Technical Field

[0001] The present application belongs to the field of computers, and specifically relates to a simulation verification method for a design to be tested, an electronic device, and a storage medium. Background Art

[0002] Before a chip is officially taped out, it is necessary to ensure that the chip functions normally. In order to ensure that the chip functions normally, it is usually necessary to perform simulation verification on the chip. In this process, it is necessary to apply a clock to the chip first, and then wait for the chip to complete initialization before performing subsequent verification.

[0003] However, the clock applied to the design under test in related technologies is usually a standard square wave. This clock signal cannot completely simulate the actual working environment of the design under test, and the simulation verification of the design under test is not complete enough, resulting in a high risk of tape-out of the design under test. Summary of the invention

[0004] The embodiments of the present application provide a simulation verification method for a design to be tested, an electronic device, and a storage medium, which can solve the problem of high tape-out risk of the design to be tested existing in the related art.

[0005] In a first aspect, an embodiment of the present application provides a simulation verification method for a design to be tested, the method comprising: Acquire a first clock signal for a first design to be tested and a second clock signal for a second design to be tested, wherein at least one of the first clock signal and the second clock signal is a clock signal with a frequency deviation; Inputting the first clock signal to the first design under test, and inputting the second clock signal to the second design under test; Performing simulation verification on the first design to be tested and the second design to be tested; The first design to be tested is communicatively connected with the second design to be tested.

[0006] In a second aspect, an embodiment of the present application provides a simulation verification device, including: a frequency deviation generator and a simulation verification module; The frequency deviation generator is used to obtain a first clock signal for a first design to be tested and a second clock signal for a second design to be tested, wherein at least one of the first clock signal and the second clock signal is a clock signal with a frequency deviation; input the first clock signal to the first design to be tested, and input the second clock signal to the second design to be tested; The simulation verification module is used to perform simulation verification on the first design to be tested and the second design to be tested; The first design to be tested is communicatively connected with the second design to be tested.

[0007] In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the program or instructions are executed by the processor, the steps of the method described in the first aspect are implemented.

[0008] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed, the steps of the method described in the first aspect are implemented.

[0009] In a fifth aspect, an embodiment of the present application provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the steps of the method described in the first aspect.

[0010] At least one of the above technical solutions provided in the embodiments of the present application can achieve the following technical effects: In an embodiment of the present application, a first clock signal for a first design to be tested and a second clock signal for a second design to be tested are obtained, and at least one of the first clock signal and the second clock signal is a clock signal with frequency deviation; the first clock signal is input to the first design to be tested, and the second clock signal is input to the second design to be tested; the first design to be tested and the second design to be tested are simulated and verified; wherein the first design to be tested and the second design to be tested are connected in communication. In this way, at least one of the first clock signal input to the first design to be tested and the second clock signal input to the second design to be tested is a clock signal with frequency deviation, and on this basis, the first design to be tested and the second design to be tested are simulated and verified, which can better simulate the real working scenario of communication between the two designs to be tested, that is, in the first design to be tested and the second design to be tested that communicate with each other, there is at least one scenario in which the working clock of the design to be tested has frequency deviation, which improves the completeness of the simulation verification of the design to be tested, reduces the risk of subsequent tape-out of the design to be tested, and solves the problem of high tape-out risk of the design to be tested existing in the related technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 It is a flow chart of a simulation verification method of a design to be tested provided by an embodiment of the present application; Figure 2is a flow chart of another simulation verification method for a design to be tested provided by an embodiment of the present application; Figure 3 It is a schematic diagram of the overall concept of a simulation verification method for a design to be tested provided in an embodiment of the present application; Figure 4 is a schematic diagram of a frequency deviation generator generating a frequency deviation provided in an embodiment of the present application; Figure 5 is a schematic diagram of a specific example of generating a non-fixed frequency deviation provided by an embodiment of the present application; Figure 6 It is a structural block diagram of a simulation verification device provided in an embodiment of the present application; Figure 7 It is a structural block diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0014] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0015] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0016] In the embodiment of the present application, the first design to be tested and the second design to be tested may be digital circuits to be tested in the simulation verification phase, for example, the first design to be tested and the second design to be tested may be chips. Meanwhile, the first design to be tested and the second design to be tested are in communication connection with each other.

[0017] Because in the actual working environment of the chip, the working clock of the chip may fluctuate, that is, the working clock may be too fast or too slow. In addition, in the process of communication and interaction between two chips, the working clock of one chip may be too fast and the working clock of the other chip may be too slow, or the working clock of one chip may be too slow and the working clock of the other chip may be too fast. Although the method of applying a standard square wave clock signal to the design to be tested used in the related art can confirm most of the functions of the digital circuit, this method cannot simulate the actual working environment of the chip, and the simulation verification completeness of the design to be tested is not high, which may bring risks to the tape-out later and reduce the success rate of the tape-out.

[0018] The simulation verification method of the design to be tested provided in the embodiment of the present application is applied to the simulation verification situation before the design to be tested is taped out, and in particular, can be applied to the simulation verification of two designs to be tested that are in communication connection. Specifically, at least one of the first clock signal input to the first design to be tested and the second clock signal input to the second design to be tested is a clock signal with frequency deviation, which can simulate the scenario in which at least one of the two designs to be tested that are in communication connection has a clock signal with frequency deviation, thereby improving the completeness of the simulation verification.

[0019] The simulation verification method of the design to be tested provided in the embodiment of the present application can be executed by a target device, wherein a Universal Verification Methodology (UVM) verification platform is deployed on the target device, the UVM verification platform can be implemented by the system Verilog language, and a frequency deviation generator and a comparison circuit can be provided on the UVM verification platform.

[0020] The simulation verification method for the design to be tested provided by the embodiment of the present application is described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.

[0021] See also Figure 1 , Figure 1 1 is a flow chart of a simulation verification method for a design to be tested provided in an embodiment of the present application. Figure 1 As shown, the method comprises the following steps: Step 110: Obtain a first clock signal for a first design under test and a second clock signal for a second design under test, wherein at least one of the first clock signal and the second clock signal is a clock signal with a frequency deviation.

[0022] In order to simulate the real working environment of the chip, a first clock signal applied to the first design to be tested and a second clock signal applied to the second design to be tested can be obtained, and at least one of the first clock signal and the second clock signal has a frequency deviation. In other words, it is possible to simulate a scenario in which the clock signal of the first design to be tested has a frequency deviation and the second clock signal of the second design to be tested does not have a frequency deviation; it is possible to simulate a scenario in which the first clock signal of the first design to be tested does not have a frequency deviation and the second clock signal of the second design to be tested has a frequency deviation; it is also possible to simulate a scenario in which the first clock signal of the first design to be tested has a frequency deviation and the second design to be tested of the second design to be tested has a frequency deviation. In this way, it is possible to simulate the real working environment of two chips connected in communication.

[0023] In one embodiment of the present application, the first design under test may include a first communication chip, and the second design under test may include a second communication chip.

[0024] In the embodiment of the present application, the first communication chip and the second communication chip may be the same communication chip, or the first communication chip and the second communication chip may be different communication chips. The first communication chip and the second communication chip may communicate via a network cable model, as described below. Figure 3 In the figure, the network cable model between the design under test A and the design under test B is connected through the RJ45 interface.

[0025] Step 120: Input the first clock signal to the first design under test, and input the second clock signal to the second design under test.

[0026] In an embodiment of the present application, after obtaining the first clock signal and the second clock signal, the first clock signal can be input to the first design to be tested, and the second clock signal can be input to the second design to be tested, and the first design to be tested and the second design to be tested can be waited for to complete their own power-on and initialization processes, and then a subsequent simulation verification process can be performed.

[0027] Step 130: Perform simulation verification on the first design under test and the second design under test; wherein the first design under test and the second design under test are in communication connection with each other.

[0028] In the embodiment of the present application, after the first clock signal and the second clock signal are applied to the first design to be tested and the second design to be tested respectively, a real working scenario in which the first design to be tested and the second design to be tested perform communication interaction can be simulated. In this way, by simulating and verifying the first design to be tested and the second design to be tested, it can be verified whether the functions of the digital circuits inside the first design to be tested and the second design to be tested are normal, and whether there are other unknown digital circuit risks.

[0029] In one embodiment of the present application, the simulation verification of the first design to be tested and the second design to be tested includes: inputting test data into the first design to be tested; obtaining target data output by the second design to be tested; and obtaining simulation verification results based on the test data and the target data.

[0030] In the embodiment of the present application, test data may be input into the first design to be tested, the test data may be a test data packet, and the first design to be tested may output an output result. Since the first design to be tested is connected to the second design to be tested by communication, the first design to be tested may input the output result into the second design to be tested, and obtain the target data output by the second design to be tested.

[0031] When the functions of the first design to be tested and the second design to be tested are normal and there are no other digital circuit problems, the target data output by the second design to be tested is the same as the test data input to the first design to be tested. Therefore, the test data and the target data can be compared by the comparison circuit on the UVM verification platform to determine whether the test data and the target data are the same, so as to obtain the simulation verification result. Specifically, when the test data and the target data are the same, it can be determined that the simulation verification of the first design to be tested and the second design to be tested has passed; when the test data and the target data are different, it can be determined that there is a problem with the digital circuit of at least one of the first design to be tested and the second design to be tested, that is, the simulation verification has failed.

[0032] In an embodiment of the present application, at least one of the first clock signal input to the first design to be tested and the second clock signal input to the second design to be tested is a clock signal with a frequency deviation. On this basis, the first design to be tested and the second design to be tested are simulated and verified, which can better simulate the actual working scenario of communication between the two designs to be tested, that is, in the first design to be tested and the second design to be tested that communicate with each other, there is at least one scenario in which the working clock of one design to be tested has a frequency deviation, which improves the completeness of the simulation verification of the design to be tested, reduces the risk of subsequent tape-out of the design to be tested, and solves the problem of high tape-out risk of the design to be tested in the related technology.

[0033] See also Figure 2 , Figure 2 1 is a flow chart of another simulation verification method for a design to be tested provided by an embodiment of the present application. Figure 2 As shown, the method comprises the following steps: Step 210: The first frequency offset generator generates the first clock signal based on the first frequency offset parameter of the first design under test and the first clock source information of the first design under test, so as to replace the original clock signal of the first design under test.

[0034] In an embodiment of the present application, the first clock source information and the first frequency deviation parameter of the first design to be tested can be obtained. The first design to be tested may include one or more clock sources inside, and the clock source may be a component for actively providing a clock signal. The first clock source information is used to describe the relevant information of the clock source in the first design to be tested. The first frequency deviation parameter is a parameter related to applying a frequency deviation to the first design to be tested, such as an applied frequency deviation value, indication information of a method for applying the frequency deviation value, etc. The first frequency deviation generator may apply a frequency deviation to the clock signal of the clock source in the first design to be tested based on the first frequency deviation parameter to obtain a first clock signal, and the number of the first clock signals may be determined based on the number of clock sources of the first design to be tested. Among them, the first clock signal can be used to replace the original clock signal of the first design to be tested, and the original clock signal of the first design to be tested is the clock signal provided by the clock source on the first design to be tested.

[0035] Step 220: The second frequency offset generator generates the second clock signal based on the second frequency offset parameter of the second design under test and the second clock source information of the second design under test, so as to replace the original clock signal of the second design under test.

[0036] In an embodiment of the present application, the second clock source information and the second frequency deviation parameter of the second design to be tested can be obtained. The second design to be tested may include one or more clock sources inside, and the second clock source information is used to describe the relevant information of the clock source in the second design to be tested. The second frequency deviation parameter is used to indicate the application of frequency deviation to the second design to be tested, such as the applied frequency deviation value, the indication information of the method of applying the frequency deviation value, etc. The second frequency deviation generator can apply a frequency deviation to the clock signal of the clock source in the second design to be tested based on the second frequency deviation parameter to obtain a second clock signal, and the number of the second clock signals can be determined based on the number of clock sources of the second design to be tested. Among them, the second clock signal can be used to replace the original clock signal of the second design to be tested, and the original clock signal of the second design to be tested can be used to replace the original clock signal of the second design to be tested. It should be noted that the following description of the first design to be tested and the description of the second design to be tested can refer to each other.

[0037] In an embodiment of the present application, since the clock signal provided by the clock source is without frequency deviation, it is impossible to simulate the actual working scenario of two designs to be tested that are communicating (for example, the clock frequency of one design to be tested is relatively fast, and the clock frequency of the other design to be tested is relatively slow). Therefore, a first clock signal can be generated based on a first frequency deviation generator, and a second clock signal can be generated based on a second frequency deviation generator, and at least one of the first clock signal and the second clock signal is with frequency deviation. By replacing the original clock signal of the first design to be tested with the first clock signal, and replacing the original clock signal of the second design to be tested with the second clock signal, the actual working scenario of communication between the first design to be tested and the second design to be tested can be more comprehensively simulated, thereby improving the completeness of the simulation verification of the designs to be tested.

[0038] The number of clock sources in the first design to be tested may be one, and the first clock source information may include the basic frequency of the clock source. The first frequency deviation generator may obtain a first clock signal with frequency deviation based on the first frequency deviation parameter and the basic frequency of the clock source. Correspondingly, the number of clock sources in the second design to be tested may also be one, and the second clock source information may include the basic frequency of the clock source. The second frequency deviation generator may obtain a second clock signal with frequency deviation based on the second frequency deviation parameter and the basic frequency of the clock source.

[0039] In one embodiment of the present application, the first clock source information includes N clock frequencies of N clock sources, and the first frequency offset generator includes N frequency offset generators for the N clock sources; the first clock signal includes N clock signals, and each of the N clock signals is generated by one of the N frequency offset generators based on the first frequency offset parameter and one of the N clock frequencies; wherein N is an integer greater than 1. The second clock source information includes M clock frequencies of M clock sources, and the second frequency offset generator includes M frequency offset generators for the M clock sources; the second clock signal includes M clock signals, and each of the M clock signals is generated by one of the M frequency offset generators based on the second frequency offset parameter and one of the M clock frequencies; wherein M is an integer greater than 1.

[0040] In an embodiment of the present application, a first frequency deviation generator for a first design to be tested and a second frequency deviation generator for a second design to be tested are deployed on the UVM verification platform. The first clock source information includes N clock frequencies of N clock sources in the first design to be tested, and the N clock frequencies are the basic frequencies of the clock signals of the N clock sources. Based on the first clock source information of the first design to be tested, a first frequency deviation generator for generating the frequency deviation of the first design to be tested can be customized, and the first frequency deviation generator includes N frequency deviation generators for the N clock sources, that is, the number of clock sources of the first design to be tested is the same as the number of frequency deviation generators included in the first frequency deviation generator. Moreover, there is a one-to-one correspondence between the N clock sources and the N frequency deviation generators. That is, the clock signal corresponding to the i-th clock source among the N clock sources is obtained by the i-th frequency deviation generator among the N frequency deviation generators, and the i-th frequency deviation generator among the N frequency deviation generators is used to generate the clock signal corresponding to the i-th clock source among the N clock sources, i is a positive integer less than or equal to N, that is, the N frequency deviation generators are used to generate N clock signals.

[0041] Correspondingly, the second clock source information includes M clock frequencies of M clock sources in the second design to be tested, and the M clock frequencies are the basic frequencies of the clock signals of the M clock sources. There is no restriction on the quantitative relationship between M and N here, M may be greater than N, or M may be less than or equal to N, and M and N are determined based on the number of clock sources in the first design to be tested and the second design to be tested. Based on the second clock source information of the second design to be tested, a second frequency deviation generator for generating the frequency deviation of the second design to be tested can be customized, and the second frequency deviation generator includes M frequency deviation generators, that is, the number of clock sources of the second design to be tested is the same as the number of frequency deviation generators included in the second frequency deviation generator. Moreover, there is a one-to-one correspondence between the M clock sources and the M frequency deviation generators. The M frequency deviation generators are used to generate M clock signals. Specifically, the j-th clock signal among the M clock signals is obtained based on the j-th frequency deviation generator among the M frequency deviation generators, and j is a positive integer less than or equal to M.

[0042] In addition, for the first design to be tested, the N clock signals correspond to the N clock frequencies one by one, and the clock signal obtained based on the clock frequency of the i-th clock source can replace the original clock signal of the i-th clock source, and the clock frequency of the i-th clock source is the base frequency of the i-th clock source. For example, the clock signal A (X1) obtained based on the base frequency of the clock source A1 corresponds to the clock source A1, and the clock signal A (X1) can be used to replace the original clock signal of the clock source A1. The clock signal A (X2) obtained based on the base frequency of the clock source A2 corresponds to the clock source A2, and the clock signal A (X2) can be used to replace the original clock signal of the clock source A2.

[0043] Correspondingly, for the second design to be tested, the M clock signals correspond to the M clock frequencies one by one, and the clock signal obtained based on the clock frequency of the jth clock source can replace the original clock signal of the jth clock source, and the clock frequency of the jth clock source is the base frequency of the jth clock source. For example, the clock signal B (X1) obtained based on the base frequency of the clock source B1 corresponds to the clock source B1, and the clock signal B (X1) can be used to replace the original clock signal of the clock source B1. The clock signal B (X2) obtained based on the base frequency of the clock source B2 corresponds to the clock source B2, and the clock signal B (X2) can be used to replace the original clock signal of the clock source B2.

[0044] In the embodiments of this application, please refer to Figure 3 , Figure 3 Schematic diagram of the overall concept of a simulation verification method for a design to be tested provided in an embodiment of the present application. Figure 3 As shown, two sets of frequency deviation generators can be introduced on the UVM verification platform (i.e. Figure 3 The frequency offset generator A and the frequency offset generator B in the figure can be applied to the design under test A and the design under test B respectively. The application point can be, for example, Figure 3 The external crystal oscillator (xtal) clock source shown in Figure 3 The first design to be tested may be, for example, a pin (e.g., a PAD pin) of xtal A and xtal B in the circuit, or other clock sources existing inside the design to be tested during simulation verification. Figure 3 The design under test A (this end) in the embodiment, the second design under test can be, for example, Figure 3 The design under test B (remote end) in the test object A and the design under test B can be connected through a network cable model (for example Figure 3 The frequency deviation generator A can generate N clock signals (A1~A N), which is used to replace the clock signals of N clock frequencies generated by the N clock sources of the first design to be tested. Correspondingly, the frequency deviation generator B is used to generate M clock signals (B1~B M ), used to replace the M clock signals of M clock frequencies generated by the M signal sources.

[0045] In one embodiment of the present application, the first frequency offset parameter includes a first frequency offset value and a first frequency offset indication information, the first frequency offset indication information is used to indicate a method for generating a frequency offset, and the first frequency offset indication information includes one of a fixed frequency offset and a non-fixed frequency offset. The second frequency offset parameter includes a second frequency offset value and a second frequency offset indication information, the second frequency offset indication information is used to indicate a method for generating a frequency offset, and the second frequency offset indication information includes one of a fixed frequency offset and a non-fixed frequency offset.

[0046] In the embodiment of the present application, for an actual chip, in most cases there is only one external crystal oscillator as a clock source. The phase-locked loop (PLL) inside the chip can generate more clock signals based on this clock source. For the entire chip, the frequency deviation of the generated clock signal is uniform.

[0047] For the design to be tested in the simulation verification stage, since the design to be tested is an analog digital circuit, the analog circuit PLL cannot be implemented on the digital circuit. In the embodiment of the present application, a simulation model is used to generate a plurality of clock signals, and the plurality of clock signals can share the same frequency offset value. In other words, the N clock signals can share the first frequency offset value, and the M clock signals can share the second frequency offset value.

[0048] In addition, when the chip is working normally, the working clock of the chip may cycle fast and slow, that is, fast and slow. In order to simulate the working environment of the working clock of the chip, in addition to providing a method for generating a fixed frequency deviation, a method for generating a non-fixed frequency deviation is also provided. The actual method for generating the frequency deviation can be determined based on the frequency deviation parameter. Specifically, the method for generating the frequency deviation by the first frequency deviation generator can be obtained based on the first frequency deviation indication information, and the method for generating the frequency deviation by the second frequency deviation generator can be obtained based on the second frequency deviation indication information.

[0049] Among them, the frequency deviation value of the clock signal obtained based on the fixed frequency deviation is fixed, that is, the clock signal may be fixedly fast or fixedly slow, and the frequency of the clock signal of the same clock source is fixed. The frequency deviation value of the clock signal obtained based on the non-fixed frequency deviation is not fixed, that is, the clock signal may be fast at one moment and slow at another moment. The frequency of the clock signal of the same clock source can be determined by the modulation method and can vary within the maximum frequency deviation range.

[0050] Please refer to Figure 4 , Figure 4 It is a schematic diagram of a frequency offset generator generating a frequency offset provided in an embodiment of the present application. In one embodiment of the present application, since the first frequency offset parameter and the second frequency offset parameter can be used to indicate the generation of two forms of frequency offset, namely, a fixed frequency offset and a non-fixed frequency offset, the first frequency offset generator may include two types of frequency offset generators (fixed frequency offset generator and non-fixed frequency offset generator), that is, the first frequency offset generator may include N fixed frequency offset generators and N non-fixed frequency offset generators. For the first design to be tested, only one type of frequency offset generator may be enabled for each simulation verification. The N frequency offset generators included in the first frequency offset generator may be the N fixed frequency offset generators, or the N non-fixed frequency offset generators. Correspondingly, the second frequency offset generator may also include M fixed frequency offset generators and M non-fixed frequency offset generators. The M frequency offset generators included in the second frequency offset generator may be the M fixed frequency offset generators, or the M non-fixed frequency offset generators.

[0051] The first frequency offset parameter and the second frequency offset parameter can be set according to simulation requirements. Figure 4 As shown, taking the first design to be tested as an example, when the first frequency deviation indication information indicates that a fixed frequency deviation is generated, the number of clock sources (i.e., N clock sources) can be determined according to the settings of the first design to be tested, and the basic frequencies of the N clock sources can be obtained. Then, based on the first frequency deviation parameter and the basic frequencies of the N clock sources, N clock signals with fixed frequency deviations (i.e., X1 to X2) can be obtained. N ), N clock signals share the first frequency offset value. In the case where the first frequency offset indication information indicates the generation of a non-fixed frequency offset, the first frequency offset value can be used as the maximum frequency offset value of the N clock signals, and the N clock signals share this maximum frequency offset value.

[0052] In the embodiment of the present application, two methods of generating frequency offset are provided: fixed frequency offset and non-fixed frequency offset. Specifically, the following will describe the specific process of generating fixed frequency offset and generating non-fixed frequency offset.

[0053] Exemplarily, in one embodiment of the present application, when the first frequency deviation indication information includes a fixed frequency deviation, the first frequency deviation generator includes a fixed frequency deviation generator, and the frequency deviation value of the first clock signal is the first frequency deviation value. The frequency deviation values ​​of the N clock signals included in the first clock signal are all the first frequency deviation values. In other words, the clock frequencies of the N clock signals finally obtained are fixed. When the second frequency deviation indication information includes a fixed frequency deviation, the second frequency deviation generator includes a fixed frequency deviation generator, and the frequency deviation value of the second clock signal is the second frequency deviation value. The frequency deviation values ​​of the M clock signals included in the second clock signal are all the second frequency deviation value. In other words, the clock frequencies of the M clock signals finally obtained are fixed.

[0054] Taking the first design to be tested as an example, there are three clock sources in the simulation verification model of the first design to be tested, namely clock source A1, clock source A2 and clock source A3, the basic frequency of clock source A1 is 1000MHz, the basic frequency of clock source A2 is 125MHz, the basic frequency of clock source A3 is 25MHz, the first frequency deviation indication information includes a fixed frequency deviation, and the first frequency deviation value is -100 parts per million (PPM). It can be obtained that the frequency of the clock signal corresponding to clock source A1 is 1000MHz*(1-100PPM)=999.9MHz, the frequency of the clock signal corresponding to clock source A2 is 125MHz*(1-100PPM)=124.9875MHz, and the frequency of the clock signal corresponding to clock source A3 is 25MHz*(1-100PPM)=24.9975MHz.

[0055] In the UVM verification platform of the current communication chip, the frequency deviation values ​​with higher frequency use are 0PPM, ±100PPM and ±200PPM, but the selection of the first frequency deviation value and the second frequency deviation value is not limited to the above-mentioned frequency deviation values, and other frequency deviation values ​​can be selected, which is not limited here.

[0056] Exemplarily, in one embodiment of the present application, the first frequency deviation parameter also includes a first frequency deviation modulation mode and a first modulation period; when the first frequency deviation indication information includes a non-fixed frequency deviation, the first frequency deviation generator includes a non-fixed frequency deviation generator, and the first clock signal is obtained based on the first frequency deviation modulation mode, the first modulation period, the first frequency deviation value and the first clock source information; wherein the frequency deviation value of the first clock signal is less than or equal to the first frequency deviation value; the second frequency deviation parameter also includes a second frequency deviation modulation mode and a second modulation period; when the second frequency deviation indication information includes a non-fixed frequency deviation, the second frequency deviation generator includes a non-fixed frequency deviation generator, and the second clock signal is obtained based on the second frequency deviation modulation mode, the second modulation period, the second frequency deviation value and the second clock source information; wherein the frequency deviation value of the second clock signal is less than or equal to the second frequency deviation value.

[0057] In an embodiment of the present application, since the first frequency deviation parameter can also be used to generate a non-fixed frequency deviation, the first frequency deviation parameter can also include a first frequency deviation modulation method and a first modulation period used to generate a non-fixed frequency deviation. Among them, the first frequency deviation modulation method is used to indicate the waveform of the generated clock signal, and the first frequency deviation modulation method may include at least one modulation method of triangle wave modulation, sine wave modulation, and cosine wave modulation, which can be set according to simulation requirements. The first modulation period can be set according to simulation requirements, for example, the first modulation period can be 32 microseconds (us).

[0058] The first frequency offset generator may include N non-fixed frequency offset generators, and the first frequency offset generator may determine N clock signals of N clock sources, i.e., the first clock signal, based on the N clock frequencies of the N clock sources, the first frequency offset modulation mode, the first modulation period, and the first frequency offset value. The frequency offset values ​​of the N clock signals obtained in this way may be different, and the frequency offset values ​​of the N clock signals are not greater than the first frequency offset value. The first frequency offset value may be used as the maximum frequency offset value of the N clock signals, and the N clock sources share this maximum frequency offset value.

[0059] Taking the first clock signal as an example, among the N clock sources, there is a clock source (clock source A) with a base frequency of 125MHz, the first frequency deviation indication information includes a non-fixed frequency deviation, and the first frequency deviation value is 100PPM. Then the maximum fluctuation amplitude of the frequency of the clock signal of clock source A is 125MHz×100PPM=0.0125MHz, the first frequency deviation modulation mode is a triangle wave modulation mode, and the first modulation period is 32 microseconds (us). Please refer to Figure 5 , Figure 5 is a schematic diagram of a specific example of generating a non-fixed frequency offset provided by an embodiment of the present application. According to the setting of the first frequency offset parameter, the following can be obtained: Figure 5 The frequency of the clock signal shown, that is, the clock signal corresponding to the clock source A, can fluctuate between 125MHz±0.0125MHz (i.e., 124.9875MHz~125.0125MHz). Figure 5 As shown, the frequency of the clock signal obtained by generating a non-fixed frequency offset may be higher than the base frequency of the clock source, or may be lower than the base frequency of the clock source, and is not a fixed frequency.

[0060] It should be understood that for the same design to be tested, fixed frequency offset and non-fixed frequency offset will not be generated at the same time. Therefore, fixed frequency offset and non-fixed frequency offset can share the same frequency offset value. Specifically, for the first design to be tested, when the first frequency offset indication information includes a fixed frequency offset, the first clock signal can be determined based on the first frequency offset value. When the first frequency offset indication information includes a non-fixed frequency offset, the first frequency offset parameter may include the first frequency offset indication information, the first frequency offset value, the first frequency offset modulation mode and the first modulation period. The first clock signal can be determined based on the first frequency offset value, the first frequency offset modulation mode and the first modulation period.

[0061] Step 230: Input the first clock signal to the first design under test, and input the second clock signal to the second design under test.

[0062] In the embodiment of the present application, since the first frequency offset parameter and the second frequency offset parameter can be flexibly selected, that is, the first frequency offset parameter and the second frequency offset parameter can be selected separately to control the clock signal to be fast, the clock signal to be slow, or the clock signal to be fast or slow, and the first frequency offset value and the second frequency offset value selected from the first frequency offset parameter and the second frequency offset parameter can be selected separately, in the entire simulation verification process, there are multiple combinations of the first frequency offset parameter and the second frequency offset parameter. In this way, the situation of the two designs to be tested in the communication process can be simulated more comprehensively, the completeness of the simulation verification can be improved, and the risk of tape-out can be reduced.

[0063] Step 240: Perform simulation verification on the first design under test and the second design under test; wherein the first design under test and the second design under test are in communication connection with each other.

[0064] In an embodiment of the present application, in the process of adding a frequency deviation to the clock signal of the clock source for simulation verification, a fixed frequency deviation can make the clock signal faster or slower, so that the digital circuit module inside the design to be tested can be verified. Specifically, it can be checked whether the flexible first-input first-out (FIFO) of the digital circuit module has overflow or underflow, and it can also be checked whether the clock recovery circuit (CDR circuit) can withstand the impact of the frequency deviation and other unknown digital circuit risks. As an additional frequency deviation test, the non-fixed frequency deviation can more comprehensively simulate the real scene of the communication chip working, and can better verify the digital circuit module inside the design to be tested.

[0065] In one embodiment of the present application, the simulation verification of the first design to be tested and the second design to be tested includes: inputting test data into the first design to be tested; obtaining target data output by the second design to be tested; and obtaining a simulation verification result based on the test data and the target data. The first design to be tested includes a first communication chip, and the second design to be tested includes a second communication chip.

[0066] In the embodiment of the present application, by setting the first frequency offset parameter and the second frequency offset parameter, various situations that may occur during the communication process between the first design to be tested and the second design to be tested can be simulated, thereby improving the completeness of the simulation verification and reducing the risk of tape-out.

[0067] It is important to understand that Figure 1 and Figure 2 The explanations of the same or corresponding steps in the above may refer to each other. For example, Figure 1 The explanation of step 120 and step 130 in Figure 2 Step 230 and step 240 in .

[0068] At the same time, it should be understood that a simulation verification method for a design to be tested provided in an embodiment of the present application may have the following beneficial effects: it may simulate the working state of a communication chip under various real working environments, and especially improve the simulation verification of the clock signals of the first design to be tested and the second design to be tested under non-ideal conditions (that is, the clock signal band of at least one of the first design to be tested and the second design to be tested has a frequency deviation), thereby improving the completeness of the simulation verification of the design to be tested and reducing the risk of tape-out of the design to be tested.

[0069] See also Figure 6 , Figure 6 is a structural block diagram of a simulation verification device provided in an embodiment of the present application. Figure 6 As shown, an embodiment of the present application provides a simulation verification device 600 , and the simulation verification device 600 includes: a frequency deviation generator 610 and a simulation verification module 620 .

[0070] The frequency deviation generator 610 is used to obtain a first clock signal for a first design under test and a second clock signal for a second design under test, wherein at least one of the first clock signal and the second clock signal is a clock signal with a frequency deviation; input the first clock signal to the first design under test, and input the second clock signal to the second design under test; The simulation verification module 620 is used to perform simulation verification on the first design to be tested and the second design to be tested.

[0071] The first design to be tested is communicatively connected with the second design to be tested.

[0072] In an embodiment of the present application, a first clock signal for a first design to be tested and a second clock signal for a second design to be tested are obtained, and at least one of the first clock signal and the second clock signal is a clock signal with frequency deviation; the first clock signal is input to the first design to be tested, and the second clock signal is input to the second design to be tested; the first design to be tested and the second design to be tested are simulated and verified; wherein the first design to be tested and the second design to be tested are connected in communication. In this way, at least one of the first clock signal input to the first design to be tested and the second clock signal input to the second design to be tested is a clock signal with frequency deviation, and on this basis, the first design to be tested and the second design to be tested are simulated and verified, which can better simulate the real working scenario of communication between the two designs to be tested, that is, in the first design to be tested and the second design to be tested that communicate with each other, there is at least one scenario in which the working clock of the design to be tested has frequency deviation, which improves the completeness of the simulation verification of the design to be tested, reduces the risk of subsequent tape-out of the design to be tested, and solves the problem of high tape-out risk of the design to be tested existing in the related technology.

[0073] The simulation verification device provided in the embodiment of the present application can implement each process implemented in the above method embodiment, and will not be described again here to avoid repetition.

[0074] like Figure 7As shown, an embodiment of the present application also provides an electronic device 700. The electronic device 700 includes: a processor 710 and a memory 720, the memory 720 stores programs or instructions, and the programs or instructions implement the steps of any of the methods described above when executed by the processor 710. For example, when the program is executed by the processor 710, the following process is implemented: obtaining a first clock signal for a first design to be tested and a second clock signal for a second design to be tested, at least one of the first clock signal and the second clock signal is a clock signal with frequency deviation; inputting the first clock signal to the first design to be tested, and inputting the second clock signal to the second design to be tested; performing simulation verification on the first design to be tested and the second design to be tested; wherein the first design to be tested and the second design to be tested are communicatively connected. In this way, at least one of the first clock signal input to the first design to be tested and the second clock signal input to the second design to be tested is a clock signal with frequency deviation. On this basis, simulation verification is performed on the first design to be tested and the second design to be tested, which can better simulate the actual working scenario of communication between the two designs to be tested, that is, in the first design to be tested and the second design to be tested that communicate with each other, there is at least one scenario in which the working clock of one design to be tested has frequency deviation, which improves the completeness of the simulation verification of the design to be tested, reduces the risk of subsequent tape-out of the design to be tested, and solves the problem of high tape-out risk of the design to be tested in the related technology.

[0075] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of each embodiment of the simulation verification method for the design to be tested are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0076] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0077] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0078] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0079] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0080] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0081] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A simulation verification method for a design to be tested, characterized in that: include: Acquire a first clock signal for a first design to be tested and a second clock signal for a second design to be tested, wherein at least one of the first clock signal and the second clock signal is a clock signal with a frequency deviation; Inputting the first clock signal to the first design under test, and inputting the second clock signal to the second design under test; Performing simulation verification on the first design to be tested and the second design to be tested; The first design to be tested is communicatively connected with the second design to be tested.

2. The method according to claim 1, characterized in that: The obtaining of a first clock signal for a first design to be tested and a second clock signal for a second design to be tested includes: The first frequency offset generator generates the first clock signal based on the first frequency offset parameter of the first design under test and the first clock source information of the first design under test, so as to replace the original clock signal of the first design under test; The second frequency offset generator generates the second clock signal based on the second frequency offset parameter of the second design under test and the second clock source information of the second design under test, so as to replace the original clock signal of the second design under test.

3. The method according to claim 2, characterized in that The first clock source information includes N clock frequencies of N clock sources, and the first frequency deviation generator includes N frequency deviation generators for the N clock sources; The first clock signal includes N clock signals; each of the N clock signals is generated by one of the N frequency deviation generators based on the first frequency deviation parameter and one of the N clock frequencies; wherein N is an integer greater than 1; The second clock source information includes M clock frequencies of M clock sources, and the second frequency deviation generator includes M frequency deviation generators for the M clock sources; the second clock signal includes M clock signals; each of the M clock signals is generated by a frequency deviation generator among the M frequency deviation generators based on the second frequency deviation parameter and one of the M clock frequencies; wherein M is an integer greater than 1.

4. The method according to claim 2, characterized in that: The first frequency offset parameter includes a first frequency offset value and first frequency offset indication information, the first frequency offset indication information is used to indicate a method for generating the frequency offset, and the first frequency offset indication information includes one of a fixed frequency offset and a non-fixed frequency offset; The second frequency offset parameter includes a second frequency offset value and second frequency offset indication information, the second frequency offset indication information is used to indicate a method for generating a frequency offset, and the second frequency offset indication information includes one of a fixed frequency offset and a non-fixed frequency offset.

5. The method according to claim 4, characterized in that In a case where the first frequency offset indication information includes a fixed frequency offset, the first frequency offset generator includes a fixed frequency offset generator, and the frequency offset value of the first clock signal is the first frequency offset value; In a case where the second frequency offset indication information includes a fixed frequency offset, the second frequency offset generator includes a fixed frequency offset generator, and the frequency offset value of the second clock signal is the second frequency offset value.

6. The method according to claim 4, characterized in that The first frequency deviation parameter also includes a first frequency deviation modulation mode and a first modulation period; In the case where the first frequency offset indication information includes a non-fixed frequency offset, the first frequency offset generator includes a non-fixed frequency offset generator, and the first clock signal is obtained based on the first frequency offset modulation mode, the first modulation period, the first frequency offset value, and the first clock source information; wherein the frequency offset value of the first clock signal is less than or equal to the first frequency offset value; The second frequency deviation parameters also include a second frequency deviation modulation mode and a second modulation period; when the second frequency deviation indication information includes a non-fixed frequency deviation, the second frequency deviation generator includes a non-fixed frequency deviation generator, and the second clock signal is obtained based on the second frequency deviation modulation mode, the second modulation period, the second frequency deviation value and the second clock source information; wherein, the frequency deviation value of the second clock signal is less than or equal to the second frequency deviation value.

7. The method according to any one of claims 1 to 6, characterized in that: The simulating and verifying the first design to be tested and the second design to be tested includes: Inputting test data into the first design to be tested; Acquire target data output by the second design under test; Based on the test data and the target data, obtaining a simulation verification result; The first design to be tested includes a first communication chip, and the second design to be tested includes a second communication chip.

8. A simulation verification device, comprising: Frequency deviation generator and simulation verification module; The frequency deviation generator is used to obtain a first clock signal for a first design to be tested and a second clock signal for a second design to be tested, wherein at least one of the first clock signal and the second clock signal is a clock signal with a frequency deviation; Inputting the first clock signal to the first design under test, and inputting the second clock signal to the second design under test; The simulation verification module is used to perform simulation verification on the first design to be tested and the second design to be tested; The first design to be tested is communicatively connected with the second design to be tested.

9. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores a program or instruction running on the processor, and when the program or instruction is executed by the processor, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium, characterized in that: The medium stores a program or an instruction, and when the program or the instruction is executed, the steps of the method according to any one of claims 1 to 7 are implemented.

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