Display device and electronic apparatus

Abstract

The invention discloses a display device and electronic equipment, the display device comprises a power supply management chip, a first voltage division circuit, a first level conversion chip, a first chip and a gate driving circuit, a low level can be generated through the first voltage division circuit and the first level conversion chip, the low level is provided for the gate driving circuit through a first low level line, and the gate driving circuit is connected with the first chip through a second low level line. And the other path of different low level is generated through the first chip and is provided for the gate driving circuit through the second low level line, so that two paths of different low levels can be provided for the gate driving circuit, and the quantity of different low levels which can be provided is increased to meet the requirements of display technology improvement.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device and an electronic device. Background Art

[0002] In the field of display technology, due to the specific requirements of voltage, a voltage / level converter (LevelShift, LS) is usually used. Among them, the level conversion chip is a kind of voltage / level converter and is widely used in display products.

[0003] In some of these display products, each display product is only equipped with one level conversion chip, each level conversion chip can only output one low level and does not have the function of voltage regulation.

[0004] With the improvement of display technology, it is difficult to meet the demand by only providing one low level. Summary of the invention

[0005] The present application provides a display device and an electronic device to alleviate the technical problem that a small number of different low-levels can be provided.

[0006] In a first aspect, the present application provides a display device, which includes a printed circuit board, a display panel and a first chip, the printed circuit board includes a power management chip, a first voltage divider circuit and a first level conversion chip, the power management chip includes a first voltage output end; the input end of the first voltage divider circuit is connected to the first voltage output end; the input end of the first level conversion chip is connected to the output end of the first voltage divider circuit, and the output end of the first level conversion chip is connected to a first low level line for outputting a first low level; the display panel includes a gate drive circuit, and the gate drive circuit is connected to the first low level line; the first chip is arranged on the printed circuit board or the display panel, the input end of the first chip is connected to the first voltage output end, the output end of the first chip is connected to the second low level line, the second low level line is used to output a second low level, and the second low level is different from the first low level.

[0007] In a second aspect, the present application provides an electronic device, which includes the above-mentioned display device.

[0008] The display device and electronic device provided in the present application can generate a low level through a first voltage divider circuit and a first level conversion chip, and provide it to a gate drive circuit via a first low level line, and generate another different low level through the first chip, and provide it to the gate drive circuit via a second low level line. In this way, two different low levels can be provided for the gate drive circuit, increasing the number of different low levels that can be provided to meet the needs of display technology improvement. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0010] Figure 1 A first structural schematic diagram of a display device provided in an embodiment of the present application.

[0011] Figure 2 A second structural schematic diagram of the display device provided in an embodiment of the present application.

[0012] Figure 3 A third structural schematic diagram of the display device provided in an embodiment of the present application.

[0013] Figure 4 A fourth structural schematic diagram of the display device provided in an embodiment of the present application.

[0014] Figure 5 A circuit schematic diagram of a shift register provided in an embodiment of the present application. DETAILED DESCRIPTION

[0015] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0016] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0017] See also Figures 1 to 5 , this embodiment provides a display device, such as Figures 1 to 4As shown, the display device includes a printed circuit board 100, a display panel 80 and a first chip 40. The printed circuit board 100 includes a power management chip 10, a first voltage divider circuit 20 and a first level conversion chip 30. The power management chip 10 includes a first voltage output terminal; the input terminal of the first voltage divider circuit 20 is connected to the first voltage output terminal; the input terminal of the first level conversion chip 30 is connected to the output terminal of the first voltage divider circuit 20, and the output terminal of the first level conversion chip 30 is connected to the first low level line VGL1 for outputting a first low level; the display panel 80 includes a gate driving circuit 50, and the gate driving circuit 50 is connected to the first low level line VGL1; the first chip 40 is arranged on the printed circuit board 100 or the display panel 80, the input terminal of the first chip 40 is connected to the first voltage output terminal, and the output terminal of the first chip 40 is connected to the second low level line VGL2 through the second low level line VGL2, and the second low level line VGL2 is used to output a second low level, which is different from the first low level.

[0018] It can be understood that the display device provided in this embodiment can generate a low level through the first voltage divider circuit 20 and the first level conversion chip 30, and provide it to the gate drive circuit 50 through the first low level line VGL1, and generate another different low level through the first chip 40, and provide it to the gate drive circuit 50 through the second low level line VGL2. In this way, two different low levels can be provided for the gate drive circuit 50, increasing the number of different low levels that can be provided to meet the needs of display technology improvement.

[0019] It should be noted that the power management chip 10 may also include other voltage output terminals, and the above-mentioned first voltage output terminal refers to a terminal or pin that outputs a low level. The low level can turn off the N-channel transistor, or can turn on the P-channel transistor. The first voltage divider circuit 20 can play a role in voltage division. For example, when the voltage at the input end of the first voltage divider circuit 20 is -10V, the voltage at the output end of the first voltage divider circuit 20 is -8V. In this way, the voltage of the first low level line VGL1 is different from the voltage of the second low level line VGL2.

[0020] In some embodiments, such as Figures 1 to 4 As shown, the first voltage divider circuit 20 includes a first resistor R1 , and the first resistor R1 is connected in series to the first voltage output terminal and the input terminal of the first level conversion chip 30 .

[0021] It should be noted that the first resistor R1 may be a chip resistor or a variable resistor, so that the voltage dividing effect of the first voltage dividing circuit 20 can be adjusted more flexibly.

[0022] In some embodiments, such as Figure 1 and Figure 2As shown, the first chip 40 is a second level conversion chip 41, and the display device also includes a source driver chip 60 separately arranged from the first chip 40. The input end of the second level conversion chip 41 is connected to the first voltage output end, and the output end of the second level conversion chip 41 is connected to the gate drive circuit 50 through the second low level line VGL2.

[0023] It should be noted that the second level conversion chip 41 can be the same as the first level conversion chip 30, for example, the same in terms of circuit structure or parameters. That is, if the input voltage of the first level conversion chip 30 is equal to the input voltage of the second level conversion chip 41, the output voltage of the first level conversion chip 30 is also equal to the output voltage of the second level conversion chip 41.

[0024] In some embodiments, such as Figure 1 and Figure 2 As shown, the display device also includes at least one of a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5; wherein the second resistor R2, the third resistor R3, the fourth resistor R4 and the fifth resistor R5 satisfy: the first resistor R1 is connected in series between the first voltage divider circuit 20 and the input end of the first level conversion chip 30; the third resistor R3 is connected in series between the first voltage output end and the input end of the second level conversion chip 41; the fourth resistor R4 is connected in series to the first low level line VGL1; the fifth resistor R5 is connected in series to the second low level line VGL2.

[0025] It should be noted that the resistance of at least one of the second resistor R2, the third resistor R3, the fourth resistor R4 and the fifth resistor R5 is zero ohm. In this way, different power supply paths can be selected by selecting whether at least one of the second resistor R2, the third resistor R3, the fourth resistor R4 and the fifth resistor R5 is needed to achieve different compatibility solutions.

[0026] For example, when the second resistor R2, the third resistor R3, the fourth resistor R4, and the fifth resistor R5 are all present, two different low levels can be used to power the gate drive circuit 50. When at least one of the third resistor R3 and the fifth resistor R5 does not exist, one of the low levels can be used to power the gate drive circuit 50. When at least one of the second resistor R2 and the fourth resistor R4 does not exist, another low level can be used to power the gate drive circuit 50.

[0027] In some embodiments, such as Figure 3 and Figure 4As shown, the first chip 40 includes a source driver chip 60 and a second level conversion chip 41 integrated with the source driver chip 60, the input end of the second level conversion chip 41 is connected to the first voltage output end, and the output end of the second level conversion chip 41 is connected to the second low level line VGL2.

[0028] It should be noted that the first chip 40 in this embodiment may be a chip integrated with multiple chips, one of which is the second level conversion chip 41, which can reduce the space occupied by the frame of the display device and is conducive to realizing a display product with a narrow frame.

[0029] In some embodiments, such as Figure 3 and Figure 4 As shown, the display device further includes at least one of a sixth resistor R6 and a seventh resistor R7; the sixth resistor R6 is connected in series to the first low level line VGL1; the seventh resistor R7 is connected in series to the second low level line VGL2.

[0030] It should be noted that the resistance of at least one of the sixth resistor R6 and the seventh resistor R7 is zero ohm. In this way, different power supply paths can be selected by selecting whether at least one of the sixth resistor R6 and the seventh resistor R7 is needed to achieve different compatibility solutions.

[0031] For example, when the sixth resistor R6 does not exist, the second level conversion chip 41 and the seventh resistor R7 can provide a low level to power the gate drive circuit 50. When the seventh resistor R7 does not exist, the first resistor R1, the first level conversion chip 30 and the sixth resistor R6 can provide another low level to power the gate drive circuit 50. When both the sixth resistor R6 and the seventh resistor R7 exist, two different low levels can be provided for the gate drive circuit 50 to meet the corresponding requirements of the gate drive circuit 50.

[0032] Please continue reading Figure 2 The display device includes a flexible circuit board 70 , and a printed circuit board 100 is connected to a display panel 80 via the flexible circuit board 70 .

[0033] The display panel 80 includes a source driver chip 60. A power management chip 10, a first voltage divider circuit 20, a first level conversion chip 30, a second level conversion chip 41, and a timing control chip 42 are arranged on the printed circuit board 100. The power management chip 10 can also supply power to the timing control chip 42 and the source driver chip 60. The timing control chip 42 can also be connected to the source driver chip 60 and the gate driver circuit 50.

[0034] The first voltage output terminal of the power management chip 10 is outputted, sequentially through the first voltage divider circuit 20, the second level conversion chip 41, the flexible circuit board 70 and the first low level line VGL1, to output the first low level to the gate driving circuit 50. The second resistor R2 and the fourth resistor R4 are both optional.

[0035] The voltage is output from the first voltage output terminal of the power management chip 10, and sequentially passes through the first level conversion chip 30, the flexible circuit board 70 and the second low level line VGL2 to output a second low level to the gate driving circuit 50. The third resistor R3 and the fifth resistor R5 are both optional.

[0036] Please continue reading Figure 4 ,and Figure 2 The difference is, Figure 4 The source driver chip 60 , the second level conversion chip 41 and the timing control chip 42 are integrated into the first chip 40 , which can reduce the space occupied by the frame.

[0037] The voltage is output from the first voltage output terminal of the power management chip 10, sequentially through the first voltage divider circuit 20 and the flexible circuit board 70 to the second level conversion chip 41 in the first chip 40 of the display panel 80, and then through the flexible circuit board 70 and the first low level line VGL1, outputting the first low level to the gate driving circuit 50. The sixth resistor R6 is optional.

[0038] The voltage is output from the first voltage output terminal of the power management chip 10, and sequentially passes through the first level conversion chip 30, the flexible circuit board 70 and the second low level line VGL2, and outputs a second low level to the gate driving circuit 50. The seventh resistor R7 is optional.

[0039] It should be noted that in Figure 2 , Figure 4 In the embodiment, the gate driving circuit 50 may be disposed on at least one of the two sides of the display device. Figure 2 , Figure 4 In the embodiment, a driving chip 90 for driving the backlight may also be disposed on the printed circuit board 100 .

[0040] In some embodiments, the gate drive circuit 50 includes a plurality of shift registers connected in cascade, such as Figure 5As shown, each shift register includes a pull-up transistor T21, a first transistor T1 and a second transistor T2, the first electrode of the pull-up transistor T21 is connected to the clock line, the second electrode of the pull-up transistor T21 is connected to the gate drive line GL, and the gate of the pull-up transistor T21 is connected to the pull-up node Q; the first electrode of the first transistor T1 is connected to the pull-up node Q, the second electrode of the first transistor T1 is connected to the second low level line VGL2, and the gate of the first transistor T1 is connected to the first control signal; the first electrode of the second transistor T2 is connected to the second electrode of the pull-up transistor T21, the second electrode of the second transistor T2 is connected to the first low level line VGL1, and the gate of the second transistor T2 is connected to the second control signal.

[0041] It should be noted that the first low level line VGL1 is used to transmit the first low level signal VSSG, and the second low level line VGL2 is used to transmit the second low level signal VSSQ. The clock line is used to transmit a clock signal, such as CK or XCK. Since the transistor is prone to parameter errors during the manufacturing process, the threshold voltage of the transistor changes. For example, if the design value of the threshold voltage of the transistor is 0V, the actual value of the threshold voltage of the transistor may be negative after the manufacturing is completed, which may cause leakage in the transistor, such as the pull-up transistor T21.

[0042] The pull-up transistor T21 is exemplarily an N-channel high-mobility oxide transistor. Even if the threshold voltage of the pull-up transistor T21 is a negative value, the present embodiment can control both the first transistor T1 and the second transistor T2 to be turned on, so that the gate potential of the pull-up transistor T21 is less than the second pole potential of the threshold voltage of the transistor, thereby making the gate-source voltage difference of the pull-up transistor T21 less than the threshold voltage, which can improve the leakage phenomenon of the pull-up transistor T21, thereby improving the horizontal stripe phenomenon of abnormal display.

[0043] The first transistor T1 and the second transistor T2 may be arranged in the pull-down maintaining unit 52 and / or the pull-down control unit 53 of the shift register. When the first transistor T1 and the second transistor T2 may be arranged in the pull-down maintaining unit 52, the input end of the inverter 521 is adjacent to the pull-up node Q, and the output signal of the inverter 521 may be at least one of the first control signal and the second control signal. When the first transistor T1 and the second transistor T2 may be arranged in the pull-down control unit 53, the first control signal and the second control signal may both be the N+1th level gate driving signal, i.e., G(N+1).

[0044] Optionally, the shift register may further include a cascade transistor T22, a first electrode of the cascade transistor T22 is connected to the clock line, a gate of the cascade transistor T22 is connected to the pull-up node Q, and a second electrode of the cascade transistor T22 is connected to a cascade line. The cascade line is used to transmit the Nth stage cascade signal, i.e., ST(N).

[0045] Optionally, the shift register may further include a first capacitor Cbt, one end of the first capacitor Cbt is connected to the pull-up node Q, and the other end of the first capacitor Cbt is connected to the gate drive line GL.

[0046] Optionally, the shift register may further include a pull-up control unit 51, the input end of the pull-up control unit 51 is connected to the N-1th level gate drive signal, namely G(N-1), and the control end of the pull-up control unit 51 is connected to the N-1th level cascade signal, namely ST(N-1).

[0047] It should be noted that, for the same transistor, the first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain. For example, when the first electrode is the source, the second electrode is the drain; or, when the first electrode is the drain, the second electrode is the source.

[0048] In some of the embodiments, the present embodiment provides an electronic device, which includes the above-mentioned display device.

[0049] It can be understood that since the electronic device provided in this embodiment includes the above-mentioned display device, it can also generate a low level through the first voltage divider circuit 20 and the first level conversion chip 30, and provide it to the gate drive circuit 50 through the first low level line VGL1, and generate another different low level through the first chip 40, and provide it to the gate drive circuit 50 through the second low level line VGL2. In this way, two different low levels can be provided for the gate drive circuit 50, thereby increasing the number of different low levels that can be provided to meet the needs of display technology improvement.

[0050] It should be noted that the electronic device may be a notebook computer.

[0051] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0052] The display device and the electronic device provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display device, characterized in that: The display device comprises a printed circuit board and a display panel, wherein the printed circuit board comprises: A power management chip, the power management chip comprising a first voltage output terminal; a first voltage divider circuit, wherein an input end of the first voltage divider circuit is connected to the first voltage output end; A first level conversion chip, wherein an input end of the first level conversion chip is connected to an output end of the first voltage divider circuit, and an output end of the first level conversion chip is connected to a first low level line for outputting a first low level; The display panel comprises a gate driving circuit, and the gate driving circuit is connected to the first low level line; A first chip, wherein the first chip is arranged on the printed circuit board or the display panel, an input end of the first chip is connected to the first voltage output end, an output end of the first chip is connected to the gate driving circuit via a second low level line, and the second low level line is used to output a second low level, which is different from the first low level.

2. The display device according to claim 1, characterized in that The first voltage divider circuit includes a first resistor, and the first resistor is connected in series to the first voltage output terminal and the input terminal of the first level conversion chip.

3. The display device according to claim 1, characterized in that The first chip is arranged on the printed circuit board, the first chip is a second level conversion chip, the display device also includes a source driver chip which is separately arranged from the first chip, the input end of the second level conversion chip is connected to the first voltage output end, and the output end of the second level conversion chip is connected to the second low level line.

4. The display device according to claim 3, characterized in that: The display device further includes at least one of a second resistor, a third resistor, a fourth resistor, and a fifth resistor; wherein the second resistor, the third resistor, the fourth resistor, and the fifth resistor satisfy: The second resistor is connected in series between the first voltage divider circuit and the input end of the first level conversion chip; The third resistor is connected in series between the first voltage output terminal and the input terminal of the second level conversion chip; The fourth resistor is connected in series to the first low level line; The fifth resistor is connected in series to the second low level line.

5. The display device according to claim 4, characterized in that: At least one of the first resistor, the third resistor, the fourth resistor and the fifth resistor has a resistance value of zero ohm.

6. The display device according to claim 1, characterized in that: The first chip is arranged on the display panel, and the first chip comprises a source driver chip and a second level conversion chip integrated with the source driver chip, an input end of the second level conversion chip is connected to the first voltage output end, and an output end of the second level conversion chip is connected to a second low level line.

7. The display device according to claim 6, characterized in that: The display device further includes at least one of a sixth resistor and a seventh resistor; A sixth resistor is connected in series to the first low level line; The seventh resistor is connected in series to the second low level line.

8. The display device according to claim 7, characterized in that: At least one of the sixth resistor and the seventh resistor has a resistance of zero ohm.

9. The display device according to any one of claims 1 to 8, characterized in that: The gate driving circuit includes a plurality of cascaded shift registers, each of which includes: A pull-up transistor, wherein a first electrode of the pull-up transistor is connected to a clock line, a second electrode of the pull-up transistor is connected to a gate drive line, and a gate of the pull-up transistor is connected to a pull-up node; a first transistor, wherein a first electrode of the first transistor is connected to the pull-up node, a second electrode of the first transistor is connected to the second low level line, and a gate of the first transistor is connected to a first control signal; A second transistor, wherein a first electrode of the second transistor is connected to a second electrode of the pull-up transistor, a second electrode of the second transistor is connected to the first low level line, and a gate of the second transistor is connected to a second control signal.

10. An electronic device, characterized in that: The electronic device comprises the display device according to any one of claims 1-9.

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